yam.c 31 KB

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  1. /*****************************************************************************/
  2. /*
  3. * yam.c -- YAM radio modem driver.
  4. *
  5. * Copyright (C) 1998 Frederic Rible F1OAT (frible@teaser.fr)
  6. * Adapted from baycom.c driver written by Thomas Sailer (sailer@ife.ee.ethz.ch)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. * Please note that the GPL allows you to use the driver, NOT the radio.
  23. * In order to use the radio, you need a license from the communications
  24. * authority of your country.
  25. *
  26. *
  27. * History:
  28. * 0.0 F1OAT 06.06.98 Begin of work with baycom.c source code V 0.3
  29. * 0.1 F1OAT 07.06.98 Add timer polling routine for channel arbitration
  30. * 0.2 F6FBB 08.06.98 Added delay after FPGA programming
  31. * 0.3 F6FBB 29.07.98 Delayed PTT implementation for dupmode=2
  32. * 0.4 F6FBB 30.07.98 Added TxTail, Slottime and Persistance
  33. * 0.5 F6FBB 01.08.98 Shared IRQs, /proc/net and network statistics
  34. * 0.6 F6FBB 25.08.98 Added 1200Bds format
  35. * 0.7 F6FBB 12.09.98 Added to the kernel configuration
  36. * 0.8 F6FBB 14.10.98 Fixed slottime/persistence timing bug
  37. * OK1ZIA 2.09.01 Fixed "kfree_skb on hard IRQ"
  38. * using dev_kfree_skb_any(). (important in 2.4 kernel)
  39. *
  40. */
  41. /*****************************************************************************/
  42. #include <linux/module.h>
  43. #include <linux/types.h>
  44. #include <linux/net.h>
  45. #include <linux/in.h>
  46. #include <linux/if.h>
  47. #include <linux/slab.h>
  48. #include <linux/errno.h>
  49. #include <linux/bitops.h>
  50. #include <linux/random.h>
  51. #include <asm/io.h>
  52. #include <asm/system.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/ioport.h>
  55. #include <linux/netdevice.h>
  56. #include <linux/if_arp.h>
  57. #include <linux/etherdevice.h>
  58. #include <linux/skbuff.h>
  59. #include <net/ax25.h>
  60. #include <linux/kernel.h>
  61. #include <linux/proc_fs.h>
  62. #include <linux/seq_file.h>
  63. #include <net/net_namespace.h>
  64. #include <asm/uaccess.h>
  65. #include <linux/init.h>
  66. #include <linux/yam.h>
  67. #include "yam9600.h"
  68. #include "yam1200.h"
  69. /* --------------------------------------------------------------------- */
  70. static const char yam_drvname[] = "yam";
  71. static char yam_drvinfo[] __initdata = KERN_INFO "YAM driver version 0.8 by F1OAT/F6FBB\n";
  72. /* --------------------------------------------------------------------- */
  73. #define YAM_9600 1
  74. #define YAM_1200 2
  75. #define NR_PORTS 4
  76. #define YAM_MAGIC 0xF10A7654
  77. /* Transmitter states */
  78. #define TX_OFF 0
  79. #define TX_HEAD 1
  80. #define TX_DATA 2
  81. #define TX_CRC1 3
  82. #define TX_CRC2 4
  83. #define TX_TAIL 5
  84. #define YAM_MAX_FRAME 1024
  85. #define DEFAULT_BITRATE 9600 /* bps */
  86. #define DEFAULT_HOLDD 10 /* sec */
  87. #define DEFAULT_TXD 300 /* ms */
  88. #define DEFAULT_TXTAIL 10 /* ms */
  89. #define DEFAULT_SLOT 100 /* ms */
  90. #define DEFAULT_PERS 64 /* 0->255 */
  91. struct yam_port {
  92. int magic;
  93. int bitrate;
  94. int baudrate;
  95. int iobase;
  96. int irq;
  97. int dupmode;
  98. struct net_device *dev;
  99. int nb_rxint;
  100. int nb_mdint;
  101. /* Parameters section */
  102. int txd; /* tx delay */
  103. int holdd; /* duplex ptt delay */
  104. int txtail; /* txtail delay */
  105. int slot; /* slottime */
  106. int pers; /* persistence */
  107. /* Tx section */
  108. int tx_state;
  109. int tx_count;
  110. int slotcnt;
  111. unsigned char tx_buf[YAM_MAX_FRAME];
  112. int tx_len;
  113. int tx_crcl, tx_crch;
  114. struct sk_buff_head send_queue; /* Packets awaiting transmission */
  115. /* Rx section */
  116. int dcd;
  117. unsigned char rx_buf[YAM_MAX_FRAME];
  118. int rx_len;
  119. int rx_crcl, rx_crch;
  120. };
  121. struct yam_mcs {
  122. unsigned char bits[YAM_FPGA_SIZE];
  123. int bitrate;
  124. struct yam_mcs *next;
  125. };
  126. static struct net_device *yam_devs[NR_PORTS];
  127. static struct yam_mcs *yam_data;
  128. static DEFINE_TIMER(yam_timer, NULL, 0, 0);
  129. /* --------------------------------------------------------------------- */
  130. #define RBR(iobase) (iobase+0)
  131. #define THR(iobase) (iobase+0)
  132. #define IER(iobase) (iobase+1)
  133. #define IIR(iobase) (iobase+2)
  134. #define FCR(iobase) (iobase+2)
  135. #define LCR(iobase) (iobase+3)
  136. #define MCR(iobase) (iobase+4)
  137. #define LSR(iobase) (iobase+5)
  138. #define MSR(iobase) (iobase+6)
  139. #define SCR(iobase) (iobase+7)
  140. #define DLL(iobase) (iobase+0)
  141. #define DLM(iobase) (iobase+1)
  142. #define YAM_EXTENT 8
  143. /* Interrupt Identification Register Bit Masks */
  144. #define IIR_NOPEND 1
  145. #define IIR_MSR 0
  146. #define IIR_TX 2
  147. #define IIR_RX 4
  148. #define IIR_LSR 6
  149. #define IIR_TIMEOUT 12 /* Fifo mode only */
  150. #define IIR_MASK 0x0F
  151. /* Interrupt Enable Register Bit Masks */
  152. #define IER_RX 1 /* enable rx interrupt */
  153. #define IER_TX 2 /* enable tx interrupt */
  154. #define IER_LSR 4 /* enable line status interrupts */
  155. #define IER_MSR 8 /* enable modem status interrupts */
  156. /* Modem Control Register Bit Masks */
  157. #define MCR_DTR 0x01 /* DTR output */
  158. #define MCR_RTS 0x02 /* RTS output */
  159. #define MCR_OUT1 0x04 /* OUT1 output (not accessible in RS232) */
  160. #define MCR_OUT2 0x08 /* Master Interrupt enable (must be set on PCs) */
  161. #define MCR_LOOP 0x10 /* Loopback enable */
  162. /* Modem Status Register Bit Masks */
  163. #define MSR_DCTS 0x01 /* Delta CTS input */
  164. #define MSR_DDSR 0x02 /* Delta DSR */
  165. #define MSR_DRIN 0x04 /* Delta RI */
  166. #define MSR_DDCD 0x08 /* Delta DCD */
  167. #define MSR_CTS 0x10 /* CTS input */
  168. #define MSR_DSR 0x20 /* DSR input */
  169. #define MSR_RING 0x40 /* RI input */
  170. #define MSR_DCD 0x80 /* DCD input */
  171. /* line status register bit mask */
  172. #define LSR_RXC 0x01
  173. #define LSR_OE 0x02
  174. #define LSR_PE 0x04
  175. #define LSR_FE 0x08
  176. #define LSR_BREAK 0x10
  177. #define LSR_THRE 0x20
  178. #define LSR_TSRE 0x40
  179. /* Line Control Register Bit Masks */
  180. #define LCR_DLAB 0x80
  181. #define LCR_BREAK 0x40
  182. #define LCR_PZERO 0x28
  183. #define LCR_PEVEN 0x18
  184. #define LCR_PODD 0x08
  185. #define LCR_STOP1 0x00
  186. #define LCR_STOP2 0x04
  187. #define LCR_BIT5 0x00
  188. #define LCR_BIT6 0x02
  189. #define LCR_BIT7 0x01
  190. #define LCR_BIT8 0x03
  191. /* YAM Modem <-> UART Port mapping */
  192. #define TX_RDY MSR_DCTS /* transmitter ready to send */
  193. #define RX_DCD MSR_DCD /* carrier detect */
  194. #define RX_FLAG MSR_RING /* hdlc flag received */
  195. #define FPGA_DONE MSR_DSR /* FPGA is configured */
  196. #define PTT_ON (MCR_RTS|MCR_OUT2) /* activate PTT */
  197. #define PTT_OFF (MCR_DTR|MCR_OUT2) /* release PTT */
  198. #define ENABLE_RXINT IER_RX /* enable uart rx interrupt during rx */
  199. #define ENABLE_TXINT IER_MSR /* enable uart ms interrupt during tx */
  200. #define ENABLE_RTXINT (IER_RX|IER_MSR) /* full duplex operations */
  201. /*************************************************************************
  202. * CRC Tables
  203. ************************************************************************/
  204. static const unsigned char chktabl[256] =
  205. {0x00, 0x89, 0x12, 0x9b, 0x24, 0xad, 0x36, 0xbf, 0x48, 0xc1, 0x5a, 0xd3, 0x6c, 0xe5, 0x7e,
  206. 0xf7, 0x81, 0x08, 0x93, 0x1a, 0xa5, 0x2c, 0xb7, 0x3e, 0xc9, 0x40, 0xdb, 0x52, 0xed, 0x64,
  207. 0xff, 0x76, 0x02, 0x8b, 0x10, 0x99, 0x26, 0xaf, 0x34, 0xbd, 0x4a, 0xc3, 0x58, 0xd1, 0x6e,
  208. 0xe7, 0x7c, 0xf5, 0x83, 0x0a, 0x91, 0x18, 0xa7, 0x2e, 0xb5, 0x3c, 0xcb, 0x42, 0xd9, 0x50,
  209. 0xef, 0x66, 0xfd, 0x74, 0x04, 0x8d, 0x16, 0x9f, 0x20, 0xa9, 0x32, 0xbb, 0x4c, 0xc5, 0x5e,
  210. 0xd7, 0x68, 0xe1, 0x7a, 0xf3, 0x85, 0x0c, 0x97, 0x1e, 0xa1, 0x28, 0xb3, 0x3a, 0xcd, 0x44,
  211. 0xdf, 0x56, 0xe9, 0x60, 0xfb, 0x72, 0x06, 0x8f, 0x14, 0x9d, 0x22, 0xab, 0x30, 0xb9, 0x4e,
  212. 0xc7, 0x5c, 0xd5, 0x6a, 0xe3, 0x78, 0xf1, 0x87, 0x0e, 0x95, 0x1c, 0xa3, 0x2a, 0xb1, 0x38,
  213. 0xcf, 0x46, 0xdd, 0x54, 0xeb, 0x62, 0xf9, 0x70, 0x08, 0x81, 0x1a, 0x93, 0x2c, 0xa5, 0x3e,
  214. 0xb7, 0x40, 0xc9, 0x52, 0xdb, 0x64, 0xed, 0x76, 0xff, 0x89, 0x00, 0x9b, 0x12, 0xad, 0x24,
  215. 0xbf, 0x36, 0xc1, 0x48, 0xd3, 0x5a, 0xe5, 0x6c, 0xf7, 0x7e, 0x0a, 0x83, 0x18, 0x91, 0x2e,
  216. 0xa7, 0x3c, 0xb5, 0x42, 0xcb, 0x50, 0xd9, 0x66, 0xef, 0x74, 0xfd, 0x8b, 0x02, 0x99, 0x10,
  217. 0xaf, 0x26, 0xbd, 0x34, 0xc3, 0x4a, 0xd1, 0x58, 0xe7, 0x6e, 0xf5, 0x7c, 0x0c, 0x85, 0x1e,
  218. 0x97, 0x28, 0xa1, 0x3a, 0xb3, 0x44, 0xcd, 0x56, 0xdf, 0x60, 0xe9, 0x72, 0xfb, 0x8d, 0x04,
  219. 0x9f, 0x16, 0xa9, 0x20, 0xbb, 0x32, 0xc5, 0x4c, 0xd7, 0x5e, 0xe1, 0x68, 0xf3, 0x7a, 0x0e,
  220. 0x87, 0x1c, 0x95, 0x2a, 0xa3, 0x38, 0xb1, 0x46, 0xcf, 0x54, 0xdd, 0x62, 0xeb, 0x70, 0xf9,
  221. 0x8f, 0x06, 0x9d, 0x14, 0xab, 0x22, 0xb9, 0x30, 0xc7, 0x4e, 0xd5, 0x5c, 0xe3, 0x6a, 0xf1,
  222. 0x78};
  223. static const unsigned char chktabh[256] =
  224. {0x00, 0x11, 0x23, 0x32, 0x46, 0x57, 0x65, 0x74, 0x8c, 0x9d, 0xaf, 0xbe, 0xca, 0xdb, 0xe9,
  225. 0xf8, 0x10, 0x01, 0x33, 0x22, 0x56, 0x47, 0x75, 0x64, 0x9c, 0x8d, 0xbf, 0xae, 0xda, 0xcb,
  226. 0xf9, 0xe8, 0x21, 0x30, 0x02, 0x13, 0x67, 0x76, 0x44, 0x55, 0xad, 0xbc, 0x8e, 0x9f, 0xeb,
  227. 0xfa, 0xc8, 0xd9, 0x31, 0x20, 0x12, 0x03, 0x77, 0x66, 0x54, 0x45, 0xbd, 0xac, 0x9e, 0x8f,
  228. 0xfb, 0xea, 0xd8, 0xc9, 0x42, 0x53, 0x61, 0x70, 0x04, 0x15, 0x27, 0x36, 0xce, 0xdf, 0xed,
  229. 0xfc, 0x88, 0x99, 0xab, 0xba, 0x52, 0x43, 0x71, 0x60, 0x14, 0x05, 0x37, 0x26, 0xde, 0xcf,
  230. 0xfd, 0xec, 0x98, 0x89, 0xbb, 0xaa, 0x63, 0x72, 0x40, 0x51, 0x25, 0x34, 0x06, 0x17, 0xef,
  231. 0xfe, 0xcc, 0xdd, 0xa9, 0xb8, 0x8a, 0x9b, 0x73, 0x62, 0x50, 0x41, 0x35, 0x24, 0x16, 0x07,
  232. 0xff, 0xee, 0xdc, 0xcd, 0xb9, 0xa8, 0x9a, 0x8b, 0x84, 0x95, 0xa7, 0xb6, 0xc2, 0xd3, 0xe1,
  233. 0xf0, 0x08, 0x19, 0x2b, 0x3a, 0x4e, 0x5f, 0x6d, 0x7c, 0x94, 0x85, 0xb7, 0xa6, 0xd2, 0xc3,
  234. 0xf1, 0xe0, 0x18, 0x09, 0x3b, 0x2a, 0x5e, 0x4f, 0x7d, 0x6c, 0xa5, 0xb4, 0x86, 0x97, 0xe3,
  235. 0xf2, 0xc0, 0xd1, 0x29, 0x38, 0x0a, 0x1b, 0x6f, 0x7e, 0x4c, 0x5d, 0xb5, 0xa4, 0x96, 0x87,
  236. 0xf3, 0xe2, 0xd0, 0xc1, 0x39, 0x28, 0x1a, 0x0b, 0x7f, 0x6e, 0x5c, 0x4d, 0xc6, 0xd7, 0xe5,
  237. 0xf4, 0x80, 0x91, 0xa3, 0xb2, 0x4a, 0x5b, 0x69, 0x78, 0x0c, 0x1d, 0x2f, 0x3e, 0xd6, 0xc7,
  238. 0xf5, 0xe4, 0x90, 0x81, 0xb3, 0xa2, 0x5a, 0x4b, 0x79, 0x68, 0x1c, 0x0d, 0x3f, 0x2e, 0xe7,
  239. 0xf6, 0xc4, 0xd5, 0xa1, 0xb0, 0x82, 0x93, 0x6b, 0x7a, 0x48, 0x59, 0x2d, 0x3c, 0x0e, 0x1f,
  240. 0xf7, 0xe6, 0xd4, 0xc5, 0xb1, 0xa0, 0x92, 0x83, 0x7b, 0x6a, 0x58, 0x49, 0x3d, 0x2c, 0x1e,
  241. 0x0f};
  242. /*************************************************************************
  243. * FPGA functions
  244. ************************************************************************/
  245. static void delay(int ms)
  246. {
  247. unsigned long timeout = jiffies + ((ms * HZ) / 1000);
  248. while (time_before(jiffies, timeout))
  249. cpu_relax();
  250. }
  251. /*
  252. * reset FPGA
  253. */
  254. static void fpga_reset(int iobase)
  255. {
  256. outb(0, IER(iobase));
  257. outb(LCR_DLAB | LCR_BIT5, LCR(iobase));
  258. outb(1, DLL(iobase));
  259. outb(0, DLM(iobase));
  260. outb(LCR_BIT5, LCR(iobase));
  261. inb(LSR(iobase));
  262. inb(MSR(iobase));
  263. /* turn off FPGA supply voltage */
  264. outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));
  265. delay(100);
  266. /* turn on FPGA supply voltage again */
  267. outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));
  268. delay(100);
  269. }
  270. /*
  271. * send one byte to FPGA
  272. */
  273. static int fpga_write(int iobase, unsigned char wrd)
  274. {
  275. unsigned char bit;
  276. int k;
  277. unsigned long timeout = jiffies + HZ / 10;
  278. for (k = 0; k < 8; k++) {
  279. bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR;
  280. outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase));
  281. wrd <<= 1;
  282. outb(0xfc, THR(iobase));
  283. while ((inb(LSR(iobase)) & LSR_TSRE) == 0)
  284. if (time_after(jiffies, timeout))
  285. return -1;
  286. }
  287. return 0;
  288. }
  289. static unsigned char *add_mcs(unsigned char *bits, int bitrate)
  290. {
  291. struct yam_mcs *p;
  292. /* If it already exists, replace the bit data */
  293. p = yam_data;
  294. while (p) {
  295. if (p->bitrate == bitrate) {
  296. memcpy(p->bits, bits, YAM_FPGA_SIZE);
  297. return p->bits;
  298. }
  299. p = p->next;
  300. }
  301. /* Allocate a new mcs */
  302. if ((p = kmalloc(sizeof(struct yam_mcs), GFP_KERNEL)) == NULL) {
  303. printk(KERN_WARNING "YAM: no memory to allocate mcs\n");
  304. return NULL;
  305. }
  306. memcpy(p->bits, bits, YAM_FPGA_SIZE);
  307. p->bitrate = bitrate;
  308. p->next = yam_data;
  309. yam_data = p;
  310. return p->bits;
  311. }
  312. static unsigned char *get_mcs(int bitrate)
  313. {
  314. struct yam_mcs *p;
  315. p = yam_data;
  316. while (p) {
  317. if (p->bitrate == bitrate)
  318. return p->bits;
  319. p = p->next;
  320. }
  321. /* Load predefined mcs data */
  322. switch (bitrate) {
  323. case 1200:
  324. return add_mcs(bits_1200, bitrate);
  325. default:
  326. return add_mcs(bits_9600, bitrate);
  327. }
  328. }
  329. /*
  330. * download bitstream to FPGA
  331. * data is contained in bits[] array in yam1200.h resp. yam9600.h
  332. */
  333. static int fpga_download(int iobase, int bitrate)
  334. {
  335. int i, rc;
  336. unsigned char *pbits;
  337. pbits = get_mcs(bitrate);
  338. if (pbits == NULL)
  339. return -1;
  340. fpga_reset(iobase);
  341. for (i = 0; i < YAM_FPGA_SIZE; i++) {
  342. if (fpga_write(iobase, pbits[i])) {
  343. printk(KERN_ERR "yam: error in write cycle\n");
  344. return -1; /* write... */
  345. }
  346. }
  347. fpga_write(iobase, 0xFF);
  348. rc = inb(MSR(iobase)); /* check DONE signal */
  349. /* Needed for some hardwares */
  350. delay(50);
  351. return (rc & MSR_DSR) ? 0 : -1;
  352. }
  353. /************************************************************************
  354. * Serial port init
  355. ************************************************************************/
  356. static void yam_set_uart(struct net_device *dev)
  357. {
  358. struct yam_port *yp = netdev_priv(dev);
  359. int divisor = 115200 / yp->baudrate;
  360. outb(0, IER(dev->base_addr));
  361. outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr));
  362. outb(divisor, DLL(dev->base_addr));
  363. outb(0, DLM(dev->base_addr));
  364. outb(LCR_BIT8, LCR(dev->base_addr));
  365. outb(PTT_OFF, MCR(dev->base_addr));
  366. outb(0x00, FCR(dev->base_addr));
  367. /* Flush pending irq */
  368. inb(RBR(dev->base_addr));
  369. inb(MSR(dev->base_addr));
  370. /* Enable rx irq */
  371. outb(ENABLE_RTXINT, IER(dev->base_addr));
  372. }
  373. /* --------------------------------------------------------------------- */
  374. enum uart {
  375. c_uart_unknown, c_uart_8250,
  376. c_uart_16450, c_uart_16550, c_uart_16550A
  377. };
  378. static const char *uart_str[] =
  379. {"unknown", "8250", "16450", "16550", "16550A"};
  380. static enum uart yam_check_uart(unsigned int iobase)
  381. {
  382. unsigned char b1, b2, b3;
  383. enum uart u;
  384. enum uart uart_tab[] =
  385. {c_uart_16450, c_uart_unknown, c_uart_16550, c_uart_16550A};
  386. b1 = inb(MCR(iobase));
  387. outb(b1 | 0x10, MCR(iobase)); /* loopback mode */
  388. b2 = inb(MSR(iobase));
  389. outb(0x1a, MCR(iobase));
  390. b3 = inb(MSR(iobase)) & 0xf0;
  391. outb(b1, MCR(iobase)); /* restore old values */
  392. outb(b2, MSR(iobase));
  393. if (b3 != 0x90)
  394. return c_uart_unknown;
  395. inb(RBR(iobase));
  396. inb(RBR(iobase));
  397. outb(0x01, FCR(iobase)); /* enable FIFOs */
  398. u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
  399. if (u == c_uart_16450) {
  400. outb(0x5a, SCR(iobase));
  401. b1 = inb(SCR(iobase));
  402. outb(0xa5, SCR(iobase));
  403. b2 = inb(SCR(iobase));
  404. if ((b1 != 0x5a) || (b2 != 0xa5))
  405. u = c_uart_8250;
  406. }
  407. return u;
  408. }
  409. /******************************************************************************
  410. * Rx Section
  411. ******************************************************************************/
  412. static inline void yam_rx_flag(struct net_device *dev, struct yam_port *yp)
  413. {
  414. if (yp->dcd && yp->rx_len >= 3 && yp->rx_len < YAM_MAX_FRAME) {
  415. int pkt_len = yp->rx_len - 2 + 1; /* -CRC + kiss */
  416. struct sk_buff *skb;
  417. if ((yp->rx_crch & yp->rx_crcl) != 0xFF) {
  418. /* Bad crc */
  419. } else {
  420. if (!(skb = dev_alloc_skb(pkt_len))) {
  421. printk(KERN_WARNING "%s: memory squeeze, dropping packet\n", dev->name);
  422. ++dev->stats.rx_dropped;
  423. } else {
  424. unsigned char *cp;
  425. cp = skb_put(skb, pkt_len);
  426. *cp++ = 0; /* KISS kludge */
  427. memcpy(cp, yp->rx_buf, pkt_len - 1);
  428. skb->protocol = ax25_type_trans(skb, dev);
  429. netif_rx(skb);
  430. ++dev->stats.rx_packets;
  431. }
  432. }
  433. }
  434. yp->rx_len = 0;
  435. yp->rx_crcl = 0x21;
  436. yp->rx_crch = 0xf3;
  437. }
  438. static inline void yam_rx_byte(struct net_device *dev, struct yam_port *yp, unsigned char rxb)
  439. {
  440. if (yp->rx_len < YAM_MAX_FRAME) {
  441. unsigned char c = yp->rx_crcl;
  442. yp->rx_crcl = (chktabl[c] ^ yp->rx_crch);
  443. yp->rx_crch = (chktabh[c] ^ rxb);
  444. yp->rx_buf[yp->rx_len++] = rxb;
  445. }
  446. }
  447. /********************************************************************************
  448. * TX Section
  449. ********************************************************************************/
  450. static void ptt_on(struct net_device *dev)
  451. {
  452. outb(PTT_ON, MCR(dev->base_addr));
  453. }
  454. static void ptt_off(struct net_device *dev)
  455. {
  456. outb(PTT_OFF, MCR(dev->base_addr));
  457. }
  458. static int yam_send_packet(struct sk_buff *skb, struct net_device *dev)
  459. {
  460. struct yam_port *yp = netdev_priv(dev);
  461. skb_queue_tail(&yp->send_queue, skb);
  462. dev->trans_start = jiffies;
  463. return 0;
  464. }
  465. static void yam_start_tx(struct net_device *dev, struct yam_port *yp)
  466. {
  467. if ((yp->tx_state == TX_TAIL) || (yp->txd == 0))
  468. yp->tx_count = 1;
  469. else
  470. yp->tx_count = (yp->bitrate * yp->txd) / 8000;
  471. yp->tx_state = TX_HEAD;
  472. ptt_on(dev);
  473. }
  474. static void yam_arbitrate(struct net_device *dev)
  475. {
  476. struct yam_port *yp = netdev_priv(dev);
  477. if (yp->magic != YAM_MAGIC || yp->tx_state != TX_OFF ||
  478. skb_queue_empty(&yp->send_queue))
  479. return;
  480. /* tx_state is TX_OFF and there is data to send */
  481. if (yp->dupmode) {
  482. /* Full duplex mode, don't wait */
  483. yam_start_tx(dev, yp);
  484. return;
  485. }
  486. if (yp->dcd) {
  487. /* DCD on, wait slotime ... */
  488. yp->slotcnt = yp->slot / 10;
  489. return;
  490. }
  491. /* Is slottime passed ? */
  492. if ((--yp->slotcnt) > 0)
  493. return;
  494. yp->slotcnt = yp->slot / 10;
  495. /* is random > persist ? */
  496. if ((random32() % 256) > yp->pers)
  497. return;
  498. yam_start_tx(dev, yp);
  499. }
  500. static void yam_dotimer(unsigned long dummy)
  501. {
  502. int i;
  503. for (i = 0; i < NR_PORTS; i++) {
  504. struct net_device *dev = yam_devs[i];
  505. if (dev && netif_running(dev))
  506. yam_arbitrate(dev);
  507. }
  508. yam_timer.expires = jiffies + HZ / 100;
  509. add_timer(&yam_timer);
  510. }
  511. static void yam_tx_byte(struct net_device *dev, struct yam_port *yp)
  512. {
  513. struct sk_buff *skb;
  514. unsigned char b, temp;
  515. switch (yp->tx_state) {
  516. case TX_OFF:
  517. break;
  518. case TX_HEAD:
  519. if (--yp->tx_count <= 0) {
  520. if (!(skb = skb_dequeue(&yp->send_queue))) {
  521. ptt_off(dev);
  522. yp->tx_state = TX_OFF;
  523. break;
  524. }
  525. yp->tx_state = TX_DATA;
  526. if (skb->data[0] != 0) {
  527. /* do_kiss_params(s, skb->data, skb->len); */
  528. dev_kfree_skb_any(skb);
  529. break;
  530. }
  531. yp->tx_len = skb->len - 1; /* strip KISS byte */
  532. if (yp->tx_len >= YAM_MAX_FRAME || yp->tx_len < 2) {
  533. dev_kfree_skb_any(skb);
  534. break;
  535. }
  536. skb_copy_from_linear_data_offset(skb, 1,
  537. yp->tx_buf,
  538. yp->tx_len);
  539. dev_kfree_skb_any(skb);
  540. yp->tx_count = 0;
  541. yp->tx_crcl = 0x21;
  542. yp->tx_crch = 0xf3;
  543. yp->tx_state = TX_DATA;
  544. }
  545. break;
  546. case TX_DATA:
  547. b = yp->tx_buf[yp->tx_count++];
  548. outb(b, THR(dev->base_addr));
  549. temp = yp->tx_crcl;
  550. yp->tx_crcl = chktabl[temp] ^ yp->tx_crch;
  551. yp->tx_crch = chktabh[temp] ^ b;
  552. if (yp->tx_count >= yp->tx_len) {
  553. yp->tx_state = TX_CRC1;
  554. }
  555. break;
  556. case TX_CRC1:
  557. yp->tx_crch = chktabl[yp->tx_crcl] ^ yp->tx_crch;
  558. yp->tx_crcl = chktabh[yp->tx_crcl] ^ chktabl[yp->tx_crch] ^ 0xff;
  559. outb(yp->tx_crcl, THR(dev->base_addr));
  560. yp->tx_state = TX_CRC2;
  561. break;
  562. case TX_CRC2:
  563. outb(chktabh[yp->tx_crch] ^ 0xFF, THR(dev->base_addr));
  564. if (skb_queue_empty(&yp->send_queue)) {
  565. yp->tx_count = (yp->bitrate * yp->txtail) / 8000;
  566. if (yp->dupmode == 2)
  567. yp->tx_count += (yp->bitrate * yp->holdd) / 8;
  568. if (yp->tx_count == 0)
  569. yp->tx_count = 1;
  570. yp->tx_state = TX_TAIL;
  571. } else {
  572. yp->tx_count = 1;
  573. yp->tx_state = TX_HEAD;
  574. }
  575. ++dev->stats.tx_packets;
  576. break;
  577. case TX_TAIL:
  578. if (--yp->tx_count <= 0) {
  579. yp->tx_state = TX_OFF;
  580. ptt_off(dev);
  581. }
  582. break;
  583. }
  584. }
  585. /***********************************************************************************
  586. * ISR routine
  587. ************************************************************************************/
  588. static irqreturn_t yam_interrupt(int irq, void *dev_id)
  589. {
  590. struct net_device *dev;
  591. struct yam_port *yp;
  592. unsigned char iir;
  593. int counter = 100;
  594. int i;
  595. int handled = 0;
  596. for (i = 0; i < NR_PORTS; i++) {
  597. dev = yam_devs[i];
  598. yp = netdev_priv(dev);
  599. if (!netif_running(dev))
  600. continue;
  601. while ((iir = IIR_MASK & inb(IIR(dev->base_addr))) != IIR_NOPEND) {
  602. unsigned char msr = inb(MSR(dev->base_addr));
  603. unsigned char lsr = inb(LSR(dev->base_addr));
  604. unsigned char rxb;
  605. handled = 1;
  606. if (lsr & LSR_OE)
  607. ++dev->stats.rx_fifo_errors;
  608. yp->dcd = (msr & RX_DCD) ? 1 : 0;
  609. if (--counter <= 0) {
  610. printk(KERN_ERR "%s: too many irq iir=%d\n",
  611. dev->name, iir);
  612. goto out;
  613. }
  614. if (msr & TX_RDY) {
  615. ++yp->nb_mdint;
  616. yam_tx_byte(dev, yp);
  617. }
  618. if (lsr & LSR_RXC) {
  619. ++yp->nb_rxint;
  620. rxb = inb(RBR(dev->base_addr));
  621. if (msr & RX_FLAG)
  622. yam_rx_flag(dev, yp);
  623. else
  624. yam_rx_byte(dev, yp, rxb);
  625. }
  626. }
  627. }
  628. out:
  629. return IRQ_RETVAL(handled);
  630. }
  631. #ifdef CONFIG_PROC_FS
  632. static void *yam_seq_start(struct seq_file *seq, loff_t *pos)
  633. {
  634. return (*pos < NR_PORTS) ? yam_devs[*pos] : NULL;
  635. }
  636. static void *yam_seq_next(struct seq_file *seq, void *v, loff_t *pos)
  637. {
  638. ++*pos;
  639. return (*pos < NR_PORTS) ? yam_devs[*pos] : NULL;
  640. }
  641. static void yam_seq_stop(struct seq_file *seq, void *v)
  642. {
  643. }
  644. static int yam_seq_show(struct seq_file *seq, void *v)
  645. {
  646. struct net_device *dev = v;
  647. const struct yam_port *yp = netdev_priv(dev);
  648. seq_printf(seq, "Device %s\n", dev->name);
  649. seq_printf(seq, " Up %d\n", netif_running(dev));
  650. seq_printf(seq, " Speed %u\n", yp->bitrate);
  651. seq_printf(seq, " IoBase 0x%x\n", yp->iobase);
  652. seq_printf(seq, " BaudRate %u\n", yp->baudrate);
  653. seq_printf(seq, " IRQ %u\n", yp->irq);
  654. seq_printf(seq, " TxState %u\n", yp->tx_state);
  655. seq_printf(seq, " Duplex %u\n", yp->dupmode);
  656. seq_printf(seq, " HoldDly %u\n", yp->holdd);
  657. seq_printf(seq, " TxDelay %u\n", yp->txd);
  658. seq_printf(seq, " TxTail %u\n", yp->txtail);
  659. seq_printf(seq, " SlotTime %u\n", yp->slot);
  660. seq_printf(seq, " Persist %u\n", yp->pers);
  661. seq_printf(seq, " TxFrames %lu\n", dev->stats.tx_packets);
  662. seq_printf(seq, " RxFrames %lu\n", dev->stats.rx_packets);
  663. seq_printf(seq, " TxInt %u\n", yp->nb_mdint);
  664. seq_printf(seq, " RxInt %u\n", yp->nb_rxint);
  665. seq_printf(seq, " RxOver %lu\n", dev->stats.rx_fifo_errors);
  666. seq_printf(seq, "\n");
  667. return 0;
  668. }
  669. static const struct seq_operations yam_seqops = {
  670. .start = yam_seq_start,
  671. .next = yam_seq_next,
  672. .stop = yam_seq_stop,
  673. .show = yam_seq_show,
  674. };
  675. static int yam_info_open(struct inode *inode, struct file *file)
  676. {
  677. return seq_open(file, &yam_seqops);
  678. }
  679. static const struct file_operations yam_info_fops = {
  680. .owner = THIS_MODULE,
  681. .open = yam_info_open,
  682. .read = seq_read,
  683. .llseek = seq_lseek,
  684. .release = seq_release,
  685. };
  686. #endif
  687. /* --------------------------------------------------------------------- */
  688. static int yam_open(struct net_device *dev)
  689. {
  690. struct yam_port *yp = netdev_priv(dev);
  691. enum uart u;
  692. int i;
  693. int ret=0;
  694. printk(KERN_INFO "Trying %s at iobase 0x%lx irq %u\n", dev->name, dev->base_addr, dev->irq);
  695. if (!dev || !yp->bitrate)
  696. return -ENXIO;
  697. if (!dev->base_addr || dev->base_addr > 0x1000 - YAM_EXTENT ||
  698. dev->irq < 2 || dev->irq > 15) {
  699. return -ENXIO;
  700. }
  701. if (!request_region(dev->base_addr, YAM_EXTENT, dev->name))
  702. {
  703. printk(KERN_ERR "%s: cannot 0x%lx busy\n", dev->name, dev->base_addr);
  704. return -EACCES;
  705. }
  706. if ((u = yam_check_uart(dev->base_addr)) == c_uart_unknown) {
  707. printk(KERN_ERR "%s: cannot find uart type\n", dev->name);
  708. ret = -EIO;
  709. goto out_release_base;
  710. }
  711. if (fpga_download(dev->base_addr, yp->bitrate)) {
  712. printk(KERN_ERR "%s: cannot init FPGA\n", dev->name);
  713. ret = -EIO;
  714. goto out_release_base;
  715. }
  716. outb(0, IER(dev->base_addr));
  717. if (request_irq(dev->irq, yam_interrupt, IRQF_DISABLED | IRQF_SHARED, dev->name, dev)) {
  718. printk(KERN_ERR "%s: irq %d busy\n", dev->name, dev->irq);
  719. ret = -EBUSY;
  720. goto out_release_base;
  721. }
  722. yam_set_uart(dev);
  723. netif_start_queue(dev);
  724. yp->slotcnt = yp->slot / 10;
  725. /* Reset overruns for all ports - FPGA programming makes overruns */
  726. for (i = 0; i < NR_PORTS; i++) {
  727. struct net_device *dev = yam_devs[i];
  728. inb(LSR(dev->base_addr));
  729. dev->stats.rx_fifo_errors = 0;
  730. }
  731. printk(KERN_INFO "%s at iobase 0x%lx irq %u uart %s\n", dev->name, dev->base_addr, dev->irq,
  732. uart_str[u]);
  733. return 0;
  734. out_release_base:
  735. release_region(dev->base_addr, YAM_EXTENT);
  736. return ret;
  737. }
  738. /* --------------------------------------------------------------------- */
  739. static int yam_close(struct net_device *dev)
  740. {
  741. struct sk_buff *skb;
  742. struct yam_port *yp = netdev_priv(dev);
  743. if (!dev)
  744. return -EINVAL;
  745. /*
  746. * disable interrupts
  747. */
  748. outb(0, IER(dev->base_addr));
  749. outb(1, MCR(dev->base_addr));
  750. /* Remove IRQ handler if last */
  751. free_irq(dev->irq,dev);
  752. release_region(dev->base_addr, YAM_EXTENT);
  753. netif_stop_queue(dev);
  754. while ((skb = skb_dequeue(&yp->send_queue)))
  755. dev_kfree_skb(skb);
  756. printk(KERN_INFO "%s: close yam at iobase 0x%lx irq %u\n",
  757. yam_drvname, dev->base_addr, dev->irq);
  758. return 0;
  759. }
  760. /* --------------------------------------------------------------------- */
  761. static int yam_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  762. {
  763. struct yam_port *yp = netdev_priv(dev);
  764. struct yamdrv_ioctl_cfg yi;
  765. struct yamdrv_ioctl_mcs *ym;
  766. int ioctl_cmd;
  767. if (copy_from_user(&ioctl_cmd, ifr->ifr_data, sizeof(int)))
  768. return -EFAULT;
  769. if (yp->magic != YAM_MAGIC)
  770. return -EINVAL;
  771. if (!capable(CAP_NET_ADMIN))
  772. return -EPERM;
  773. if (cmd != SIOCDEVPRIVATE)
  774. return -EINVAL;
  775. switch (ioctl_cmd) {
  776. case SIOCYAMRESERVED:
  777. return -EINVAL; /* unused */
  778. case SIOCYAMSMCS:
  779. if (netif_running(dev))
  780. return -EINVAL; /* Cannot change this parameter when up */
  781. if ((ym = kmalloc(sizeof(struct yamdrv_ioctl_mcs), GFP_KERNEL)) == NULL)
  782. return -ENOBUFS;
  783. ym->bitrate = 9600;
  784. if (copy_from_user(ym, ifr->ifr_data, sizeof(struct yamdrv_ioctl_mcs))) {
  785. kfree(ym);
  786. return -EFAULT;
  787. }
  788. if (ym->bitrate > YAM_MAXBITRATE) {
  789. kfree(ym);
  790. return -EINVAL;
  791. }
  792. add_mcs(ym->bits, ym->bitrate);
  793. kfree(ym);
  794. break;
  795. case SIOCYAMSCFG:
  796. if (!capable(CAP_SYS_RAWIO))
  797. return -EPERM;
  798. if (copy_from_user(&yi, ifr->ifr_data, sizeof(struct yamdrv_ioctl_cfg)))
  799. return -EFAULT;
  800. if ((yi.cfg.mask & YAM_IOBASE) && netif_running(dev))
  801. return -EINVAL; /* Cannot change this parameter when up */
  802. if ((yi.cfg.mask & YAM_IRQ) && netif_running(dev))
  803. return -EINVAL; /* Cannot change this parameter when up */
  804. if ((yi.cfg.mask & YAM_BITRATE) && netif_running(dev))
  805. return -EINVAL; /* Cannot change this parameter when up */
  806. if ((yi.cfg.mask & YAM_BAUDRATE) && netif_running(dev))
  807. return -EINVAL; /* Cannot change this parameter when up */
  808. if (yi.cfg.mask & YAM_IOBASE) {
  809. yp->iobase = yi.cfg.iobase;
  810. dev->base_addr = yi.cfg.iobase;
  811. }
  812. if (yi.cfg.mask & YAM_IRQ) {
  813. if (yi.cfg.irq > 15)
  814. return -EINVAL;
  815. yp->irq = yi.cfg.irq;
  816. dev->irq = yi.cfg.irq;
  817. }
  818. if (yi.cfg.mask & YAM_BITRATE) {
  819. if (yi.cfg.bitrate > YAM_MAXBITRATE)
  820. return -EINVAL;
  821. yp->bitrate = yi.cfg.bitrate;
  822. }
  823. if (yi.cfg.mask & YAM_BAUDRATE) {
  824. if (yi.cfg.baudrate > YAM_MAXBAUDRATE)
  825. return -EINVAL;
  826. yp->baudrate = yi.cfg.baudrate;
  827. }
  828. if (yi.cfg.mask & YAM_MODE) {
  829. if (yi.cfg.mode > YAM_MAXMODE)
  830. return -EINVAL;
  831. yp->dupmode = yi.cfg.mode;
  832. }
  833. if (yi.cfg.mask & YAM_HOLDDLY) {
  834. if (yi.cfg.holddly > YAM_MAXHOLDDLY)
  835. return -EINVAL;
  836. yp->holdd = yi.cfg.holddly;
  837. }
  838. if (yi.cfg.mask & YAM_TXDELAY) {
  839. if (yi.cfg.txdelay > YAM_MAXTXDELAY)
  840. return -EINVAL;
  841. yp->txd = yi.cfg.txdelay;
  842. }
  843. if (yi.cfg.mask & YAM_TXTAIL) {
  844. if (yi.cfg.txtail > YAM_MAXTXTAIL)
  845. return -EINVAL;
  846. yp->txtail = yi.cfg.txtail;
  847. }
  848. if (yi.cfg.mask & YAM_PERSIST) {
  849. if (yi.cfg.persist > YAM_MAXPERSIST)
  850. return -EINVAL;
  851. yp->pers = yi.cfg.persist;
  852. }
  853. if (yi.cfg.mask & YAM_SLOTTIME) {
  854. if (yi.cfg.slottime > YAM_MAXSLOTTIME)
  855. return -EINVAL;
  856. yp->slot = yi.cfg.slottime;
  857. yp->slotcnt = yp->slot / 10;
  858. }
  859. break;
  860. case SIOCYAMGCFG:
  861. yi.cfg.mask = 0xffffffff;
  862. yi.cfg.iobase = yp->iobase;
  863. yi.cfg.irq = yp->irq;
  864. yi.cfg.bitrate = yp->bitrate;
  865. yi.cfg.baudrate = yp->baudrate;
  866. yi.cfg.mode = yp->dupmode;
  867. yi.cfg.txdelay = yp->txd;
  868. yi.cfg.holddly = yp->holdd;
  869. yi.cfg.txtail = yp->txtail;
  870. yi.cfg.persist = yp->pers;
  871. yi.cfg.slottime = yp->slot;
  872. if (copy_to_user(ifr->ifr_data, &yi, sizeof(struct yamdrv_ioctl_cfg)))
  873. return -EFAULT;
  874. break;
  875. default:
  876. return -EINVAL;
  877. }
  878. return 0;
  879. }
  880. /* --------------------------------------------------------------------- */
  881. static int yam_set_mac_address(struct net_device *dev, void *addr)
  882. {
  883. struct sockaddr *sa = (struct sockaddr *) addr;
  884. /* addr is an AX.25 shifted ASCII mac address */
  885. memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
  886. return 0;
  887. }
  888. /* --------------------------------------------------------------------- */
  889. static const struct net_device_ops yam_netdev_ops = {
  890. .ndo_open = yam_open,
  891. .ndo_stop = yam_close,
  892. .ndo_start_xmit = yam_send_packet,
  893. .ndo_do_ioctl = yam_ioctl,
  894. .ndo_set_mac_address = yam_set_mac_address,
  895. };
  896. static void yam_setup(struct net_device *dev)
  897. {
  898. struct yam_port *yp = netdev_priv(dev);
  899. yp->magic = YAM_MAGIC;
  900. yp->bitrate = DEFAULT_BITRATE;
  901. yp->baudrate = DEFAULT_BITRATE * 2;
  902. yp->iobase = 0;
  903. yp->irq = 0;
  904. yp->dupmode = 0;
  905. yp->holdd = DEFAULT_HOLDD;
  906. yp->txd = DEFAULT_TXD;
  907. yp->txtail = DEFAULT_TXTAIL;
  908. yp->slot = DEFAULT_SLOT;
  909. yp->pers = DEFAULT_PERS;
  910. yp->dev = dev;
  911. dev->base_addr = yp->iobase;
  912. dev->irq = yp->irq;
  913. skb_queue_head_init(&yp->send_queue);
  914. dev->netdev_ops = &yam_netdev_ops;
  915. dev->header_ops = &ax25_header_ops;
  916. dev->type = ARPHRD_AX25;
  917. dev->hard_header_len = AX25_MAX_HEADER_LEN;
  918. dev->mtu = AX25_MTU;
  919. dev->addr_len = AX25_ADDR_LEN;
  920. memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
  921. memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
  922. }
  923. static int __init yam_init_driver(void)
  924. {
  925. struct net_device *dev;
  926. int i, err;
  927. char name[IFNAMSIZ];
  928. printk(yam_drvinfo);
  929. for (i = 0; i < NR_PORTS; i++) {
  930. sprintf(name, "yam%d", i);
  931. dev = alloc_netdev(sizeof(struct yam_port), name,
  932. yam_setup);
  933. if (!dev) {
  934. printk(KERN_ERR "yam: cannot allocate net device %s\n",
  935. dev->name);
  936. err = -ENOMEM;
  937. goto error;
  938. }
  939. err = register_netdev(dev);
  940. if (err) {
  941. printk(KERN_WARNING "yam: cannot register net device %s\n", dev->name);
  942. goto error;
  943. }
  944. yam_devs[i] = dev;
  945. }
  946. yam_timer.function = yam_dotimer;
  947. yam_timer.expires = jiffies + HZ / 100;
  948. add_timer(&yam_timer);
  949. proc_net_fops_create(&init_net, "yam", S_IRUGO, &yam_info_fops);
  950. return 0;
  951. error:
  952. while (--i >= 0) {
  953. unregister_netdev(yam_devs[i]);
  954. free_netdev(yam_devs[i]);
  955. }
  956. return err;
  957. }
  958. /* --------------------------------------------------------------------- */
  959. static void __exit yam_cleanup_driver(void)
  960. {
  961. struct yam_mcs *p;
  962. int i;
  963. del_timer(&yam_timer);
  964. for (i = 0; i < NR_PORTS; i++) {
  965. struct net_device *dev = yam_devs[i];
  966. if (dev) {
  967. unregister_netdev(dev);
  968. free_netdev(dev);
  969. }
  970. }
  971. while (yam_data) {
  972. p = yam_data;
  973. yam_data = yam_data->next;
  974. kfree(p);
  975. }
  976. proc_net_remove(&init_net, "yam");
  977. }
  978. /* --------------------------------------------------------------------- */
  979. MODULE_AUTHOR("Frederic Rible F1OAT frible@teaser.fr");
  980. MODULE_DESCRIPTION("Yam amateur radio modem driver");
  981. MODULE_LICENSE("GPL");
  982. module_init(yam_init_driver);
  983. module_exit(yam_cleanup_driver);
  984. /* --------------------------------------------------------------------- */