intel_dp.c 71 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Keith Packard <keithp@keithp.com>
  25. *
  26. */
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <linux/export.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "drm_crtc.h"
  33. #include "drm_crtc_helper.h"
  34. #include "drm_edid.h"
  35. #include "intel_drv.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #define DP_RECEIVER_CAP_SIZE 0xf
  39. #define DP_LINK_STATUS_SIZE 6
  40. #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
  41. /**
  42. * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43. * @intel_dp: DP struct
  44. *
  45. * If a CPU or PCH DP output is attached to an eDP panel, this function
  46. * will return true, and false otherwise.
  47. */
  48. static bool is_edp(struct intel_dp *intel_dp)
  49. {
  50. return intel_dp->base.type == INTEL_OUTPUT_EDP;
  51. }
  52. /**
  53. * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  54. * @intel_dp: DP struct
  55. *
  56. * Returns true if the given DP struct corresponds to a PCH DP port attached
  57. * to an eDP panel, false otherwise. Helpful for determining whether we
  58. * may need FDI resources for a given DP output or not.
  59. */
  60. static bool is_pch_edp(struct intel_dp *intel_dp)
  61. {
  62. return intel_dp->is_pch_edp;
  63. }
  64. /**
  65. * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  66. * @intel_dp: DP struct
  67. *
  68. * Returns true if the given DP struct corresponds to a CPU eDP port.
  69. */
  70. static bool is_cpu_edp(struct intel_dp *intel_dp)
  71. {
  72. return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  73. }
  74. static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  75. {
  76. return container_of(encoder, struct intel_dp, base.base);
  77. }
  78. static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  79. {
  80. return container_of(intel_attached_encoder(connector),
  81. struct intel_dp, base);
  82. }
  83. /**
  84. * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  85. * @encoder: DRM encoder
  86. *
  87. * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
  88. * by intel_display.c.
  89. */
  90. bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  91. {
  92. struct intel_dp *intel_dp;
  93. if (!encoder)
  94. return false;
  95. intel_dp = enc_to_intel_dp(encoder);
  96. return is_pch_edp(intel_dp);
  97. }
  98. static void intel_dp_start_link_train(struct intel_dp *intel_dp);
  99. static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  100. static void intel_dp_link_down(struct intel_dp *intel_dp);
  101. void
  102. intel_edp_link_config(struct intel_encoder *intel_encoder,
  103. int *lane_num, int *link_bw)
  104. {
  105. struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
  106. *lane_num = intel_dp->lane_count;
  107. if (intel_dp->link_bw == DP_LINK_BW_1_62)
  108. *link_bw = 162000;
  109. else if (intel_dp->link_bw == DP_LINK_BW_2_7)
  110. *link_bw = 270000;
  111. }
  112. int
  113. intel_edp_target_clock(struct intel_encoder *intel_encoder,
  114. struct drm_display_mode *mode)
  115. {
  116. struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
  117. if (intel_dp->panel_fixed_mode)
  118. return intel_dp->panel_fixed_mode->clock;
  119. else
  120. return mode->clock;
  121. }
  122. static int
  123. intel_dp_max_lane_count(struct intel_dp *intel_dp)
  124. {
  125. int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
  126. switch (max_lane_count) {
  127. case 1: case 2: case 4:
  128. break;
  129. default:
  130. max_lane_count = 4;
  131. }
  132. return max_lane_count;
  133. }
  134. static int
  135. intel_dp_max_link_bw(struct intel_dp *intel_dp)
  136. {
  137. int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  138. switch (max_link_bw) {
  139. case DP_LINK_BW_1_62:
  140. case DP_LINK_BW_2_7:
  141. break;
  142. default:
  143. max_link_bw = DP_LINK_BW_1_62;
  144. break;
  145. }
  146. return max_link_bw;
  147. }
  148. static int
  149. intel_dp_link_clock(uint8_t link_bw)
  150. {
  151. if (link_bw == DP_LINK_BW_2_7)
  152. return 270000;
  153. else
  154. return 162000;
  155. }
  156. /*
  157. * The units on the numbers in the next two are... bizarre. Examples will
  158. * make it clearer; this one parallels an example in the eDP spec.
  159. *
  160. * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
  161. *
  162. * 270000 * 1 * 8 / 10 == 216000
  163. *
  164. * The actual data capacity of that configuration is 2.16Gbit/s, so the
  165. * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
  166. * or equivalently, kilopixels per second - so for 1680x1050R it'd be
  167. * 119000. At 18bpp that's 2142000 kilobits per second.
  168. *
  169. * Thus the strange-looking division by 10 in intel_dp_link_required, to
  170. * get the result in decakilobits instead of kilobits.
  171. */
  172. static int
  173. intel_dp_link_required(int pixel_clock, int bpp)
  174. {
  175. return (pixel_clock * bpp + 9) / 10;
  176. }
  177. static int
  178. intel_dp_max_data_rate(int max_link_clock, int max_lanes)
  179. {
  180. return (max_link_clock * max_lanes * 8) / 10;
  181. }
  182. static bool
  183. intel_dp_adjust_dithering(struct intel_dp *intel_dp,
  184. struct drm_display_mode *mode,
  185. bool adjust_mode)
  186. {
  187. int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
  188. int max_lanes = intel_dp_max_lane_count(intel_dp);
  189. int max_rate, mode_rate;
  190. mode_rate = intel_dp_link_required(mode->clock, 24);
  191. max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
  192. if (mode_rate > max_rate) {
  193. mode_rate = intel_dp_link_required(mode->clock, 18);
  194. if (mode_rate > max_rate)
  195. return false;
  196. if (adjust_mode)
  197. mode->private_flags
  198. |= INTEL_MODE_DP_FORCE_6BPC;
  199. return true;
  200. }
  201. return true;
  202. }
  203. static int
  204. intel_dp_mode_valid(struct drm_connector *connector,
  205. struct drm_display_mode *mode)
  206. {
  207. struct intel_dp *intel_dp = intel_attached_dp(connector);
  208. if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
  209. if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
  210. return MODE_PANEL;
  211. if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
  212. return MODE_PANEL;
  213. }
  214. if (!intel_dp_adjust_dithering(intel_dp, mode, false))
  215. return MODE_CLOCK_HIGH;
  216. if (mode->clock < 10000)
  217. return MODE_CLOCK_LOW;
  218. if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  219. return MODE_H_ILLEGAL;
  220. return MODE_OK;
  221. }
  222. static uint32_t
  223. pack_aux(uint8_t *src, int src_bytes)
  224. {
  225. int i;
  226. uint32_t v = 0;
  227. if (src_bytes > 4)
  228. src_bytes = 4;
  229. for (i = 0; i < src_bytes; i++)
  230. v |= ((uint32_t) src[i]) << ((3-i) * 8);
  231. return v;
  232. }
  233. static void
  234. unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
  235. {
  236. int i;
  237. if (dst_bytes > 4)
  238. dst_bytes = 4;
  239. for (i = 0; i < dst_bytes; i++)
  240. dst[i] = src >> ((3-i) * 8);
  241. }
  242. /* hrawclock is 1/4 the FSB frequency */
  243. static int
  244. intel_hrawclk(struct drm_device *dev)
  245. {
  246. struct drm_i915_private *dev_priv = dev->dev_private;
  247. uint32_t clkcfg;
  248. clkcfg = I915_READ(CLKCFG);
  249. switch (clkcfg & CLKCFG_FSB_MASK) {
  250. case CLKCFG_FSB_400:
  251. return 100;
  252. case CLKCFG_FSB_533:
  253. return 133;
  254. case CLKCFG_FSB_667:
  255. return 166;
  256. case CLKCFG_FSB_800:
  257. return 200;
  258. case CLKCFG_FSB_1067:
  259. return 266;
  260. case CLKCFG_FSB_1333:
  261. return 333;
  262. /* these two are just a guess; one of them might be right */
  263. case CLKCFG_FSB_1600:
  264. case CLKCFG_FSB_1600_ALT:
  265. return 400;
  266. default:
  267. return 133;
  268. }
  269. }
  270. static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
  271. {
  272. struct drm_device *dev = intel_dp->base.base.dev;
  273. struct drm_i915_private *dev_priv = dev->dev_private;
  274. return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
  275. }
  276. static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
  277. {
  278. struct drm_device *dev = intel_dp->base.base.dev;
  279. struct drm_i915_private *dev_priv = dev->dev_private;
  280. return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
  281. }
  282. static void
  283. intel_dp_check_edp(struct intel_dp *intel_dp)
  284. {
  285. struct drm_device *dev = intel_dp->base.base.dev;
  286. struct drm_i915_private *dev_priv = dev->dev_private;
  287. if (!is_edp(intel_dp))
  288. return;
  289. if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
  290. WARN(1, "eDP powered off while attempting aux channel communication.\n");
  291. DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
  292. I915_READ(PCH_PP_STATUS),
  293. I915_READ(PCH_PP_CONTROL));
  294. }
  295. }
  296. static int
  297. intel_dp_aux_ch(struct intel_dp *intel_dp,
  298. uint8_t *send, int send_bytes,
  299. uint8_t *recv, int recv_size)
  300. {
  301. uint32_t output_reg = intel_dp->output_reg;
  302. struct drm_device *dev = intel_dp->base.base.dev;
  303. struct drm_i915_private *dev_priv = dev->dev_private;
  304. uint32_t ch_ctl = output_reg + 0x10;
  305. uint32_t ch_data = ch_ctl + 4;
  306. int i;
  307. int recv_bytes;
  308. uint32_t status;
  309. uint32_t aux_clock_divider;
  310. int try, precharge;
  311. intel_dp_check_edp(intel_dp);
  312. /* The clock divider is based off the hrawclk,
  313. * and would like to run at 2MHz. So, take the
  314. * hrawclk value and divide by 2 and use that
  315. *
  316. * Note that PCH attached eDP panels should use a 125MHz input
  317. * clock divider.
  318. */
  319. if (is_cpu_edp(intel_dp)) {
  320. if (IS_GEN6(dev) || IS_GEN7(dev))
  321. aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
  322. else
  323. aux_clock_divider = 225; /* eDP input clock at 450Mhz */
  324. } else if (HAS_PCH_SPLIT(dev))
  325. aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
  326. else
  327. aux_clock_divider = intel_hrawclk(dev) / 2;
  328. if (IS_GEN6(dev))
  329. precharge = 3;
  330. else
  331. precharge = 5;
  332. /* Try to wait for any previous AUX channel activity */
  333. for (try = 0; try < 3; try++) {
  334. status = I915_READ(ch_ctl);
  335. if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  336. break;
  337. msleep(1);
  338. }
  339. if (try == 3) {
  340. WARN(1, "dp_aux_ch not started status 0x%08x\n",
  341. I915_READ(ch_ctl));
  342. return -EBUSY;
  343. }
  344. /* Must try at least 3 times according to DP spec */
  345. for (try = 0; try < 5; try++) {
  346. /* Load the send data into the aux channel data registers */
  347. for (i = 0; i < send_bytes; i += 4)
  348. I915_WRITE(ch_data + i,
  349. pack_aux(send + i, send_bytes - i));
  350. /* Send the command and wait for it to complete */
  351. I915_WRITE(ch_ctl,
  352. DP_AUX_CH_CTL_SEND_BUSY |
  353. DP_AUX_CH_CTL_TIME_OUT_400us |
  354. (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
  355. (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
  356. (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
  357. DP_AUX_CH_CTL_DONE |
  358. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  359. DP_AUX_CH_CTL_RECEIVE_ERROR);
  360. for (;;) {
  361. status = I915_READ(ch_ctl);
  362. if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  363. break;
  364. udelay(100);
  365. }
  366. /* Clear done status and any errors */
  367. I915_WRITE(ch_ctl,
  368. status |
  369. DP_AUX_CH_CTL_DONE |
  370. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  371. DP_AUX_CH_CTL_RECEIVE_ERROR);
  372. if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
  373. DP_AUX_CH_CTL_RECEIVE_ERROR))
  374. continue;
  375. if (status & DP_AUX_CH_CTL_DONE)
  376. break;
  377. }
  378. if ((status & DP_AUX_CH_CTL_DONE) == 0) {
  379. DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
  380. return -EBUSY;
  381. }
  382. /* Check for timeout or receive error.
  383. * Timeouts occur when the sink is not connected
  384. */
  385. if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
  386. DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
  387. return -EIO;
  388. }
  389. /* Timeouts occur when the device isn't connected, so they're
  390. * "normal" -- don't fill the kernel log with these */
  391. if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
  392. DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
  393. return -ETIMEDOUT;
  394. }
  395. /* Unload any bytes sent back from the other side */
  396. recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
  397. DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
  398. if (recv_bytes > recv_size)
  399. recv_bytes = recv_size;
  400. for (i = 0; i < recv_bytes; i += 4)
  401. unpack_aux(I915_READ(ch_data + i),
  402. recv + i, recv_bytes - i);
  403. return recv_bytes;
  404. }
  405. /* Write data to the aux channel in native mode */
  406. static int
  407. intel_dp_aux_native_write(struct intel_dp *intel_dp,
  408. uint16_t address, uint8_t *send, int send_bytes)
  409. {
  410. int ret;
  411. uint8_t msg[20];
  412. int msg_bytes;
  413. uint8_t ack;
  414. intel_dp_check_edp(intel_dp);
  415. if (send_bytes > 16)
  416. return -1;
  417. msg[0] = AUX_NATIVE_WRITE << 4;
  418. msg[1] = address >> 8;
  419. msg[2] = address & 0xff;
  420. msg[3] = send_bytes - 1;
  421. memcpy(&msg[4], send, send_bytes);
  422. msg_bytes = send_bytes + 4;
  423. for (;;) {
  424. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
  425. if (ret < 0)
  426. return ret;
  427. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
  428. break;
  429. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  430. udelay(100);
  431. else
  432. return -EIO;
  433. }
  434. return send_bytes;
  435. }
  436. /* Write a single byte to the aux channel in native mode */
  437. static int
  438. intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
  439. uint16_t address, uint8_t byte)
  440. {
  441. return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
  442. }
  443. /* read bytes from a native aux channel */
  444. static int
  445. intel_dp_aux_native_read(struct intel_dp *intel_dp,
  446. uint16_t address, uint8_t *recv, int recv_bytes)
  447. {
  448. uint8_t msg[4];
  449. int msg_bytes;
  450. uint8_t reply[20];
  451. int reply_bytes;
  452. uint8_t ack;
  453. int ret;
  454. intel_dp_check_edp(intel_dp);
  455. msg[0] = AUX_NATIVE_READ << 4;
  456. msg[1] = address >> 8;
  457. msg[2] = address & 0xff;
  458. msg[3] = recv_bytes - 1;
  459. msg_bytes = 4;
  460. reply_bytes = recv_bytes + 1;
  461. for (;;) {
  462. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
  463. reply, reply_bytes);
  464. if (ret == 0)
  465. return -EPROTO;
  466. if (ret < 0)
  467. return ret;
  468. ack = reply[0];
  469. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
  470. memcpy(recv, reply + 1, ret - 1);
  471. return ret - 1;
  472. }
  473. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  474. udelay(100);
  475. else
  476. return -EIO;
  477. }
  478. }
  479. static int
  480. intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
  481. uint8_t write_byte, uint8_t *read_byte)
  482. {
  483. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  484. struct intel_dp *intel_dp = container_of(adapter,
  485. struct intel_dp,
  486. adapter);
  487. uint16_t address = algo_data->address;
  488. uint8_t msg[5];
  489. uint8_t reply[2];
  490. unsigned retry;
  491. int msg_bytes;
  492. int reply_bytes;
  493. int ret;
  494. intel_dp_check_edp(intel_dp);
  495. /* Set up the command byte */
  496. if (mode & MODE_I2C_READ)
  497. msg[0] = AUX_I2C_READ << 4;
  498. else
  499. msg[0] = AUX_I2C_WRITE << 4;
  500. if (!(mode & MODE_I2C_STOP))
  501. msg[0] |= AUX_I2C_MOT << 4;
  502. msg[1] = address >> 8;
  503. msg[2] = address;
  504. switch (mode) {
  505. case MODE_I2C_WRITE:
  506. msg[3] = 0;
  507. msg[4] = write_byte;
  508. msg_bytes = 5;
  509. reply_bytes = 1;
  510. break;
  511. case MODE_I2C_READ:
  512. msg[3] = 0;
  513. msg_bytes = 4;
  514. reply_bytes = 2;
  515. break;
  516. default:
  517. msg_bytes = 3;
  518. reply_bytes = 1;
  519. break;
  520. }
  521. for (retry = 0; retry < 5; retry++) {
  522. ret = intel_dp_aux_ch(intel_dp,
  523. msg, msg_bytes,
  524. reply, reply_bytes);
  525. if (ret < 0) {
  526. DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
  527. return ret;
  528. }
  529. switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
  530. case AUX_NATIVE_REPLY_ACK:
  531. /* I2C-over-AUX Reply field is only valid
  532. * when paired with AUX ACK.
  533. */
  534. break;
  535. case AUX_NATIVE_REPLY_NACK:
  536. DRM_DEBUG_KMS("aux_ch native nack\n");
  537. return -EREMOTEIO;
  538. case AUX_NATIVE_REPLY_DEFER:
  539. udelay(100);
  540. continue;
  541. default:
  542. DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
  543. reply[0]);
  544. return -EREMOTEIO;
  545. }
  546. switch (reply[0] & AUX_I2C_REPLY_MASK) {
  547. case AUX_I2C_REPLY_ACK:
  548. if (mode == MODE_I2C_READ) {
  549. *read_byte = reply[1];
  550. }
  551. return reply_bytes - 1;
  552. case AUX_I2C_REPLY_NACK:
  553. DRM_DEBUG_KMS("aux_i2c nack\n");
  554. return -EREMOTEIO;
  555. case AUX_I2C_REPLY_DEFER:
  556. DRM_DEBUG_KMS("aux_i2c defer\n");
  557. udelay(100);
  558. break;
  559. default:
  560. DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
  561. return -EREMOTEIO;
  562. }
  563. }
  564. DRM_ERROR("too many retries, giving up\n");
  565. return -EREMOTEIO;
  566. }
  567. static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
  568. static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  569. static int
  570. intel_dp_i2c_init(struct intel_dp *intel_dp,
  571. struct intel_connector *intel_connector, const char *name)
  572. {
  573. int ret;
  574. DRM_DEBUG_KMS("i2c_init %s\n", name);
  575. intel_dp->algo.running = false;
  576. intel_dp->algo.address = 0;
  577. intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
  578. memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
  579. intel_dp->adapter.owner = THIS_MODULE;
  580. intel_dp->adapter.class = I2C_CLASS_DDC;
  581. strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
  582. intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
  583. intel_dp->adapter.algo_data = &intel_dp->algo;
  584. intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
  585. ironlake_edp_panel_vdd_on(intel_dp);
  586. ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
  587. ironlake_edp_panel_vdd_off(intel_dp, false);
  588. return ret;
  589. }
  590. static bool
  591. intel_dp_mode_fixup(struct drm_encoder *encoder,
  592. const struct drm_display_mode *mode,
  593. struct drm_display_mode *adjusted_mode)
  594. {
  595. struct drm_device *dev = encoder->dev;
  596. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  597. int lane_count, clock;
  598. int max_lane_count = intel_dp_max_lane_count(intel_dp);
  599. int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
  600. int bpp, mode_rate;
  601. static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
  602. if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
  603. intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
  604. intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
  605. mode, adjusted_mode);
  606. }
  607. if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  608. return false;
  609. DRM_DEBUG_KMS("DP link computation with max lane count %i "
  610. "max bw %02x pixel clock %iKHz\n",
  611. max_lane_count, bws[max_clock], adjusted_mode->clock);
  612. if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
  613. return false;
  614. bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
  615. mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
  616. for (clock = 0; clock <= max_clock; clock++) {
  617. for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
  618. int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
  619. if (mode_rate <= link_avail) {
  620. intel_dp->link_bw = bws[clock];
  621. intel_dp->lane_count = lane_count;
  622. adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
  623. DRM_DEBUG_KMS("DP link bw %02x lane "
  624. "count %d clock %d bpp %d\n",
  625. intel_dp->link_bw, intel_dp->lane_count,
  626. adjusted_mode->clock, bpp);
  627. DRM_DEBUG_KMS("DP link bw required %i available %i\n",
  628. mode_rate, link_avail);
  629. return true;
  630. }
  631. }
  632. }
  633. return false;
  634. }
  635. struct intel_dp_m_n {
  636. uint32_t tu;
  637. uint32_t gmch_m;
  638. uint32_t gmch_n;
  639. uint32_t link_m;
  640. uint32_t link_n;
  641. };
  642. static void
  643. intel_reduce_ratio(uint32_t *num, uint32_t *den)
  644. {
  645. while (*num > 0xffffff || *den > 0xffffff) {
  646. *num >>= 1;
  647. *den >>= 1;
  648. }
  649. }
  650. static void
  651. intel_dp_compute_m_n(int bpp,
  652. int nlanes,
  653. int pixel_clock,
  654. int link_clock,
  655. struct intel_dp_m_n *m_n)
  656. {
  657. m_n->tu = 64;
  658. m_n->gmch_m = (pixel_clock * bpp) >> 3;
  659. m_n->gmch_n = link_clock * nlanes;
  660. intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  661. m_n->link_m = pixel_clock;
  662. m_n->link_n = link_clock;
  663. intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
  664. }
  665. void
  666. intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
  667. struct drm_display_mode *adjusted_mode)
  668. {
  669. struct drm_device *dev = crtc->dev;
  670. struct intel_encoder *encoder;
  671. struct drm_i915_private *dev_priv = dev->dev_private;
  672. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  673. int lane_count = 4;
  674. struct intel_dp_m_n m_n;
  675. int pipe = intel_crtc->pipe;
  676. /*
  677. * Find the lane count in the intel_encoder private
  678. */
  679. for_each_encoder_on_crtc(dev, crtc, encoder) {
  680. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  681. if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
  682. intel_dp->base.type == INTEL_OUTPUT_EDP)
  683. {
  684. lane_count = intel_dp->lane_count;
  685. break;
  686. }
  687. }
  688. /*
  689. * Compute the GMCH and Link ratios. The '3' here is
  690. * the number of bytes_per_pixel post-LUT, which we always
  691. * set up for 8-bits of R/G/B, or 3 bytes total.
  692. */
  693. intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
  694. mode->clock, adjusted_mode->clock, &m_n);
  695. if (HAS_PCH_SPLIT(dev)) {
  696. I915_WRITE(TRANSDATA_M1(pipe),
  697. ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
  698. m_n.gmch_m);
  699. I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
  700. I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
  701. I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
  702. } else {
  703. I915_WRITE(PIPE_GMCH_DATA_M(pipe),
  704. ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
  705. m_n.gmch_m);
  706. I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
  707. I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
  708. I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
  709. }
  710. }
  711. static void
  712. intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
  713. struct drm_display_mode *adjusted_mode)
  714. {
  715. struct drm_device *dev = encoder->dev;
  716. struct drm_i915_private *dev_priv = dev->dev_private;
  717. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  718. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  719. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  720. /*
  721. * There are four kinds of DP registers:
  722. *
  723. * IBX PCH
  724. * SNB CPU
  725. * IVB CPU
  726. * CPT PCH
  727. *
  728. * IBX PCH and CPU are the same for almost everything,
  729. * except that the CPU DP PLL is configured in this
  730. * register
  731. *
  732. * CPT PCH is quite different, having many bits moved
  733. * to the TRANS_DP_CTL register instead. That
  734. * configuration happens (oddly) in ironlake_pch_enable
  735. */
  736. /* Preserve the BIOS-computed detected bit. This is
  737. * supposed to be read-only.
  738. */
  739. intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
  740. /* Handle DP bits in common between all three register formats */
  741. intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  742. switch (intel_dp->lane_count) {
  743. case 1:
  744. intel_dp->DP |= DP_PORT_WIDTH_1;
  745. break;
  746. case 2:
  747. intel_dp->DP |= DP_PORT_WIDTH_2;
  748. break;
  749. case 4:
  750. intel_dp->DP |= DP_PORT_WIDTH_4;
  751. break;
  752. }
  753. if (intel_dp->has_audio) {
  754. DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
  755. pipe_name(intel_crtc->pipe));
  756. intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
  757. intel_write_eld(encoder, adjusted_mode);
  758. }
  759. memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
  760. intel_dp->link_configuration[0] = intel_dp->link_bw;
  761. intel_dp->link_configuration[1] = intel_dp->lane_count;
  762. intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
  763. /*
  764. * Check for DPCD version > 1.1 and enhanced framing support
  765. */
  766. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  767. (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
  768. intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  769. }
  770. /* Split out the IBX/CPU vs CPT settings */
  771. if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
  772. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  773. intel_dp->DP |= DP_SYNC_HS_HIGH;
  774. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  775. intel_dp->DP |= DP_SYNC_VS_HIGH;
  776. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  777. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  778. intel_dp->DP |= DP_ENHANCED_FRAMING;
  779. intel_dp->DP |= intel_crtc->pipe << 29;
  780. /* don't miss out required setting for eDP */
  781. if (adjusted_mode->clock < 200000)
  782. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  783. else
  784. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  785. } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
  786. intel_dp->DP |= intel_dp->color_range;
  787. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  788. intel_dp->DP |= DP_SYNC_HS_HIGH;
  789. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  790. intel_dp->DP |= DP_SYNC_VS_HIGH;
  791. intel_dp->DP |= DP_LINK_TRAIN_OFF;
  792. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  793. intel_dp->DP |= DP_ENHANCED_FRAMING;
  794. if (intel_crtc->pipe == 1)
  795. intel_dp->DP |= DP_PIPEB_SELECT;
  796. if (is_cpu_edp(intel_dp)) {
  797. /* don't miss out required setting for eDP */
  798. if (adjusted_mode->clock < 200000)
  799. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  800. else
  801. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  802. }
  803. } else {
  804. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  805. }
  806. }
  807. #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  808. #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
  809. #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  810. #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  811. #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
  812. #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  813. static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
  814. u32 mask,
  815. u32 value)
  816. {
  817. struct drm_device *dev = intel_dp->base.base.dev;
  818. struct drm_i915_private *dev_priv = dev->dev_private;
  819. DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
  820. mask, value,
  821. I915_READ(PCH_PP_STATUS),
  822. I915_READ(PCH_PP_CONTROL));
  823. if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
  824. DRM_ERROR("Panel status timeout: status %08x control %08x\n",
  825. I915_READ(PCH_PP_STATUS),
  826. I915_READ(PCH_PP_CONTROL));
  827. }
  828. }
  829. static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
  830. {
  831. DRM_DEBUG_KMS("Wait for panel power on\n");
  832. ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
  833. }
  834. static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
  835. {
  836. DRM_DEBUG_KMS("Wait for panel power off time\n");
  837. ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
  838. }
  839. static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
  840. {
  841. DRM_DEBUG_KMS("Wait for panel power cycle\n");
  842. ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
  843. }
  844. /* Read the current pp_control value, unlocking the register if it
  845. * is locked
  846. */
  847. static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
  848. {
  849. u32 control = I915_READ(PCH_PP_CONTROL);
  850. control &= ~PANEL_UNLOCK_MASK;
  851. control |= PANEL_UNLOCK_REGS;
  852. return control;
  853. }
  854. static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
  855. {
  856. struct drm_device *dev = intel_dp->base.base.dev;
  857. struct drm_i915_private *dev_priv = dev->dev_private;
  858. u32 pp;
  859. if (!is_edp(intel_dp))
  860. return;
  861. DRM_DEBUG_KMS("Turn eDP VDD on\n");
  862. WARN(intel_dp->want_panel_vdd,
  863. "eDP VDD already requested on\n");
  864. intel_dp->want_panel_vdd = true;
  865. if (ironlake_edp_have_panel_vdd(intel_dp)) {
  866. DRM_DEBUG_KMS("eDP VDD already on\n");
  867. return;
  868. }
  869. if (!ironlake_edp_have_panel_power(intel_dp))
  870. ironlake_wait_panel_power_cycle(intel_dp);
  871. pp = ironlake_get_pp_control(dev_priv);
  872. pp |= EDP_FORCE_VDD;
  873. I915_WRITE(PCH_PP_CONTROL, pp);
  874. POSTING_READ(PCH_PP_CONTROL);
  875. DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
  876. I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
  877. /*
  878. * If the panel wasn't on, delay before accessing aux channel
  879. */
  880. if (!ironlake_edp_have_panel_power(intel_dp)) {
  881. DRM_DEBUG_KMS("eDP was not running\n");
  882. msleep(intel_dp->panel_power_up_delay);
  883. }
  884. }
  885. static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
  886. {
  887. struct drm_device *dev = intel_dp->base.base.dev;
  888. struct drm_i915_private *dev_priv = dev->dev_private;
  889. u32 pp;
  890. if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
  891. pp = ironlake_get_pp_control(dev_priv);
  892. pp &= ~EDP_FORCE_VDD;
  893. I915_WRITE(PCH_PP_CONTROL, pp);
  894. POSTING_READ(PCH_PP_CONTROL);
  895. /* Make sure sequencer is idle before allowing subsequent activity */
  896. DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
  897. I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
  898. msleep(intel_dp->panel_power_down_delay);
  899. }
  900. }
  901. static void ironlake_panel_vdd_work(struct work_struct *__work)
  902. {
  903. struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
  904. struct intel_dp, panel_vdd_work);
  905. struct drm_device *dev = intel_dp->base.base.dev;
  906. mutex_lock(&dev->mode_config.mutex);
  907. ironlake_panel_vdd_off_sync(intel_dp);
  908. mutex_unlock(&dev->mode_config.mutex);
  909. }
  910. static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
  911. {
  912. if (!is_edp(intel_dp))
  913. return;
  914. DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
  915. WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
  916. intel_dp->want_panel_vdd = false;
  917. if (sync) {
  918. ironlake_panel_vdd_off_sync(intel_dp);
  919. } else {
  920. /*
  921. * Queue the timer to fire a long
  922. * time from now (relative to the power down delay)
  923. * to keep the panel power up across a sequence of operations
  924. */
  925. schedule_delayed_work(&intel_dp->panel_vdd_work,
  926. msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
  927. }
  928. }
  929. static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
  930. {
  931. struct drm_device *dev = intel_dp->base.base.dev;
  932. struct drm_i915_private *dev_priv = dev->dev_private;
  933. u32 pp;
  934. if (!is_edp(intel_dp))
  935. return;
  936. DRM_DEBUG_KMS("Turn eDP power on\n");
  937. if (ironlake_edp_have_panel_power(intel_dp)) {
  938. DRM_DEBUG_KMS("eDP power already on\n");
  939. return;
  940. }
  941. ironlake_wait_panel_power_cycle(intel_dp);
  942. pp = ironlake_get_pp_control(dev_priv);
  943. if (IS_GEN5(dev)) {
  944. /* ILK workaround: disable reset around power sequence */
  945. pp &= ~PANEL_POWER_RESET;
  946. I915_WRITE(PCH_PP_CONTROL, pp);
  947. POSTING_READ(PCH_PP_CONTROL);
  948. }
  949. pp |= POWER_TARGET_ON;
  950. if (!IS_GEN5(dev))
  951. pp |= PANEL_POWER_RESET;
  952. I915_WRITE(PCH_PP_CONTROL, pp);
  953. POSTING_READ(PCH_PP_CONTROL);
  954. ironlake_wait_panel_on(intel_dp);
  955. if (IS_GEN5(dev)) {
  956. pp |= PANEL_POWER_RESET; /* restore panel reset bit */
  957. I915_WRITE(PCH_PP_CONTROL, pp);
  958. POSTING_READ(PCH_PP_CONTROL);
  959. }
  960. }
  961. static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
  962. {
  963. struct drm_device *dev = intel_dp->base.base.dev;
  964. struct drm_i915_private *dev_priv = dev->dev_private;
  965. u32 pp;
  966. if (!is_edp(intel_dp))
  967. return;
  968. DRM_DEBUG_KMS("Turn eDP power off\n");
  969. WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
  970. pp = ironlake_get_pp_control(dev_priv);
  971. /* We need to switch off panel power _and_ force vdd, for otherwise some
  972. * panels get very unhappy and cease to work. */
  973. pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
  974. I915_WRITE(PCH_PP_CONTROL, pp);
  975. POSTING_READ(PCH_PP_CONTROL);
  976. intel_dp->want_panel_vdd = false;
  977. ironlake_wait_panel_off(intel_dp);
  978. }
  979. static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
  980. {
  981. struct drm_device *dev = intel_dp->base.base.dev;
  982. struct drm_i915_private *dev_priv = dev->dev_private;
  983. u32 pp;
  984. if (!is_edp(intel_dp))
  985. return;
  986. DRM_DEBUG_KMS("\n");
  987. /*
  988. * If we enable the backlight right away following a panel power
  989. * on, we may see slight flicker as the panel syncs with the eDP
  990. * link. So delay a bit to make sure the image is solid before
  991. * allowing it to appear.
  992. */
  993. msleep(intel_dp->backlight_on_delay);
  994. pp = ironlake_get_pp_control(dev_priv);
  995. pp |= EDP_BLC_ENABLE;
  996. I915_WRITE(PCH_PP_CONTROL, pp);
  997. POSTING_READ(PCH_PP_CONTROL);
  998. }
  999. static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
  1000. {
  1001. struct drm_device *dev = intel_dp->base.base.dev;
  1002. struct drm_i915_private *dev_priv = dev->dev_private;
  1003. u32 pp;
  1004. if (!is_edp(intel_dp))
  1005. return;
  1006. DRM_DEBUG_KMS("\n");
  1007. pp = ironlake_get_pp_control(dev_priv);
  1008. pp &= ~EDP_BLC_ENABLE;
  1009. I915_WRITE(PCH_PP_CONTROL, pp);
  1010. POSTING_READ(PCH_PP_CONTROL);
  1011. msleep(intel_dp->backlight_off_delay);
  1012. }
  1013. static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
  1014. {
  1015. struct drm_device *dev = intel_dp->base.base.dev;
  1016. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  1017. struct drm_i915_private *dev_priv = dev->dev_private;
  1018. u32 dpa_ctl;
  1019. assert_pipe_disabled(dev_priv,
  1020. to_intel_crtc(crtc)->pipe);
  1021. DRM_DEBUG_KMS("\n");
  1022. dpa_ctl = I915_READ(DP_A);
  1023. WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
  1024. WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
  1025. /* We don't adjust intel_dp->DP while tearing down the link, to
  1026. * facilitate link retraining (e.g. after hotplug). Hence clear all
  1027. * enable bits here to ensure that we don't enable too much. */
  1028. intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
  1029. intel_dp->DP |= DP_PLL_ENABLE;
  1030. I915_WRITE(DP_A, intel_dp->DP);
  1031. POSTING_READ(DP_A);
  1032. udelay(200);
  1033. }
  1034. static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
  1035. {
  1036. struct drm_device *dev = intel_dp->base.base.dev;
  1037. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  1038. struct drm_i915_private *dev_priv = dev->dev_private;
  1039. u32 dpa_ctl;
  1040. assert_pipe_disabled(dev_priv,
  1041. to_intel_crtc(crtc)->pipe);
  1042. dpa_ctl = I915_READ(DP_A);
  1043. WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
  1044. "dp pll off, should be on\n");
  1045. WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
  1046. /* We can't rely on the value tracked for the DP register in
  1047. * intel_dp->DP because link_down must not change that (otherwise link
  1048. * re-training will fail. */
  1049. dpa_ctl &= ~DP_PLL_ENABLE;
  1050. I915_WRITE(DP_A, dpa_ctl);
  1051. POSTING_READ(DP_A);
  1052. udelay(200);
  1053. }
  1054. /* If the sink supports it, try to set the power state appropriately */
  1055. static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
  1056. {
  1057. int ret, i;
  1058. /* Should have a valid DPCD by this point */
  1059. if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
  1060. return;
  1061. if (mode != DRM_MODE_DPMS_ON) {
  1062. ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
  1063. DP_SET_POWER_D3);
  1064. if (ret != 1)
  1065. DRM_DEBUG_DRIVER("failed to write sink power state\n");
  1066. } else {
  1067. /*
  1068. * When turning on, we need to retry for 1ms to give the sink
  1069. * time to wake up.
  1070. */
  1071. for (i = 0; i < 3; i++) {
  1072. ret = intel_dp_aux_native_write_1(intel_dp,
  1073. DP_SET_POWER,
  1074. DP_SET_POWER_D0);
  1075. if (ret == 1)
  1076. break;
  1077. msleep(1);
  1078. }
  1079. }
  1080. }
  1081. static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
  1082. enum pipe *pipe)
  1083. {
  1084. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1085. struct drm_device *dev = encoder->base.dev;
  1086. struct drm_i915_private *dev_priv = dev->dev_private;
  1087. u32 tmp = I915_READ(intel_dp->output_reg);
  1088. if (!(tmp & DP_PORT_EN))
  1089. return false;
  1090. if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
  1091. *pipe = PORT_TO_PIPE_CPT(tmp);
  1092. } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
  1093. *pipe = PORT_TO_PIPE(tmp);
  1094. } else {
  1095. u32 trans_sel;
  1096. u32 trans_dp;
  1097. int i;
  1098. switch (intel_dp->output_reg) {
  1099. case PCH_DP_B:
  1100. trans_sel = TRANS_DP_PORT_SEL_B;
  1101. break;
  1102. case PCH_DP_C:
  1103. trans_sel = TRANS_DP_PORT_SEL_C;
  1104. break;
  1105. case PCH_DP_D:
  1106. trans_sel = TRANS_DP_PORT_SEL_D;
  1107. break;
  1108. default:
  1109. return true;
  1110. }
  1111. for_each_pipe(i) {
  1112. trans_dp = I915_READ(TRANS_DP_CTL(i));
  1113. if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
  1114. *pipe = i;
  1115. return true;
  1116. }
  1117. }
  1118. }
  1119. DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
  1120. return true;
  1121. }
  1122. static void intel_disable_dp(struct intel_encoder *encoder)
  1123. {
  1124. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1125. /* Make sure the panel is off before trying to change the mode. But also
  1126. * ensure that we have vdd while we switch off the panel. */
  1127. ironlake_edp_panel_vdd_on(intel_dp);
  1128. ironlake_edp_backlight_off(intel_dp);
  1129. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1130. ironlake_edp_panel_off(intel_dp);
  1131. /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
  1132. if (!is_cpu_edp(intel_dp))
  1133. intel_dp_link_down(intel_dp);
  1134. }
  1135. static void intel_post_disable_dp(struct intel_encoder *encoder)
  1136. {
  1137. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1138. if (is_cpu_edp(intel_dp)) {
  1139. intel_dp_link_down(intel_dp);
  1140. ironlake_edp_pll_off(intel_dp);
  1141. }
  1142. }
  1143. static void intel_enable_dp(struct intel_encoder *encoder)
  1144. {
  1145. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1146. struct drm_device *dev = encoder->base.dev;
  1147. struct drm_i915_private *dev_priv = dev->dev_private;
  1148. uint32_t dp_reg = I915_READ(intel_dp->output_reg);
  1149. if (WARN_ON(dp_reg & DP_PORT_EN))
  1150. return;
  1151. ironlake_edp_panel_vdd_on(intel_dp);
  1152. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1153. intel_dp_start_link_train(intel_dp);
  1154. ironlake_edp_panel_on(intel_dp);
  1155. ironlake_edp_panel_vdd_off(intel_dp, true);
  1156. intel_dp_complete_link_train(intel_dp);
  1157. ironlake_edp_backlight_on(intel_dp);
  1158. }
  1159. static void intel_pre_enable_dp(struct intel_encoder *encoder)
  1160. {
  1161. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1162. if (is_cpu_edp(intel_dp))
  1163. ironlake_edp_pll_on(intel_dp);
  1164. }
  1165. /*
  1166. * Native read with retry for link status and receiver capability reads for
  1167. * cases where the sink may still be asleep.
  1168. */
  1169. static bool
  1170. intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
  1171. uint8_t *recv, int recv_bytes)
  1172. {
  1173. int ret, i;
  1174. /*
  1175. * Sinks are *supposed* to come up within 1ms from an off state,
  1176. * but we're also supposed to retry 3 times per the spec.
  1177. */
  1178. for (i = 0; i < 3; i++) {
  1179. ret = intel_dp_aux_native_read(intel_dp, address, recv,
  1180. recv_bytes);
  1181. if (ret == recv_bytes)
  1182. return true;
  1183. msleep(1);
  1184. }
  1185. return false;
  1186. }
  1187. /*
  1188. * Fetch AUX CH registers 0x202 - 0x207 which contain
  1189. * link status information
  1190. */
  1191. static bool
  1192. intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1193. {
  1194. return intel_dp_aux_native_read_retry(intel_dp,
  1195. DP_LANE0_1_STATUS,
  1196. link_status,
  1197. DP_LINK_STATUS_SIZE);
  1198. }
  1199. static uint8_t
  1200. intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
  1201. int r)
  1202. {
  1203. return link_status[r - DP_LANE0_1_STATUS];
  1204. }
  1205. static uint8_t
  1206. intel_get_adjust_request_voltage(uint8_t adjust_request[2],
  1207. int lane)
  1208. {
  1209. int s = ((lane & 1) ?
  1210. DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
  1211. DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
  1212. uint8_t l = adjust_request[lane>>1];
  1213. return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
  1214. }
  1215. static uint8_t
  1216. intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
  1217. int lane)
  1218. {
  1219. int s = ((lane & 1) ?
  1220. DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
  1221. DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
  1222. uint8_t l = adjust_request[lane>>1];
  1223. return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
  1224. }
  1225. #if 0
  1226. static char *voltage_names[] = {
  1227. "0.4V", "0.6V", "0.8V", "1.2V"
  1228. };
  1229. static char *pre_emph_names[] = {
  1230. "0dB", "3.5dB", "6dB", "9.5dB"
  1231. };
  1232. static char *link_train_names[] = {
  1233. "pattern 1", "pattern 2", "idle", "off"
  1234. };
  1235. #endif
  1236. /*
  1237. * These are source-specific values; current Intel hardware supports
  1238. * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
  1239. */
  1240. static uint8_t
  1241. intel_dp_voltage_max(struct intel_dp *intel_dp)
  1242. {
  1243. struct drm_device *dev = intel_dp->base.base.dev;
  1244. if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
  1245. return DP_TRAIN_VOLTAGE_SWING_800;
  1246. else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
  1247. return DP_TRAIN_VOLTAGE_SWING_1200;
  1248. else
  1249. return DP_TRAIN_VOLTAGE_SWING_800;
  1250. }
  1251. static uint8_t
  1252. intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
  1253. {
  1254. struct drm_device *dev = intel_dp->base.base.dev;
  1255. if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
  1256. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1257. case DP_TRAIN_VOLTAGE_SWING_400:
  1258. return DP_TRAIN_PRE_EMPHASIS_6;
  1259. case DP_TRAIN_VOLTAGE_SWING_600:
  1260. case DP_TRAIN_VOLTAGE_SWING_800:
  1261. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1262. default:
  1263. return DP_TRAIN_PRE_EMPHASIS_0;
  1264. }
  1265. } else {
  1266. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1267. case DP_TRAIN_VOLTAGE_SWING_400:
  1268. return DP_TRAIN_PRE_EMPHASIS_6;
  1269. case DP_TRAIN_VOLTAGE_SWING_600:
  1270. return DP_TRAIN_PRE_EMPHASIS_6;
  1271. case DP_TRAIN_VOLTAGE_SWING_800:
  1272. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1273. case DP_TRAIN_VOLTAGE_SWING_1200:
  1274. default:
  1275. return DP_TRAIN_PRE_EMPHASIS_0;
  1276. }
  1277. }
  1278. }
  1279. static void
  1280. intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1281. {
  1282. uint8_t v = 0;
  1283. uint8_t p = 0;
  1284. int lane;
  1285. uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
  1286. uint8_t voltage_max;
  1287. uint8_t preemph_max;
  1288. for (lane = 0; lane < intel_dp->lane_count; lane++) {
  1289. uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
  1290. uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
  1291. if (this_v > v)
  1292. v = this_v;
  1293. if (this_p > p)
  1294. p = this_p;
  1295. }
  1296. voltage_max = intel_dp_voltage_max(intel_dp);
  1297. if (v >= voltage_max)
  1298. v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  1299. preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
  1300. if (p >= preemph_max)
  1301. p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  1302. for (lane = 0; lane < 4; lane++)
  1303. intel_dp->train_set[lane] = v | p;
  1304. }
  1305. static uint32_t
  1306. intel_dp_signal_levels(uint8_t train_set)
  1307. {
  1308. uint32_t signal_levels = 0;
  1309. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1310. case DP_TRAIN_VOLTAGE_SWING_400:
  1311. default:
  1312. signal_levels |= DP_VOLTAGE_0_4;
  1313. break;
  1314. case DP_TRAIN_VOLTAGE_SWING_600:
  1315. signal_levels |= DP_VOLTAGE_0_6;
  1316. break;
  1317. case DP_TRAIN_VOLTAGE_SWING_800:
  1318. signal_levels |= DP_VOLTAGE_0_8;
  1319. break;
  1320. case DP_TRAIN_VOLTAGE_SWING_1200:
  1321. signal_levels |= DP_VOLTAGE_1_2;
  1322. break;
  1323. }
  1324. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  1325. case DP_TRAIN_PRE_EMPHASIS_0:
  1326. default:
  1327. signal_levels |= DP_PRE_EMPHASIS_0;
  1328. break;
  1329. case DP_TRAIN_PRE_EMPHASIS_3_5:
  1330. signal_levels |= DP_PRE_EMPHASIS_3_5;
  1331. break;
  1332. case DP_TRAIN_PRE_EMPHASIS_6:
  1333. signal_levels |= DP_PRE_EMPHASIS_6;
  1334. break;
  1335. case DP_TRAIN_PRE_EMPHASIS_9_5:
  1336. signal_levels |= DP_PRE_EMPHASIS_9_5;
  1337. break;
  1338. }
  1339. return signal_levels;
  1340. }
  1341. /* Gen6's DP voltage swing and pre-emphasis control */
  1342. static uint32_t
  1343. intel_gen6_edp_signal_levels(uint8_t train_set)
  1344. {
  1345. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1346. DP_TRAIN_PRE_EMPHASIS_MASK);
  1347. switch (signal_levels) {
  1348. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1349. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1350. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1351. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1352. return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
  1353. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1354. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  1355. return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
  1356. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1357. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1358. return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
  1359. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1360. case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
  1361. return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
  1362. default:
  1363. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1364. "0x%x\n", signal_levels);
  1365. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1366. }
  1367. }
  1368. /* Gen7's DP voltage swing and pre-emphasis control */
  1369. static uint32_t
  1370. intel_gen7_edp_signal_levels(uint8_t train_set)
  1371. {
  1372. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1373. DP_TRAIN_PRE_EMPHASIS_MASK);
  1374. switch (signal_levels) {
  1375. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1376. return EDP_LINK_TRAIN_400MV_0DB_IVB;
  1377. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1378. return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
  1379. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1380. return EDP_LINK_TRAIN_400MV_6DB_IVB;
  1381. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1382. return EDP_LINK_TRAIN_600MV_0DB_IVB;
  1383. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1384. return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
  1385. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1386. return EDP_LINK_TRAIN_800MV_0DB_IVB;
  1387. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1388. return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
  1389. default:
  1390. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1391. "0x%x\n", signal_levels);
  1392. return EDP_LINK_TRAIN_500MV_0DB_IVB;
  1393. }
  1394. }
  1395. static uint8_t
  1396. intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
  1397. int lane)
  1398. {
  1399. int s = (lane & 1) * 4;
  1400. uint8_t l = link_status[lane>>1];
  1401. return (l >> s) & 0xf;
  1402. }
  1403. /* Check for clock recovery is done on all channels */
  1404. static bool
  1405. intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
  1406. {
  1407. int lane;
  1408. uint8_t lane_status;
  1409. for (lane = 0; lane < lane_count; lane++) {
  1410. lane_status = intel_get_lane_status(link_status, lane);
  1411. if ((lane_status & DP_LANE_CR_DONE) == 0)
  1412. return false;
  1413. }
  1414. return true;
  1415. }
  1416. /* Check to see if channel eq is done on all channels */
  1417. #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
  1418. DP_LANE_CHANNEL_EQ_DONE|\
  1419. DP_LANE_SYMBOL_LOCKED)
  1420. static bool
  1421. intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1422. {
  1423. uint8_t lane_align;
  1424. uint8_t lane_status;
  1425. int lane;
  1426. lane_align = intel_dp_link_status(link_status,
  1427. DP_LANE_ALIGN_STATUS_UPDATED);
  1428. if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
  1429. return false;
  1430. for (lane = 0; lane < intel_dp->lane_count; lane++) {
  1431. lane_status = intel_get_lane_status(link_status, lane);
  1432. if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
  1433. return false;
  1434. }
  1435. return true;
  1436. }
  1437. static bool
  1438. intel_dp_set_link_train(struct intel_dp *intel_dp,
  1439. uint32_t dp_reg_value,
  1440. uint8_t dp_train_pat)
  1441. {
  1442. struct drm_device *dev = intel_dp->base.base.dev;
  1443. struct drm_i915_private *dev_priv = dev->dev_private;
  1444. int ret;
  1445. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
  1446. dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
  1447. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1448. case DP_TRAINING_PATTERN_DISABLE:
  1449. dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
  1450. break;
  1451. case DP_TRAINING_PATTERN_1:
  1452. dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
  1453. break;
  1454. case DP_TRAINING_PATTERN_2:
  1455. dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
  1456. break;
  1457. case DP_TRAINING_PATTERN_3:
  1458. DRM_ERROR("DP training pattern 3 not supported\n");
  1459. dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
  1460. break;
  1461. }
  1462. } else {
  1463. dp_reg_value &= ~DP_LINK_TRAIN_MASK;
  1464. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1465. case DP_TRAINING_PATTERN_DISABLE:
  1466. dp_reg_value |= DP_LINK_TRAIN_OFF;
  1467. break;
  1468. case DP_TRAINING_PATTERN_1:
  1469. dp_reg_value |= DP_LINK_TRAIN_PAT_1;
  1470. break;
  1471. case DP_TRAINING_PATTERN_2:
  1472. dp_reg_value |= DP_LINK_TRAIN_PAT_2;
  1473. break;
  1474. case DP_TRAINING_PATTERN_3:
  1475. DRM_ERROR("DP training pattern 3 not supported\n");
  1476. dp_reg_value |= DP_LINK_TRAIN_PAT_2;
  1477. break;
  1478. }
  1479. }
  1480. I915_WRITE(intel_dp->output_reg, dp_reg_value);
  1481. POSTING_READ(intel_dp->output_reg);
  1482. intel_dp_aux_native_write_1(intel_dp,
  1483. DP_TRAINING_PATTERN_SET,
  1484. dp_train_pat);
  1485. if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
  1486. DP_TRAINING_PATTERN_DISABLE) {
  1487. ret = intel_dp_aux_native_write(intel_dp,
  1488. DP_TRAINING_LANE0_SET,
  1489. intel_dp->train_set,
  1490. intel_dp->lane_count);
  1491. if (ret != intel_dp->lane_count)
  1492. return false;
  1493. }
  1494. return true;
  1495. }
  1496. /* Enable corresponding port and start training pattern 1 */
  1497. static void
  1498. intel_dp_start_link_train(struct intel_dp *intel_dp)
  1499. {
  1500. struct drm_device *dev = intel_dp->base.base.dev;
  1501. int i;
  1502. uint8_t voltage;
  1503. bool clock_recovery = false;
  1504. int voltage_tries, loop_tries;
  1505. uint32_t DP = intel_dp->DP;
  1506. /* Write the link configuration data */
  1507. intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
  1508. intel_dp->link_configuration,
  1509. DP_LINK_CONFIGURATION_SIZE);
  1510. DP |= DP_PORT_EN;
  1511. memset(intel_dp->train_set, 0, 4);
  1512. voltage = 0xff;
  1513. voltage_tries = 0;
  1514. loop_tries = 0;
  1515. clock_recovery = false;
  1516. for (;;) {
  1517. /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
  1518. uint8_t link_status[DP_LINK_STATUS_SIZE];
  1519. uint32_t signal_levels;
  1520. if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
  1521. signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
  1522. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
  1523. } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
  1524. signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
  1525. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
  1526. } else {
  1527. signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
  1528. DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
  1529. DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
  1530. }
  1531. if (!intel_dp_set_link_train(intel_dp, DP,
  1532. DP_TRAINING_PATTERN_1 |
  1533. DP_LINK_SCRAMBLING_DISABLE))
  1534. break;
  1535. /* Set training pattern 1 */
  1536. udelay(100);
  1537. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  1538. DRM_ERROR("failed to get link status\n");
  1539. break;
  1540. }
  1541. if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  1542. DRM_DEBUG_KMS("clock recovery OK\n");
  1543. clock_recovery = true;
  1544. break;
  1545. }
  1546. /* Check to see if we've tried the max voltage */
  1547. for (i = 0; i < intel_dp->lane_count; i++)
  1548. if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
  1549. break;
  1550. if (i == intel_dp->lane_count && voltage_tries == 5) {
  1551. ++loop_tries;
  1552. if (loop_tries == 5) {
  1553. DRM_DEBUG_KMS("too many full retries, give up\n");
  1554. break;
  1555. }
  1556. memset(intel_dp->train_set, 0, 4);
  1557. voltage_tries = 0;
  1558. continue;
  1559. }
  1560. /* Check to see if we've tried the same voltage 5 times */
  1561. if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
  1562. ++voltage_tries;
  1563. if (voltage_tries == 5) {
  1564. DRM_DEBUG_KMS("too many voltage retries, give up\n");
  1565. break;
  1566. }
  1567. } else
  1568. voltage_tries = 0;
  1569. voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  1570. /* Compute new intel_dp->train_set as requested by target */
  1571. intel_get_adjust_train(intel_dp, link_status);
  1572. }
  1573. intel_dp->DP = DP;
  1574. }
  1575. static void
  1576. intel_dp_complete_link_train(struct intel_dp *intel_dp)
  1577. {
  1578. struct drm_device *dev = intel_dp->base.base.dev;
  1579. bool channel_eq = false;
  1580. int tries, cr_tries;
  1581. uint32_t DP = intel_dp->DP;
  1582. /* channel equalization */
  1583. tries = 0;
  1584. cr_tries = 0;
  1585. channel_eq = false;
  1586. for (;;) {
  1587. /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
  1588. uint32_t signal_levels;
  1589. uint8_t link_status[DP_LINK_STATUS_SIZE];
  1590. if (cr_tries > 5) {
  1591. DRM_ERROR("failed to train DP, aborting\n");
  1592. intel_dp_link_down(intel_dp);
  1593. break;
  1594. }
  1595. if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
  1596. signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
  1597. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
  1598. } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
  1599. signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
  1600. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
  1601. } else {
  1602. signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
  1603. DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
  1604. }
  1605. /* channel eq pattern */
  1606. if (!intel_dp_set_link_train(intel_dp, DP,
  1607. DP_TRAINING_PATTERN_2 |
  1608. DP_LINK_SCRAMBLING_DISABLE))
  1609. break;
  1610. udelay(400);
  1611. if (!intel_dp_get_link_status(intel_dp, link_status))
  1612. break;
  1613. /* Make sure clock is still ok */
  1614. if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  1615. intel_dp_start_link_train(intel_dp);
  1616. cr_tries++;
  1617. continue;
  1618. }
  1619. if (intel_channel_eq_ok(intel_dp, link_status)) {
  1620. channel_eq = true;
  1621. break;
  1622. }
  1623. /* Try 5 times, then try clock recovery if that fails */
  1624. if (tries > 5) {
  1625. intel_dp_link_down(intel_dp);
  1626. intel_dp_start_link_train(intel_dp);
  1627. tries = 0;
  1628. cr_tries++;
  1629. continue;
  1630. }
  1631. /* Compute new intel_dp->train_set as requested by target */
  1632. intel_get_adjust_train(intel_dp, link_status);
  1633. ++tries;
  1634. }
  1635. intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
  1636. }
  1637. static void
  1638. intel_dp_link_down(struct intel_dp *intel_dp)
  1639. {
  1640. struct drm_device *dev = intel_dp->base.base.dev;
  1641. struct drm_i915_private *dev_priv = dev->dev_private;
  1642. uint32_t DP = intel_dp->DP;
  1643. if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
  1644. return;
  1645. DRM_DEBUG_KMS("\n");
  1646. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
  1647. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  1648. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
  1649. } else {
  1650. DP &= ~DP_LINK_TRAIN_MASK;
  1651. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
  1652. }
  1653. POSTING_READ(intel_dp->output_reg);
  1654. msleep(17);
  1655. if (HAS_PCH_IBX(dev) &&
  1656. I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
  1657. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  1658. /* Hardware workaround: leaving our transcoder select
  1659. * set to transcoder B while it's off will prevent the
  1660. * corresponding HDMI output on transcoder A.
  1661. *
  1662. * Combine this with another hardware workaround:
  1663. * transcoder select bit can only be cleared while the
  1664. * port is enabled.
  1665. */
  1666. DP &= ~DP_PIPEB_SELECT;
  1667. I915_WRITE(intel_dp->output_reg, DP);
  1668. /* Changes to enable or select take place the vblank
  1669. * after being written.
  1670. */
  1671. if (crtc == NULL) {
  1672. /* We can arrive here never having been attached
  1673. * to a CRTC, for instance, due to inheriting
  1674. * random state from the BIOS.
  1675. *
  1676. * If the pipe is not running, play safe and
  1677. * wait for the clocks to stabilise before
  1678. * continuing.
  1679. */
  1680. POSTING_READ(intel_dp->output_reg);
  1681. msleep(50);
  1682. } else
  1683. intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
  1684. }
  1685. DP &= ~DP_AUDIO_OUTPUT_ENABLE;
  1686. I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
  1687. POSTING_READ(intel_dp->output_reg);
  1688. msleep(intel_dp->panel_power_down_delay);
  1689. }
  1690. static bool
  1691. intel_dp_get_dpcd(struct intel_dp *intel_dp)
  1692. {
  1693. if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
  1694. sizeof(intel_dp->dpcd)) == 0)
  1695. return false; /* aux transfer failed */
  1696. if (intel_dp->dpcd[DP_DPCD_REV] == 0)
  1697. return false; /* DPCD not present */
  1698. if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
  1699. DP_DWN_STRM_PORT_PRESENT))
  1700. return true; /* native DP sink */
  1701. if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
  1702. return true; /* no per-port downstream info */
  1703. if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
  1704. intel_dp->downstream_ports,
  1705. DP_MAX_DOWNSTREAM_PORTS) == 0)
  1706. return false; /* downstream port status fetch failed */
  1707. return true;
  1708. }
  1709. static void
  1710. intel_dp_probe_oui(struct intel_dp *intel_dp)
  1711. {
  1712. u8 buf[3];
  1713. if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
  1714. return;
  1715. ironlake_edp_panel_vdd_on(intel_dp);
  1716. if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
  1717. DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
  1718. buf[0], buf[1], buf[2]);
  1719. if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
  1720. DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
  1721. buf[0], buf[1], buf[2]);
  1722. ironlake_edp_panel_vdd_off(intel_dp, false);
  1723. }
  1724. static bool
  1725. intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
  1726. {
  1727. int ret;
  1728. ret = intel_dp_aux_native_read_retry(intel_dp,
  1729. DP_DEVICE_SERVICE_IRQ_VECTOR,
  1730. sink_irq_vector, 1);
  1731. if (!ret)
  1732. return false;
  1733. return true;
  1734. }
  1735. static void
  1736. intel_dp_handle_test_request(struct intel_dp *intel_dp)
  1737. {
  1738. /* NAK by default */
  1739. intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
  1740. }
  1741. /*
  1742. * According to DP spec
  1743. * 5.1.2:
  1744. * 1. Read DPCD
  1745. * 2. Configure link according to Receiver Capabilities
  1746. * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
  1747. * 4. Check link status on receipt of hot-plug interrupt
  1748. */
  1749. static void
  1750. intel_dp_check_link_status(struct intel_dp *intel_dp)
  1751. {
  1752. u8 sink_irq_vector;
  1753. u8 link_status[DP_LINK_STATUS_SIZE];
  1754. if (!intel_dp->base.connectors_active)
  1755. return;
  1756. if (WARN_ON(!intel_dp->base.base.crtc))
  1757. return;
  1758. /* Try to read receiver status if the link appears to be up */
  1759. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  1760. intel_dp_link_down(intel_dp);
  1761. return;
  1762. }
  1763. /* Now read the DPCD to see if it's actually running */
  1764. if (!intel_dp_get_dpcd(intel_dp)) {
  1765. intel_dp_link_down(intel_dp);
  1766. return;
  1767. }
  1768. /* Try to read the source of the interrupt */
  1769. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  1770. intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
  1771. /* Clear interrupt source */
  1772. intel_dp_aux_native_write_1(intel_dp,
  1773. DP_DEVICE_SERVICE_IRQ_VECTOR,
  1774. sink_irq_vector);
  1775. if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
  1776. intel_dp_handle_test_request(intel_dp);
  1777. if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
  1778. DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
  1779. }
  1780. if (!intel_channel_eq_ok(intel_dp, link_status)) {
  1781. DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
  1782. drm_get_encoder_name(&intel_dp->base.base));
  1783. intel_dp_start_link_train(intel_dp);
  1784. intel_dp_complete_link_train(intel_dp);
  1785. }
  1786. }
  1787. /* XXX this is probably wrong for multiple downstream ports */
  1788. static enum drm_connector_status
  1789. intel_dp_detect_dpcd(struct intel_dp *intel_dp)
  1790. {
  1791. uint8_t *dpcd = intel_dp->dpcd;
  1792. bool hpd;
  1793. uint8_t type;
  1794. if (!intel_dp_get_dpcd(intel_dp))
  1795. return connector_status_disconnected;
  1796. /* if there's no downstream port, we're done */
  1797. if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
  1798. return connector_status_connected;
  1799. /* If we're HPD-aware, SINK_COUNT changes dynamically */
  1800. hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
  1801. if (hpd) {
  1802. uint8_t sink_count;
  1803. if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
  1804. &sink_count, 1))
  1805. return connector_status_unknown;
  1806. sink_count &= DP_SINK_COUNT_MASK;
  1807. return sink_count ? connector_status_connected
  1808. : connector_status_disconnected;
  1809. }
  1810. /* If no HPD, poke DDC gently */
  1811. if (drm_probe_ddc(&intel_dp->adapter))
  1812. return connector_status_connected;
  1813. /* Well we tried, say unknown for unreliable port types */
  1814. type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
  1815. if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
  1816. return connector_status_unknown;
  1817. /* Anything else is out of spec, warn and ignore */
  1818. DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
  1819. return connector_status_disconnected;
  1820. }
  1821. static enum drm_connector_status
  1822. ironlake_dp_detect(struct intel_dp *intel_dp)
  1823. {
  1824. enum drm_connector_status status;
  1825. /* Can't disconnect eDP, but you can close the lid... */
  1826. if (is_edp(intel_dp)) {
  1827. status = intel_panel_detect(intel_dp->base.base.dev);
  1828. if (status == connector_status_unknown)
  1829. status = connector_status_connected;
  1830. return status;
  1831. }
  1832. return intel_dp_detect_dpcd(intel_dp);
  1833. }
  1834. static enum drm_connector_status
  1835. g4x_dp_detect(struct intel_dp *intel_dp)
  1836. {
  1837. struct drm_device *dev = intel_dp->base.base.dev;
  1838. struct drm_i915_private *dev_priv = dev->dev_private;
  1839. uint32_t bit;
  1840. switch (intel_dp->output_reg) {
  1841. case DP_B:
  1842. bit = DPB_HOTPLUG_LIVE_STATUS;
  1843. break;
  1844. case DP_C:
  1845. bit = DPC_HOTPLUG_LIVE_STATUS;
  1846. break;
  1847. case DP_D:
  1848. bit = DPD_HOTPLUG_LIVE_STATUS;
  1849. break;
  1850. default:
  1851. return connector_status_unknown;
  1852. }
  1853. if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
  1854. return connector_status_disconnected;
  1855. return intel_dp_detect_dpcd(intel_dp);
  1856. }
  1857. static struct edid *
  1858. intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
  1859. {
  1860. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1861. struct edid *edid;
  1862. int size;
  1863. if (is_edp(intel_dp)) {
  1864. if (!intel_dp->edid)
  1865. return NULL;
  1866. size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
  1867. edid = kmalloc(size, GFP_KERNEL);
  1868. if (!edid)
  1869. return NULL;
  1870. memcpy(edid, intel_dp->edid, size);
  1871. return edid;
  1872. }
  1873. edid = drm_get_edid(connector, adapter);
  1874. return edid;
  1875. }
  1876. static int
  1877. intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
  1878. {
  1879. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1880. int ret;
  1881. if (is_edp(intel_dp)) {
  1882. drm_mode_connector_update_edid_property(connector,
  1883. intel_dp->edid);
  1884. ret = drm_add_edid_modes(connector, intel_dp->edid);
  1885. drm_edid_to_eld(connector,
  1886. intel_dp->edid);
  1887. return intel_dp->edid_mode_count;
  1888. }
  1889. ret = intel_ddc_get_modes(connector, adapter);
  1890. return ret;
  1891. }
  1892. /**
  1893. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
  1894. *
  1895. * \return true if DP port is connected.
  1896. * \return false if DP port is disconnected.
  1897. */
  1898. static enum drm_connector_status
  1899. intel_dp_detect(struct drm_connector *connector, bool force)
  1900. {
  1901. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1902. struct drm_device *dev = intel_dp->base.base.dev;
  1903. enum drm_connector_status status;
  1904. struct edid *edid = NULL;
  1905. intel_dp->has_audio = false;
  1906. if (HAS_PCH_SPLIT(dev))
  1907. status = ironlake_dp_detect(intel_dp);
  1908. else
  1909. status = g4x_dp_detect(intel_dp);
  1910. DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
  1911. intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
  1912. intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
  1913. intel_dp->dpcd[6], intel_dp->dpcd[7]);
  1914. if (status != connector_status_connected)
  1915. return status;
  1916. intel_dp_probe_oui(intel_dp);
  1917. if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
  1918. intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
  1919. } else {
  1920. edid = intel_dp_get_edid(connector, &intel_dp->adapter);
  1921. if (edid) {
  1922. intel_dp->has_audio = drm_detect_monitor_audio(edid);
  1923. kfree(edid);
  1924. }
  1925. }
  1926. return connector_status_connected;
  1927. }
  1928. static int intel_dp_get_modes(struct drm_connector *connector)
  1929. {
  1930. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1931. struct drm_device *dev = intel_dp->base.base.dev;
  1932. struct drm_i915_private *dev_priv = dev->dev_private;
  1933. int ret;
  1934. /* We should parse the EDID data and find out if it has an audio sink
  1935. */
  1936. ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
  1937. if (ret) {
  1938. if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
  1939. struct drm_display_mode *newmode;
  1940. list_for_each_entry(newmode, &connector->probed_modes,
  1941. head) {
  1942. if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
  1943. intel_dp->panel_fixed_mode =
  1944. drm_mode_duplicate(dev, newmode);
  1945. break;
  1946. }
  1947. }
  1948. }
  1949. return ret;
  1950. }
  1951. /* if eDP has no EDID, try to use fixed panel mode from VBT */
  1952. if (is_edp(intel_dp)) {
  1953. /* initialize panel mode from VBT if available for eDP */
  1954. if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
  1955. intel_dp->panel_fixed_mode =
  1956. drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
  1957. if (intel_dp->panel_fixed_mode) {
  1958. intel_dp->panel_fixed_mode->type |=
  1959. DRM_MODE_TYPE_PREFERRED;
  1960. }
  1961. }
  1962. if (intel_dp->panel_fixed_mode) {
  1963. struct drm_display_mode *mode;
  1964. mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
  1965. drm_mode_probed_add(connector, mode);
  1966. return 1;
  1967. }
  1968. }
  1969. return 0;
  1970. }
  1971. static bool
  1972. intel_dp_detect_audio(struct drm_connector *connector)
  1973. {
  1974. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1975. struct edid *edid;
  1976. bool has_audio = false;
  1977. edid = intel_dp_get_edid(connector, &intel_dp->adapter);
  1978. if (edid) {
  1979. has_audio = drm_detect_monitor_audio(edid);
  1980. kfree(edid);
  1981. }
  1982. return has_audio;
  1983. }
  1984. static int
  1985. intel_dp_set_property(struct drm_connector *connector,
  1986. struct drm_property *property,
  1987. uint64_t val)
  1988. {
  1989. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1990. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1991. int ret;
  1992. ret = drm_connector_property_set_value(connector, property, val);
  1993. if (ret)
  1994. return ret;
  1995. if (property == dev_priv->force_audio_property) {
  1996. int i = val;
  1997. bool has_audio;
  1998. if (i == intel_dp->force_audio)
  1999. return 0;
  2000. intel_dp->force_audio = i;
  2001. if (i == HDMI_AUDIO_AUTO)
  2002. has_audio = intel_dp_detect_audio(connector);
  2003. else
  2004. has_audio = (i == HDMI_AUDIO_ON);
  2005. if (has_audio == intel_dp->has_audio)
  2006. return 0;
  2007. intel_dp->has_audio = has_audio;
  2008. goto done;
  2009. }
  2010. if (property == dev_priv->broadcast_rgb_property) {
  2011. if (val == !!intel_dp->color_range)
  2012. return 0;
  2013. intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
  2014. goto done;
  2015. }
  2016. return -EINVAL;
  2017. done:
  2018. if (intel_dp->base.base.crtc) {
  2019. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  2020. intel_set_mode(crtc, &crtc->mode,
  2021. crtc->x, crtc->y, crtc->fb);
  2022. }
  2023. return 0;
  2024. }
  2025. static void
  2026. intel_dp_destroy(struct drm_connector *connector)
  2027. {
  2028. struct drm_device *dev = connector->dev;
  2029. if (intel_dpd_is_edp(dev))
  2030. intel_panel_destroy_backlight(dev);
  2031. drm_sysfs_connector_remove(connector);
  2032. drm_connector_cleanup(connector);
  2033. kfree(connector);
  2034. }
  2035. static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
  2036. {
  2037. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  2038. i2c_del_adapter(&intel_dp->adapter);
  2039. drm_encoder_cleanup(encoder);
  2040. if (is_edp(intel_dp)) {
  2041. kfree(intel_dp->edid);
  2042. cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
  2043. ironlake_panel_vdd_off_sync(intel_dp);
  2044. }
  2045. kfree(intel_dp);
  2046. }
  2047. static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
  2048. .mode_fixup = intel_dp_mode_fixup,
  2049. .mode_set = intel_dp_mode_set,
  2050. .disable = intel_encoder_noop,
  2051. };
  2052. static const struct drm_connector_funcs intel_dp_connector_funcs = {
  2053. .dpms = intel_connector_dpms,
  2054. .detect = intel_dp_detect,
  2055. .fill_modes = drm_helper_probe_single_connector_modes,
  2056. .set_property = intel_dp_set_property,
  2057. .destroy = intel_dp_destroy,
  2058. };
  2059. static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
  2060. .get_modes = intel_dp_get_modes,
  2061. .mode_valid = intel_dp_mode_valid,
  2062. .best_encoder = intel_best_encoder,
  2063. };
  2064. static const struct drm_encoder_funcs intel_dp_enc_funcs = {
  2065. .destroy = intel_dp_encoder_destroy,
  2066. };
  2067. static void
  2068. intel_dp_hot_plug(struct intel_encoder *intel_encoder)
  2069. {
  2070. struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
  2071. intel_dp_check_link_status(intel_dp);
  2072. }
  2073. /* Return which DP Port should be selected for Transcoder DP control */
  2074. int
  2075. intel_trans_dp_port_sel(struct drm_crtc *crtc)
  2076. {
  2077. struct drm_device *dev = crtc->dev;
  2078. struct intel_encoder *encoder;
  2079. for_each_encoder_on_crtc(dev, crtc, encoder) {
  2080. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  2081. if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
  2082. intel_dp->base.type == INTEL_OUTPUT_EDP)
  2083. return intel_dp->output_reg;
  2084. }
  2085. return -1;
  2086. }
  2087. /* check the VBT to see whether the eDP is on DP-D port */
  2088. bool intel_dpd_is_edp(struct drm_device *dev)
  2089. {
  2090. struct drm_i915_private *dev_priv = dev->dev_private;
  2091. struct child_device_config *p_child;
  2092. int i;
  2093. if (!dev_priv->child_dev_num)
  2094. return false;
  2095. for (i = 0; i < dev_priv->child_dev_num; i++) {
  2096. p_child = dev_priv->child_dev + i;
  2097. if (p_child->dvo_port == PORT_IDPD &&
  2098. p_child->device_type == DEVICE_TYPE_eDP)
  2099. return true;
  2100. }
  2101. return false;
  2102. }
  2103. static void
  2104. intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
  2105. {
  2106. intel_attach_force_audio_property(connector);
  2107. intel_attach_broadcast_rgb_property(connector);
  2108. }
  2109. void
  2110. intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
  2111. {
  2112. struct drm_i915_private *dev_priv = dev->dev_private;
  2113. struct drm_connector *connector;
  2114. struct intel_dp *intel_dp;
  2115. struct intel_encoder *intel_encoder;
  2116. struct intel_connector *intel_connector;
  2117. const char *name = NULL;
  2118. int type;
  2119. intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
  2120. if (!intel_dp)
  2121. return;
  2122. intel_dp->output_reg = output_reg;
  2123. intel_dp->port = port;
  2124. /* Preserve the current hw state. */
  2125. intel_dp->DP = I915_READ(intel_dp->output_reg);
  2126. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  2127. if (!intel_connector) {
  2128. kfree(intel_dp);
  2129. return;
  2130. }
  2131. intel_encoder = &intel_dp->base;
  2132. if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
  2133. if (intel_dpd_is_edp(dev))
  2134. intel_dp->is_pch_edp = true;
  2135. if (output_reg == DP_A || is_pch_edp(intel_dp)) {
  2136. type = DRM_MODE_CONNECTOR_eDP;
  2137. intel_encoder->type = INTEL_OUTPUT_EDP;
  2138. } else {
  2139. type = DRM_MODE_CONNECTOR_DisplayPort;
  2140. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  2141. }
  2142. connector = &intel_connector->base;
  2143. drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
  2144. drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
  2145. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2146. intel_encoder->cloneable = false;
  2147. INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
  2148. ironlake_panel_vdd_work);
  2149. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2150. connector->interlace_allowed = true;
  2151. connector->doublescan_allowed = 0;
  2152. drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
  2153. DRM_MODE_ENCODER_TMDS);
  2154. drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
  2155. intel_connector_attach_encoder(intel_connector, intel_encoder);
  2156. drm_sysfs_connector_add(connector);
  2157. intel_encoder->enable = intel_enable_dp;
  2158. intel_encoder->pre_enable = intel_pre_enable_dp;
  2159. intel_encoder->disable = intel_disable_dp;
  2160. intel_encoder->post_disable = intel_post_disable_dp;
  2161. intel_encoder->get_hw_state = intel_dp_get_hw_state;
  2162. intel_connector->get_hw_state = intel_connector_get_hw_state;
  2163. /* Set up the DDC bus. */
  2164. switch (port) {
  2165. case PORT_A:
  2166. name = "DPDDC-A";
  2167. break;
  2168. case PORT_B:
  2169. dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
  2170. name = "DPDDC-B";
  2171. break;
  2172. case PORT_C:
  2173. dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
  2174. name = "DPDDC-C";
  2175. break;
  2176. case PORT_D:
  2177. dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
  2178. name = "DPDDC-D";
  2179. break;
  2180. default:
  2181. WARN(1, "Invalid port %c\n", port_name(port));
  2182. break;
  2183. }
  2184. /* Cache some DPCD data in the eDP case */
  2185. if (is_edp(intel_dp)) {
  2186. struct edp_power_seq cur, vbt;
  2187. u32 pp_on, pp_off, pp_div;
  2188. pp_on = I915_READ(PCH_PP_ON_DELAYS);
  2189. pp_off = I915_READ(PCH_PP_OFF_DELAYS);
  2190. pp_div = I915_READ(PCH_PP_DIVISOR);
  2191. if (!pp_on || !pp_off || !pp_div) {
  2192. DRM_INFO("bad panel power sequencing delays, disabling panel\n");
  2193. intel_dp_encoder_destroy(&intel_dp->base.base);
  2194. intel_dp_destroy(&intel_connector->base);
  2195. return;
  2196. }
  2197. /* Pull timing values out of registers */
  2198. cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
  2199. PANEL_POWER_UP_DELAY_SHIFT;
  2200. cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
  2201. PANEL_LIGHT_ON_DELAY_SHIFT;
  2202. cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
  2203. PANEL_LIGHT_OFF_DELAY_SHIFT;
  2204. cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
  2205. PANEL_POWER_DOWN_DELAY_SHIFT;
  2206. cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
  2207. PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
  2208. DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  2209. cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
  2210. vbt = dev_priv->edp.pps;
  2211. DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  2212. vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
  2213. #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
  2214. intel_dp->panel_power_up_delay = get_delay(t1_t3);
  2215. intel_dp->backlight_on_delay = get_delay(t8);
  2216. intel_dp->backlight_off_delay = get_delay(t9);
  2217. intel_dp->panel_power_down_delay = get_delay(t10);
  2218. intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
  2219. DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
  2220. intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
  2221. intel_dp->panel_power_cycle_delay);
  2222. DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
  2223. intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
  2224. }
  2225. intel_dp_i2c_init(intel_dp, intel_connector, name);
  2226. if (is_edp(intel_dp)) {
  2227. bool ret;
  2228. struct edid *edid;
  2229. ironlake_edp_panel_vdd_on(intel_dp);
  2230. ret = intel_dp_get_dpcd(intel_dp);
  2231. ironlake_edp_panel_vdd_off(intel_dp, false);
  2232. if (ret) {
  2233. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
  2234. dev_priv->no_aux_handshake =
  2235. intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
  2236. DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
  2237. } else {
  2238. /* if this fails, presume the device is a ghost */
  2239. DRM_INFO("failed to retrieve link info, disabling eDP\n");
  2240. intel_dp_encoder_destroy(&intel_dp->base.base);
  2241. intel_dp_destroy(&intel_connector->base);
  2242. return;
  2243. }
  2244. ironlake_edp_panel_vdd_on(intel_dp);
  2245. edid = drm_get_edid(connector, &intel_dp->adapter);
  2246. if (edid) {
  2247. drm_mode_connector_update_edid_property(connector,
  2248. edid);
  2249. intel_dp->edid_mode_count =
  2250. drm_add_edid_modes(connector, edid);
  2251. drm_edid_to_eld(connector, edid);
  2252. intel_dp->edid = edid;
  2253. }
  2254. ironlake_edp_panel_vdd_off(intel_dp, false);
  2255. }
  2256. intel_encoder->hot_plug = intel_dp_hot_plug;
  2257. if (is_edp(intel_dp)) {
  2258. dev_priv->int_edp_connector = connector;
  2259. intel_panel_setup_backlight(dev);
  2260. }
  2261. intel_dp_add_properties(intel_dp, connector);
  2262. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  2263. * 0xd. Failure to do so will result in spurious interrupts being
  2264. * generated on the port when a cable is not attached.
  2265. */
  2266. if (IS_G4X(dev) && !IS_GM45(dev)) {
  2267. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  2268. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  2269. }
  2270. }