mthca_memfree.c 18 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Cisco Systems. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id$
  35. */
  36. #include <linux/mm.h>
  37. #include <linux/scatterlist.h>
  38. #include <asm/page.h>
  39. #include "mthca_memfree.h"
  40. #include "mthca_dev.h"
  41. #include "mthca_cmd.h"
  42. /*
  43. * We allocate in as big chunks as we can, up to a maximum of 256 KB
  44. * per chunk.
  45. */
  46. enum {
  47. MTHCA_ICM_ALLOC_SIZE = 1 << 18,
  48. MTHCA_TABLE_CHUNK_SIZE = 1 << 18
  49. };
  50. struct mthca_user_db_table {
  51. struct mutex mutex;
  52. struct {
  53. u64 uvirt;
  54. struct scatterlist mem;
  55. int refcount;
  56. } page[0];
  57. };
  58. static void mthca_free_icm_pages(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
  59. {
  60. int i;
  61. if (chunk->nsg > 0)
  62. pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages,
  63. PCI_DMA_BIDIRECTIONAL);
  64. for (i = 0; i < chunk->npages; ++i)
  65. __free_pages(chunk->mem[i].page,
  66. get_order(chunk->mem[i].length));
  67. }
  68. static void mthca_free_icm_coherent(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
  69. {
  70. int i;
  71. for (i = 0; i < chunk->npages; ++i) {
  72. dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length,
  73. lowmem_page_address(chunk->mem[i].page),
  74. sg_dma_address(&chunk->mem[i]));
  75. }
  76. }
  77. void mthca_free_icm(struct mthca_dev *dev, struct mthca_icm *icm, int coherent)
  78. {
  79. struct mthca_icm_chunk *chunk, *tmp;
  80. if (!icm)
  81. return;
  82. list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) {
  83. if (coherent)
  84. mthca_free_icm_coherent(dev, chunk);
  85. else
  86. mthca_free_icm_pages(dev, chunk);
  87. kfree(chunk);
  88. }
  89. kfree(icm);
  90. }
  91. static int mthca_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_mask)
  92. {
  93. mem->page = alloc_pages(gfp_mask, order);
  94. if (!mem->page)
  95. return -ENOMEM;
  96. mem->length = PAGE_SIZE << order;
  97. mem->offset = 0;
  98. return 0;
  99. }
  100. static int mthca_alloc_icm_coherent(struct device *dev, struct scatterlist *mem,
  101. int order, gfp_t gfp_mask)
  102. {
  103. void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order, &sg_dma_address(mem),
  104. gfp_mask);
  105. if (!buf)
  106. return -ENOMEM;
  107. sg_set_buf(mem, buf, PAGE_SIZE << order);
  108. BUG_ON(mem->offset);
  109. sg_dma_len(mem) = PAGE_SIZE << order;
  110. return 0;
  111. }
  112. struct mthca_icm *mthca_alloc_icm(struct mthca_dev *dev, int npages,
  113. gfp_t gfp_mask, int coherent)
  114. {
  115. struct mthca_icm *icm;
  116. struct mthca_icm_chunk *chunk = NULL;
  117. int cur_order;
  118. int ret;
  119. /* We use sg_set_buf for coherent allocs, which assumes low memory */
  120. BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM));
  121. icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
  122. if (!icm)
  123. return icm;
  124. icm->refcount = 0;
  125. INIT_LIST_HEAD(&icm->chunk_list);
  126. cur_order = get_order(MTHCA_ICM_ALLOC_SIZE);
  127. while (npages > 0) {
  128. if (!chunk) {
  129. chunk = kmalloc(sizeof *chunk,
  130. gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
  131. if (!chunk)
  132. goto fail;
  133. chunk->npages = 0;
  134. chunk->nsg = 0;
  135. list_add_tail(&chunk->list, &icm->chunk_list);
  136. }
  137. while (1 << cur_order > npages)
  138. --cur_order;
  139. if (coherent)
  140. ret = mthca_alloc_icm_coherent(&dev->pdev->dev,
  141. &chunk->mem[chunk->npages],
  142. cur_order, gfp_mask);
  143. else
  144. ret = mthca_alloc_icm_pages(&chunk->mem[chunk->npages],
  145. cur_order, gfp_mask);
  146. if (!ret) {
  147. ++chunk->npages;
  148. if (!coherent && chunk->npages == MTHCA_ICM_CHUNK_LEN) {
  149. chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
  150. chunk->npages,
  151. PCI_DMA_BIDIRECTIONAL);
  152. if (chunk->nsg <= 0)
  153. goto fail;
  154. }
  155. if (chunk->npages == MTHCA_ICM_CHUNK_LEN)
  156. chunk = NULL;
  157. npages -= 1 << cur_order;
  158. } else {
  159. --cur_order;
  160. if (cur_order < 0)
  161. goto fail;
  162. }
  163. }
  164. if (!coherent && chunk) {
  165. chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
  166. chunk->npages,
  167. PCI_DMA_BIDIRECTIONAL);
  168. if (chunk->nsg <= 0)
  169. goto fail;
  170. }
  171. return icm;
  172. fail:
  173. mthca_free_icm(dev, icm, coherent);
  174. return NULL;
  175. }
  176. int mthca_table_get(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
  177. {
  178. int i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
  179. int ret = 0;
  180. u8 status;
  181. mutex_lock(&table->mutex);
  182. if (table->icm[i]) {
  183. ++table->icm[i]->refcount;
  184. goto out;
  185. }
  186. table->icm[i] = mthca_alloc_icm(dev, MTHCA_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
  187. (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
  188. __GFP_NOWARN, table->coherent);
  189. if (!table->icm[i]) {
  190. ret = -ENOMEM;
  191. goto out;
  192. }
  193. if (mthca_MAP_ICM(dev, table->icm[i], table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  194. &status) || status) {
  195. mthca_free_icm(dev, table->icm[i], table->coherent);
  196. table->icm[i] = NULL;
  197. ret = -ENOMEM;
  198. goto out;
  199. }
  200. ++table->icm[i]->refcount;
  201. out:
  202. mutex_unlock(&table->mutex);
  203. return ret;
  204. }
  205. void mthca_table_put(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
  206. {
  207. int i;
  208. u8 status;
  209. if (!mthca_is_memfree(dev))
  210. return;
  211. i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
  212. mutex_lock(&table->mutex);
  213. if (--table->icm[i]->refcount == 0) {
  214. mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  215. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  216. &status);
  217. mthca_free_icm(dev, table->icm[i], table->coherent);
  218. table->icm[i] = NULL;
  219. }
  220. mutex_unlock(&table->mutex);
  221. }
  222. void *mthca_table_find(struct mthca_icm_table *table, int obj, dma_addr_t *dma_handle)
  223. {
  224. int idx, offset, dma_offset, i;
  225. struct mthca_icm_chunk *chunk;
  226. struct mthca_icm *icm;
  227. struct page *page = NULL;
  228. if (!table->lowmem)
  229. return NULL;
  230. mutex_lock(&table->mutex);
  231. idx = (obj & (table->num_obj - 1)) * table->obj_size;
  232. icm = table->icm[idx / MTHCA_TABLE_CHUNK_SIZE];
  233. dma_offset = offset = idx % MTHCA_TABLE_CHUNK_SIZE;
  234. if (!icm)
  235. goto out;
  236. list_for_each_entry(chunk, &icm->chunk_list, list) {
  237. for (i = 0; i < chunk->npages; ++i) {
  238. if (dma_handle && dma_offset >= 0) {
  239. if (sg_dma_len(&chunk->mem[i]) > dma_offset)
  240. *dma_handle = sg_dma_address(&chunk->mem[i]) +
  241. dma_offset;
  242. dma_offset -= sg_dma_len(&chunk->mem[i]);
  243. }
  244. /* DMA mapping can merge pages but not split them,
  245. * so if we found the page, dma_handle has already
  246. * been assigned to. */
  247. if (chunk->mem[i].length > offset) {
  248. page = chunk->mem[i].page;
  249. goto out;
  250. }
  251. offset -= chunk->mem[i].length;
  252. }
  253. }
  254. out:
  255. mutex_unlock(&table->mutex);
  256. return page ? lowmem_page_address(page) + offset : NULL;
  257. }
  258. int mthca_table_get_range(struct mthca_dev *dev, struct mthca_icm_table *table,
  259. int start, int end)
  260. {
  261. int inc = MTHCA_TABLE_CHUNK_SIZE / table->obj_size;
  262. int i, err;
  263. for (i = start; i <= end; i += inc) {
  264. err = mthca_table_get(dev, table, i);
  265. if (err)
  266. goto fail;
  267. }
  268. return 0;
  269. fail:
  270. while (i > start) {
  271. i -= inc;
  272. mthca_table_put(dev, table, i);
  273. }
  274. return err;
  275. }
  276. void mthca_table_put_range(struct mthca_dev *dev, struct mthca_icm_table *table,
  277. int start, int end)
  278. {
  279. int i;
  280. if (!mthca_is_memfree(dev))
  281. return;
  282. for (i = start; i <= end; i += MTHCA_TABLE_CHUNK_SIZE / table->obj_size)
  283. mthca_table_put(dev, table, i);
  284. }
  285. struct mthca_icm_table *mthca_alloc_icm_table(struct mthca_dev *dev,
  286. u64 virt, int obj_size,
  287. int nobj, int reserved,
  288. int use_lowmem, int use_coherent)
  289. {
  290. struct mthca_icm_table *table;
  291. int num_icm;
  292. unsigned chunk_size;
  293. int i;
  294. u8 status;
  295. num_icm = (obj_size * nobj + MTHCA_TABLE_CHUNK_SIZE - 1) / MTHCA_TABLE_CHUNK_SIZE;
  296. table = kmalloc(sizeof *table + num_icm * sizeof *table->icm, GFP_KERNEL);
  297. if (!table)
  298. return NULL;
  299. table->virt = virt;
  300. table->num_icm = num_icm;
  301. table->num_obj = nobj;
  302. table->obj_size = obj_size;
  303. table->lowmem = use_lowmem;
  304. table->coherent = use_coherent;
  305. mutex_init(&table->mutex);
  306. for (i = 0; i < num_icm; ++i)
  307. table->icm[i] = NULL;
  308. for (i = 0; i * MTHCA_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) {
  309. chunk_size = MTHCA_TABLE_CHUNK_SIZE;
  310. if ((i + 1) * MTHCA_TABLE_CHUNK_SIZE > nobj * obj_size)
  311. chunk_size = nobj * obj_size - i * MTHCA_TABLE_CHUNK_SIZE;
  312. table->icm[i] = mthca_alloc_icm(dev, chunk_size >> PAGE_SHIFT,
  313. (use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
  314. __GFP_NOWARN, use_coherent);
  315. if (!table->icm[i])
  316. goto err;
  317. if (mthca_MAP_ICM(dev, table->icm[i], virt + i * MTHCA_TABLE_CHUNK_SIZE,
  318. &status) || status) {
  319. mthca_free_icm(dev, table->icm[i], table->coherent);
  320. table->icm[i] = NULL;
  321. goto err;
  322. }
  323. /*
  324. * Add a reference to this ICM chunk so that it never
  325. * gets freed (since it contains reserved firmware objects).
  326. */
  327. ++table->icm[i]->refcount;
  328. }
  329. return table;
  330. err:
  331. for (i = 0; i < num_icm; ++i)
  332. if (table->icm[i]) {
  333. mthca_UNMAP_ICM(dev, virt + i * MTHCA_TABLE_CHUNK_SIZE,
  334. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  335. &status);
  336. mthca_free_icm(dev, table->icm[i], table->coherent);
  337. }
  338. kfree(table);
  339. return NULL;
  340. }
  341. void mthca_free_icm_table(struct mthca_dev *dev, struct mthca_icm_table *table)
  342. {
  343. int i;
  344. u8 status;
  345. for (i = 0; i < table->num_icm; ++i)
  346. if (table->icm[i]) {
  347. mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  348. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  349. &status);
  350. mthca_free_icm(dev, table->icm[i], table->coherent);
  351. }
  352. kfree(table);
  353. }
  354. static u64 mthca_uarc_virt(struct mthca_dev *dev, struct mthca_uar *uar, int page)
  355. {
  356. return dev->uar_table.uarc_base +
  357. uar->index * dev->uar_table.uarc_size +
  358. page * MTHCA_ICM_PAGE_SIZE;
  359. }
  360. int mthca_map_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
  361. struct mthca_user_db_table *db_tab, int index, u64 uaddr)
  362. {
  363. int ret = 0;
  364. u8 status;
  365. int i;
  366. if (!mthca_is_memfree(dev))
  367. return 0;
  368. if (index < 0 || index > dev->uar_table.uarc_size / 8)
  369. return -EINVAL;
  370. mutex_lock(&db_tab->mutex);
  371. i = index / MTHCA_DB_REC_PER_PAGE;
  372. if ((db_tab->page[i].refcount >= MTHCA_DB_REC_PER_PAGE) ||
  373. (db_tab->page[i].uvirt && db_tab->page[i].uvirt != uaddr) ||
  374. (uaddr & 4095)) {
  375. ret = -EINVAL;
  376. goto out;
  377. }
  378. if (db_tab->page[i].refcount) {
  379. ++db_tab->page[i].refcount;
  380. goto out;
  381. }
  382. ret = get_user_pages(current, current->mm, uaddr & PAGE_MASK, 1, 1, 0,
  383. &db_tab->page[i].mem.page, NULL);
  384. if (ret < 0)
  385. goto out;
  386. db_tab->page[i].mem.length = MTHCA_ICM_PAGE_SIZE;
  387. db_tab->page[i].mem.offset = uaddr & ~PAGE_MASK;
  388. ret = pci_map_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  389. if (ret < 0) {
  390. put_page(db_tab->page[i].mem.page);
  391. goto out;
  392. }
  393. ret = mthca_MAP_ICM_page(dev, sg_dma_address(&db_tab->page[i].mem),
  394. mthca_uarc_virt(dev, uar, i), &status);
  395. if (!ret && status)
  396. ret = -EINVAL;
  397. if (ret) {
  398. pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  399. put_page(db_tab->page[i].mem.page);
  400. goto out;
  401. }
  402. db_tab->page[i].uvirt = uaddr;
  403. db_tab->page[i].refcount = 1;
  404. out:
  405. mutex_unlock(&db_tab->mutex);
  406. return ret;
  407. }
  408. void mthca_unmap_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
  409. struct mthca_user_db_table *db_tab, int index)
  410. {
  411. if (!mthca_is_memfree(dev))
  412. return;
  413. /*
  414. * To make our bookkeeping simpler, we don't unmap DB
  415. * pages until we clean up the whole db table.
  416. */
  417. mutex_lock(&db_tab->mutex);
  418. --db_tab->page[index / MTHCA_DB_REC_PER_PAGE].refcount;
  419. mutex_unlock(&db_tab->mutex);
  420. }
  421. struct mthca_user_db_table *mthca_init_user_db_tab(struct mthca_dev *dev)
  422. {
  423. struct mthca_user_db_table *db_tab;
  424. int npages;
  425. int i;
  426. if (!mthca_is_memfree(dev))
  427. return NULL;
  428. npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
  429. db_tab = kmalloc(sizeof *db_tab + npages * sizeof *db_tab->page, GFP_KERNEL);
  430. if (!db_tab)
  431. return ERR_PTR(-ENOMEM);
  432. mutex_init(&db_tab->mutex);
  433. for (i = 0; i < npages; ++i) {
  434. db_tab->page[i].refcount = 0;
  435. db_tab->page[i].uvirt = 0;
  436. }
  437. return db_tab;
  438. }
  439. void mthca_cleanup_user_db_tab(struct mthca_dev *dev, struct mthca_uar *uar,
  440. struct mthca_user_db_table *db_tab)
  441. {
  442. int i;
  443. u8 status;
  444. if (!mthca_is_memfree(dev))
  445. return;
  446. for (i = 0; i < dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE; ++i) {
  447. if (db_tab->page[i].uvirt) {
  448. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, uar, i), 1, &status);
  449. pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  450. put_page(db_tab->page[i].mem.page);
  451. }
  452. }
  453. kfree(db_tab);
  454. }
  455. int mthca_alloc_db(struct mthca_dev *dev, enum mthca_db_type type,
  456. u32 qn, __be32 **db)
  457. {
  458. int group;
  459. int start, end, dir;
  460. int i, j;
  461. struct mthca_db_page *page;
  462. int ret = 0;
  463. u8 status;
  464. mutex_lock(&dev->db_tab->mutex);
  465. switch (type) {
  466. case MTHCA_DB_TYPE_CQ_ARM:
  467. case MTHCA_DB_TYPE_SQ:
  468. group = 0;
  469. start = 0;
  470. end = dev->db_tab->max_group1;
  471. dir = 1;
  472. break;
  473. case MTHCA_DB_TYPE_CQ_SET_CI:
  474. case MTHCA_DB_TYPE_RQ:
  475. case MTHCA_DB_TYPE_SRQ:
  476. group = 1;
  477. start = dev->db_tab->npages - 1;
  478. end = dev->db_tab->min_group2;
  479. dir = -1;
  480. break;
  481. default:
  482. ret = -EINVAL;
  483. goto out;
  484. }
  485. for (i = start; i != end; i += dir)
  486. if (dev->db_tab->page[i].db_rec &&
  487. !bitmap_full(dev->db_tab->page[i].used,
  488. MTHCA_DB_REC_PER_PAGE)) {
  489. page = dev->db_tab->page + i;
  490. goto found;
  491. }
  492. for (i = start; i != end; i += dir)
  493. if (!dev->db_tab->page[i].db_rec) {
  494. page = dev->db_tab->page + i;
  495. goto alloc;
  496. }
  497. if (dev->db_tab->max_group1 >= dev->db_tab->min_group2 - 1) {
  498. ret = -ENOMEM;
  499. goto out;
  500. }
  501. if (group == 0)
  502. ++dev->db_tab->max_group1;
  503. else
  504. --dev->db_tab->min_group2;
  505. page = dev->db_tab->page + end;
  506. alloc:
  507. page->db_rec = dma_alloc_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  508. &page->mapping, GFP_KERNEL);
  509. if (!page->db_rec) {
  510. ret = -ENOMEM;
  511. goto out;
  512. }
  513. memset(page->db_rec, 0, MTHCA_ICM_PAGE_SIZE);
  514. ret = mthca_MAP_ICM_page(dev, page->mapping,
  515. mthca_uarc_virt(dev, &dev->driver_uar, i), &status);
  516. if (!ret && status)
  517. ret = -EINVAL;
  518. if (ret) {
  519. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  520. page->db_rec, page->mapping);
  521. goto out;
  522. }
  523. bitmap_zero(page->used, MTHCA_DB_REC_PER_PAGE);
  524. found:
  525. j = find_first_zero_bit(page->used, MTHCA_DB_REC_PER_PAGE);
  526. set_bit(j, page->used);
  527. if (group == 1)
  528. j = MTHCA_DB_REC_PER_PAGE - 1 - j;
  529. ret = i * MTHCA_DB_REC_PER_PAGE + j;
  530. page->db_rec[j] = cpu_to_be64((qn << 8) | (type << 5));
  531. *db = (__be32 *) &page->db_rec[j];
  532. out:
  533. mutex_unlock(&dev->db_tab->mutex);
  534. return ret;
  535. }
  536. void mthca_free_db(struct mthca_dev *dev, int type, int db_index)
  537. {
  538. int i, j;
  539. struct mthca_db_page *page;
  540. u8 status;
  541. i = db_index / MTHCA_DB_REC_PER_PAGE;
  542. j = db_index % MTHCA_DB_REC_PER_PAGE;
  543. page = dev->db_tab->page + i;
  544. mutex_lock(&dev->db_tab->mutex);
  545. page->db_rec[j] = 0;
  546. if (i >= dev->db_tab->min_group2)
  547. j = MTHCA_DB_REC_PER_PAGE - 1 - j;
  548. clear_bit(j, page->used);
  549. if (bitmap_empty(page->used, MTHCA_DB_REC_PER_PAGE) &&
  550. i >= dev->db_tab->max_group1 - 1) {
  551. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1, &status);
  552. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  553. page->db_rec, page->mapping);
  554. page->db_rec = NULL;
  555. if (i == dev->db_tab->max_group1) {
  556. --dev->db_tab->max_group1;
  557. /* XXX may be able to unmap more pages now */
  558. }
  559. if (i == dev->db_tab->min_group2)
  560. ++dev->db_tab->min_group2;
  561. }
  562. mutex_unlock(&dev->db_tab->mutex);
  563. }
  564. int mthca_init_db_tab(struct mthca_dev *dev)
  565. {
  566. int i;
  567. if (!mthca_is_memfree(dev))
  568. return 0;
  569. dev->db_tab = kmalloc(sizeof *dev->db_tab, GFP_KERNEL);
  570. if (!dev->db_tab)
  571. return -ENOMEM;
  572. mutex_init(&dev->db_tab->mutex);
  573. dev->db_tab->npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
  574. dev->db_tab->max_group1 = 0;
  575. dev->db_tab->min_group2 = dev->db_tab->npages - 1;
  576. dev->db_tab->page = kmalloc(dev->db_tab->npages *
  577. sizeof *dev->db_tab->page,
  578. GFP_KERNEL);
  579. if (!dev->db_tab->page) {
  580. kfree(dev->db_tab);
  581. return -ENOMEM;
  582. }
  583. for (i = 0; i < dev->db_tab->npages; ++i)
  584. dev->db_tab->page[i].db_rec = NULL;
  585. return 0;
  586. }
  587. void mthca_cleanup_db_tab(struct mthca_dev *dev)
  588. {
  589. int i;
  590. u8 status;
  591. if (!mthca_is_memfree(dev))
  592. return;
  593. /*
  594. * Because we don't always free our UARC pages when they
  595. * become empty to make mthca_free_db() simpler we need to
  596. * make a sweep through the doorbell pages and free any
  597. * leftover pages now.
  598. */
  599. for (i = 0; i < dev->db_tab->npages; ++i) {
  600. if (!dev->db_tab->page[i].db_rec)
  601. continue;
  602. if (!bitmap_empty(dev->db_tab->page[i].used, MTHCA_DB_REC_PER_PAGE))
  603. mthca_warn(dev, "Kernel UARC page %d not empty\n", i);
  604. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1, &status);
  605. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  606. dev->db_tab->page[i].db_rec,
  607. dev->db_tab->page[i].mapping);
  608. }
  609. kfree(dev->db_tab->page);
  610. kfree(dev->db_tab);
  611. }