ucb1x00-core.c 19 KB

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  1. /*
  2. * linux/drivers/mfd/ucb1x00-core.c
  3. *
  4. * Copyright (C) 2001 Russell King, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License.
  9. *
  10. * The UCB1x00 core driver provides basic services for handling IO,
  11. * the ADC, interrupts, and accessing registers. It is designed
  12. * such that everything goes through this layer, thereby providing
  13. * a consistent locking methodology, as well as allowing the drivers
  14. * to be used on other non-MCP-enabled hardware platforms.
  15. *
  16. * Note that all locks are private to this file. Nothing else may
  17. * touch them.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/kernel.h>
  21. #include <linux/sched.h>
  22. #include <linux/slab.h>
  23. #include <linux/init.h>
  24. #include <linux/errno.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/device.h>
  27. #include <linux/mutex.h>
  28. #include <linux/mfd/ucb1x00.h>
  29. #include <linux/gpio.h>
  30. static DEFINE_MUTEX(ucb1x00_mutex);
  31. static LIST_HEAD(ucb1x00_drivers);
  32. static LIST_HEAD(ucb1x00_devices);
  33. /**
  34. * ucb1x00_io_set_dir - set IO direction
  35. * @ucb: UCB1x00 structure describing chip
  36. * @in: bitfield of IO pins to be set as inputs
  37. * @out: bitfield of IO pins to be set as outputs
  38. *
  39. * Set the IO direction of the ten general purpose IO pins on
  40. * the UCB1x00 chip. The @in bitfield has priority over the
  41. * @out bitfield, in that if you specify a pin as both input
  42. * and output, it will end up as an input.
  43. *
  44. * ucb1x00_enable must have been called to enable the comms
  45. * before using this function.
  46. *
  47. * This function takes a spinlock, disabling interrupts.
  48. */
  49. void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out)
  50. {
  51. unsigned long flags;
  52. spin_lock_irqsave(&ucb->io_lock, flags);
  53. ucb->io_dir |= out;
  54. ucb->io_dir &= ~in;
  55. ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
  56. spin_unlock_irqrestore(&ucb->io_lock, flags);
  57. }
  58. /**
  59. * ucb1x00_io_write - set or clear IO outputs
  60. * @ucb: UCB1x00 structure describing chip
  61. * @set: bitfield of IO pins to set to logic '1'
  62. * @clear: bitfield of IO pins to set to logic '0'
  63. *
  64. * Set the IO output state of the specified IO pins. The value
  65. * is retained if the pins are subsequently configured as inputs.
  66. * The @clear bitfield has priority over the @set bitfield -
  67. * outputs will be cleared.
  68. *
  69. * ucb1x00_enable must have been called to enable the comms
  70. * before using this function.
  71. *
  72. * This function takes a spinlock, disabling interrupts.
  73. */
  74. void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear)
  75. {
  76. unsigned long flags;
  77. spin_lock_irqsave(&ucb->io_lock, flags);
  78. ucb->io_out |= set;
  79. ucb->io_out &= ~clear;
  80. ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
  81. spin_unlock_irqrestore(&ucb->io_lock, flags);
  82. }
  83. /**
  84. * ucb1x00_io_read - read the current state of the IO pins
  85. * @ucb: UCB1x00 structure describing chip
  86. *
  87. * Return a bitfield describing the logic state of the ten
  88. * general purpose IO pins.
  89. *
  90. * ucb1x00_enable must have been called to enable the comms
  91. * before using this function.
  92. *
  93. * This function does not take any mutexes or spinlocks.
  94. */
  95. unsigned int ucb1x00_io_read(struct ucb1x00 *ucb)
  96. {
  97. return ucb1x00_reg_read(ucb, UCB_IO_DATA);
  98. }
  99. static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  100. {
  101. struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
  102. unsigned long flags;
  103. spin_lock_irqsave(&ucb->io_lock, flags);
  104. if (value)
  105. ucb->io_out |= 1 << offset;
  106. else
  107. ucb->io_out &= ~(1 << offset);
  108. ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
  109. spin_unlock_irqrestore(&ucb->io_lock, flags);
  110. }
  111. static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset)
  112. {
  113. struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
  114. return ucb1x00_reg_read(ucb, UCB_IO_DATA) & (1 << offset);
  115. }
  116. static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  117. {
  118. struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
  119. unsigned long flags;
  120. spin_lock_irqsave(&ucb->io_lock, flags);
  121. ucb->io_dir &= ~(1 << offset);
  122. ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
  123. spin_unlock_irqrestore(&ucb->io_lock, flags);
  124. return 0;
  125. }
  126. static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset
  127. , int value)
  128. {
  129. struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
  130. unsigned long flags;
  131. unsigned old, mask = 1 << offset;
  132. spin_lock_irqsave(&ucb->io_lock, flags);
  133. old = ucb->io_out;
  134. if (value)
  135. ucb->io_out |= mask;
  136. else
  137. ucb->io_out &= ~mask;
  138. if (old != ucb->io_out)
  139. ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
  140. if (!(ucb->io_dir & mask)) {
  141. ucb->io_dir |= mask;
  142. ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
  143. }
  144. spin_unlock_irqrestore(&ucb->io_lock, flags);
  145. return 0;
  146. }
  147. /*
  148. * UCB1300 data sheet says we must:
  149. * 1. enable ADC => 5us (including reference startup time)
  150. * 2. select input => 51*tsibclk => 4.3us
  151. * 3. start conversion => 102*tsibclk => 8.5us
  152. * (tsibclk = 1/11981000)
  153. * Period between SIB 128-bit frames = 10.7us
  154. */
  155. /**
  156. * ucb1x00_adc_enable - enable the ADC converter
  157. * @ucb: UCB1x00 structure describing chip
  158. *
  159. * Enable the ucb1x00 and ADC converter on the UCB1x00 for use.
  160. * Any code wishing to use the ADC converter must call this
  161. * function prior to using it.
  162. *
  163. * This function takes the ADC mutex to prevent two or more
  164. * concurrent uses, and therefore may sleep. As a result, it
  165. * can only be called from process context, not interrupt
  166. * context.
  167. *
  168. * You should release the ADC as soon as possible using
  169. * ucb1x00_adc_disable.
  170. */
  171. void ucb1x00_adc_enable(struct ucb1x00 *ucb)
  172. {
  173. mutex_lock(&ucb->adc_mutex);
  174. ucb->adc_cr |= UCB_ADC_ENA;
  175. ucb1x00_enable(ucb);
  176. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
  177. }
  178. /**
  179. * ucb1x00_adc_read - read the specified ADC channel
  180. * @ucb: UCB1x00 structure describing chip
  181. * @adc_channel: ADC channel mask
  182. * @sync: wait for syncronisation pulse.
  183. *
  184. * Start an ADC conversion and wait for the result. Note that
  185. * synchronised ADC conversions (via the ADCSYNC pin) must wait
  186. * until the trigger is asserted and the conversion is finished.
  187. *
  188. * This function currently spins waiting for the conversion to
  189. * complete (2 frames max without sync).
  190. *
  191. * If called for a synchronised ADC conversion, it may sleep
  192. * with the ADC mutex held.
  193. */
  194. unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
  195. {
  196. unsigned int val;
  197. if (sync)
  198. adc_channel |= UCB_ADC_SYNC_ENA;
  199. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel);
  200. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START);
  201. for (;;) {
  202. val = ucb1x00_reg_read(ucb, UCB_ADC_DATA);
  203. if (val & UCB_ADC_DAT_VAL)
  204. break;
  205. /* yield to other processes */
  206. set_current_state(TASK_INTERRUPTIBLE);
  207. schedule_timeout(1);
  208. }
  209. return UCB_ADC_DAT(val);
  210. }
  211. /**
  212. * ucb1x00_adc_disable - disable the ADC converter
  213. * @ucb: UCB1x00 structure describing chip
  214. *
  215. * Disable the ADC converter and release the ADC mutex.
  216. */
  217. void ucb1x00_adc_disable(struct ucb1x00 *ucb)
  218. {
  219. ucb->adc_cr &= ~UCB_ADC_ENA;
  220. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
  221. ucb1x00_disable(ucb);
  222. mutex_unlock(&ucb->adc_mutex);
  223. }
  224. /*
  225. * UCB1x00 Interrupt handling.
  226. *
  227. * The UCB1x00 can generate interrupts when the SIBCLK is stopped.
  228. * Since we need to read an internal register, we must re-enable
  229. * SIBCLK to talk to the chip. We leave the clock running until
  230. * we have finished processing all interrupts from the chip.
  231. */
  232. static irqreturn_t ucb1x00_irq(int irqnr, void *devid)
  233. {
  234. struct ucb1x00 *ucb = devid;
  235. struct ucb1x00_irq *irq;
  236. unsigned int isr, i;
  237. ucb1x00_enable(ucb);
  238. isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
  239. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
  240. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  241. for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++)
  242. if (isr & 1 && irq->fn)
  243. irq->fn(i, irq->devid);
  244. ucb1x00_disable(ucb);
  245. return IRQ_HANDLED;
  246. }
  247. /**
  248. * ucb1x00_hook_irq - hook a UCB1x00 interrupt
  249. * @ucb: UCB1x00 structure describing chip
  250. * @idx: interrupt index
  251. * @fn: function to call when interrupt is triggered
  252. * @devid: device id to pass to interrupt handler
  253. *
  254. * Hook the specified interrupt. You can only register one handler
  255. * for each interrupt source. The interrupt source is not enabled
  256. * by this function; use ucb1x00_enable_irq instead.
  257. *
  258. * Interrupt handlers will be called with other interrupts enabled.
  259. *
  260. * Returns zero on success, or one of the following errors:
  261. * -EINVAL if the interrupt index is invalid
  262. * -EBUSY if the interrupt has already been hooked
  263. */
  264. int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid)
  265. {
  266. struct ucb1x00_irq *irq;
  267. int ret = -EINVAL;
  268. if (idx < 16) {
  269. irq = ucb->irq_handler + idx;
  270. ret = -EBUSY;
  271. spin_lock_irq(&ucb->lock);
  272. if (irq->fn == NULL) {
  273. irq->devid = devid;
  274. irq->fn = fn;
  275. ret = 0;
  276. }
  277. spin_unlock_irq(&ucb->lock);
  278. }
  279. return ret;
  280. }
  281. /**
  282. * ucb1x00_enable_irq - enable an UCB1x00 interrupt source
  283. * @ucb: UCB1x00 structure describing chip
  284. * @idx: interrupt index
  285. * @edges: interrupt edges to enable
  286. *
  287. * Enable the specified interrupt to trigger on %UCB_RISING,
  288. * %UCB_FALLING or both edges. The interrupt should have been
  289. * hooked by ucb1x00_hook_irq.
  290. */
  291. void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
  292. {
  293. unsigned long flags;
  294. if (idx < 16) {
  295. spin_lock_irqsave(&ucb->lock, flags);
  296. ucb1x00_enable(ucb);
  297. if (edges & UCB_RISING) {
  298. ucb->irq_ris_enbl |= 1 << idx;
  299. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  300. }
  301. if (edges & UCB_FALLING) {
  302. ucb->irq_fal_enbl |= 1 << idx;
  303. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  304. }
  305. ucb1x00_disable(ucb);
  306. spin_unlock_irqrestore(&ucb->lock, flags);
  307. }
  308. }
  309. /**
  310. * ucb1x00_disable_irq - disable an UCB1x00 interrupt source
  311. * @ucb: UCB1x00 structure describing chip
  312. * @edges: interrupt edges to disable
  313. *
  314. * Disable the specified interrupt triggering on the specified
  315. * (%UCB_RISING, %UCB_FALLING or both) edges.
  316. */
  317. void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
  318. {
  319. unsigned long flags;
  320. if (idx < 16) {
  321. spin_lock_irqsave(&ucb->lock, flags);
  322. ucb1x00_enable(ucb);
  323. if (edges & UCB_RISING) {
  324. ucb->irq_ris_enbl &= ~(1 << idx);
  325. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  326. }
  327. if (edges & UCB_FALLING) {
  328. ucb->irq_fal_enbl &= ~(1 << idx);
  329. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  330. }
  331. ucb1x00_disable(ucb);
  332. spin_unlock_irqrestore(&ucb->lock, flags);
  333. }
  334. }
  335. /**
  336. * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt
  337. * @ucb: UCB1x00 structure describing chip
  338. * @idx: interrupt index
  339. * @devid: device id.
  340. *
  341. * Disable the interrupt source and remove the handler. devid must
  342. * match the devid passed when hooking the interrupt.
  343. *
  344. * Returns zero on success, or one of the following errors:
  345. * -EINVAL if the interrupt index is invalid
  346. * -ENOENT if devid does not match
  347. */
  348. int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid)
  349. {
  350. struct ucb1x00_irq *irq;
  351. int ret;
  352. if (idx >= 16)
  353. goto bad;
  354. irq = ucb->irq_handler + idx;
  355. ret = -ENOENT;
  356. spin_lock_irq(&ucb->lock);
  357. if (irq->devid == devid) {
  358. ucb->irq_ris_enbl &= ~(1 << idx);
  359. ucb->irq_fal_enbl &= ~(1 << idx);
  360. ucb1x00_enable(ucb);
  361. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  362. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  363. ucb1x00_disable(ucb);
  364. irq->fn = NULL;
  365. irq->devid = NULL;
  366. ret = 0;
  367. }
  368. spin_unlock_irq(&ucb->lock);
  369. return ret;
  370. bad:
  371. printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx);
  372. return -EINVAL;
  373. }
  374. static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv)
  375. {
  376. struct ucb1x00_dev *dev;
  377. int ret = -ENOMEM;
  378. dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL);
  379. if (dev) {
  380. dev->ucb = ucb;
  381. dev->drv = drv;
  382. ret = drv->add(dev);
  383. if (ret == 0) {
  384. list_add(&dev->dev_node, &ucb->devs);
  385. list_add(&dev->drv_node, &drv->devs);
  386. } else {
  387. kfree(dev);
  388. }
  389. }
  390. return ret;
  391. }
  392. static void ucb1x00_remove_dev(struct ucb1x00_dev *dev)
  393. {
  394. dev->drv->remove(dev);
  395. list_del(&dev->dev_node);
  396. list_del(&dev->drv_node);
  397. kfree(dev);
  398. }
  399. /*
  400. * Try to probe our interrupt, rather than relying on lots of
  401. * hard-coded machine dependencies. For reference, the expected
  402. * IRQ mappings are:
  403. *
  404. * Machine Default IRQ
  405. * adsbitsy IRQ_GPCIN4
  406. * cerf IRQ_GPIO_UCB1200_IRQ
  407. * flexanet IRQ_GPIO_GUI
  408. * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ
  409. * graphicsclient ADS_EXT_IRQ(8)
  410. * graphicsmaster ADS_EXT_IRQ(8)
  411. * lart LART_IRQ_UCB1200
  412. * omnimeter IRQ_GPIO23
  413. * pfs168 IRQ_GPIO_UCB1300_IRQ
  414. * simpad IRQ_GPIO_UCB1300_IRQ
  415. * shannon SHANNON_IRQ_GPIO_IRQ_CODEC
  416. * yopy IRQ_GPIO_UCB1200_IRQ
  417. */
  418. static int ucb1x00_detect_irq(struct ucb1x00 *ucb)
  419. {
  420. unsigned long mask;
  421. mask = probe_irq_on();
  422. if (!mask) {
  423. probe_irq_off(mask);
  424. return NO_IRQ;
  425. }
  426. /*
  427. * Enable the ADC interrupt.
  428. */
  429. ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
  430. ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
  431. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  432. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  433. /*
  434. * Cause an ADC interrupt.
  435. */
  436. ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  437. ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
  438. /*
  439. * Wait for the conversion to complete.
  440. */
  441. while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0);
  442. ucb1x00_reg_write(ucb, UCB_ADC_CR, 0);
  443. /*
  444. * Disable and clear interrupt.
  445. */
  446. ucb1x00_reg_write(ucb, UCB_IE_RIS, 0);
  447. ucb1x00_reg_write(ucb, UCB_IE_FAL, 0);
  448. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  449. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  450. /*
  451. * Read triggered interrupt.
  452. */
  453. return probe_irq_off(mask);
  454. }
  455. static void ucb1x00_release(struct device *dev)
  456. {
  457. struct ucb1x00 *ucb = classdev_to_ucb1x00(dev);
  458. kfree(ucb);
  459. }
  460. static struct class ucb1x00_class = {
  461. .name = "ucb1x00",
  462. .dev_release = ucb1x00_release,
  463. };
  464. static int ucb1x00_probe(struct mcp *mcp)
  465. {
  466. struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data;
  467. struct ucb1x00_driver *drv;
  468. struct ucb1x00 *ucb;
  469. unsigned int id;
  470. int ret = -ENODEV;
  471. int temp;
  472. /* Tell the platform to deassert the UCB1x00 reset */
  473. if (pdata && pdata->reset)
  474. pdata->reset(UCB_RST_PROBE);
  475. mcp_enable(mcp);
  476. id = mcp_reg_read(mcp, UCB_ID);
  477. if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) {
  478. printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id);
  479. goto err_disable;
  480. }
  481. ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL);
  482. ret = -ENOMEM;
  483. if (!ucb)
  484. goto err_disable;
  485. ucb->dev.class = &ucb1x00_class;
  486. ucb->dev.parent = &mcp->attached_device;
  487. dev_set_name(&ucb->dev, "ucb1x00");
  488. spin_lock_init(&ucb->lock);
  489. spin_lock_init(&ucb->io_lock);
  490. mutex_init(&ucb->adc_mutex);
  491. ucb->id = id;
  492. ucb->mcp = mcp;
  493. ucb->irq = ucb1x00_detect_irq(ucb);
  494. if (ucb->irq == NO_IRQ) {
  495. printk(KERN_ERR "UCB1x00: IRQ probe failed\n");
  496. ret = -ENODEV;
  497. goto err_free;
  498. }
  499. ucb->gpio.base = -1;
  500. if (pdata && pdata->gpio_base) {
  501. ucb->gpio.label = dev_name(&ucb->dev);
  502. ucb->gpio.base = pdata->gpio_base;
  503. ucb->gpio.ngpio = 10;
  504. ucb->gpio.set = ucb1x00_gpio_set;
  505. ucb->gpio.get = ucb1x00_gpio_get;
  506. ucb->gpio.direction_input = ucb1x00_gpio_direction_input;
  507. ucb->gpio.direction_output = ucb1x00_gpio_direction_output;
  508. ret = gpiochip_add(&ucb->gpio);
  509. if (ret)
  510. goto err_free;
  511. } else
  512. dev_info(&ucb->dev, "gpio_base not set so no gpiolib support");
  513. ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING,
  514. "UCB1x00", ucb);
  515. if (ret) {
  516. printk(KERN_ERR "ucb1x00: unable to grab irq%d: %d\n",
  517. ucb->irq, ret);
  518. goto err_gpio;
  519. }
  520. mcp_set_drvdata(mcp, ucb);
  521. ret = device_register(&ucb->dev);
  522. if (ret)
  523. goto err_irq;
  524. INIT_LIST_HEAD(&ucb->devs);
  525. mutex_lock(&ucb1x00_mutex);
  526. list_add(&ucb->node, &ucb1x00_devices);
  527. list_for_each_entry(drv, &ucb1x00_drivers, node) {
  528. ucb1x00_add_dev(ucb, drv);
  529. }
  530. mutex_unlock(&ucb1x00_mutex);
  531. return ret;
  532. err_irq:
  533. free_irq(ucb->irq, ucb);
  534. err_gpio:
  535. if (ucb->gpio.base != -1)
  536. temp = gpiochip_remove(&ucb->gpio);
  537. err_free:
  538. kfree(ucb);
  539. err_disable:
  540. mcp_disable(mcp);
  541. out:
  542. if (pdata && pdata->reset)
  543. pdata->reset(UCB_RST_PROBE_FAIL);
  544. return ret;
  545. }
  546. static void ucb1x00_remove(struct mcp *mcp)
  547. {
  548. struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data;
  549. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  550. struct list_head *l, *n;
  551. int ret;
  552. mutex_lock(&ucb1x00_mutex);
  553. list_del(&ucb->node);
  554. list_for_each_safe(l, n, &ucb->devs) {
  555. struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node);
  556. ucb1x00_remove_dev(dev);
  557. }
  558. mutex_unlock(&ucb1x00_mutex);
  559. if (ucb->gpio.base != -1) {
  560. ret = gpiochip_remove(&ucb->gpio);
  561. if (ret)
  562. dev_err(&ucb->dev, "Can't remove gpio chip: %d\n", ret);
  563. }
  564. free_irq(ucb->irq, ucb);
  565. device_unregister(&ucb->dev);
  566. if (pdata && pdata->reset)
  567. pdata->reset(UCB_RST_REMOVE);
  568. }
  569. int ucb1x00_register_driver(struct ucb1x00_driver *drv)
  570. {
  571. struct ucb1x00 *ucb;
  572. INIT_LIST_HEAD(&drv->devs);
  573. mutex_lock(&ucb1x00_mutex);
  574. list_add(&drv->node, &ucb1x00_drivers);
  575. list_for_each_entry(ucb, &ucb1x00_devices, node) {
  576. ucb1x00_add_dev(ucb, drv);
  577. }
  578. mutex_unlock(&ucb1x00_mutex);
  579. return 0;
  580. }
  581. void ucb1x00_unregister_driver(struct ucb1x00_driver *drv)
  582. {
  583. struct list_head *n, *l;
  584. mutex_lock(&ucb1x00_mutex);
  585. list_del(&drv->node);
  586. list_for_each_safe(l, n, &drv->devs) {
  587. struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node);
  588. ucb1x00_remove_dev(dev);
  589. }
  590. mutex_unlock(&ucb1x00_mutex);
  591. }
  592. static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state)
  593. {
  594. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  595. struct ucb1x00_dev *dev;
  596. mutex_lock(&ucb1x00_mutex);
  597. list_for_each_entry(dev, &ucb->devs, dev_node) {
  598. if (dev->drv->suspend)
  599. dev->drv->suspend(dev, state);
  600. }
  601. mutex_unlock(&ucb1x00_mutex);
  602. return 0;
  603. }
  604. static int ucb1x00_resume(struct mcp *mcp)
  605. {
  606. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  607. struct ucb1x00_dev *dev;
  608. ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
  609. ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
  610. mutex_lock(&ucb1x00_mutex);
  611. list_for_each_entry(dev, &ucb->devs, dev_node) {
  612. if (dev->drv->resume)
  613. dev->drv->resume(dev);
  614. }
  615. mutex_unlock(&ucb1x00_mutex);
  616. return 0;
  617. }
  618. static struct mcp_driver ucb1x00_driver = {
  619. .drv = {
  620. .name = "ucb1x00",
  621. .owner = THIS_MODULE,
  622. },
  623. .probe = ucb1x00_probe,
  624. .remove = ucb1x00_remove,
  625. .suspend = ucb1x00_suspend,
  626. .resume = ucb1x00_resume,
  627. };
  628. static int __init ucb1x00_init(void)
  629. {
  630. int ret = class_register(&ucb1x00_class);
  631. if (ret == 0) {
  632. ret = mcp_driver_register(&ucb1x00_driver);
  633. if (ret)
  634. class_unregister(&ucb1x00_class);
  635. }
  636. return ret;
  637. }
  638. static void __exit ucb1x00_exit(void)
  639. {
  640. mcp_driver_unregister(&ucb1x00_driver);
  641. class_unregister(&ucb1x00_class);
  642. }
  643. module_init(ucb1x00_init);
  644. module_exit(ucb1x00_exit);
  645. EXPORT_SYMBOL(ucb1x00_io_set_dir);
  646. EXPORT_SYMBOL(ucb1x00_io_write);
  647. EXPORT_SYMBOL(ucb1x00_io_read);
  648. EXPORT_SYMBOL(ucb1x00_adc_enable);
  649. EXPORT_SYMBOL(ucb1x00_adc_read);
  650. EXPORT_SYMBOL(ucb1x00_adc_disable);
  651. EXPORT_SYMBOL(ucb1x00_hook_irq);
  652. EXPORT_SYMBOL(ucb1x00_free_irq);
  653. EXPORT_SYMBOL(ucb1x00_enable_irq);
  654. EXPORT_SYMBOL(ucb1x00_disable_irq);
  655. EXPORT_SYMBOL(ucb1x00_register_driver);
  656. EXPORT_SYMBOL(ucb1x00_unregister_driver);
  657. MODULE_ALIAS("mcp:ucb1x00");
  658. MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
  659. MODULE_DESCRIPTION("UCB1x00 core driver");
  660. MODULE_LICENSE("GPL");