dhd_sdio.c 106 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/types.h>
  17. #include <linux/kernel.h>
  18. #include <linux/kthread.h>
  19. #include <linux/printk.h>
  20. #include <linux/pci_ids.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/sched.h>
  24. #include <linux/mmc/sdio.h>
  25. #include <linux/mmc/sdio_func.h>
  26. #include <linux/mmc/card.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/firmware.h>
  29. #include <linux/module.h>
  30. #include <linux/bcma/bcma.h>
  31. #include <asm/unaligned.h>
  32. #include <defs.h>
  33. #include <brcmu_wifi.h>
  34. #include <brcmu_utils.h>
  35. #include <brcm_hw_ids.h>
  36. #include <soc.h>
  37. #include "sdio_host.h"
  38. #include "sdio_chip.h"
  39. #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
  40. #ifdef BCMDBG
  41. #define BRCMF_TRAP_INFO_SIZE 80
  42. #define CBUF_LEN (128)
  43. struct rte_log_le {
  44. __le32 buf; /* Can't be pointer on (64-bit) hosts */
  45. __le32 buf_size;
  46. __le32 idx;
  47. char *_buf_compat; /* Redundant pointer for backward compat. */
  48. };
  49. struct rte_console {
  50. /* Virtual UART
  51. * When there is no UART (e.g. Quickturn),
  52. * the host should write a complete
  53. * input line directly into cbuf and then write
  54. * the length into vcons_in.
  55. * This may also be used when there is a real UART
  56. * (at risk of conflicting with
  57. * the real UART). vcons_out is currently unused.
  58. */
  59. uint vcons_in;
  60. uint vcons_out;
  61. /* Output (logging) buffer
  62. * Console output is written to a ring buffer log_buf at index log_idx.
  63. * The host may read the output when it sees log_idx advance.
  64. * Output will be lost if the output wraps around faster than the host
  65. * polls.
  66. */
  67. struct rte_log_le log_le;
  68. /* Console input line buffer
  69. * Characters are read one at a time into cbuf
  70. * until <CR> is received, then
  71. * the buffer is processed as a command line.
  72. * Also used for virtual UART.
  73. */
  74. uint cbuf_idx;
  75. char cbuf[CBUF_LEN];
  76. };
  77. #endif /* BCMDBG */
  78. #include <chipcommon.h>
  79. #include "dhd.h"
  80. #include "dhd_bus.h"
  81. #include "dhd_proto.h"
  82. #include "dhd_dbg.h"
  83. #define TXQLEN 2048 /* bulk tx queue length */
  84. #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
  85. #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
  86. #define PRIOMASK 7
  87. #define TXRETRIES 2 /* # of retries for tx frames */
  88. #define BRCMF_RXBOUND 50 /* Default for max rx frames in
  89. one scheduling */
  90. #define BRCMF_TXBOUND 20 /* Default for max tx frames in
  91. one scheduling */
  92. #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
  93. #define MEMBLOCK 2048 /* Block size used for downloading
  94. of dongle image */
  95. #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
  96. biggest possible glom */
  97. #define BRCMF_FIRSTREAD (1 << 6)
  98. /* SBSDIO_DEVICE_CTL */
  99. /* 1: device will assert busy signal when receiving CMD53 */
  100. #define SBSDIO_DEVCTL_SETBUSY 0x01
  101. /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
  102. #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
  103. /* 1: mask all interrupts to host except the chipActive (rev 8) */
  104. #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
  105. /* 1: isolate internal sdio signals, put external pads in tri-state; requires
  106. * sdio bus power cycle to clear (rev 9) */
  107. #define SBSDIO_DEVCTL_PADS_ISO 0x08
  108. /* Force SD->SB reset mapping (rev 11) */
  109. #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
  110. /* Determined by CoreControl bit */
  111. #define SBSDIO_DEVCTL_RST_CORECTL 0x00
  112. /* Force backplane reset */
  113. #define SBSDIO_DEVCTL_RST_BPRESET 0x10
  114. /* Force no backplane reset */
  115. #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
  116. /* direct(mapped) cis space */
  117. /* MAPPED common CIS address */
  118. #define SBSDIO_CIS_BASE_COMMON 0x1000
  119. /* maximum bytes in one CIS */
  120. #define SBSDIO_CIS_SIZE_LIMIT 0x200
  121. /* cis offset addr is < 17 bits */
  122. #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
  123. /* manfid tuple length, include tuple, link bytes */
  124. #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
  125. /* intstatus */
  126. #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
  127. #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
  128. #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
  129. #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
  130. #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
  131. #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
  132. #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
  133. #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
  134. #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
  135. #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
  136. #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
  137. #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
  138. #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
  139. #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
  140. #define I_PC (1 << 10) /* descriptor error */
  141. #define I_PD (1 << 11) /* data error */
  142. #define I_DE (1 << 12) /* Descriptor protocol Error */
  143. #define I_RU (1 << 13) /* Receive descriptor Underflow */
  144. #define I_RO (1 << 14) /* Receive fifo Overflow */
  145. #define I_XU (1 << 15) /* Transmit fifo Underflow */
  146. #define I_RI (1 << 16) /* Receive Interrupt */
  147. #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
  148. #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
  149. #define I_XI (1 << 24) /* Transmit Interrupt */
  150. #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
  151. #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
  152. #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
  153. #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
  154. #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
  155. #define I_SRESET (1 << 30) /* CCCR RES interrupt */
  156. #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
  157. #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
  158. #define I_DMA (I_RI | I_XI | I_ERRORS)
  159. /* corecontrol */
  160. #define CC_CISRDY (1 << 0) /* CIS Ready */
  161. #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
  162. #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
  163. #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
  164. #define CC_XMTDATAAVAIL_MODE (1 << 4)
  165. #define CC_XMTDATAAVAIL_CTRL (1 << 5)
  166. /* SDA_FRAMECTRL */
  167. #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
  168. #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
  169. #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
  170. #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
  171. /* HW frame tag */
  172. #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
  173. /* Total length of frame header for dongle protocol */
  174. #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
  175. #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
  176. /*
  177. * Software allocation of To SB Mailbox resources
  178. */
  179. /* tosbmailbox bits corresponding to intstatus bits */
  180. #define SMB_NAK (1 << 0) /* Frame NAK */
  181. #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
  182. #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
  183. #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
  184. /* tosbmailboxdata */
  185. #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
  186. /*
  187. * Software allocation of To Host Mailbox resources
  188. */
  189. /* intstatus bits */
  190. #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
  191. #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
  192. #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
  193. #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
  194. /* tohostmailboxdata */
  195. #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
  196. #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
  197. #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
  198. #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
  199. #define HMB_DATA_FCDATA_MASK 0xff000000
  200. #define HMB_DATA_FCDATA_SHIFT 24
  201. #define HMB_DATA_VERSION_MASK 0x00ff0000
  202. #define HMB_DATA_VERSION_SHIFT 16
  203. /*
  204. * Software-defined protocol header
  205. */
  206. /* Current protocol version */
  207. #define SDPCM_PROT_VERSION 4
  208. /* SW frame header */
  209. #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
  210. #define SDPCM_CHANNEL_MASK 0x00000f00
  211. #define SDPCM_CHANNEL_SHIFT 8
  212. #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
  213. #define SDPCM_NEXTLEN_OFFSET 2
  214. /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
  215. #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
  216. #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
  217. #define SDPCM_DOFFSET_MASK 0xff000000
  218. #define SDPCM_DOFFSET_SHIFT 24
  219. #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
  220. #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
  221. #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
  222. #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
  223. #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
  224. /* logical channel numbers */
  225. #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
  226. #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
  227. #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
  228. #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
  229. #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
  230. #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
  231. #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
  232. /*
  233. * Shared structure between dongle and the host.
  234. * The structure contains pointers to trap or assert information.
  235. */
  236. #define SDPCM_SHARED_VERSION 0x0002
  237. #define SDPCM_SHARED_VERSION_MASK 0x00FF
  238. #define SDPCM_SHARED_ASSERT_BUILT 0x0100
  239. #define SDPCM_SHARED_ASSERT 0x0200
  240. #define SDPCM_SHARED_TRAP 0x0400
  241. /* Space for header read, limit for data packets */
  242. #define MAX_HDR_READ (1 << 6)
  243. #define MAX_RX_DATASZ 2048
  244. /* Maximum milliseconds to wait for F2 to come up */
  245. #define BRCMF_WAIT_F2RDY 3000
  246. /* Bump up limit on waiting for HT to account for first startup;
  247. * if the image is doing a CRC calculation before programming the PMU
  248. * for HT availability, it could take a couple hundred ms more, so
  249. * max out at a 1 second (1000000us).
  250. */
  251. #undef PMU_MAX_TRANSITION_DLY
  252. #define PMU_MAX_TRANSITION_DLY 1000000
  253. /* Value for ChipClockCSR during initial setup */
  254. #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
  255. SBSDIO_ALP_AVAIL_REQ)
  256. /* Flags for SDH calls */
  257. #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
  258. #define BRCMFMAC_FW_NAME "brcm/brcmfmac.bin"
  259. #define BRCMFMAC_NV_NAME "brcm/brcmfmac.txt"
  260. MODULE_FIRMWARE(BRCMFMAC_FW_NAME);
  261. MODULE_FIRMWARE(BRCMFMAC_NV_NAME);
  262. /*
  263. * Conversion of 802.1D priority to precedence level
  264. */
  265. static uint prio2prec(u32 prio)
  266. {
  267. return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
  268. (prio^2) : prio;
  269. }
  270. /* core registers */
  271. struct sdpcmd_regs {
  272. u32 corecontrol; /* 0x00, rev8 */
  273. u32 corestatus; /* rev8 */
  274. u32 PAD[1];
  275. u32 biststatus; /* rev8 */
  276. /* PCMCIA access */
  277. u16 pcmciamesportaladdr; /* 0x010, rev8 */
  278. u16 PAD[1];
  279. u16 pcmciamesportalmask; /* rev8 */
  280. u16 PAD[1];
  281. u16 pcmciawrframebc; /* rev8 */
  282. u16 PAD[1];
  283. u16 pcmciaunderflowtimer; /* rev8 */
  284. u16 PAD[1];
  285. /* interrupt */
  286. u32 intstatus; /* 0x020, rev8 */
  287. u32 hostintmask; /* rev8 */
  288. u32 intmask; /* rev8 */
  289. u32 sbintstatus; /* rev8 */
  290. u32 sbintmask; /* rev8 */
  291. u32 funcintmask; /* rev4 */
  292. u32 PAD[2];
  293. u32 tosbmailbox; /* 0x040, rev8 */
  294. u32 tohostmailbox; /* rev8 */
  295. u32 tosbmailboxdata; /* rev8 */
  296. u32 tohostmailboxdata; /* rev8 */
  297. /* synchronized access to registers in SDIO clock domain */
  298. u32 sdioaccess; /* 0x050, rev8 */
  299. u32 PAD[3];
  300. /* PCMCIA frame control */
  301. u8 pcmciaframectrl; /* 0x060, rev8 */
  302. u8 PAD[3];
  303. u8 pcmciawatermark; /* rev8 */
  304. u8 PAD[155];
  305. /* interrupt batching control */
  306. u32 intrcvlazy; /* 0x100, rev8 */
  307. u32 PAD[3];
  308. /* counters */
  309. u32 cmd52rd; /* 0x110, rev8 */
  310. u32 cmd52wr; /* rev8 */
  311. u32 cmd53rd; /* rev8 */
  312. u32 cmd53wr; /* rev8 */
  313. u32 abort; /* rev8 */
  314. u32 datacrcerror; /* rev8 */
  315. u32 rdoutofsync; /* rev8 */
  316. u32 wroutofsync; /* rev8 */
  317. u32 writebusy; /* rev8 */
  318. u32 readwait; /* rev8 */
  319. u32 readterm; /* rev8 */
  320. u32 writeterm; /* rev8 */
  321. u32 PAD[40];
  322. u32 clockctlstatus; /* rev8 */
  323. u32 PAD[7];
  324. u32 PAD[128]; /* DMA engines */
  325. /* SDIO/PCMCIA CIS region */
  326. char cis[512]; /* 0x400-0x5ff, rev6 */
  327. /* PCMCIA function control registers */
  328. char pcmciafcr[256]; /* 0x600-6ff, rev6 */
  329. u16 PAD[55];
  330. /* PCMCIA backplane access */
  331. u16 backplanecsr; /* 0x76E, rev6 */
  332. u16 backplaneaddr0; /* rev6 */
  333. u16 backplaneaddr1; /* rev6 */
  334. u16 backplaneaddr2; /* rev6 */
  335. u16 backplaneaddr3; /* rev6 */
  336. u16 backplanedata0; /* rev6 */
  337. u16 backplanedata1; /* rev6 */
  338. u16 backplanedata2; /* rev6 */
  339. u16 backplanedata3; /* rev6 */
  340. u16 PAD[31];
  341. /* sprom "size" & "blank" info */
  342. u16 spromstatus; /* 0x7BE, rev2 */
  343. u32 PAD[464];
  344. u16 PAD[0x80];
  345. };
  346. #ifdef BCMDBG
  347. /* Device console log buffer state */
  348. struct brcmf_console {
  349. uint count; /* Poll interval msec counter */
  350. uint log_addr; /* Log struct address (fixed) */
  351. struct rte_log_le log_le; /* Log struct (host copy) */
  352. uint bufsize; /* Size of log buffer */
  353. u8 *buf; /* Log buffer (host copy) */
  354. uint last; /* Last buffer read index */
  355. };
  356. #endif /* BCMDBG */
  357. struct sdpcm_shared {
  358. u32 flags;
  359. u32 trap_addr;
  360. u32 assert_exp_addr;
  361. u32 assert_file_addr;
  362. u32 assert_line;
  363. u32 console_addr; /* Address of struct rte_console */
  364. u32 msgtrace_addr;
  365. u8 tag[32];
  366. };
  367. struct sdpcm_shared_le {
  368. __le32 flags;
  369. __le32 trap_addr;
  370. __le32 assert_exp_addr;
  371. __le32 assert_file_addr;
  372. __le32 assert_line;
  373. __le32 console_addr; /* Address of struct rte_console */
  374. __le32 msgtrace_addr;
  375. u8 tag[32];
  376. };
  377. /* misc chip info needed by some of the routines */
  378. /* Private data for SDIO bus interaction */
  379. struct brcmf_sdio {
  380. struct brcmf_pub *drvr;
  381. struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
  382. struct chip_info *ci; /* Chip info struct */
  383. char *vars; /* Variables (from CIS and/or other) */
  384. uint varsz; /* Size of variables buffer */
  385. u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
  386. u32 hostintmask; /* Copy of Host Interrupt Mask */
  387. u32 intstatus; /* Intstatus bits (events) pending */
  388. bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
  389. bool fcstate; /* State of dongle flow-control */
  390. uint blocksize; /* Block size of SDIO transfers */
  391. uint roundup; /* Max roundup limit */
  392. struct pktq txq; /* Queue length used for flow-control */
  393. u8 flowcontrol; /* per prio flow control bitmask */
  394. u8 tx_seq; /* Transmit sequence number (next) */
  395. u8 tx_max; /* Maximum transmit sequence allowed */
  396. u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
  397. u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
  398. u16 nextlen; /* Next Read Len from last header */
  399. u8 rx_seq; /* Receive sequence number (expected) */
  400. bool rxskip; /* Skip receive (awaiting NAK ACK) */
  401. uint rxbound; /* Rx frames to read before resched */
  402. uint txbound; /* Tx frames to send before resched */
  403. uint txminmax;
  404. struct sk_buff *glomd; /* Packet containing glomming descriptor */
  405. struct sk_buff_head glom; /* Packet list for glommed superframe */
  406. uint glomerr; /* Glom packet read errors */
  407. u8 *rxbuf; /* Buffer for receiving control packets */
  408. uint rxblen; /* Allocated length of rxbuf */
  409. u8 *rxctl; /* Aligned pointer into rxbuf */
  410. u8 *databuf; /* Buffer for receiving big glom packet */
  411. u8 *dataptr; /* Aligned pointer into databuf */
  412. uint rxlen; /* Length of valid data in buffer */
  413. u8 sdpcm_ver; /* Bus protocol reported by dongle */
  414. bool intr; /* Use interrupts */
  415. bool poll; /* Use polling */
  416. bool ipend; /* Device interrupt is pending */
  417. uint intrcount; /* Count of device interrupt callbacks */
  418. uint lastintrs; /* Count as of last watchdog timer */
  419. uint spurious; /* Count of spurious interrupts */
  420. uint pollrate; /* Ticks between device polls */
  421. uint polltick; /* Tick counter */
  422. uint pollcnt; /* Count of active polls */
  423. #ifdef BCMDBG
  424. uint console_interval;
  425. struct brcmf_console console; /* Console output polling support */
  426. uint console_addr; /* Console address from shared struct */
  427. #endif /* BCMDBG */
  428. uint regfails; /* Count of R_REG failures */
  429. uint clkstate; /* State of sd and backplane clock(s) */
  430. bool activity; /* Activity flag for clock down */
  431. s32 idletime; /* Control for activity timeout */
  432. s32 idlecount; /* Activity timeout counter */
  433. s32 idleclock; /* How to set bus driver when idle */
  434. s32 sd_rxchain;
  435. bool use_rxchain; /* If brcmf should use PKT chains */
  436. bool sleeping; /* Is SDIO bus sleeping? */
  437. bool rxflow_mode; /* Rx flow control mode */
  438. bool rxflow; /* Is rx flow control on */
  439. bool alp_only; /* Don't use HT clock (ALP only) */
  440. /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
  441. bool usebufpool;
  442. /* Some additional counters */
  443. uint tx_sderrs; /* Count of tx attempts with sd errors */
  444. uint fcqueued; /* Tx packets that got queued */
  445. uint rxrtx; /* Count of rtx requests (NAK to dongle) */
  446. uint rx_toolong; /* Receive frames too long to receive */
  447. uint rxc_errors; /* SDIO errors when reading control frames */
  448. uint rx_hdrfail; /* SDIO errors on header reads */
  449. uint rx_badhdr; /* Bad received headers (roosync?) */
  450. uint rx_badseq; /* Mismatched rx sequence number */
  451. uint fc_rcvd; /* Number of flow-control events received */
  452. uint fc_xoff; /* Number which turned on flow-control */
  453. uint fc_xon; /* Number which turned off flow-control */
  454. uint rxglomfail; /* Failed deglom attempts */
  455. uint rxglomframes; /* Number of glom frames (superframes) */
  456. uint rxglompkts; /* Number of packets from glom frames */
  457. uint f2rxhdrs; /* Number of header reads */
  458. uint f2rxdata; /* Number of frame data reads */
  459. uint f2txdata; /* Number of f2 frame writes */
  460. uint f1regdata; /* Number of f1 register accesses */
  461. u8 *ctrl_frame_buf;
  462. u32 ctrl_frame_len;
  463. bool ctrl_frame_stat;
  464. spinlock_t txqlock;
  465. wait_queue_head_t ctrl_wait;
  466. wait_queue_head_t dcmd_resp_wait;
  467. struct timer_list timer;
  468. struct completion watchdog_wait;
  469. struct task_struct *watchdog_tsk;
  470. bool wd_timer_valid;
  471. uint save_ms;
  472. struct task_struct *dpc_tsk;
  473. struct completion dpc_wait;
  474. struct semaphore sdsem;
  475. const struct firmware *firmware;
  476. u32 fw_ptr;
  477. };
  478. /* clkstate */
  479. #define CLK_NONE 0
  480. #define CLK_SDONLY 1
  481. #define CLK_PENDING 2 /* Not used yet */
  482. #define CLK_AVAIL 3
  483. #ifdef BCMDBG
  484. static int qcount[NUMPRIO];
  485. static int tx_packets[NUMPRIO];
  486. #endif /* BCMDBG */
  487. #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
  488. #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
  489. /* Retry count for register access failures */
  490. static const uint retry_limit = 2;
  491. /* Limit on rounding up frames */
  492. static const uint max_roundup = 512;
  493. #define ALIGNMENT 4
  494. static void pkt_align(struct sk_buff *p, int len, int align)
  495. {
  496. uint datalign;
  497. datalign = (unsigned long)(p->data);
  498. datalign = roundup(datalign, (align)) - datalign;
  499. if (datalign)
  500. skb_pull(p, datalign);
  501. __skb_trim(p, len);
  502. }
  503. /* To check if there's window offered */
  504. static bool data_ok(struct brcmf_sdio *bus)
  505. {
  506. return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
  507. ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
  508. }
  509. /*
  510. * Reads a register in the SDIO hardware block. This block occupies a series of
  511. * adresses on the 32 bit backplane bus.
  512. */
  513. static void
  514. r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
  515. {
  516. u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
  517. *retryvar = 0;
  518. do {
  519. *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
  520. bus->ci->c_inf[idx].base + reg_offset,
  521. sizeof(u32));
  522. } while (brcmf_sdcard_regfail(bus->sdiodev) &&
  523. (++(*retryvar) <= retry_limit));
  524. if (*retryvar) {
  525. bus->regfails += (*retryvar-1);
  526. if (*retryvar > retry_limit) {
  527. brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
  528. *regvar = 0;
  529. }
  530. }
  531. }
  532. static void
  533. w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset, u32 *retryvar)
  534. {
  535. u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
  536. *retryvar = 0;
  537. do {
  538. brcmf_sdcard_reg_write(bus->sdiodev,
  539. bus->ci->c_inf[idx].base + reg_offset,
  540. sizeof(u32), regval);
  541. } while (brcmf_sdcard_regfail(bus->sdiodev) &&
  542. (++(*retryvar) <= retry_limit));
  543. if (*retryvar) {
  544. bus->regfails += (*retryvar-1);
  545. if (*retryvar > retry_limit)
  546. brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
  547. reg_offset);
  548. }
  549. }
  550. #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
  551. #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
  552. /* Packet free applicable unconditionally for sdio and sdspi.
  553. * Conditional if bufpool was present for gspi bus.
  554. */
  555. static void brcmf_sdbrcm_pktfree2(struct brcmf_sdio *bus, struct sk_buff *pkt)
  556. {
  557. if (bus->usebufpool)
  558. brcmu_pkt_buf_free_skb(pkt);
  559. }
  560. /* Turn backplane clock on or off */
  561. static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
  562. {
  563. int err;
  564. u8 clkctl, clkreq, devctl;
  565. unsigned long timeout;
  566. brcmf_dbg(TRACE, "Enter\n");
  567. clkctl = 0;
  568. if (on) {
  569. /* Request HT Avail */
  570. clkreq =
  571. bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
  572. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  573. SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
  574. if (err) {
  575. brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
  576. return -EBADE;
  577. }
  578. /* Check current status */
  579. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  580. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  581. if (err) {
  582. brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
  583. return -EBADE;
  584. }
  585. /* Go to pending and await interrupt if appropriate */
  586. if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
  587. /* Allow only clock-available interrupt */
  588. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  589. SDIO_FUNC_1,
  590. SBSDIO_DEVICE_CTL, &err);
  591. if (err) {
  592. brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
  593. err);
  594. return -EBADE;
  595. }
  596. devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
  597. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  598. SBSDIO_DEVICE_CTL, devctl, &err);
  599. brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
  600. bus->clkstate = CLK_PENDING;
  601. return 0;
  602. } else if (bus->clkstate == CLK_PENDING) {
  603. /* Cancel CA-only interrupt filter */
  604. devctl =
  605. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  606. SBSDIO_DEVICE_CTL, &err);
  607. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  608. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  609. SBSDIO_DEVICE_CTL, devctl, &err);
  610. }
  611. /* Otherwise, wait here (polling) for HT Avail */
  612. timeout = jiffies +
  613. msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
  614. while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  615. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  616. SDIO_FUNC_1,
  617. SBSDIO_FUNC1_CHIPCLKCSR,
  618. &err);
  619. if (time_after(jiffies, timeout))
  620. break;
  621. else
  622. usleep_range(5000, 10000);
  623. }
  624. if (err) {
  625. brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
  626. return -EBADE;
  627. }
  628. if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  629. brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
  630. PMU_MAX_TRANSITION_DLY, clkctl);
  631. return -EBADE;
  632. }
  633. /* Mark clock available */
  634. bus->clkstate = CLK_AVAIL;
  635. brcmf_dbg(INFO, "CLKCTL: turned ON\n");
  636. #if defined(BCMDBG)
  637. if (bus->alp_only != true) {
  638. if (SBSDIO_ALPONLY(clkctl))
  639. brcmf_dbg(ERROR, "HT Clock should be on\n");
  640. }
  641. #endif /* defined (BCMDBG) */
  642. bus->activity = true;
  643. } else {
  644. clkreq = 0;
  645. if (bus->clkstate == CLK_PENDING) {
  646. /* Cancel CA-only interrupt filter */
  647. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  648. SDIO_FUNC_1,
  649. SBSDIO_DEVICE_CTL, &err);
  650. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  651. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  652. SBSDIO_DEVICE_CTL, devctl, &err);
  653. }
  654. bus->clkstate = CLK_SDONLY;
  655. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  656. SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
  657. brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
  658. if (err) {
  659. brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
  660. err);
  661. return -EBADE;
  662. }
  663. }
  664. return 0;
  665. }
  666. /* Change idle/active SD state */
  667. static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on)
  668. {
  669. brcmf_dbg(TRACE, "Enter\n");
  670. if (on)
  671. bus->clkstate = CLK_SDONLY;
  672. else
  673. bus->clkstate = CLK_NONE;
  674. return 0;
  675. }
  676. /* Transition SD and backplane clock readiness */
  677. static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
  678. {
  679. #ifdef BCMDBG
  680. uint oldstate = bus->clkstate;
  681. #endif /* BCMDBG */
  682. brcmf_dbg(TRACE, "Enter\n");
  683. /* Early exit if we're already there */
  684. if (bus->clkstate == target) {
  685. if (target == CLK_AVAIL) {
  686. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  687. bus->activity = true;
  688. }
  689. return 0;
  690. }
  691. switch (target) {
  692. case CLK_AVAIL:
  693. /* Make sure SD clock is available */
  694. if (bus->clkstate == CLK_NONE)
  695. brcmf_sdbrcm_sdclk(bus, true);
  696. /* Now request HT Avail on the backplane */
  697. brcmf_sdbrcm_htclk(bus, true, pendok);
  698. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  699. bus->activity = true;
  700. break;
  701. case CLK_SDONLY:
  702. /* Remove HT request, or bring up SD clock */
  703. if (bus->clkstate == CLK_NONE)
  704. brcmf_sdbrcm_sdclk(bus, true);
  705. else if (bus->clkstate == CLK_AVAIL)
  706. brcmf_sdbrcm_htclk(bus, false, false);
  707. else
  708. brcmf_dbg(ERROR, "request for %d -> %d\n",
  709. bus->clkstate, target);
  710. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  711. break;
  712. case CLK_NONE:
  713. /* Make sure to remove HT request */
  714. if (bus->clkstate == CLK_AVAIL)
  715. brcmf_sdbrcm_htclk(bus, false, false);
  716. /* Now remove the SD clock */
  717. brcmf_sdbrcm_sdclk(bus, false);
  718. brcmf_sdbrcm_wd_timer(bus, 0);
  719. break;
  720. }
  721. #ifdef BCMDBG
  722. brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
  723. #endif /* BCMDBG */
  724. return 0;
  725. }
  726. static int brcmf_sdbrcm_bussleep(struct brcmf_sdio *bus, bool sleep)
  727. {
  728. uint retries = 0;
  729. brcmf_dbg(INFO, "request %s (currently %s)\n",
  730. sleep ? "SLEEP" : "WAKE",
  731. bus->sleeping ? "SLEEP" : "WAKE");
  732. /* Done if we're already in the requested state */
  733. if (sleep == bus->sleeping)
  734. return 0;
  735. /* Going to sleep: set the alarm and turn off the lights... */
  736. if (sleep) {
  737. /* Don't sleep if something is pending */
  738. if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
  739. return -EBUSY;
  740. /* Make sure the controller has the bus up */
  741. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  742. /* Tell device to start using OOB wakeup */
  743. w_sdreg32(bus, SMB_USE_OOB,
  744. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  745. if (retries > retry_limit)
  746. brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
  747. /* Turn off our contribution to the HT clock request */
  748. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  749. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  750. SBSDIO_FUNC1_CHIPCLKCSR,
  751. SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
  752. /* Isolate the bus */
  753. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  754. SBSDIO_DEVICE_CTL,
  755. SBSDIO_DEVCTL_PADS_ISO, NULL);
  756. /* Change state */
  757. bus->sleeping = true;
  758. } else {
  759. /* Waking up: bus power up is ok, set local state */
  760. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  761. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  762. /* Make sure the controller has the bus up */
  763. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  764. /* Send misc interrupt to indicate OOB not needed */
  765. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
  766. &retries);
  767. if (retries <= retry_limit)
  768. w_sdreg32(bus, SMB_DEV_INT,
  769. offsetof(struct sdpcmd_regs, tosbmailbox),
  770. &retries);
  771. if (retries > retry_limit)
  772. brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
  773. /* Make sure we have SD bus access */
  774. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  775. /* Change state */
  776. bus->sleeping = false;
  777. }
  778. return 0;
  779. }
  780. static void bus_wake(struct brcmf_sdio *bus)
  781. {
  782. if (bus->sleeping)
  783. brcmf_sdbrcm_bussleep(bus, false);
  784. }
  785. static u32 brcmf_sdbrcm_hostmail(struct brcmf_sdio *bus)
  786. {
  787. u32 intstatus = 0;
  788. u32 hmb_data;
  789. u8 fcbits;
  790. uint retries = 0;
  791. brcmf_dbg(TRACE, "Enter\n");
  792. /* Read mailbox data and ack that we did so */
  793. r_sdreg32(bus, &hmb_data,
  794. offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
  795. if (retries <= retry_limit)
  796. w_sdreg32(bus, SMB_INT_ACK,
  797. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  798. bus->f1regdata += 2;
  799. /* Dongle recomposed rx frames, accept them again */
  800. if (hmb_data & HMB_DATA_NAKHANDLED) {
  801. brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
  802. bus->rx_seq);
  803. if (!bus->rxskip)
  804. brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
  805. bus->rxskip = false;
  806. intstatus |= I_HMB_FRAME_IND;
  807. }
  808. /*
  809. * DEVREADY does not occur with gSPI.
  810. */
  811. if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
  812. bus->sdpcm_ver =
  813. (hmb_data & HMB_DATA_VERSION_MASK) >>
  814. HMB_DATA_VERSION_SHIFT;
  815. if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
  816. brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
  817. "expecting %d\n",
  818. bus->sdpcm_ver, SDPCM_PROT_VERSION);
  819. else
  820. brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
  821. bus->sdpcm_ver);
  822. }
  823. /*
  824. * Flow Control has been moved into the RX headers and this out of band
  825. * method isn't used any more.
  826. * remaining backward compatible with older dongles.
  827. */
  828. if (hmb_data & HMB_DATA_FC) {
  829. fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
  830. HMB_DATA_FCDATA_SHIFT;
  831. if (fcbits & ~bus->flowcontrol)
  832. bus->fc_xoff++;
  833. if (bus->flowcontrol & ~fcbits)
  834. bus->fc_xon++;
  835. bus->fc_rcvd++;
  836. bus->flowcontrol = fcbits;
  837. }
  838. /* Shouldn't be any others */
  839. if (hmb_data & ~(HMB_DATA_DEVREADY |
  840. HMB_DATA_NAKHANDLED |
  841. HMB_DATA_FC |
  842. HMB_DATA_FWREADY |
  843. HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
  844. brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
  845. hmb_data);
  846. return intstatus;
  847. }
  848. static void brcmf_sdbrcm_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
  849. {
  850. uint retries = 0;
  851. u16 lastrbc;
  852. u8 hi, lo;
  853. int err;
  854. brcmf_dbg(ERROR, "%sterminate frame%s\n",
  855. abort ? "abort command, " : "",
  856. rtx ? ", send NAK" : "");
  857. if (abort)
  858. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  859. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  860. SBSDIO_FUNC1_FRAMECTRL,
  861. SFC_RF_TERM, &err);
  862. bus->f1regdata++;
  863. /* Wait until the packet has been flushed (device/FIFO stable) */
  864. for (lastrbc = retries = 0xffff; retries > 0; retries--) {
  865. hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  866. SBSDIO_FUNC1_RFRAMEBCHI, NULL);
  867. lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  868. SBSDIO_FUNC1_RFRAMEBCLO, NULL);
  869. bus->f1regdata += 2;
  870. if ((hi == 0) && (lo == 0))
  871. break;
  872. if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
  873. brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
  874. lastrbc, (hi << 8) + lo);
  875. }
  876. lastrbc = (hi << 8) + lo;
  877. }
  878. if (!retries)
  879. brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
  880. else
  881. brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
  882. if (rtx) {
  883. bus->rxrtx++;
  884. w_sdreg32(bus, SMB_NAK,
  885. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  886. bus->f1regdata++;
  887. if (retries <= retry_limit)
  888. bus->rxskip = true;
  889. }
  890. /* Clear partial in any case */
  891. bus->nextlen = 0;
  892. /* If we can't reach the device, signal failure */
  893. if (err || brcmf_sdcard_regfail(bus->sdiodev))
  894. bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
  895. }
  896. /* copy a buffer into a pkt buffer chain */
  897. static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_sdio *bus, uint len)
  898. {
  899. uint n, ret = 0;
  900. struct sk_buff *p;
  901. u8 *buf;
  902. buf = bus->dataptr;
  903. /* copy the data */
  904. skb_queue_walk(&bus->glom, p) {
  905. n = min_t(uint, p->len, len);
  906. memcpy(p->data, buf, n);
  907. buf += n;
  908. len -= n;
  909. ret += n;
  910. if (!len)
  911. break;
  912. }
  913. return ret;
  914. }
  915. /* return total length of buffer chain */
  916. static uint brcmf_sdbrcm_glom_len(struct brcmf_sdio *bus)
  917. {
  918. struct sk_buff *p;
  919. uint total;
  920. total = 0;
  921. skb_queue_walk(&bus->glom, p)
  922. total += p->len;
  923. return total;
  924. }
  925. static void brcmf_sdbrcm_free_glom(struct brcmf_sdio *bus)
  926. {
  927. struct sk_buff *cur, *next;
  928. skb_queue_walk_safe(&bus->glom, cur, next) {
  929. skb_unlink(cur, &bus->glom);
  930. brcmu_pkt_buf_free_skb(cur);
  931. }
  932. }
  933. static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
  934. {
  935. u16 dlen, totlen;
  936. u8 *dptr, num = 0;
  937. u16 sublen, check;
  938. struct sk_buff *pfirst, *pnext;
  939. int errcode;
  940. u8 chan, seq, doff, sfdoff;
  941. u8 txmax;
  942. int ifidx = 0;
  943. bool usechain = bus->use_rxchain;
  944. /* If packets, issue read(s) and send up packet chain */
  945. /* Return sequence numbers consumed? */
  946. brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
  947. bus->glomd, skb_peek(&bus->glom));
  948. /* If there's a descriptor, generate the packet chain */
  949. if (bus->glomd) {
  950. pfirst = pnext = NULL;
  951. dlen = (u16) (bus->glomd->len);
  952. dptr = bus->glomd->data;
  953. if (!dlen || (dlen & 1)) {
  954. brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
  955. dlen);
  956. dlen = 0;
  957. }
  958. for (totlen = num = 0; dlen; num++) {
  959. /* Get (and move past) next length */
  960. sublen = get_unaligned_le16(dptr);
  961. dlen -= sizeof(u16);
  962. dptr += sizeof(u16);
  963. if ((sublen < SDPCM_HDRLEN) ||
  964. ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
  965. brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
  966. num, sublen);
  967. pnext = NULL;
  968. break;
  969. }
  970. if (sublen % BRCMF_SDALIGN) {
  971. brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
  972. sublen, BRCMF_SDALIGN);
  973. usechain = false;
  974. }
  975. totlen += sublen;
  976. /* For last frame, adjust read len so total
  977. is a block multiple */
  978. if (!dlen) {
  979. sublen +=
  980. (roundup(totlen, bus->blocksize) - totlen);
  981. totlen = roundup(totlen, bus->blocksize);
  982. }
  983. /* Allocate/chain packet for next subframe */
  984. pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
  985. if (pnext == NULL) {
  986. brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
  987. num, sublen);
  988. break;
  989. }
  990. skb_queue_tail(&bus->glom, pnext);
  991. /* Adhere to start alignment requirements */
  992. pkt_align(pnext, sublen, BRCMF_SDALIGN);
  993. }
  994. /* If all allocations succeeded, save packet chain
  995. in bus structure */
  996. if (pnext) {
  997. brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
  998. totlen, num);
  999. if (BRCMF_GLOM_ON() && bus->nextlen &&
  1000. totlen != bus->nextlen) {
  1001. brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
  1002. bus->nextlen, totlen, rxseq);
  1003. }
  1004. pfirst = pnext = NULL;
  1005. } else {
  1006. brcmf_sdbrcm_free_glom(bus);
  1007. num = 0;
  1008. }
  1009. /* Done with descriptor packet */
  1010. brcmu_pkt_buf_free_skb(bus->glomd);
  1011. bus->glomd = NULL;
  1012. bus->nextlen = 0;
  1013. }
  1014. /* Ok -- either we just generated a packet chain,
  1015. or had one from before */
  1016. if (!skb_queue_empty(&bus->glom)) {
  1017. if (BRCMF_GLOM_ON()) {
  1018. brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
  1019. skb_queue_walk(&bus->glom, pnext) {
  1020. brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
  1021. pnext, (u8 *) (pnext->data),
  1022. pnext->len, pnext->len);
  1023. }
  1024. }
  1025. pfirst = skb_peek(&bus->glom);
  1026. dlen = (u16) brcmf_sdbrcm_glom_len(bus);
  1027. /* Do an SDIO read for the superframe. Configurable iovar to
  1028. * read directly into the chained packet, or allocate a large
  1029. * packet and and copy into the chain.
  1030. */
  1031. if (usechain) {
  1032. errcode = brcmf_sdcard_recv_chain(bus->sdiodev,
  1033. bus->sdiodev->sbwad,
  1034. SDIO_FUNC_2, F2SYNC, &bus->glom);
  1035. } else if (bus->dataptr) {
  1036. errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
  1037. bus->sdiodev->sbwad,
  1038. SDIO_FUNC_2, F2SYNC,
  1039. bus->dataptr, dlen);
  1040. sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
  1041. if (sublen != dlen) {
  1042. brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
  1043. dlen, sublen);
  1044. errcode = -1;
  1045. }
  1046. pnext = NULL;
  1047. } else {
  1048. brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
  1049. dlen);
  1050. errcode = -1;
  1051. }
  1052. bus->f2rxdata++;
  1053. /* On failure, kill the superframe, allow a couple retries */
  1054. if (errcode < 0) {
  1055. brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
  1056. dlen, errcode);
  1057. bus->drvr->rx_errors++;
  1058. if (bus->glomerr++ < 3) {
  1059. brcmf_sdbrcm_rxfail(bus, true, true);
  1060. } else {
  1061. bus->glomerr = 0;
  1062. brcmf_sdbrcm_rxfail(bus, true, false);
  1063. bus->rxglomfail++;
  1064. brcmf_sdbrcm_free_glom(bus);
  1065. }
  1066. return 0;
  1067. }
  1068. #ifdef BCMDBG
  1069. if (BRCMF_GLOM_ON()) {
  1070. printk(KERN_DEBUG "SUPERFRAME:\n");
  1071. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1072. pfirst->data, min_t(int, pfirst->len, 48));
  1073. }
  1074. #endif
  1075. /* Validate the superframe header */
  1076. dptr = (u8 *) (pfirst->data);
  1077. sublen = get_unaligned_le16(dptr);
  1078. check = get_unaligned_le16(dptr + sizeof(u16));
  1079. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1080. seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
  1081. bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
  1082. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1083. brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
  1084. bus->nextlen, seq);
  1085. bus->nextlen = 0;
  1086. }
  1087. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1088. txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1089. errcode = 0;
  1090. if ((u16)~(sublen ^ check)) {
  1091. brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
  1092. sublen, check);
  1093. errcode = -1;
  1094. } else if (roundup(sublen, bus->blocksize) != dlen) {
  1095. brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
  1096. sublen, roundup(sublen, bus->blocksize),
  1097. dlen);
  1098. errcode = -1;
  1099. } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
  1100. SDPCM_GLOM_CHANNEL) {
  1101. brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
  1102. SDPCM_PACKET_CHANNEL(
  1103. &dptr[SDPCM_FRAMETAG_LEN]));
  1104. errcode = -1;
  1105. } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
  1106. brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
  1107. errcode = -1;
  1108. } else if ((doff < SDPCM_HDRLEN) ||
  1109. (doff > (pfirst->len - SDPCM_HDRLEN))) {
  1110. brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
  1111. doff, sublen, pfirst->len, SDPCM_HDRLEN);
  1112. errcode = -1;
  1113. }
  1114. /* Check sequence number of superframe SW header */
  1115. if (rxseq != seq) {
  1116. brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
  1117. seq, rxseq);
  1118. bus->rx_badseq++;
  1119. rxseq = seq;
  1120. }
  1121. /* Check window for sanity */
  1122. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1123. brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
  1124. txmax, bus->tx_seq);
  1125. txmax = bus->tx_seq + 2;
  1126. }
  1127. bus->tx_max = txmax;
  1128. /* Remove superframe header, remember offset */
  1129. skb_pull(pfirst, doff);
  1130. sfdoff = doff;
  1131. num = 0;
  1132. /* Validate all the subframe headers */
  1133. skb_queue_walk(&bus->glom, pnext) {
  1134. /* leave when invalid subframe is found */
  1135. if (errcode)
  1136. break;
  1137. dptr = (u8 *) (pnext->data);
  1138. dlen = (u16) (pnext->len);
  1139. sublen = get_unaligned_le16(dptr);
  1140. check = get_unaligned_le16(dptr + sizeof(u16));
  1141. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1142. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1143. #ifdef BCMDBG
  1144. if (BRCMF_GLOM_ON()) {
  1145. printk(KERN_DEBUG "subframe:\n");
  1146. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1147. dptr, 32);
  1148. }
  1149. #endif
  1150. if ((u16)~(sublen ^ check)) {
  1151. brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
  1152. num, sublen, check);
  1153. errcode = -1;
  1154. } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
  1155. brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
  1156. num, sublen, dlen);
  1157. errcode = -1;
  1158. } else if ((chan != SDPCM_DATA_CHANNEL) &&
  1159. (chan != SDPCM_EVENT_CHANNEL)) {
  1160. brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
  1161. num, chan);
  1162. errcode = -1;
  1163. } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
  1164. brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
  1165. num, doff, sublen, SDPCM_HDRLEN);
  1166. errcode = -1;
  1167. }
  1168. /* increase the subframe count */
  1169. num++;
  1170. }
  1171. if (errcode) {
  1172. /* Terminate frame on error, request
  1173. a couple retries */
  1174. if (bus->glomerr++ < 3) {
  1175. /* Restore superframe header space */
  1176. skb_push(pfirst, sfdoff);
  1177. brcmf_sdbrcm_rxfail(bus, true, true);
  1178. } else {
  1179. bus->glomerr = 0;
  1180. brcmf_sdbrcm_rxfail(bus, true, false);
  1181. bus->rxglomfail++;
  1182. brcmf_sdbrcm_free_glom(bus);
  1183. }
  1184. bus->nextlen = 0;
  1185. return 0;
  1186. }
  1187. /* Basic SD framing looks ok - process each packet (header) */
  1188. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  1189. dptr = (u8 *) (pfirst->data);
  1190. sublen = get_unaligned_le16(dptr);
  1191. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1192. seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
  1193. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1194. brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
  1195. num, pfirst, pfirst->data,
  1196. pfirst->len, sublen, chan, seq);
  1197. /* precondition: chan == SDPCM_DATA_CHANNEL ||
  1198. chan == SDPCM_EVENT_CHANNEL */
  1199. if (rxseq != seq) {
  1200. brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
  1201. seq, rxseq);
  1202. bus->rx_badseq++;
  1203. rxseq = seq;
  1204. }
  1205. rxseq++;
  1206. #ifdef BCMDBG
  1207. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1208. printk(KERN_DEBUG "Rx Subframe Data:\n");
  1209. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1210. dptr, dlen);
  1211. }
  1212. #endif
  1213. __skb_trim(pfirst, sublen);
  1214. skb_pull(pfirst, doff);
  1215. if (pfirst->len == 0) {
  1216. skb_unlink(pfirst, &bus->glom);
  1217. brcmu_pkt_buf_free_skb(pfirst);
  1218. continue;
  1219. } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
  1220. pfirst) != 0) {
  1221. brcmf_dbg(ERROR, "rx protocol error\n");
  1222. bus->drvr->rx_errors++;
  1223. skb_unlink(pfirst, &bus->glom);
  1224. brcmu_pkt_buf_free_skb(pfirst);
  1225. continue;
  1226. }
  1227. #ifdef BCMDBG
  1228. if (BRCMF_GLOM_ON()) {
  1229. brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
  1230. bus->glom.qlen, pfirst, pfirst->data,
  1231. pfirst->len, pfirst->next,
  1232. pfirst->prev);
  1233. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1234. pfirst->data,
  1235. min_t(int, pfirst->len, 32));
  1236. }
  1237. #endif /* BCMDBG */
  1238. }
  1239. /* sent any remaining packets up */
  1240. if (bus->glom.qlen) {
  1241. up(&bus->sdsem);
  1242. brcmf_rx_frame(bus->drvr, ifidx, &bus->glom);
  1243. down(&bus->sdsem);
  1244. }
  1245. bus->rxglomframes++;
  1246. bus->rxglompkts += bus->glom.qlen;
  1247. }
  1248. return num;
  1249. }
  1250. static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
  1251. bool *pending)
  1252. {
  1253. DECLARE_WAITQUEUE(wait, current);
  1254. int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
  1255. /* Wait until control frame is available */
  1256. add_wait_queue(&bus->dcmd_resp_wait, &wait);
  1257. set_current_state(TASK_INTERRUPTIBLE);
  1258. while (!(*condition) && (!signal_pending(current) && timeout))
  1259. timeout = schedule_timeout(timeout);
  1260. if (signal_pending(current))
  1261. *pending = true;
  1262. set_current_state(TASK_RUNNING);
  1263. remove_wait_queue(&bus->dcmd_resp_wait, &wait);
  1264. return timeout;
  1265. }
  1266. static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_sdio *bus)
  1267. {
  1268. if (waitqueue_active(&bus->dcmd_resp_wait))
  1269. wake_up_interruptible(&bus->dcmd_resp_wait);
  1270. return 0;
  1271. }
  1272. static void
  1273. brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
  1274. {
  1275. uint rdlen, pad;
  1276. int sdret;
  1277. brcmf_dbg(TRACE, "Enter\n");
  1278. /* Set rxctl for frame (w/optional alignment) */
  1279. bus->rxctl = bus->rxbuf;
  1280. bus->rxctl += BRCMF_FIRSTREAD;
  1281. pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
  1282. if (pad)
  1283. bus->rxctl += (BRCMF_SDALIGN - pad);
  1284. bus->rxctl -= BRCMF_FIRSTREAD;
  1285. /* Copy the already-read portion over */
  1286. memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
  1287. if (len <= BRCMF_FIRSTREAD)
  1288. goto gotpkt;
  1289. /* Raise rdlen to next SDIO block to avoid tail command */
  1290. rdlen = len - BRCMF_FIRSTREAD;
  1291. if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
  1292. pad = bus->blocksize - (rdlen % bus->blocksize);
  1293. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1294. ((len + pad) < bus->drvr->maxctl))
  1295. rdlen += pad;
  1296. } else if (rdlen % BRCMF_SDALIGN) {
  1297. rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
  1298. }
  1299. /* Satisfy length-alignment requirements */
  1300. if (rdlen & (ALIGNMENT - 1))
  1301. rdlen = roundup(rdlen, ALIGNMENT);
  1302. /* Drop if the read is too big or it exceeds our maximum */
  1303. if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
  1304. brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
  1305. rdlen, bus->drvr->maxctl);
  1306. bus->drvr->rx_errors++;
  1307. brcmf_sdbrcm_rxfail(bus, false, false);
  1308. goto done;
  1309. }
  1310. if ((len - doff) > bus->drvr->maxctl) {
  1311. brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
  1312. len, len - doff, bus->drvr->maxctl);
  1313. bus->drvr->rx_errors++;
  1314. bus->rx_toolong++;
  1315. brcmf_sdbrcm_rxfail(bus, false, false);
  1316. goto done;
  1317. }
  1318. /* Read remainder of frame body into the rxctl buffer */
  1319. sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
  1320. bus->sdiodev->sbwad,
  1321. SDIO_FUNC_2,
  1322. F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen);
  1323. bus->f2rxdata++;
  1324. /* Control frame failures need retransmission */
  1325. if (sdret < 0) {
  1326. brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
  1327. rdlen, sdret);
  1328. bus->rxc_errors++;
  1329. brcmf_sdbrcm_rxfail(bus, true, true);
  1330. goto done;
  1331. }
  1332. gotpkt:
  1333. #ifdef BCMDBG
  1334. if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
  1335. printk(KERN_DEBUG "RxCtrl:\n");
  1336. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
  1337. }
  1338. #endif
  1339. /* Point to valid data and indicate its length */
  1340. bus->rxctl += doff;
  1341. bus->rxlen = len - doff;
  1342. done:
  1343. /* Awake any waiters */
  1344. brcmf_sdbrcm_dcmd_resp_wake(bus);
  1345. }
  1346. /* Pad read to blocksize for efficiency */
  1347. static void brcmf_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
  1348. {
  1349. if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
  1350. *pad = bus->blocksize - (*rdlen % bus->blocksize);
  1351. if (*pad <= bus->roundup && *pad < bus->blocksize &&
  1352. *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
  1353. *rdlen += *pad;
  1354. } else if (*rdlen % BRCMF_SDALIGN) {
  1355. *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
  1356. }
  1357. }
  1358. static void
  1359. brcmf_alloc_pkt_and_read(struct brcmf_sdio *bus, u16 rdlen,
  1360. struct sk_buff **pkt, u8 **rxbuf)
  1361. {
  1362. int sdret; /* Return code from calls */
  1363. *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
  1364. if (*pkt == NULL)
  1365. return;
  1366. pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
  1367. *rxbuf = (u8 *) ((*pkt)->data);
  1368. /* Read the entire frame */
  1369. sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
  1370. SDIO_FUNC_2, F2SYNC, *pkt);
  1371. bus->f2rxdata++;
  1372. if (sdret < 0) {
  1373. brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
  1374. rdlen, sdret);
  1375. brcmu_pkt_buf_free_skb(*pkt);
  1376. bus->drvr->rx_errors++;
  1377. /* Force retry w/normal header read.
  1378. * Don't attempt NAK for
  1379. * gSPI
  1380. */
  1381. brcmf_sdbrcm_rxfail(bus, true, true);
  1382. *pkt = NULL;
  1383. }
  1384. }
  1385. /* Checks the header */
  1386. static int
  1387. brcmf_check_rxbuf(struct brcmf_sdio *bus, struct sk_buff *pkt, u8 *rxbuf,
  1388. u8 rxseq, u16 nextlen, u16 *len)
  1389. {
  1390. u16 check;
  1391. bool len_consistent; /* Result of comparing readahead len and
  1392. len from hw-hdr */
  1393. memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
  1394. /* Extract hardware header fields */
  1395. *len = get_unaligned_le16(bus->rxhdr);
  1396. check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
  1397. /* All zeros means readahead info was bad */
  1398. if (!(*len | check)) {
  1399. brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
  1400. goto fail;
  1401. }
  1402. /* Validate check bytes */
  1403. if ((u16)~(*len ^ check)) {
  1404. brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
  1405. nextlen, *len, check);
  1406. bus->rx_badhdr++;
  1407. brcmf_sdbrcm_rxfail(bus, false, false);
  1408. goto fail;
  1409. }
  1410. /* Validate frame length */
  1411. if (*len < SDPCM_HDRLEN) {
  1412. brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
  1413. *len);
  1414. goto fail;
  1415. }
  1416. /* Check for consistency with readahead info */
  1417. len_consistent = (nextlen != (roundup(*len, 16) >> 4));
  1418. if (len_consistent) {
  1419. /* Mismatch, force retry w/normal
  1420. header (may be >4K) */
  1421. brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
  1422. nextlen, *len, roundup(*len, 16),
  1423. rxseq);
  1424. brcmf_sdbrcm_rxfail(bus, true, true);
  1425. goto fail;
  1426. }
  1427. return 0;
  1428. fail:
  1429. brcmf_sdbrcm_pktfree2(bus, pkt);
  1430. return -EINVAL;
  1431. }
  1432. /* Return true if there may be more frames to read */
  1433. static uint
  1434. brcmf_sdbrcm_readframes(struct brcmf_sdio *bus, uint maxframes, bool *finished)
  1435. {
  1436. u16 len, check; /* Extracted hardware header fields */
  1437. u8 chan, seq, doff; /* Extracted software header fields */
  1438. u8 fcbits; /* Extracted fcbits from software header */
  1439. struct sk_buff *pkt; /* Packet for event or data frames */
  1440. u16 pad; /* Number of pad bytes to read */
  1441. u16 rdlen; /* Total number of bytes to read */
  1442. u8 rxseq; /* Next sequence number to expect */
  1443. uint rxleft = 0; /* Remaining number of frames allowed */
  1444. int sdret; /* Return code from calls */
  1445. u8 txmax; /* Maximum tx sequence offered */
  1446. u8 *rxbuf;
  1447. int ifidx = 0;
  1448. uint rxcount = 0; /* Total frames read */
  1449. brcmf_dbg(TRACE, "Enter\n");
  1450. /* Not finished unless we encounter no more frames indication */
  1451. *finished = false;
  1452. for (rxseq = bus->rx_seq, rxleft = maxframes;
  1453. !bus->rxskip && rxleft &&
  1454. bus->drvr->bus_if->state != BRCMF_BUS_DOWN;
  1455. rxseq++, rxleft--) {
  1456. /* Handle glomming separately */
  1457. if (bus->glomd || !skb_queue_empty(&bus->glom)) {
  1458. u8 cnt;
  1459. brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
  1460. bus->glomd, skb_peek(&bus->glom));
  1461. cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
  1462. brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
  1463. rxseq += cnt - 1;
  1464. rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
  1465. continue;
  1466. }
  1467. /* Try doing single read if we can */
  1468. if (bus->nextlen) {
  1469. u16 nextlen = bus->nextlen;
  1470. bus->nextlen = 0;
  1471. rdlen = len = nextlen << 4;
  1472. brcmf_pad(bus, &pad, &rdlen);
  1473. /*
  1474. * After the frame is received we have to
  1475. * distinguish whether it is data
  1476. * or non-data frame.
  1477. */
  1478. brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
  1479. if (pkt == NULL) {
  1480. /* Give up on data, request rtx of events */
  1481. brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
  1482. len, rdlen, rxseq);
  1483. continue;
  1484. }
  1485. if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
  1486. &len) < 0)
  1487. continue;
  1488. /* Extract software header fields */
  1489. chan = SDPCM_PACKET_CHANNEL(
  1490. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1491. seq = SDPCM_PACKET_SEQUENCE(
  1492. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1493. doff = SDPCM_DOFFSET_VALUE(
  1494. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1495. txmax = SDPCM_WINDOW_VALUE(
  1496. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1497. bus->nextlen =
  1498. bus->rxhdr[SDPCM_FRAMETAG_LEN +
  1499. SDPCM_NEXTLEN_OFFSET];
  1500. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1501. brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
  1502. bus->nextlen, seq);
  1503. bus->nextlen = 0;
  1504. }
  1505. bus->drvr->rx_readahead_cnt++;
  1506. /* Handle Flow Control */
  1507. fcbits = SDPCM_FCMASK_VALUE(
  1508. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1509. if (bus->flowcontrol != fcbits) {
  1510. if (~bus->flowcontrol & fcbits)
  1511. bus->fc_xoff++;
  1512. if (bus->flowcontrol & ~fcbits)
  1513. bus->fc_xon++;
  1514. bus->fc_rcvd++;
  1515. bus->flowcontrol = fcbits;
  1516. }
  1517. /* Check and update sequence number */
  1518. if (rxseq != seq) {
  1519. brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
  1520. seq, rxseq);
  1521. bus->rx_badseq++;
  1522. rxseq = seq;
  1523. }
  1524. /* Check window for sanity */
  1525. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1526. brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
  1527. txmax, bus->tx_seq);
  1528. txmax = bus->tx_seq + 2;
  1529. }
  1530. bus->tx_max = txmax;
  1531. #ifdef BCMDBG
  1532. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1533. printk(KERN_DEBUG "Rx Data:\n");
  1534. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1535. rxbuf, len);
  1536. } else if (BRCMF_HDRS_ON()) {
  1537. printk(KERN_DEBUG "RxHdr:\n");
  1538. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1539. bus->rxhdr, SDPCM_HDRLEN);
  1540. }
  1541. #endif
  1542. if (chan == SDPCM_CONTROL_CHANNEL) {
  1543. brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
  1544. seq);
  1545. /* Force retry w/normal header read */
  1546. bus->nextlen = 0;
  1547. brcmf_sdbrcm_rxfail(bus, false, true);
  1548. brcmf_sdbrcm_pktfree2(bus, pkt);
  1549. continue;
  1550. }
  1551. /* Validate data offset */
  1552. if ((doff < SDPCM_HDRLEN) || (doff > len)) {
  1553. brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
  1554. doff, len, SDPCM_HDRLEN);
  1555. brcmf_sdbrcm_rxfail(bus, false, false);
  1556. brcmf_sdbrcm_pktfree2(bus, pkt);
  1557. continue;
  1558. }
  1559. /* All done with this one -- now deliver the packet */
  1560. goto deliver;
  1561. }
  1562. /* Read frame header (hardware and software) */
  1563. sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
  1564. SDIO_FUNC_2, F2SYNC, bus->rxhdr,
  1565. BRCMF_FIRSTREAD);
  1566. bus->f2rxhdrs++;
  1567. if (sdret < 0) {
  1568. brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
  1569. bus->rx_hdrfail++;
  1570. brcmf_sdbrcm_rxfail(bus, true, true);
  1571. continue;
  1572. }
  1573. #ifdef BCMDBG
  1574. if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
  1575. printk(KERN_DEBUG "RxHdr:\n");
  1576. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1577. bus->rxhdr, SDPCM_HDRLEN);
  1578. }
  1579. #endif
  1580. /* Extract hardware header fields */
  1581. len = get_unaligned_le16(bus->rxhdr);
  1582. check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
  1583. /* All zeros means no more frames */
  1584. if (!(len | check)) {
  1585. *finished = true;
  1586. break;
  1587. }
  1588. /* Validate check bytes */
  1589. if ((u16) ~(len ^ check)) {
  1590. brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
  1591. len, check);
  1592. bus->rx_badhdr++;
  1593. brcmf_sdbrcm_rxfail(bus, false, false);
  1594. continue;
  1595. }
  1596. /* Validate frame length */
  1597. if (len < SDPCM_HDRLEN) {
  1598. brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
  1599. continue;
  1600. }
  1601. /* Extract software header fields */
  1602. chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1603. seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1604. doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1605. txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1606. /* Validate data offset */
  1607. if ((doff < SDPCM_HDRLEN) || (doff > len)) {
  1608. brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
  1609. doff, len, SDPCM_HDRLEN, seq);
  1610. bus->rx_badhdr++;
  1611. brcmf_sdbrcm_rxfail(bus, false, false);
  1612. continue;
  1613. }
  1614. /* Save the readahead length if there is one */
  1615. bus->nextlen =
  1616. bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
  1617. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1618. brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
  1619. bus->nextlen, seq);
  1620. bus->nextlen = 0;
  1621. }
  1622. /* Handle Flow Control */
  1623. fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1624. if (bus->flowcontrol != fcbits) {
  1625. if (~bus->flowcontrol & fcbits)
  1626. bus->fc_xoff++;
  1627. if (bus->flowcontrol & ~fcbits)
  1628. bus->fc_xon++;
  1629. bus->fc_rcvd++;
  1630. bus->flowcontrol = fcbits;
  1631. }
  1632. /* Check and update sequence number */
  1633. if (rxseq != seq) {
  1634. brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
  1635. bus->rx_badseq++;
  1636. rxseq = seq;
  1637. }
  1638. /* Check window for sanity */
  1639. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1640. brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
  1641. txmax, bus->tx_seq);
  1642. txmax = bus->tx_seq + 2;
  1643. }
  1644. bus->tx_max = txmax;
  1645. /* Call a separate function for control frames */
  1646. if (chan == SDPCM_CONTROL_CHANNEL) {
  1647. brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
  1648. continue;
  1649. }
  1650. /* precondition: chan is either SDPCM_DATA_CHANNEL,
  1651. SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
  1652. SDPCM_GLOM_CHANNEL */
  1653. /* Length to read */
  1654. rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
  1655. /* May pad read to blocksize for efficiency */
  1656. if (bus->roundup && bus->blocksize &&
  1657. (rdlen > bus->blocksize)) {
  1658. pad = bus->blocksize - (rdlen % bus->blocksize);
  1659. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1660. ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
  1661. rdlen += pad;
  1662. } else if (rdlen % BRCMF_SDALIGN) {
  1663. rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
  1664. }
  1665. /* Satisfy length-alignment requirements */
  1666. if (rdlen & (ALIGNMENT - 1))
  1667. rdlen = roundup(rdlen, ALIGNMENT);
  1668. if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
  1669. /* Too long -- skip this frame */
  1670. brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
  1671. len, rdlen);
  1672. bus->drvr->rx_errors++;
  1673. bus->rx_toolong++;
  1674. brcmf_sdbrcm_rxfail(bus, false, false);
  1675. continue;
  1676. }
  1677. pkt = brcmu_pkt_buf_get_skb(rdlen +
  1678. BRCMF_FIRSTREAD + BRCMF_SDALIGN);
  1679. if (!pkt) {
  1680. /* Give up on data, request rtx of events */
  1681. brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
  1682. rdlen, chan);
  1683. bus->drvr->rx_dropped++;
  1684. brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
  1685. continue;
  1686. }
  1687. /* Leave room for what we already read, and align remainder */
  1688. skb_pull(pkt, BRCMF_FIRSTREAD);
  1689. pkt_align(pkt, rdlen, BRCMF_SDALIGN);
  1690. /* Read the remaining frame data */
  1691. sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
  1692. SDIO_FUNC_2, F2SYNC, pkt);
  1693. bus->f2rxdata++;
  1694. if (sdret < 0) {
  1695. brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
  1696. ((chan == SDPCM_EVENT_CHANNEL) ? "event"
  1697. : ((chan == SDPCM_DATA_CHANNEL) ? "data"
  1698. : "test")), sdret);
  1699. brcmu_pkt_buf_free_skb(pkt);
  1700. bus->drvr->rx_errors++;
  1701. brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
  1702. continue;
  1703. }
  1704. /* Copy the already-read portion */
  1705. skb_push(pkt, BRCMF_FIRSTREAD);
  1706. memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
  1707. #ifdef BCMDBG
  1708. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1709. printk(KERN_DEBUG "Rx Data:\n");
  1710. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1711. pkt->data, len);
  1712. }
  1713. #endif
  1714. deliver:
  1715. /* Save superframe descriptor and allocate packet frame */
  1716. if (chan == SDPCM_GLOM_CHANNEL) {
  1717. if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
  1718. brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
  1719. len);
  1720. #ifdef BCMDBG
  1721. if (BRCMF_GLOM_ON()) {
  1722. printk(KERN_DEBUG "Glom Data:\n");
  1723. print_hex_dump_bytes("",
  1724. DUMP_PREFIX_OFFSET,
  1725. pkt->data, len);
  1726. }
  1727. #endif
  1728. __skb_trim(pkt, len);
  1729. skb_pull(pkt, SDPCM_HDRLEN);
  1730. bus->glomd = pkt;
  1731. } else {
  1732. brcmf_dbg(ERROR, "%s: glom superframe w/o "
  1733. "descriptor!\n", __func__);
  1734. brcmf_sdbrcm_rxfail(bus, false, false);
  1735. }
  1736. continue;
  1737. }
  1738. /* Fill in packet len and prio, deliver upward */
  1739. __skb_trim(pkt, len);
  1740. skb_pull(pkt, doff);
  1741. if (pkt->len == 0) {
  1742. brcmu_pkt_buf_free_skb(pkt);
  1743. continue;
  1744. } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
  1745. brcmf_dbg(ERROR, "rx protocol error\n");
  1746. brcmu_pkt_buf_free_skb(pkt);
  1747. bus->drvr->rx_errors++;
  1748. continue;
  1749. }
  1750. /* Unlock during rx call */
  1751. up(&bus->sdsem);
  1752. brcmf_rx_packet(bus->drvr, ifidx, pkt);
  1753. down(&bus->sdsem);
  1754. }
  1755. rxcount = maxframes - rxleft;
  1756. #ifdef BCMDBG
  1757. /* Message if we hit the limit */
  1758. if (!rxleft)
  1759. brcmf_dbg(DATA, "hit rx limit of %d frames\n",
  1760. maxframes);
  1761. else
  1762. #endif /* BCMDBG */
  1763. brcmf_dbg(DATA, "processed %d frames\n", rxcount);
  1764. /* Back off rxseq if awaiting rtx, update rx_seq */
  1765. if (bus->rxskip)
  1766. rxseq--;
  1767. bus->rx_seq = rxseq;
  1768. return rxcount;
  1769. }
  1770. static void
  1771. brcmf_sdbrcm_wait_for_event(struct brcmf_sdio *bus, bool *lockvar)
  1772. {
  1773. up(&bus->sdsem);
  1774. wait_event_interruptible_timeout(bus->ctrl_wait,
  1775. (*lockvar == false), HZ * 2);
  1776. down(&bus->sdsem);
  1777. return;
  1778. }
  1779. static void
  1780. brcmf_sdbrcm_wait_event_wakeup(struct brcmf_sdio *bus)
  1781. {
  1782. if (waitqueue_active(&bus->ctrl_wait))
  1783. wake_up_interruptible(&bus->ctrl_wait);
  1784. return;
  1785. }
  1786. /* Writes a HW/SW header into the packet and sends it. */
  1787. /* Assumes: (a) header space already there, (b) caller holds lock */
  1788. static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff *pkt,
  1789. uint chan, bool free_pkt)
  1790. {
  1791. int ret;
  1792. u8 *frame;
  1793. u16 len, pad = 0;
  1794. u32 swheader;
  1795. struct sk_buff *new;
  1796. int i;
  1797. brcmf_dbg(TRACE, "Enter\n");
  1798. frame = (u8 *) (pkt->data);
  1799. /* Add alignment padding, allocate new packet if needed */
  1800. pad = ((unsigned long)frame % BRCMF_SDALIGN);
  1801. if (pad) {
  1802. if (skb_headroom(pkt) < pad) {
  1803. brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
  1804. skb_headroom(pkt), pad);
  1805. bus->drvr->tx_realloc++;
  1806. new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
  1807. if (!new) {
  1808. brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
  1809. pkt->len + BRCMF_SDALIGN);
  1810. ret = -ENOMEM;
  1811. goto done;
  1812. }
  1813. pkt_align(new, pkt->len, BRCMF_SDALIGN);
  1814. memcpy(new->data, pkt->data, pkt->len);
  1815. if (free_pkt)
  1816. brcmu_pkt_buf_free_skb(pkt);
  1817. /* free the pkt if canned one is not used */
  1818. free_pkt = true;
  1819. pkt = new;
  1820. frame = (u8 *) (pkt->data);
  1821. /* precondition: (frame % BRCMF_SDALIGN) == 0) */
  1822. pad = 0;
  1823. } else {
  1824. skb_push(pkt, pad);
  1825. frame = (u8 *) (pkt->data);
  1826. /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
  1827. memset(frame, 0, pad + SDPCM_HDRLEN);
  1828. }
  1829. }
  1830. /* precondition: pad < BRCMF_SDALIGN */
  1831. /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
  1832. len = (u16) (pkt->len);
  1833. *(__le16 *) frame = cpu_to_le16(len);
  1834. *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
  1835. /* Software tag: channel, sequence number, data offset */
  1836. swheader =
  1837. ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
  1838. (((pad +
  1839. SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
  1840. put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
  1841. put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
  1842. #ifdef BCMDBG
  1843. tx_packets[pkt->priority]++;
  1844. if (BRCMF_BYTES_ON() &&
  1845. (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
  1846. (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
  1847. printk(KERN_DEBUG "Tx Frame:\n");
  1848. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
  1849. } else if (BRCMF_HDRS_ON()) {
  1850. printk(KERN_DEBUG "TxHdr:\n");
  1851. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1852. frame, min_t(u16, len, 16));
  1853. }
  1854. #endif
  1855. /* Raise len to next SDIO block to eliminate tail command */
  1856. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  1857. u16 pad = bus->blocksize - (len % bus->blocksize);
  1858. if ((pad <= bus->roundup) && (pad < bus->blocksize))
  1859. len += pad;
  1860. } else if (len % BRCMF_SDALIGN) {
  1861. len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
  1862. }
  1863. /* Some controllers have trouble with odd bytes -- round to even */
  1864. if (len & (ALIGNMENT - 1))
  1865. len = roundup(len, ALIGNMENT);
  1866. ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad,
  1867. SDIO_FUNC_2, F2SYNC, pkt);
  1868. bus->f2txdata++;
  1869. if (ret < 0) {
  1870. /* On failure, abort the command and terminate the frame */
  1871. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  1872. ret);
  1873. bus->tx_sderrs++;
  1874. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  1875. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  1876. SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
  1877. NULL);
  1878. bus->f1regdata++;
  1879. for (i = 0; i < 3; i++) {
  1880. u8 hi, lo;
  1881. hi = brcmf_sdcard_cfg_read(bus->sdiodev,
  1882. SDIO_FUNC_1,
  1883. SBSDIO_FUNC1_WFRAMEBCHI,
  1884. NULL);
  1885. lo = brcmf_sdcard_cfg_read(bus->sdiodev,
  1886. SDIO_FUNC_1,
  1887. SBSDIO_FUNC1_WFRAMEBCLO,
  1888. NULL);
  1889. bus->f1regdata += 2;
  1890. if ((hi == 0) && (lo == 0))
  1891. break;
  1892. }
  1893. }
  1894. if (ret == 0)
  1895. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  1896. done:
  1897. /* restore pkt buffer pointer before calling tx complete routine */
  1898. skb_pull(pkt, SDPCM_HDRLEN + pad);
  1899. up(&bus->sdsem);
  1900. brcmf_txcomplete(bus->drvr, pkt, ret != 0);
  1901. down(&bus->sdsem);
  1902. if (free_pkt)
  1903. brcmu_pkt_buf_free_skb(pkt);
  1904. return ret;
  1905. }
  1906. static uint brcmf_sdbrcm_sendfromq(struct brcmf_sdio *bus, uint maxframes)
  1907. {
  1908. struct sk_buff *pkt;
  1909. u32 intstatus = 0;
  1910. uint retries = 0;
  1911. int ret = 0, prec_out;
  1912. uint cnt = 0;
  1913. uint datalen;
  1914. u8 tx_prec_map;
  1915. struct brcmf_pub *drvr = bus->drvr;
  1916. brcmf_dbg(TRACE, "Enter\n");
  1917. tx_prec_map = ~bus->flowcontrol;
  1918. /* Send frames until the limit or some other event */
  1919. for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
  1920. spin_lock_bh(&bus->txqlock);
  1921. pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
  1922. if (pkt == NULL) {
  1923. spin_unlock_bh(&bus->txqlock);
  1924. break;
  1925. }
  1926. spin_unlock_bh(&bus->txqlock);
  1927. datalen = pkt->len - SDPCM_HDRLEN;
  1928. ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
  1929. if (ret)
  1930. bus->drvr->tx_errors++;
  1931. else
  1932. bus->drvr->dstats.tx_bytes += datalen;
  1933. /* In poll mode, need to check for other events */
  1934. if (!bus->intr && cnt) {
  1935. /* Check device status, signal pending interrupt */
  1936. r_sdreg32(bus, &intstatus,
  1937. offsetof(struct sdpcmd_regs, intstatus),
  1938. &retries);
  1939. bus->f2txdata++;
  1940. if (brcmf_sdcard_regfail(bus->sdiodev))
  1941. break;
  1942. if (intstatus & bus->hostintmask)
  1943. bus->ipend = true;
  1944. }
  1945. }
  1946. /* Deflow-control stack if needed */
  1947. if (drvr->up && (drvr->bus_if->state == BRCMF_BUS_DATA) &&
  1948. drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
  1949. brcmf_txflowcontrol(drvr, 0, OFF);
  1950. return cnt;
  1951. }
  1952. static bool brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
  1953. {
  1954. u32 intstatus, newstatus = 0;
  1955. uint retries = 0;
  1956. uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
  1957. uint txlimit = bus->txbound; /* Tx frames to send before resched */
  1958. uint framecnt = 0; /* Temporary counter of tx/rx frames */
  1959. bool rxdone = true; /* Flag for no more read data */
  1960. bool resched = false; /* Flag indicating resched wanted */
  1961. brcmf_dbg(TRACE, "Enter\n");
  1962. /* Start with leftover status bits */
  1963. intstatus = bus->intstatus;
  1964. down(&bus->sdsem);
  1965. /* If waiting for HTAVAIL, check status */
  1966. if (bus->clkstate == CLK_PENDING) {
  1967. int err;
  1968. u8 clkctl, devctl = 0;
  1969. #ifdef BCMDBG
  1970. /* Check for inconsistent device control */
  1971. devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  1972. SBSDIO_DEVICE_CTL, &err);
  1973. if (err) {
  1974. brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
  1975. bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
  1976. }
  1977. #endif /* BCMDBG */
  1978. /* Read CSR, if clock on switch to AVAIL, else ignore */
  1979. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  1980. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  1981. if (err) {
  1982. brcmf_dbg(ERROR, "error reading CSR: %d\n",
  1983. err);
  1984. bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
  1985. }
  1986. brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
  1987. devctl, clkctl);
  1988. if (SBSDIO_HTAV(clkctl)) {
  1989. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  1990. SDIO_FUNC_1,
  1991. SBSDIO_DEVICE_CTL, &err);
  1992. if (err) {
  1993. brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
  1994. err);
  1995. bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
  1996. }
  1997. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  1998. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  1999. SBSDIO_DEVICE_CTL, devctl, &err);
  2000. if (err) {
  2001. brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
  2002. err);
  2003. bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
  2004. }
  2005. bus->clkstate = CLK_AVAIL;
  2006. } else {
  2007. goto clkwait;
  2008. }
  2009. }
  2010. bus_wake(bus);
  2011. /* Make sure backplane clock is on */
  2012. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
  2013. if (bus->clkstate == CLK_PENDING)
  2014. goto clkwait;
  2015. /* Pending interrupt indicates new device status */
  2016. if (bus->ipend) {
  2017. bus->ipend = false;
  2018. r_sdreg32(bus, &newstatus,
  2019. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2020. bus->f1regdata++;
  2021. if (brcmf_sdcard_regfail(bus->sdiodev))
  2022. newstatus = 0;
  2023. newstatus &= bus->hostintmask;
  2024. bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
  2025. if (newstatus) {
  2026. w_sdreg32(bus, newstatus,
  2027. offsetof(struct sdpcmd_regs, intstatus),
  2028. &retries);
  2029. bus->f1regdata++;
  2030. }
  2031. }
  2032. /* Merge new bits with previous */
  2033. intstatus |= newstatus;
  2034. bus->intstatus = 0;
  2035. /* Handle flow-control change: read new state in case our ack
  2036. * crossed another change interrupt. If change still set, assume
  2037. * FC ON for safety, let next loop through do the debounce.
  2038. */
  2039. if (intstatus & I_HMB_FC_CHANGE) {
  2040. intstatus &= ~I_HMB_FC_CHANGE;
  2041. w_sdreg32(bus, I_HMB_FC_CHANGE,
  2042. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2043. r_sdreg32(bus, &newstatus,
  2044. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2045. bus->f1regdata += 2;
  2046. bus->fcstate =
  2047. !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
  2048. intstatus |= (newstatus & bus->hostintmask);
  2049. }
  2050. /* Handle host mailbox indication */
  2051. if (intstatus & I_HMB_HOST_INT) {
  2052. intstatus &= ~I_HMB_HOST_INT;
  2053. intstatus |= brcmf_sdbrcm_hostmail(bus);
  2054. }
  2055. /* Generally don't ask for these, can get CRC errors... */
  2056. if (intstatus & I_WR_OOSYNC) {
  2057. brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
  2058. intstatus &= ~I_WR_OOSYNC;
  2059. }
  2060. if (intstatus & I_RD_OOSYNC) {
  2061. brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
  2062. intstatus &= ~I_RD_OOSYNC;
  2063. }
  2064. if (intstatus & I_SBINT) {
  2065. brcmf_dbg(ERROR, "Dongle reports SBINT\n");
  2066. intstatus &= ~I_SBINT;
  2067. }
  2068. /* Would be active due to wake-wlan in gSPI */
  2069. if (intstatus & I_CHIPACTIVE) {
  2070. brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
  2071. intstatus &= ~I_CHIPACTIVE;
  2072. }
  2073. /* Ignore frame indications if rxskip is set */
  2074. if (bus->rxskip)
  2075. intstatus &= ~I_HMB_FRAME_IND;
  2076. /* On frame indication, read available frames */
  2077. if (PKT_AVAILABLE()) {
  2078. framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
  2079. if (rxdone || bus->rxskip)
  2080. intstatus &= ~I_HMB_FRAME_IND;
  2081. rxlimit -= min(framecnt, rxlimit);
  2082. }
  2083. /* Keep still-pending events for next scheduling */
  2084. bus->intstatus = intstatus;
  2085. clkwait:
  2086. if (data_ok(bus) && bus->ctrl_frame_stat &&
  2087. (bus->clkstate == CLK_AVAIL)) {
  2088. int ret, i;
  2089. ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
  2090. SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
  2091. (u32) bus->ctrl_frame_len);
  2092. if (ret < 0) {
  2093. /* On failure, abort the command and
  2094. terminate the frame */
  2095. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2096. ret);
  2097. bus->tx_sderrs++;
  2098. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2099. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2100. SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
  2101. NULL);
  2102. bus->f1regdata++;
  2103. for (i = 0; i < 3; i++) {
  2104. u8 hi, lo;
  2105. hi = brcmf_sdcard_cfg_read(bus->sdiodev,
  2106. SDIO_FUNC_1,
  2107. SBSDIO_FUNC1_WFRAMEBCHI,
  2108. NULL);
  2109. lo = brcmf_sdcard_cfg_read(bus->sdiodev,
  2110. SDIO_FUNC_1,
  2111. SBSDIO_FUNC1_WFRAMEBCLO,
  2112. NULL);
  2113. bus->f1regdata += 2;
  2114. if ((hi == 0) && (lo == 0))
  2115. break;
  2116. }
  2117. }
  2118. if (ret == 0)
  2119. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2120. brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
  2121. bus->ctrl_frame_stat = false;
  2122. brcmf_sdbrcm_wait_event_wakeup(bus);
  2123. }
  2124. /* Send queued frames (limit 1 if rx may still be pending) */
  2125. else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
  2126. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
  2127. && data_ok(bus)) {
  2128. framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
  2129. framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
  2130. txlimit -= framecnt;
  2131. }
  2132. /* Resched if events or tx frames are pending,
  2133. else await next interrupt */
  2134. /* On failed register access, all bets are off:
  2135. no resched or interrupts */
  2136. if ((bus->drvr->bus_if->state == BRCMF_BUS_DOWN) ||
  2137. brcmf_sdcard_regfail(bus->sdiodev)) {
  2138. brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
  2139. brcmf_sdcard_regfail(bus->sdiodev));
  2140. bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
  2141. bus->intstatus = 0;
  2142. } else if (bus->clkstate == CLK_PENDING) {
  2143. brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
  2144. resched = true;
  2145. } else if (bus->intstatus || bus->ipend ||
  2146. (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
  2147. && data_ok(bus)) || PKT_AVAILABLE()) {
  2148. resched = true;
  2149. }
  2150. bus->dpc_sched = resched;
  2151. /* If we're done for now, turn off clock request. */
  2152. if ((bus->clkstate != CLK_PENDING)
  2153. && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
  2154. bus->activity = false;
  2155. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  2156. }
  2157. up(&bus->sdsem);
  2158. return resched;
  2159. }
  2160. static int brcmf_sdbrcm_dpc_thread(void *data)
  2161. {
  2162. struct brcmf_sdio *bus = (struct brcmf_sdio *) data;
  2163. allow_signal(SIGTERM);
  2164. /* Run until signal received */
  2165. while (1) {
  2166. if (kthread_should_stop())
  2167. break;
  2168. if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
  2169. /* Call bus dpc unless it indicated down
  2170. (then clean stop) */
  2171. if (bus->drvr->bus_if->state != BRCMF_BUS_DOWN) {
  2172. if (brcmf_sdbrcm_dpc(bus))
  2173. complete(&bus->dpc_wait);
  2174. } else {
  2175. /* after stopping the bus, exit thread */
  2176. brcmf_sdbrcm_bus_stop(bus);
  2177. bus->dpc_tsk = NULL;
  2178. break;
  2179. }
  2180. } else
  2181. break;
  2182. }
  2183. return 0;
  2184. }
  2185. int brcmf_sdbrcm_bus_txdata(struct brcmf_sdio *bus, struct sk_buff *pkt)
  2186. {
  2187. int ret = -EBADE;
  2188. uint datalen, prec;
  2189. brcmf_dbg(TRACE, "Enter\n");
  2190. datalen = pkt->len;
  2191. /* Add space for the header */
  2192. skb_push(pkt, SDPCM_HDRLEN);
  2193. /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
  2194. prec = prio2prec((pkt->priority & PRIOMASK));
  2195. /* Check for existing queue, current flow-control,
  2196. pending event, or pending clock */
  2197. brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
  2198. bus->fcqueued++;
  2199. /* Priority based enq */
  2200. spin_lock_bh(&bus->txqlock);
  2201. if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
  2202. skb_pull(pkt, SDPCM_HDRLEN);
  2203. brcmf_txcomplete(bus->drvr, pkt, false);
  2204. brcmu_pkt_buf_free_skb(pkt);
  2205. brcmf_dbg(ERROR, "out of bus->txq !!!\n");
  2206. ret = -ENOSR;
  2207. } else {
  2208. ret = 0;
  2209. }
  2210. spin_unlock_bh(&bus->txqlock);
  2211. if (pktq_len(&bus->txq) >= TXHI)
  2212. brcmf_txflowcontrol(bus->drvr, 0, ON);
  2213. #ifdef BCMDBG
  2214. if (pktq_plen(&bus->txq, prec) > qcount[prec])
  2215. qcount[prec] = pktq_plen(&bus->txq, prec);
  2216. #endif
  2217. /* Schedule DPC if needed to send queued packet(s) */
  2218. if (!bus->dpc_sched) {
  2219. bus->dpc_sched = true;
  2220. if (bus->dpc_tsk)
  2221. complete(&bus->dpc_wait);
  2222. }
  2223. return ret;
  2224. }
  2225. static int
  2226. brcmf_sdbrcm_membytes(struct brcmf_sdio *bus, bool write, u32 address, u8 *data,
  2227. uint size)
  2228. {
  2229. int bcmerror = 0;
  2230. u32 sdaddr;
  2231. uint dsize;
  2232. /* Determine initial transfer parameters */
  2233. sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
  2234. if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
  2235. dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
  2236. else
  2237. dsize = size;
  2238. /* Set the backplane window to include the start address */
  2239. bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
  2240. if (bcmerror) {
  2241. brcmf_dbg(ERROR, "window change failed\n");
  2242. goto xfer_done;
  2243. }
  2244. /* Do the transfer(s) */
  2245. while (size) {
  2246. brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
  2247. write ? "write" : "read", dsize,
  2248. sdaddr, address & SBSDIO_SBWINDOW_MASK);
  2249. bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
  2250. sdaddr, data, dsize);
  2251. if (bcmerror) {
  2252. brcmf_dbg(ERROR, "membytes transfer failed\n");
  2253. break;
  2254. }
  2255. /* Adjust for next transfer (if any) */
  2256. size -= dsize;
  2257. if (size) {
  2258. data += dsize;
  2259. address += dsize;
  2260. bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
  2261. address);
  2262. if (bcmerror) {
  2263. brcmf_dbg(ERROR, "window change failed\n");
  2264. break;
  2265. }
  2266. sdaddr = 0;
  2267. dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
  2268. }
  2269. }
  2270. xfer_done:
  2271. /* Return the window to backplane enumeration space for core access */
  2272. if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
  2273. brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
  2274. bus->sdiodev->sbwad);
  2275. return bcmerror;
  2276. }
  2277. #ifdef BCMDBG
  2278. #define CONSOLE_LINE_MAX 192
  2279. static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus)
  2280. {
  2281. struct brcmf_console *c = &bus->console;
  2282. u8 line[CONSOLE_LINE_MAX], ch;
  2283. u32 n, idx, addr;
  2284. int rv;
  2285. /* Don't do anything until FWREADY updates console address */
  2286. if (bus->console_addr == 0)
  2287. return 0;
  2288. /* Read console log struct */
  2289. addr = bus->console_addr + offsetof(struct rte_console, log_le);
  2290. rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
  2291. sizeof(c->log_le));
  2292. if (rv < 0)
  2293. return rv;
  2294. /* Allocate console buffer (one time only) */
  2295. if (c->buf == NULL) {
  2296. c->bufsize = le32_to_cpu(c->log_le.buf_size);
  2297. c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
  2298. if (c->buf == NULL)
  2299. return -ENOMEM;
  2300. }
  2301. idx = le32_to_cpu(c->log_le.idx);
  2302. /* Protect against corrupt value */
  2303. if (idx > c->bufsize)
  2304. return -EBADE;
  2305. /* Skip reading the console buffer if the index pointer
  2306. has not moved */
  2307. if (idx == c->last)
  2308. return 0;
  2309. /* Read the console buffer */
  2310. addr = le32_to_cpu(c->log_le.buf);
  2311. rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
  2312. if (rv < 0)
  2313. return rv;
  2314. while (c->last != idx) {
  2315. for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
  2316. if (c->last == idx) {
  2317. /* This would output a partial line.
  2318. * Instead, back up
  2319. * the buffer pointer and output this
  2320. * line next time around.
  2321. */
  2322. if (c->last >= n)
  2323. c->last -= n;
  2324. else
  2325. c->last = c->bufsize - n;
  2326. goto break2;
  2327. }
  2328. ch = c->buf[c->last];
  2329. c->last = (c->last + 1) % c->bufsize;
  2330. if (ch == '\n')
  2331. break;
  2332. line[n] = ch;
  2333. }
  2334. if (n > 0) {
  2335. if (line[n - 1] == '\r')
  2336. n--;
  2337. line[n] = 0;
  2338. printk(KERN_DEBUG "CONSOLE: %s\n", line);
  2339. }
  2340. }
  2341. break2:
  2342. return 0;
  2343. }
  2344. #endif /* BCMDBG */
  2345. static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
  2346. {
  2347. int i;
  2348. int ret;
  2349. bus->ctrl_frame_stat = false;
  2350. ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
  2351. SDIO_FUNC_2, F2SYNC, frame, len);
  2352. if (ret < 0) {
  2353. /* On failure, abort the command and terminate the frame */
  2354. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2355. ret);
  2356. bus->tx_sderrs++;
  2357. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2358. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2359. SBSDIO_FUNC1_FRAMECTRL,
  2360. SFC_WF_TERM, NULL);
  2361. bus->f1regdata++;
  2362. for (i = 0; i < 3; i++) {
  2363. u8 hi, lo;
  2364. hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2365. SBSDIO_FUNC1_WFRAMEBCHI,
  2366. NULL);
  2367. lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2368. SBSDIO_FUNC1_WFRAMEBCLO,
  2369. NULL);
  2370. bus->f1regdata += 2;
  2371. if (hi == 0 && lo == 0)
  2372. break;
  2373. }
  2374. return ret;
  2375. }
  2376. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2377. return ret;
  2378. }
  2379. int
  2380. brcmf_sdbrcm_bus_txctl(struct brcmf_sdio *bus, unsigned char *msg, uint msglen)
  2381. {
  2382. u8 *frame;
  2383. u16 len;
  2384. u32 swheader;
  2385. uint retries = 0;
  2386. u8 doff = 0;
  2387. int ret = -1;
  2388. brcmf_dbg(TRACE, "Enter\n");
  2389. /* Back the pointer to make a room for bus header */
  2390. frame = msg - SDPCM_HDRLEN;
  2391. len = (msglen += SDPCM_HDRLEN);
  2392. /* Add alignment padding (optional for ctl frames) */
  2393. doff = ((unsigned long)frame % BRCMF_SDALIGN);
  2394. if (doff) {
  2395. frame -= doff;
  2396. len += doff;
  2397. msglen += doff;
  2398. memset(frame, 0, doff + SDPCM_HDRLEN);
  2399. }
  2400. /* precondition: doff < BRCMF_SDALIGN */
  2401. doff += SDPCM_HDRLEN;
  2402. /* Round send length to next SDIO block */
  2403. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  2404. u16 pad = bus->blocksize - (len % bus->blocksize);
  2405. if ((pad <= bus->roundup) && (pad < bus->blocksize))
  2406. len += pad;
  2407. } else if (len % BRCMF_SDALIGN) {
  2408. len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
  2409. }
  2410. /* Satisfy length-alignment requirements */
  2411. if (len & (ALIGNMENT - 1))
  2412. len = roundup(len, ALIGNMENT);
  2413. /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
  2414. /* Need to lock here to protect txseq and SDIO tx calls */
  2415. down(&bus->sdsem);
  2416. bus_wake(bus);
  2417. /* Make sure backplane clock is on */
  2418. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2419. /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
  2420. *(__le16 *) frame = cpu_to_le16((u16) msglen);
  2421. *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
  2422. /* Software tag: channel, sequence number, data offset */
  2423. swheader =
  2424. ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
  2425. SDPCM_CHANNEL_MASK)
  2426. | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
  2427. SDPCM_DOFFSET_MASK);
  2428. put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
  2429. put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
  2430. if (!data_ok(bus)) {
  2431. brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
  2432. bus->tx_max, bus->tx_seq);
  2433. bus->ctrl_frame_stat = true;
  2434. /* Send from dpc */
  2435. bus->ctrl_frame_buf = frame;
  2436. bus->ctrl_frame_len = len;
  2437. brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
  2438. if (bus->ctrl_frame_stat == false) {
  2439. brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
  2440. ret = 0;
  2441. } else {
  2442. brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
  2443. ret = -1;
  2444. }
  2445. }
  2446. if (ret == -1) {
  2447. #ifdef BCMDBG
  2448. if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
  2449. printk(KERN_DEBUG "Tx Frame:\n");
  2450. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  2451. frame, len);
  2452. } else if (BRCMF_HDRS_ON()) {
  2453. printk(KERN_DEBUG "TxHdr:\n");
  2454. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  2455. frame, min_t(u16, len, 16));
  2456. }
  2457. #endif
  2458. do {
  2459. ret = brcmf_tx_frame(bus, frame, len);
  2460. } while (ret < 0 && retries++ < TXRETRIES);
  2461. }
  2462. if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
  2463. bus->activity = false;
  2464. brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
  2465. }
  2466. up(&bus->sdsem);
  2467. if (ret)
  2468. bus->drvr->tx_ctlerrs++;
  2469. else
  2470. bus->drvr->tx_ctlpkts++;
  2471. return ret ? -EIO : 0;
  2472. }
  2473. int
  2474. brcmf_sdbrcm_bus_rxctl(struct brcmf_sdio *bus, unsigned char *msg, uint msglen)
  2475. {
  2476. int timeleft;
  2477. uint rxlen = 0;
  2478. bool pending;
  2479. brcmf_dbg(TRACE, "Enter\n");
  2480. /* Wait until control frame is available */
  2481. timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
  2482. down(&bus->sdsem);
  2483. rxlen = bus->rxlen;
  2484. memcpy(msg, bus->rxctl, min(msglen, rxlen));
  2485. bus->rxlen = 0;
  2486. up(&bus->sdsem);
  2487. if (rxlen) {
  2488. brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
  2489. rxlen, msglen);
  2490. } else if (timeleft == 0) {
  2491. brcmf_dbg(ERROR, "resumed on timeout\n");
  2492. } else if (pending == true) {
  2493. brcmf_dbg(CTL, "cancelled\n");
  2494. return -ERESTARTSYS;
  2495. } else {
  2496. brcmf_dbg(CTL, "resumed for unknown reason?\n");
  2497. }
  2498. if (rxlen)
  2499. bus->drvr->rx_ctlpkts++;
  2500. else
  2501. bus->drvr->rx_ctlerrs++;
  2502. return rxlen ? (int)rxlen : -ETIMEDOUT;
  2503. }
  2504. static int brcmf_sdbrcm_downloadvars(struct brcmf_sdio *bus, void *arg, int len)
  2505. {
  2506. int bcmerror = 0;
  2507. brcmf_dbg(TRACE, "Enter\n");
  2508. /* Basic sanity checks */
  2509. if (bus->drvr->up) {
  2510. bcmerror = -EISCONN;
  2511. goto err;
  2512. }
  2513. if (!len) {
  2514. bcmerror = -EOVERFLOW;
  2515. goto err;
  2516. }
  2517. /* Free the old ones and replace with passed variables */
  2518. kfree(bus->vars);
  2519. bus->vars = kmalloc(len, GFP_ATOMIC);
  2520. bus->varsz = bus->vars ? len : 0;
  2521. if (bus->vars == NULL) {
  2522. bcmerror = -ENOMEM;
  2523. goto err;
  2524. }
  2525. /* Copy the passed variables, which should include the
  2526. terminating double-null */
  2527. memcpy(bus->vars, arg, bus->varsz);
  2528. err:
  2529. return bcmerror;
  2530. }
  2531. static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
  2532. {
  2533. int bcmerror = 0;
  2534. u32 varsize;
  2535. u32 varaddr;
  2536. u8 *vbuffer;
  2537. u32 varsizew;
  2538. __le32 varsizew_le;
  2539. #ifdef BCMDBG
  2540. char *nvram_ularray;
  2541. #endif /* BCMDBG */
  2542. /* Even if there are no vars are to be written, we still
  2543. need to set the ramsize. */
  2544. varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
  2545. varaddr = (bus->ramsize - 4) - varsize;
  2546. if (bus->vars) {
  2547. vbuffer = kzalloc(varsize, GFP_ATOMIC);
  2548. if (!vbuffer)
  2549. return -ENOMEM;
  2550. memcpy(vbuffer, bus->vars, bus->varsz);
  2551. /* Write the vars list */
  2552. bcmerror =
  2553. brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
  2554. #ifdef BCMDBG
  2555. /* Verify NVRAM bytes */
  2556. brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
  2557. nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
  2558. if (!nvram_ularray)
  2559. return -ENOMEM;
  2560. /* Upload image to verify downloaded contents. */
  2561. memset(nvram_ularray, 0xaa, varsize);
  2562. /* Read the vars list to temp buffer for comparison */
  2563. bcmerror =
  2564. brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
  2565. varsize);
  2566. if (bcmerror) {
  2567. brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
  2568. bcmerror, varsize, varaddr);
  2569. }
  2570. /* Compare the org NVRAM with the one read from RAM */
  2571. if (memcmp(vbuffer, nvram_ularray, varsize))
  2572. brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
  2573. else
  2574. brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
  2575. kfree(nvram_ularray);
  2576. #endif /* BCMDBG */
  2577. kfree(vbuffer);
  2578. }
  2579. /* adjust to the user specified RAM */
  2580. brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
  2581. brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
  2582. varaddr, varsize);
  2583. varsize = ((bus->ramsize - 4) - varaddr);
  2584. /*
  2585. * Determine the length token:
  2586. * Varsize, converted to words, in lower 16-bits, checksum
  2587. * in upper 16-bits.
  2588. */
  2589. if (bcmerror) {
  2590. varsizew = 0;
  2591. varsizew_le = cpu_to_le32(0);
  2592. } else {
  2593. varsizew = varsize / 4;
  2594. varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
  2595. varsizew_le = cpu_to_le32(varsizew);
  2596. }
  2597. brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
  2598. varsize, varsizew);
  2599. /* Write the length token to the last word */
  2600. bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
  2601. (u8 *)&varsizew_le, 4);
  2602. return bcmerror;
  2603. }
  2604. static int brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter)
  2605. {
  2606. uint retries;
  2607. int bcmerror = 0;
  2608. struct chip_info *ci = bus->ci;
  2609. /* To enter download state, disable ARM and reset SOCRAM.
  2610. * To exit download state, simply reset ARM (default is RAM boot).
  2611. */
  2612. if (enter) {
  2613. bus->alp_only = true;
  2614. ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
  2615. ci->resetcore(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM);
  2616. /* Clear the top bit of memory */
  2617. if (bus->ramsize) {
  2618. u32 zeros = 0;
  2619. brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
  2620. (u8 *)&zeros, 4);
  2621. }
  2622. } else {
  2623. if (!ci->iscoreup(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM)) {
  2624. brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
  2625. bcmerror = -EBADE;
  2626. goto fail;
  2627. }
  2628. bcmerror = brcmf_sdbrcm_write_vars(bus);
  2629. if (bcmerror) {
  2630. brcmf_dbg(ERROR, "no vars written to RAM\n");
  2631. bcmerror = 0;
  2632. }
  2633. w_sdreg32(bus, 0xFFFFFFFF,
  2634. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2635. ci->resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
  2636. /* Allow HT Clock now that the ARM is running. */
  2637. bus->alp_only = false;
  2638. bus->drvr->bus_if->state = BRCMF_BUS_LOAD;
  2639. }
  2640. fail:
  2641. return bcmerror;
  2642. }
  2643. static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_sdio *bus)
  2644. {
  2645. if (bus->firmware->size < bus->fw_ptr + len)
  2646. len = bus->firmware->size - bus->fw_ptr;
  2647. memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
  2648. bus->fw_ptr += len;
  2649. return len;
  2650. }
  2651. static int brcmf_sdbrcm_download_code_file(struct brcmf_sdio *bus)
  2652. {
  2653. int offset = 0;
  2654. uint len;
  2655. u8 *memblock = NULL, *memptr;
  2656. int ret;
  2657. brcmf_dbg(INFO, "Enter\n");
  2658. ret = request_firmware(&bus->firmware, BRCMFMAC_FW_NAME,
  2659. &bus->sdiodev->func[2]->dev);
  2660. if (ret) {
  2661. brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
  2662. return ret;
  2663. }
  2664. bus->fw_ptr = 0;
  2665. memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
  2666. if (memblock == NULL) {
  2667. ret = -ENOMEM;
  2668. goto err;
  2669. }
  2670. if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
  2671. memptr += (BRCMF_SDALIGN -
  2672. ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
  2673. /* Download image */
  2674. while ((len =
  2675. brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
  2676. ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
  2677. if (ret) {
  2678. brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
  2679. ret, MEMBLOCK, offset);
  2680. goto err;
  2681. }
  2682. offset += MEMBLOCK;
  2683. }
  2684. err:
  2685. kfree(memblock);
  2686. release_firmware(bus->firmware);
  2687. bus->fw_ptr = 0;
  2688. return ret;
  2689. }
  2690. /*
  2691. * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
  2692. * and ending in a NUL.
  2693. * Removes carriage returns, empty lines, comment lines, and converts
  2694. * newlines to NULs.
  2695. * Shortens buffer as needed and pads with NULs. End of buffer is marked
  2696. * by two NULs.
  2697. */
  2698. static uint brcmf_process_nvram_vars(char *varbuf, uint len)
  2699. {
  2700. char *dp;
  2701. bool findNewline;
  2702. int column;
  2703. uint buf_len, n;
  2704. dp = varbuf;
  2705. findNewline = false;
  2706. column = 0;
  2707. for (n = 0; n < len; n++) {
  2708. if (varbuf[n] == 0)
  2709. break;
  2710. if (varbuf[n] == '\r')
  2711. continue;
  2712. if (findNewline && varbuf[n] != '\n')
  2713. continue;
  2714. findNewline = false;
  2715. if (varbuf[n] == '#') {
  2716. findNewline = true;
  2717. continue;
  2718. }
  2719. if (varbuf[n] == '\n') {
  2720. if (column == 0)
  2721. continue;
  2722. *dp++ = 0;
  2723. column = 0;
  2724. continue;
  2725. }
  2726. *dp++ = varbuf[n];
  2727. column++;
  2728. }
  2729. buf_len = dp - varbuf;
  2730. while (dp < varbuf + n)
  2731. *dp++ = 0;
  2732. return buf_len;
  2733. }
  2734. static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus)
  2735. {
  2736. uint len;
  2737. char *memblock = NULL;
  2738. char *bufp;
  2739. int ret;
  2740. ret = request_firmware(&bus->firmware, BRCMFMAC_NV_NAME,
  2741. &bus->sdiodev->func[2]->dev);
  2742. if (ret) {
  2743. brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
  2744. return ret;
  2745. }
  2746. bus->fw_ptr = 0;
  2747. memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
  2748. if (memblock == NULL) {
  2749. ret = -ENOMEM;
  2750. goto err;
  2751. }
  2752. len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
  2753. if (len > 0 && len < MEMBLOCK) {
  2754. bufp = (char *)memblock;
  2755. bufp[len] = 0;
  2756. len = brcmf_process_nvram_vars(bufp, len);
  2757. bufp += len;
  2758. *bufp++ = 0;
  2759. if (len)
  2760. ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
  2761. if (ret)
  2762. brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
  2763. } else {
  2764. brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
  2765. ret = -EIO;
  2766. }
  2767. err:
  2768. kfree(memblock);
  2769. release_firmware(bus->firmware);
  2770. bus->fw_ptr = 0;
  2771. return ret;
  2772. }
  2773. static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
  2774. {
  2775. int bcmerror = -1;
  2776. /* Keep arm in reset */
  2777. if (brcmf_sdbrcm_download_state(bus, true)) {
  2778. brcmf_dbg(ERROR, "error placing ARM core in reset\n");
  2779. goto err;
  2780. }
  2781. /* External image takes precedence if specified */
  2782. if (brcmf_sdbrcm_download_code_file(bus)) {
  2783. brcmf_dbg(ERROR, "dongle image file download failed\n");
  2784. goto err;
  2785. }
  2786. /* External nvram takes precedence if specified */
  2787. if (brcmf_sdbrcm_download_nvram(bus))
  2788. brcmf_dbg(ERROR, "dongle nvram file download failed\n");
  2789. /* Take arm out of reset */
  2790. if (brcmf_sdbrcm_download_state(bus, false)) {
  2791. brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
  2792. goto err;
  2793. }
  2794. bcmerror = 0;
  2795. err:
  2796. return bcmerror;
  2797. }
  2798. static bool
  2799. brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
  2800. {
  2801. bool ret;
  2802. /* Download the firmware */
  2803. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2804. ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
  2805. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  2806. return ret;
  2807. }
  2808. void brcmf_sdbrcm_bus_stop(struct brcmf_sdio *bus)
  2809. {
  2810. u32 local_hostintmask;
  2811. u8 saveclk;
  2812. uint retries;
  2813. int err;
  2814. brcmf_dbg(TRACE, "Enter\n");
  2815. if (bus->watchdog_tsk) {
  2816. send_sig(SIGTERM, bus->watchdog_tsk, 1);
  2817. kthread_stop(bus->watchdog_tsk);
  2818. bus->watchdog_tsk = NULL;
  2819. }
  2820. if (bus->dpc_tsk && bus->dpc_tsk != current) {
  2821. send_sig(SIGTERM, bus->dpc_tsk, 1);
  2822. kthread_stop(bus->dpc_tsk);
  2823. bus->dpc_tsk = NULL;
  2824. }
  2825. down(&bus->sdsem);
  2826. bus_wake(bus);
  2827. /* Enable clock for device interrupts */
  2828. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2829. /* Disable and clear interrupts at the chip level also */
  2830. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
  2831. local_hostintmask = bus->hostintmask;
  2832. bus->hostintmask = 0;
  2833. /* Change our idea of bus state */
  2834. bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
  2835. /* Force clocks on backplane to be sure F2 interrupt propagates */
  2836. saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2837. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2838. if (!err) {
  2839. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2840. SBSDIO_FUNC1_CHIPCLKCSR,
  2841. (saveclk | SBSDIO_FORCE_HT), &err);
  2842. }
  2843. if (err)
  2844. brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
  2845. /* Turn off the bus (F2), free any pending packets */
  2846. brcmf_dbg(INTR, "disable SDIO interrupts\n");
  2847. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  2848. SDIO_FUNC_ENABLE_1, NULL);
  2849. /* Clear any pending interrupts now that F2 is disabled */
  2850. w_sdreg32(bus, local_hostintmask,
  2851. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2852. /* Turn off the backplane clock (only) */
  2853. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  2854. /* Clear the data packet queues */
  2855. brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
  2856. /* Clear any held glomming stuff */
  2857. if (bus->glomd)
  2858. brcmu_pkt_buf_free_skb(bus->glomd);
  2859. brcmf_sdbrcm_free_glom(bus);
  2860. /* Clear rx control and wake any waiters */
  2861. bus->rxlen = 0;
  2862. brcmf_sdbrcm_dcmd_resp_wake(bus);
  2863. /* Reset some F2 state stuff */
  2864. bus->rxskip = false;
  2865. bus->tx_seq = bus->rx_seq = 0;
  2866. up(&bus->sdsem);
  2867. }
  2868. int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
  2869. {
  2870. struct brcmf_sdio *bus = drvr->bus;
  2871. unsigned long timeout;
  2872. uint retries = 0;
  2873. u8 ready, enable;
  2874. int err, ret = 0;
  2875. u8 saveclk;
  2876. brcmf_dbg(TRACE, "Enter\n");
  2877. /* try to download image and nvram to the dongle */
  2878. if (drvr->bus_if->state == BRCMF_BUS_DOWN) {
  2879. if (!(brcmf_sdbrcm_download_firmware(bus)))
  2880. return -1;
  2881. }
  2882. if (!bus->drvr)
  2883. return 0;
  2884. /* Start the watchdog timer */
  2885. bus->drvr->tickcnt = 0;
  2886. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  2887. down(&bus->sdsem);
  2888. /* Make sure backplane clock is on, needed to generate F2 interrupt */
  2889. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2890. if (bus->clkstate != CLK_AVAIL)
  2891. goto exit;
  2892. /* Force clocks on backplane to be sure F2 interrupt propagates */
  2893. saveclk =
  2894. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2895. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2896. if (!err) {
  2897. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2898. SBSDIO_FUNC1_CHIPCLKCSR,
  2899. (saveclk | SBSDIO_FORCE_HT), &err);
  2900. }
  2901. if (err) {
  2902. brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
  2903. goto exit;
  2904. }
  2905. /* Enable function 2 (frame transfers) */
  2906. w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
  2907. offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
  2908. enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
  2909. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  2910. enable, NULL);
  2911. timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
  2912. ready = 0;
  2913. while (enable != ready) {
  2914. ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
  2915. SDIO_CCCR_IORx, NULL);
  2916. if (time_after(jiffies, timeout))
  2917. break;
  2918. else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
  2919. /* prevent busy waiting if it takes too long */
  2920. msleep_interruptible(20);
  2921. }
  2922. brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
  2923. /* If F2 successfully enabled, set core and enable interrupts */
  2924. if (ready == enable) {
  2925. /* Set up the interrupt mask and enable interrupts */
  2926. bus->hostintmask = HOSTINTMASK;
  2927. w_sdreg32(bus, bus->hostintmask,
  2928. offsetof(struct sdpcmd_regs, hostintmask), &retries);
  2929. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2930. SBSDIO_WATERMARK, 8, &err);
  2931. /* Set bus state according to enable result */
  2932. drvr->bus_if->state = BRCMF_BUS_DATA;
  2933. }
  2934. else {
  2935. /* Disable F2 again */
  2936. enable = SDIO_FUNC_ENABLE_1;
  2937. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
  2938. SDIO_CCCR_IOEx, enable, NULL);
  2939. }
  2940. /* Restore previous clock setting */
  2941. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2942. SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
  2943. /* If we didn't come up, turn off backplane clock */
  2944. if (drvr->bus_if->state != BRCMF_BUS_DATA)
  2945. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  2946. exit:
  2947. up(&bus->sdsem);
  2948. return ret;
  2949. }
  2950. void brcmf_sdbrcm_isr(void *arg)
  2951. {
  2952. struct brcmf_sdio *bus = (struct brcmf_sdio *) arg;
  2953. brcmf_dbg(TRACE, "Enter\n");
  2954. if (!bus) {
  2955. brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
  2956. return;
  2957. }
  2958. if (bus->drvr->bus_if->state == BRCMF_BUS_DOWN) {
  2959. brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
  2960. return;
  2961. }
  2962. /* Count the interrupt call */
  2963. bus->intrcount++;
  2964. bus->ipend = true;
  2965. /* Shouldn't get this interrupt if we're sleeping? */
  2966. if (bus->sleeping) {
  2967. brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
  2968. return;
  2969. }
  2970. /* Disable additional interrupts (is this needed now)? */
  2971. if (!bus->intr)
  2972. brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
  2973. bus->dpc_sched = true;
  2974. if (bus->dpc_tsk)
  2975. complete(&bus->dpc_wait);
  2976. }
  2977. static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
  2978. {
  2979. #ifdef BCMDBG
  2980. struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev);
  2981. #endif /* BCMDBG */
  2982. brcmf_dbg(TIMER, "Enter\n");
  2983. /* Ignore the timer if simulating bus down */
  2984. if (bus->sleeping)
  2985. return false;
  2986. down(&bus->sdsem);
  2987. /* Poll period: check device if appropriate. */
  2988. if (bus->poll && (++bus->polltick >= bus->pollrate)) {
  2989. u32 intstatus = 0;
  2990. /* Reset poll tick */
  2991. bus->polltick = 0;
  2992. /* Check device if no interrupts */
  2993. if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
  2994. if (!bus->dpc_sched) {
  2995. u8 devpend;
  2996. devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
  2997. SDIO_FUNC_0, SDIO_CCCR_INTx,
  2998. NULL);
  2999. intstatus =
  3000. devpend & (INTR_STATUS_FUNC1 |
  3001. INTR_STATUS_FUNC2);
  3002. }
  3003. /* If there is something, make like the ISR and
  3004. schedule the DPC */
  3005. if (intstatus) {
  3006. bus->pollcnt++;
  3007. bus->ipend = true;
  3008. bus->dpc_sched = true;
  3009. if (bus->dpc_tsk)
  3010. complete(&bus->dpc_wait);
  3011. }
  3012. }
  3013. /* Update interrupt tracking */
  3014. bus->lastintrs = bus->intrcount;
  3015. }
  3016. #ifdef BCMDBG
  3017. /* Poll for console output periodically */
  3018. if (bus_if->state == BRCMF_BUS_DATA &&
  3019. bus->console_interval != 0) {
  3020. bus->console.count += BRCMF_WD_POLL_MS;
  3021. if (bus->console.count >= bus->console_interval) {
  3022. bus->console.count -= bus->console_interval;
  3023. /* Make sure backplane clock is on */
  3024. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3025. if (brcmf_sdbrcm_readconsole(bus) < 0)
  3026. /* stop on error */
  3027. bus->console_interval = 0;
  3028. }
  3029. }
  3030. #endif /* BCMDBG */
  3031. /* On idle timeout clear activity flag and/or turn off clock */
  3032. if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
  3033. if (++bus->idlecount >= bus->idletime) {
  3034. bus->idlecount = 0;
  3035. if (bus->activity) {
  3036. bus->activity = false;
  3037. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  3038. } else {
  3039. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3040. }
  3041. }
  3042. }
  3043. up(&bus->sdsem);
  3044. return bus->ipend;
  3045. }
  3046. static bool brcmf_sdbrcm_chipmatch(u16 chipid)
  3047. {
  3048. if (chipid == BCM4329_CHIP_ID)
  3049. return true;
  3050. return false;
  3051. }
  3052. static void brcmf_sdbrcm_release_malloc(struct brcmf_sdio *bus)
  3053. {
  3054. brcmf_dbg(TRACE, "Enter\n");
  3055. kfree(bus->rxbuf);
  3056. bus->rxctl = bus->rxbuf = NULL;
  3057. bus->rxlen = 0;
  3058. kfree(bus->databuf);
  3059. bus->databuf = NULL;
  3060. }
  3061. static bool brcmf_sdbrcm_probe_malloc(struct brcmf_sdio *bus)
  3062. {
  3063. brcmf_dbg(TRACE, "Enter\n");
  3064. if (bus->drvr->maxctl) {
  3065. bus->rxblen =
  3066. roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
  3067. ALIGNMENT) + BRCMF_SDALIGN;
  3068. bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
  3069. if (!(bus->rxbuf))
  3070. goto fail;
  3071. }
  3072. /* Allocate buffer to receive glomed packet */
  3073. bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
  3074. if (!(bus->databuf)) {
  3075. /* release rxbuf which was already located as above */
  3076. if (!bus->rxblen)
  3077. kfree(bus->rxbuf);
  3078. goto fail;
  3079. }
  3080. /* Align the buffer */
  3081. if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
  3082. bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
  3083. ((unsigned long)bus->databuf % BRCMF_SDALIGN));
  3084. else
  3085. bus->dataptr = bus->databuf;
  3086. return true;
  3087. fail:
  3088. return false;
  3089. }
  3090. static bool
  3091. brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva)
  3092. {
  3093. u8 clkctl = 0;
  3094. int err = 0;
  3095. int reg_addr;
  3096. u32 reg_val;
  3097. u8 idx;
  3098. bus->alp_only = true;
  3099. /* Return the window to backplane enumeration space for core access */
  3100. if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
  3101. brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
  3102. #ifdef BCMDBG
  3103. printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
  3104. brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
  3105. #endif /* BCMDBG */
  3106. /*
  3107. * Force PLL off until brcmf_sdio_chip_attach()
  3108. * programs PLL control regs
  3109. */
  3110. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3111. SBSDIO_FUNC1_CHIPCLKCSR,
  3112. BRCMF_INIT_CLKCTL1, &err);
  3113. if (!err)
  3114. clkctl =
  3115. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  3116. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  3117. if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
  3118. brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
  3119. err, BRCMF_INIT_CLKCTL1, clkctl);
  3120. goto fail;
  3121. }
  3122. if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) {
  3123. brcmf_dbg(ERROR, "brcmf_sdio_chip_attach failed!\n");
  3124. goto fail;
  3125. }
  3126. if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
  3127. brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
  3128. goto fail;
  3129. }
  3130. brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci,
  3131. SDIO_DRIVE_STRENGTH);
  3132. /* Get info on the SOCRAM cores... */
  3133. bus->ramsize = bus->ci->ramsize;
  3134. if (!(bus->ramsize)) {
  3135. brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
  3136. goto fail;
  3137. }
  3138. /* Set core control so an SDIO reset does a backplane reset */
  3139. idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
  3140. reg_addr = bus->ci->c_inf[idx].base +
  3141. offsetof(struct sdpcmd_regs, corecontrol);
  3142. reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
  3143. brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
  3144. reg_val | CC_BPRESEN);
  3145. brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
  3146. /* Locate an appropriately-aligned portion of hdrbuf */
  3147. bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
  3148. BRCMF_SDALIGN);
  3149. /* Set the poll and/or interrupt flags */
  3150. bus->intr = true;
  3151. bus->poll = false;
  3152. if (bus->poll)
  3153. bus->pollrate = 1;
  3154. return true;
  3155. fail:
  3156. return false;
  3157. }
  3158. static bool brcmf_sdbrcm_probe_init(struct brcmf_sdio *bus)
  3159. {
  3160. brcmf_dbg(TRACE, "Enter\n");
  3161. /* Disable F2 to clear any intermediate frame state on the dongle */
  3162. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  3163. SDIO_FUNC_ENABLE_1, NULL);
  3164. bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
  3165. bus->sleeping = false;
  3166. bus->rxflow = false;
  3167. /* Done with backplane-dependent accesses, can drop clock... */
  3168. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3169. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  3170. /* ...and initialize clock/power states */
  3171. bus->clkstate = CLK_SDONLY;
  3172. bus->idletime = BRCMF_IDLE_INTERVAL;
  3173. bus->idleclock = BRCMF_IDLE_ACTIVE;
  3174. /* Query the F2 block size, set roundup accordingly */
  3175. bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
  3176. bus->roundup = min(max_roundup, bus->blocksize);
  3177. /* bus module does not support packet chaining */
  3178. bus->use_rxchain = false;
  3179. bus->sd_rxchain = false;
  3180. return true;
  3181. }
  3182. static int
  3183. brcmf_sdbrcm_watchdog_thread(void *data)
  3184. {
  3185. struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
  3186. allow_signal(SIGTERM);
  3187. /* Run until signal received */
  3188. while (1) {
  3189. if (kthread_should_stop())
  3190. break;
  3191. if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
  3192. brcmf_sdbrcm_bus_watchdog(bus);
  3193. /* Count the tick for reference */
  3194. bus->drvr->tickcnt++;
  3195. } else
  3196. break;
  3197. }
  3198. return 0;
  3199. }
  3200. static void
  3201. brcmf_sdbrcm_watchdog(unsigned long data)
  3202. {
  3203. struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
  3204. if (bus->watchdog_tsk) {
  3205. complete(&bus->watchdog_wait);
  3206. /* Reschedule the watchdog */
  3207. if (bus->wd_timer_valid)
  3208. mod_timer(&bus->timer,
  3209. jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
  3210. }
  3211. }
  3212. static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus)
  3213. {
  3214. brcmf_dbg(TRACE, "Enter\n");
  3215. if (bus->ci) {
  3216. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3217. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3218. brcmf_sdio_chip_detach(&bus->ci);
  3219. if (bus->vars && bus->varsz)
  3220. kfree(bus->vars);
  3221. bus->vars = NULL;
  3222. }
  3223. brcmf_dbg(TRACE, "Disconnected\n");
  3224. }
  3225. /* Detach and free everything */
  3226. static void brcmf_sdbrcm_release(struct brcmf_sdio *bus)
  3227. {
  3228. brcmf_dbg(TRACE, "Enter\n");
  3229. if (bus) {
  3230. /* De-register interrupt handler */
  3231. brcmf_sdcard_intr_dereg(bus->sdiodev);
  3232. if (bus->drvr) {
  3233. brcmf_detach(bus->drvr);
  3234. brcmf_sdbrcm_release_dongle(bus);
  3235. bus->drvr = NULL;
  3236. }
  3237. brcmf_sdbrcm_release_malloc(bus);
  3238. kfree(bus);
  3239. }
  3240. brcmf_dbg(TRACE, "Disconnected\n");
  3241. }
  3242. void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
  3243. {
  3244. int ret;
  3245. struct brcmf_sdio *bus;
  3246. brcmf_dbg(TRACE, "Enter\n");
  3247. /* We make an assumption about address window mappings:
  3248. * regsva == SI_ENUM_BASE*/
  3249. /* Allocate private bus interface state */
  3250. bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
  3251. if (!bus)
  3252. goto fail;
  3253. bus->sdiodev = sdiodev;
  3254. sdiodev->bus = bus;
  3255. skb_queue_head_init(&bus->glom);
  3256. bus->txbound = BRCMF_TXBOUND;
  3257. bus->rxbound = BRCMF_RXBOUND;
  3258. bus->txminmax = BRCMF_TXMINMAX;
  3259. bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
  3260. bus->usebufpool = false; /* Use bufpool if allocated,
  3261. else use locally malloced rxbuf */
  3262. /* attempt to attach to the dongle */
  3263. if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
  3264. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
  3265. goto fail;
  3266. }
  3267. spin_lock_init(&bus->txqlock);
  3268. init_waitqueue_head(&bus->ctrl_wait);
  3269. init_waitqueue_head(&bus->dcmd_resp_wait);
  3270. /* Set up the watchdog timer */
  3271. init_timer(&bus->timer);
  3272. bus->timer.data = (unsigned long)bus;
  3273. bus->timer.function = brcmf_sdbrcm_watchdog;
  3274. /* Initialize thread based operation and lock */
  3275. sema_init(&bus->sdsem, 1);
  3276. /* Initialize watchdog thread */
  3277. init_completion(&bus->watchdog_wait);
  3278. bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
  3279. bus, "brcmf_watchdog");
  3280. if (IS_ERR(bus->watchdog_tsk)) {
  3281. printk(KERN_WARNING
  3282. "brcmf_watchdog thread failed to start\n");
  3283. bus->watchdog_tsk = NULL;
  3284. }
  3285. /* Initialize DPC thread */
  3286. init_completion(&bus->dpc_wait);
  3287. bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
  3288. bus, "brcmf_dpc");
  3289. if (IS_ERR(bus->dpc_tsk)) {
  3290. printk(KERN_WARNING
  3291. "brcmf_dpc thread failed to start\n");
  3292. bus->dpc_tsk = NULL;
  3293. }
  3294. /* Attach to the brcmf/OS/network interface */
  3295. bus->drvr = brcmf_attach(bus, SDPCM_RESERVE, bus->sdiodev->dev);
  3296. if (!bus->drvr) {
  3297. brcmf_dbg(ERROR, "brcmf_attach failed\n");
  3298. goto fail;
  3299. }
  3300. /* Allocate buffers */
  3301. if (!(brcmf_sdbrcm_probe_malloc(bus))) {
  3302. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
  3303. goto fail;
  3304. }
  3305. if (!(brcmf_sdbrcm_probe_init(bus))) {
  3306. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
  3307. goto fail;
  3308. }
  3309. /* Register interrupt callback, but mask it (not operational yet). */
  3310. brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
  3311. ret = brcmf_sdcard_intr_reg(bus->sdiodev);
  3312. if (ret != 0) {
  3313. brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
  3314. goto fail;
  3315. }
  3316. brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
  3317. brcmf_dbg(INFO, "completed!!\n");
  3318. /* if firmware path present try to download and bring up bus */
  3319. ret = brcmf_bus_start(bus->drvr);
  3320. if (ret != 0) {
  3321. if (ret == -ENOLINK) {
  3322. brcmf_dbg(ERROR, "dongle is not responding\n");
  3323. goto fail;
  3324. }
  3325. }
  3326. /* add interface and open for business */
  3327. if (brcmf_add_if((struct brcmf_info *)bus->drvr, 0, "wlan%d", NULL)) {
  3328. brcmf_dbg(ERROR, "Add primary net device interface failed!!\n");
  3329. goto fail;
  3330. }
  3331. return bus;
  3332. fail:
  3333. brcmf_sdbrcm_release(bus);
  3334. return NULL;
  3335. }
  3336. void brcmf_sdbrcm_disconnect(void *ptr)
  3337. {
  3338. struct brcmf_sdio *bus = (struct brcmf_sdio *)ptr;
  3339. brcmf_dbg(TRACE, "Enter\n");
  3340. if (bus)
  3341. brcmf_sdbrcm_release(bus);
  3342. brcmf_dbg(TRACE, "Disconnected\n");
  3343. }
  3344. struct device *brcmf_bus_get_device(struct brcmf_sdio *bus)
  3345. {
  3346. return &bus->sdiodev->func[2]->dev;
  3347. }
  3348. void
  3349. brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick)
  3350. {
  3351. /* Totally stop the timer */
  3352. if (!wdtick && bus->wd_timer_valid == true) {
  3353. del_timer_sync(&bus->timer);
  3354. bus->wd_timer_valid = false;
  3355. bus->save_ms = wdtick;
  3356. return;
  3357. }
  3358. /* don't start the wd until fw is loaded */
  3359. if (bus->drvr->bus_if->state == BRCMF_BUS_DOWN)
  3360. return;
  3361. if (wdtick) {
  3362. if (bus->save_ms != BRCMF_WD_POLL_MS) {
  3363. if (bus->wd_timer_valid == true)
  3364. /* Stop timer and restart at new value */
  3365. del_timer_sync(&bus->timer);
  3366. /* Create timer again when watchdog period is
  3367. dynamically changed or in the first instance
  3368. */
  3369. bus->timer.expires =
  3370. jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
  3371. add_timer(&bus->timer);
  3372. } else {
  3373. /* Re arm the timer, at last watchdog period */
  3374. mod_timer(&bus->timer,
  3375. jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
  3376. }
  3377. bus->wd_timer_valid = true;
  3378. bus->save_ms = wdtick;
  3379. }
  3380. }