omap3.dtsi 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115
  1. /*
  2. * Device Tree Source for OMAP3 SoC
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "ti,omap3430", "ti,omap3";
  13. aliases {
  14. serial0 = &uart1;
  15. serial1 = &uart2;
  16. serial2 = &uart3;
  17. serial3 = &uart4;
  18. };
  19. cpus {
  20. cpu@0 {
  21. compatible = "arm,cortex-a8";
  22. };
  23. };
  24. /*
  25. * The soc node represents the soc top level view. It is uses for IPs
  26. * that are not memory mapped in the MPU view or for the MPU itself.
  27. */
  28. soc {
  29. compatible = "ti,omap-infra";
  30. mpu {
  31. compatible = "ti,omap3-mpu";
  32. ti,hwmods = "mpu";
  33. };
  34. iva {
  35. compatible = "ti,iva2.2";
  36. ti,hwmods = "iva";
  37. dsp {
  38. compatible = "ti,omap3-c64";
  39. };
  40. };
  41. };
  42. /*
  43. * XXX: Use a flat representation of the OMAP3 interconnect.
  44. * The real OMAP interconnect network is quite complex.
  45. * Since that will not bring real advantage to represent that in DT for
  46. * the moment, just use a fake OCP bus entry to represent the whole bus
  47. * hierarchy.
  48. */
  49. ocp {
  50. compatible = "simple-bus";
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. ranges;
  54. ti,hwmods = "l3_main";
  55. intc: interrupt-controller@1 {
  56. compatible = "ti,omap3-intc";
  57. interrupt-controller;
  58. #interrupt-cells = <1>;
  59. };
  60. uart1: serial@0x4806a000 {
  61. compatible = "ti,omap3-uart";
  62. ti,hwmods = "uart1";
  63. clock-frequency = <48000000>;
  64. };
  65. uart2: serial@0x4806c000 {
  66. compatible = "ti,omap3-uart";
  67. ti,hwmods = "uart2";
  68. clock-frequency = <48000000>;
  69. };
  70. uart3: serial@0x49020000 {
  71. compatible = "ti,omap3-uart";
  72. ti,hwmods = "uart3";
  73. clock-frequency = <48000000>;
  74. };
  75. uart4: serial@0x49042000 {
  76. compatible = "ti,omap3-uart";
  77. ti,hwmods = "uart4";
  78. clock-frequency = <48000000>;
  79. };
  80. i2c1: i2c@48070000 {
  81. compatible = "ti,omap3-i2c";
  82. #address-cells = <1>;
  83. #size-cells = <0>;
  84. ti,hwmods = "i2c1";
  85. };
  86. i2c2: i2c@48072000 {
  87. compatible = "ti,omap3-i2c";
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. ti,hwmods = "i2c2";
  91. };
  92. i2c3: i2c@48060000 {
  93. compatible = "ti,omap3-i2c";
  94. #address-cells = <1>;
  95. #size-cells = <0>;
  96. ti,hwmods = "i2c3";
  97. };
  98. };
  99. };