azt3328.c 61 KB

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  1. /*
  2. * azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
  3. * Copyright (C) 2002, 2005 by Andreas Mohr <andi AT lisas.de>
  4. *
  5. * Framework borrowed from Bart Hartgers's als4000.c.
  6. * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
  7. * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
  8. * Other versions are:
  9. * PCI168 A(W), sub ID 1800
  10. * PCI168 A/AP, sub ID 8000
  11. * Please give me feedback in case you try my driver with one of these!!
  12. *
  13. * GPL LICENSE
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26. *
  27. * NOTES
  28. * Since Aztech does not provide any chipset documentation,
  29. * even on repeated request to various addresses,
  30. * and the answer that was finally given was negative
  31. * (and I was stupid enough to manage to get hold of a PCI168 soundcard
  32. * in the first place >:-P}),
  33. * I was forced to base this driver on reverse engineering
  34. * (3 weeks' worth of evenings filled with driver work).
  35. * (and no, I did NOT go the easy way: to pick up a PCI128 for 9 Euros)
  36. *
  37. * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
  38. * for compatibility reasons) has the following features:
  39. *
  40. * - builtin AC97 conformant codec (SNR over 80dB)
  41. * (really AC97 compliant?? I really doubt it when looking
  42. * at the mixer register layout)
  43. * - builtin genuine OPL3
  44. * - full duplex 16bit playback/record at independent sampling rate
  45. * - MPU401 (+ legacy address support) FIXME: how to enable legacy addr??
  46. * - game port (legacy address support)
  47. * - built-in General DirectX timer having a 20 bits counter
  48. * with 1us resolution (see below!)
  49. * - I2S serial port for external DAC
  50. * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
  51. * - supports hardware volume control
  52. * - single chip low cost solution (128 pin QFP)
  53. * - supports programmable Sub-vendor and Sub-system ID
  54. * required for Microsoft's logo compliance (FIXME: where?)
  55. * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
  56. *
  57. * Note that this driver now is actually *better* than the Windows driver,
  58. * since it additionally supports the card's 1MHz DirectX timer - just try
  59. * the following snd-seq module parameters etc.:
  60. * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
  61. * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
  62. * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
  63. * - "timidity -iAv -B2,8 -Os -EFreverb=0"
  64. * - "pmidi -p 128:0 jazz.mid"
  65. *
  66. * Certain PCI versions of this card are susceptible to DMA traffic underruns
  67. * in some systems (resulting in sound crackling/clicking/popping),
  68. * probably because they don't have a DMA FIFO buffer or so.
  69. * Overview (PCI ID/PCI subID/PCI rev.):
  70. * - no DMA crackling on SiS735: 0x50DC/0x1801/16
  71. * - unknown performance: 0x50DC/0x1801/10
  72. * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
  73. *
  74. * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
  75. * supposed to be very fast and supposed to get rid of crackling much
  76. * better than a VIA, yet ironically I still get crackling, like many other
  77. * people with the same chipset.
  78. * Possible remedies:
  79. * - plug card into a different PCI slot, preferrably one that isn't shared
  80. * too much (this helps a lot, but not completely!)
  81. * - get rid of PCI VGA card, use AGP instead
  82. * - upgrade or downgrade BIOS
  83. * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
  84. * Not too helpful.
  85. * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
  86. *
  87. * BUGS
  88. * - full-duplex might *still* be problematic, not fully tested recently
  89. *
  90. * TODO
  91. * - test MPU401 MIDI playback etc.
  92. * - add some power micro-management (disable various units of the card
  93. * as long as they're unused). However this requires I/O ports which I
  94. * haven't figured out yet and which thus might not even exist...
  95. * The standard suspend/resume functionality could probably make use of
  96. * some improvement, too...
  97. * - figure out what all unknown port bits are responsible for
  98. */
  99. #include <sound/driver.h>
  100. #include <asm/io.h>
  101. #include <linux/init.h>
  102. #include <linux/pci.h>
  103. #include <linux/delay.h>
  104. #include <linux/slab.h>
  105. #include <linux/gameport.h>
  106. #include <linux/moduleparam.h>
  107. #include <linux/dma-mapping.h>
  108. #include <sound/core.h>
  109. #include <sound/control.h>
  110. #include <sound/pcm.h>
  111. #include <sound/rawmidi.h>
  112. #include <sound/mpu401.h>
  113. #include <sound/opl3.h>
  114. #include <sound/initval.h>
  115. #include "azt3328.h"
  116. MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
  117. MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
  118. MODULE_LICENSE("GPL");
  119. MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
  120. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  121. #define SUPPORT_JOYSTICK 1
  122. #endif
  123. #define DEBUG_MISC 0
  124. #define DEBUG_CALLS 0
  125. #define DEBUG_MIXER 0
  126. #define DEBUG_PLAY_REC 0
  127. #define DEBUG_IO 0
  128. #define DEBUG_TIMER 0
  129. #define MIXER_TESTING 0
  130. #if DEBUG_MISC
  131. #define snd_azf3328_dbgmisc(format, args...) printk(KERN_ERR format, ##args)
  132. #else
  133. #define snd_azf3328_dbgmisc(format, args...)
  134. #endif
  135. #if DEBUG_CALLS
  136. #define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
  137. #define snd_azf3328_dbgcallenter() printk(KERN_ERR "--> %s\n", __FUNCTION__)
  138. #define snd_azf3328_dbgcallleave() printk(KERN_ERR "<-- %s\n", __FUNCTION__)
  139. #else
  140. #define snd_azf3328_dbgcalls(format, args...)
  141. #define snd_azf3328_dbgcallenter()
  142. #define snd_azf3328_dbgcallleave()
  143. #endif
  144. #if DEBUG_MIXER
  145. #define snd_azf3328_dbgmixer(format, args...) printk(format, ##args)
  146. #else
  147. #define snd_azf3328_dbgmixer(format, args...)
  148. #endif
  149. #if DEBUG_PLAY_REC
  150. #define snd_azf3328_dbgplay(format, args...) printk(KERN_ERR format, ##args)
  151. #else
  152. #define snd_azf3328_dbgplay(format, args...)
  153. #endif
  154. #if DEBUG_MISC
  155. #define snd_azf3328_dbgtimer(format, args...) printk(KERN_ERR format, ##args)
  156. #else
  157. #define snd_azf3328_dbgtimer(format, args...)
  158. #endif
  159. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  160. module_param_array(index, int, NULL, 0444);
  161. MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
  162. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  163. module_param_array(id, charp, NULL, 0444);
  164. MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
  165. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  166. module_param_array(enable, bool, NULL, 0444);
  167. MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
  168. #ifdef SUPPORT_JOYSTICK
  169. static int joystick[SNDRV_CARDS];
  170. module_param_array(joystick, bool, NULL, 0444);
  171. MODULE_PARM_DESC(joystick, "Enable joystick for AZF3328 soundcard.");
  172. #endif
  173. static int seqtimer_scaling = 128;
  174. module_param(seqtimer_scaling, int, 0444);
  175. MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
  176. struct snd_azf3328 {
  177. /* often-used fields towards beginning, then grouped */
  178. unsigned long codec_port;
  179. unsigned long io2_port;
  180. unsigned long mpu_port;
  181. unsigned long synth_port;
  182. unsigned long mixer_port;
  183. spinlock_t reg_lock;
  184. struct snd_timer *timer;
  185. struct snd_pcm *pcm;
  186. struct snd_pcm_substream *playback_substream;
  187. struct snd_pcm_substream *capture_substream;
  188. unsigned int is_playing;
  189. unsigned int is_recording;
  190. struct snd_card *card;
  191. struct snd_rawmidi *rmidi;
  192. #ifdef SUPPORT_JOYSTICK
  193. struct gameport *gameport;
  194. #endif
  195. struct pci_dev *pci;
  196. int irq;
  197. #ifdef CONFIG_PM
  198. /* register value containers for power management
  199. * Note: not always full I/O range preserved (just like Win driver!) */
  200. u16 saved_regs_codec [AZF_IO_SIZE_CODEC_PM / 2];
  201. u16 saved_regs_io2 [AZF_IO_SIZE_IO2_PM / 2];
  202. u16 saved_regs_mpu [AZF_IO_SIZE_MPU_PM / 2];
  203. u16 saved_regs_synth[AZF_IO_SIZE_SYNTH_PM / 2];
  204. u16 saved_regs_mixer[AZF_IO_SIZE_MIXER_PM / 2];
  205. #endif
  206. };
  207. static const struct pci_device_id snd_azf3328_ids[] __devinitdata = {
  208. { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
  209. { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
  210. { 0, }
  211. };
  212. MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
  213. static inline void
  214. snd_azf3328_codec_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  215. {
  216. outb(value, chip->codec_port + reg);
  217. }
  218. static inline u8
  219. snd_azf3328_codec_inb(const struct snd_azf3328 *chip, int reg)
  220. {
  221. return inb(chip->codec_port + reg);
  222. }
  223. static inline void
  224. snd_azf3328_codec_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  225. {
  226. outw(value, chip->codec_port + reg);
  227. }
  228. static inline u16
  229. snd_azf3328_codec_inw(const struct snd_azf3328 *chip, int reg)
  230. {
  231. return inw(chip->codec_port + reg);
  232. }
  233. static inline void
  234. snd_azf3328_codec_outl(const struct snd_azf3328 *chip, int reg, u32 value)
  235. {
  236. outl(value, chip->codec_port + reg);
  237. }
  238. static inline void
  239. snd_azf3328_io2_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  240. {
  241. outb(value, chip->io2_port + reg);
  242. }
  243. static inline u8
  244. snd_azf3328_io2_inb(const struct snd_azf3328 *chip, int reg)
  245. {
  246. return inb(chip->io2_port + reg);
  247. }
  248. static inline void
  249. snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  250. {
  251. outw(value, chip->mixer_port + reg);
  252. }
  253. static inline u16
  254. snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, int reg)
  255. {
  256. return inw(chip->mixer_port + reg);
  257. }
  258. static void
  259. snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip, int reg, int do_mute)
  260. {
  261. unsigned long portbase = chip->mixer_port + reg + 1;
  262. unsigned char oldval;
  263. /* the mute bit is on the *second* (i.e. right) register of a
  264. * left/right channel setting */
  265. oldval = inb(portbase);
  266. if (do_mute)
  267. oldval |= 0x80;
  268. else
  269. oldval &= ~0x80;
  270. outb(oldval, portbase);
  271. }
  272. static void
  273. snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, int reg, unsigned char dst_vol_left, unsigned char dst_vol_right, int chan_sel, int delay)
  274. {
  275. unsigned long portbase = chip->mixer_port + reg;
  276. unsigned char curr_vol_left = 0, curr_vol_right = 0;
  277. int left_done = 0, right_done = 0;
  278. snd_azf3328_dbgcallenter();
  279. if (chan_sel & SET_CHAN_LEFT)
  280. curr_vol_left = inb(portbase + 1);
  281. else
  282. left_done = 1;
  283. if (chan_sel & SET_CHAN_RIGHT)
  284. curr_vol_right = inb(portbase + 0);
  285. else
  286. right_done = 1;
  287. /* take care of muting flag (0x80) contained in left channel */
  288. if (curr_vol_left & 0x80)
  289. dst_vol_left |= 0x80;
  290. else
  291. dst_vol_left &= ~0x80;
  292. do
  293. {
  294. if (!left_done)
  295. {
  296. if (curr_vol_left > dst_vol_left)
  297. curr_vol_left--;
  298. else
  299. if (curr_vol_left < dst_vol_left)
  300. curr_vol_left++;
  301. else
  302. left_done = 1;
  303. outb(curr_vol_left, portbase + 1);
  304. }
  305. if (!right_done)
  306. {
  307. if (curr_vol_right > dst_vol_right)
  308. curr_vol_right--;
  309. else
  310. if (curr_vol_right < dst_vol_right)
  311. curr_vol_right++;
  312. else
  313. right_done = 1;
  314. /* during volume change, the right channel is crackling
  315. * somewhat more than the left channel, unfortunately.
  316. * This seems to be a hardware issue. */
  317. outb(curr_vol_right, portbase + 0);
  318. }
  319. if (delay)
  320. mdelay(delay);
  321. }
  322. while ((!left_done) || (!right_done));
  323. snd_azf3328_dbgcallleave();
  324. }
  325. /*
  326. * general mixer element
  327. */
  328. struct azf3328_mixer_reg {
  329. unsigned int reg;
  330. unsigned int lchan_shift, rchan_shift;
  331. unsigned int mask;
  332. unsigned int invert: 1;
  333. unsigned int stereo: 1;
  334. unsigned int enum_c: 4;
  335. };
  336. #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
  337. ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
  338. (mask << 16) | \
  339. (invert << 24) | \
  340. (stereo << 25) | \
  341. (enum_c << 26))
  342. static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
  343. {
  344. r->reg = val & 0xff;
  345. r->lchan_shift = (val >> 8) & 0x0f;
  346. r->rchan_shift = (val >> 12) & 0x0f;
  347. r->mask = (val >> 16) & 0xff;
  348. r->invert = (val >> 24) & 1;
  349. r->stereo = (val >> 25) & 1;
  350. r->enum_c = (val >> 26) & 0x0f;
  351. }
  352. /*
  353. * mixer switches/volumes
  354. */
  355. #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
  356. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  357. .info = snd_azf3328_info_mixer, \
  358. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  359. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
  360. }
  361. #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
  362. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  363. .info = snd_azf3328_info_mixer, \
  364. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  365. .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
  366. }
  367. #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
  368. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  369. .info = snd_azf3328_info_mixer, \
  370. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  371. .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
  372. }
  373. #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
  374. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  375. .info = snd_azf3328_info_mixer, \
  376. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  377. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
  378. }
  379. #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
  380. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  381. .info = snd_azf3328_info_mixer_enum, \
  382. .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
  383. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
  384. }
  385. static int
  386. snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
  387. struct snd_ctl_elem_info *uinfo)
  388. {
  389. struct azf3328_mixer_reg reg;
  390. snd_azf3328_dbgcallenter();
  391. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  392. uinfo->type = reg.mask == 1 ?
  393. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  394. uinfo->count = reg.stereo + 1;
  395. uinfo->value.integer.min = 0;
  396. uinfo->value.integer.max = reg.mask;
  397. snd_azf3328_dbgcallleave();
  398. return 0;
  399. }
  400. static int
  401. snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
  402. struct snd_ctl_elem_value *ucontrol)
  403. {
  404. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  405. struct azf3328_mixer_reg reg;
  406. unsigned int oreg, val;
  407. snd_azf3328_dbgcallenter();
  408. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  409. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  410. val = (oreg >> reg.lchan_shift) & reg.mask;
  411. if (reg.invert)
  412. val = reg.mask - val;
  413. ucontrol->value.integer.value[0] = val;
  414. if (reg.stereo) {
  415. val = (oreg >> reg.rchan_shift) & reg.mask;
  416. if (reg.invert)
  417. val = reg.mask - val;
  418. ucontrol->value.integer.value[1] = val;
  419. }
  420. snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx "
  421. "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
  422. reg.reg, oreg,
  423. ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  424. reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
  425. snd_azf3328_dbgcallleave();
  426. return 0;
  427. }
  428. static int
  429. snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
  430. struct snd_ctl_elem_value *ucontrol)
  431. {
  432. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  433. struct azf3328_mixer_reg reg;
  434. unsigned int oreg, nreg, val;
  435. snd_azf3328_dbgcallenter();
  436. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  437. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  438. val = ucontrol->value.integer.value[0] & reg.mask;
  439. if (reg.invert)
  440. val = reg.mask - val;
  441. nreg = oreg & ~(reg.mask << reg.lchan_shift);
  442. nreg |= (val << reg.lchan_shift);
  443. if (reg.stereo) {
  444. val = ucontrol->value.integer.value[1] & reg.mask;
  445. if (reg.invert)
  446. val = reg.mask - val;
  447. nreg &= ~(reg.mask << reg.rchan_shift);
  448. nreg |= (val << reg.rchan_shift);
  449. }
  450. if (reg.mask >= 0x07) /* it's a volume control, so better take care */
  451. snd_azf3328_mixer_write_volume_gradually(
  452. chip, reg.reg, nreg >> 8, nreg & 0xff,
  453. /* just set both channels, doesn't matter */
  454. SET_CHAN_LEFT|SET_CHAN_RIGHT,
  455. 0);
  456. else
  457. snd_azf3328_mixer_outw(chip, reg.reg, nreg);
  458. snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, "
  459. "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
  460. reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  461. oreg, reg.lchan_shift, reg.rchan_shift,
  462. nreg, snd_azf3328_mixer_inw(chip, reg.reg));
  463. snd_azf3328_dbgcallleave();
  464. return (nreg != oreg);
  465. }
  466. static int
  467. snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
  468. struct snd_ctl_elem_info *uinfo)
  469. {
  470. static const char * const texts1[] = {
  471. "ModemOut1", "ModemOut2"
  472. };
  473. static const char * const texts2[] = {
  474. "MonoSelectSource1", "MonoSelectSource2"
  475. };
  476. static const char * const texts3[] = {
  477. "Mic", "CD", "Video", "Aux",
  478. "Line", "Mix", "Mix Mono", "Phone"
  479. };
  480. struct azf3328_mixer_reg reg;
  481. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  482. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  483. uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1;
  484. uinfo->value.enumerated.items = reg.enum_c;
  485. if (uinfo->value.enumerated.item > reg.enum_c - 1U)
  486. uinfo->value.enumerated.item = reg.enum_c - 1U;
  487. if (reg.reg == IDX_MIXER_ADVCTL2)
  488. {
  489. if (reg.lchan_shift == 8) /* modem out sel */
  490. strcpy(uinfo->value.enumerated.name, texts1[uinfo->value.enumerated.item]);
  491. else /* mono sel source */
  492. strcpy(uinfo->value.enumerated.name, texts2[uinfo->value.enumerated.item]);
  493. }
  494. else
  495. strcpy(uinfo->value.enumerated.name, texts3[uinfo->value.enumerated.item]
  496. );
  497. return 0;
  498. }
  499. static int
  500. snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
  501. struct snd_ctl_elem_value *ucontrol)
  502. {
  503. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  504. struct azf3328_mixer_reg reg;
  505. unsigned short val;
  506. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  507. val = snd_azf3328_mixer_inw(chip, reg.reg);
  508. if (reg.reg == IDX_MIXER_REC_SELECT)
  509. {
  510. ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
  511. ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
  512. }
  513. else
  514. ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
  515. snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
  516. reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
  517. reg.lchan_shift, reg.enum_c);
  518. return 0;
  519. }
  520. static int
  521. snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
  522. struct snd_ctl_elem_value *ucontrol)
  523. {
  524. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  525. struct azf3328_mixer_reg reg;
  526. unsigned int oreg, nreg, val;
  527. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  528. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  529. val = oreg;
  530. if (reg.reg == IDX_MIXER_REC_SELECT)
  531. {
  532. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
  533. ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
  534. return -EINVAL;
  535. val = (ucontrol->value.enumerated.item[0] << 8) |
  536. (ucontrol->value.enumerated.item[1] << 0);
  537. }
  538. else
  539. {
  540. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
  541. return -EINVAL;
  542. val &= ~((reg.enum_c - 1) << reg.lchan_shift);
  543. val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
  544. }
  545. snd_azf3328_mixer_outw(chip, reg.reg, val);
  546. nreg = val;
  547. snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
  548. return (nreg != oreg);
  549. }
  550. static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
  551. AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
  552. AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
  553. AZF3328_MIXER_SWITCH("Wave Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
  554. AZF3328_MIXER_VOL_STEREO("Wave Playback Volume", IDX_MIXER_WAVEOUT, 0x1f, 1),
  555. AZF3328_MIXER_SWITCH("Wave 3D Bypass Playback Switch", IDX_MIXER_ADVCTL2, 7, 1),
  556. AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
  557. AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
  558. AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
  559. AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
  560. AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
  561. AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
  562. AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
  563. AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
  564. AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
  565. AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
  566. AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
  567. AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
  568. AZF3328_MIXER_SWITCH("PC Speaker Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
  569. AZF3328_MIXER_VOL_SPECIAL("PC Speaker Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
  570. AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
  571. AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
  572. AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
  573. AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
  574. AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
  575. AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
  576. AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
  577. AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
  578. AZF3328_MIXER_ENUM("Modem Out Select", IDX_MIXER_ADVCTL2, 2, 8),
  579. AZF3328_MIXER_ENUM("Mono Select Source", IDX_MIXER_ADVCTL2, 2, 9),
  580. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
  581. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
  582. AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
  583. AZF3328_MIXER_VOL_SPECIAL("3D Control - Wide", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
  584. AZF3328_MIXER_VOL_SPECIAL("3D Control - Space", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
  585. #if MIXER_TESTING
  586. AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
  587. AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
  588. AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
  589. AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
  590. AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
  591. AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
  592. AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
  593. AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
  594. AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
  595. AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
  596. AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
  597. AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
  598. AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
  599. AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
  600. AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
  601. AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
  602. #endif
  603. };
  604. static const u16 __devinitdata snd_azf3328_init_values[][2] = {
  605. { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
  606. { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
  607. { IDX_MIXER_BASSTREBLE, 0x0000 },
  608. { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
  609. { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
  610. { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
  611. { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
  612. { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
  613. { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
  614. { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
  615. { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
  616. { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
  617. { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
  618. };
  619. static int __devinit
  620. snd_azf3328_mixer_new(struct snd_azf3328 *chip)
  621. {
  622. struct snd_card *card;
  623. const struct snd_kcontrol_new *sw;
  624. unsigned int idx;
  625. int err;
  626. snd_azf3328_dbgcallenter();
  627. snd_assert(chip != NULL && chip->card != NULL, return -EINVAL);
  628. card = chip->card;
  629. /* mixer reset */
  630. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  631. /* mute and zero volume channels */
  632. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); idx++) {
  633. snd_azf3328_mixer_outw(chip,
  634. snd_azf3328_init_values[idx][0],
  635. snd_azf3328_init_values[idx][1]);
  636. }
  637. /* add mixer controls */
  638. sw = snd_azf3328_mixer_controls;
  639. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); idx++, sw++) {
  640. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
  641. return err;
  642. }
  643. snd_component_add(card, "AZF3328 mixer");
  644. strcpy(card->mixername, "AZF3328 mixer");
  645. snd_azf3328_dbgcallleave();
  646. return 0;
  647. }
  648. static int
  649. snd_azf3328_hw_params(struct snd_pcm_substream *substream,
  650. struct snd_pcm_hw_params *hw_params)
  651. {
  652. int res;
  653. snd_azf3328_dbgcallenter();
  654. res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  655. snd_azf3328_dbgcallleave();
  656. return res;
  657. }
  658. static int
  659. snd_azf3328_hw_free(struct snd_pcm_substream *substream)
  660. {
  661. snd_azf3328_dbgcallenter();
  662. snd_pcm_lib_free_pages(substream);
  663. snd_azf3328_dbgcallleave();
  664. return 0;
  665. }
  666. static void
  667. snd_azf3328_setfmt(struct snd_azf3328 *chip,
  668. unsigned int reg,
  669. unsigned int bitrate,
  670. unsigned int format_width,
  671. unsigned int channels
  672. )
  673. {
  674. u16 val = 0xff00;
  675. unsigned long flags;
  676. snd_azf3328_dbgcallenter();
  677. switch (bitrate) {
  678. case 4000: val |= SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
  679. case 4800: val |= SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
  680. case 5512: val |= SOUNDFORMAT_FREQ_5510; break; /* the AZF3328 names it "5510" for some strange reason */
  681. case 6620: val |= SOUNDFORMAT_FREQ_6620; break;
  682. case 8000: val |= SOUNDFORMAT_FREQ_8000; break;
  683. case 9600: val |= SOUNDFORMAT_FREQ_9600; break;
  684. case 11025: val |= SOUNDFORMAT_FREQ_11025; break;
  685. case 13240: val |= SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
  686. case 16000: val |= SOUNDFORMAT_FREQ_16000; break;
  687. case 22050: val |= SOUNDFORMAT_FREQ_22050; break;
  688. case 32000: val |= SOUNDFORMAT_FREQ_32000; break;
  689. case 44100: val |= SOUNDFORMAT_FREQ_44100; break;
  690. case 48000: val |= SOUNDFORMAT_FREQ_48000; break;
  691. case 66200: val |= SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
  692. default:
  693. snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
  694. val |= SOUNDFORMAT_FREQ_44100;
  695. break;
  696. }
  697. /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
  698. /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
  699. /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
  700. /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
  701. /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
  702. /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
  703. /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
  704. /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
  705. /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
  706. if (channels == 2)
  707. val |= SOUNDFORMAT_FLAG_2CHANNELS;
  708. if (format_width == 16)
  709. val |= SOUNDFORMAT_FLAG_16BIT;
  710. spin_lock_irqsave(&chip->reg_lock, flags);
  711. /* set bitrate/format */
  712. snd_azf3328_codec_outw(chip, reg, val);
  713. /* changing the bitrate/format settings switches off the
  714. * audio output with an annoying click in case of 8/16bit format change
  715. * (maybe shutting down DAC/ADC?), thus immediately
  716. * do some tweaking to reenable it and get rid of the clicking
  717. * (FIXME: yes, it works, but what exactly am I doing here?? :)
  718. * FIXME: does this have some side effects for full-duplex
  719. * or other dramatic side effects? */
  720. if (reg == IDX_IO_PLAY_SOUNDFORMAT) /* only do it for playback */
  721. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  722. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) |
  723. DMA_PLAY_SOMETHING1 |
  724. DMA_PLAY_SOMETHING2 |
  725. SOMETHING_ALMOST_ALWAYS_SET |
  726. DMA_EPILOGUE_SOMETHING |
  727. DMA_SOMETHING_ELSE
  728. );
  729. spin_unlock_irqrestore(&chip->reg_lock, flags);
  730. snd_azf3328_dbgcallleave();
  731. }
  732. static void
  733. snd_azf3328_setdmaa(struct snd_azf3328 *chip,
  734. long unsigned int addr,
  735. unsigned int count,
  736. unsigned int size,
  737. int do_recording)
  738. {
  739. unsigned long flags, portbase;
  740. unsigned int is_running;
  741. snd_azf3328_dbgcallenter();
  742. if (do_recording)
  743. {
  744. /* access capture registers, i.e. skip playback reg section */
  745. portbase = chip->codec_port + 0x20;
  746. is_running = chip->is_recording;
  747. }
  748. else
  749. {
  750. /* access the playback register section */
  751. portbase = chip->codec_port + 0x00;
  752. is_running = chip->is_playing;
  753. }
  754. /* AZF3328 uses a two buffer pointer DMA playback approach */
  755. if (!is_running)
  756. {
  757. unsigned long addr_area2;
  758. unsigned long count_areas, count_tmp; /* width 32bit -- overflow!! */
  759. count_areas = size/2;
  760. addr_area2 = addr+count_areas;
  761. count_areas--; /* max. index */
  762. snd_azf3328_dbgplay("set DMA: buf1 %08lx[%lu], buf2 %08lx[%lu]\n", addr, count_areas, addr_area2, count_areas);
  763. /* build combined I/O buffer length word */
  764. count_tmp = count_areas;
  765. count_areas |= (count_tmp << 16);
  766. spin_lock_irqsave(&chip->reg_lock, flags);
  767. outl(addr, portbase + IDX_IO_PLAY_DMA_START_1);
  768. outl(addr_area2, portbase + IDX_IO_PLAY_DMA_START_2);
  769. outl(count_areas, portbase + IDX_IO_PLAY_DMA_LEN_1);
  770. spin_unlock_irqrestore(&chip->reg_lock, flags);
  771. }
  772. snd_azf3328_dbgcallleave();
  773. }
  774. static int
  775. snd_azf3328_playback_prepare(struct snd_pcm_substream *substream)
  776. {
  777. #if 0
  778. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  779. struct snd_pcm_runtime *runtime = substream->runtime;
  780. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  781. unsigned int count = snd_pcm_lib_period_bytes(substream);
  782. #endif
  783. snd_azf3328_dbgcallenter();
  784. #if 0
  785. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  786. runtime->rate,
  787. snd_pcm_format_width(runtime->format),
  788. runtime->channels);
  789. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 0);
  790. #endif
  791. snd_azf3328_dbgcallleave();
  792. return 0;
  793. }
  794. static int
  795. snd_azf3328_capture_prepare(struct snd_pcm_substream *substream)
  796. {
  797. #if 0
  798. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  799. struct snd_pcm_runtime *runtime = substream->runtime;
  800. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  801. unsigned int count = snd_pcm_lib_period_bytes(substream);
  802. #endif
  803. snd_azf3328_dbgcallenter();
  804. #if 0
  805. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  806. runtime->rate,
  807. snd_pcm_format_width(runtime->format),
  808. runtime->channels);
  809. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 1);
  810. #endif
  811. snd_azf3328_dbgcallleave();
  812. return 0;
  813. }
  814. static int
  815. snd_azf3328_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  816. {
  817. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  818. struct snd_pcm_runtime *runtime = substream->runtime;
  819. int result = 0;
  820. unsigned int status1;
  821. snd_azf3328_dbgcalls("snd_azf3328_playback_trigger cmd %d\n", cmd);
  822. switch (cmd) {
  823. case SNDRV_PCM_TRIGGER_START:
  824. snd_azf3328_dbgplay("START PLAYBACK\n");
  825. /* mute WaveOut */
  826. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  827. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  828. runtime->rate,
  829. snd_pcm_format_width(runtime->format),
  830. runtime->channels);
  831. spin_lock(&chip->reg_lock);
  832. /* stop playback */
  833. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  834. status1 &= ~DMA_RESUME;
  835. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  836. /* FIXME: clear interrupts or what??? */
  837. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_IRQTYPE, 0xffff);
  838. spin_unlock(&chip->reg_lock);
  839. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  840. snd_pcm_lib_period_bytes(substream),
  841. snd_pcm_lib_buffer_bytes(substream),
  842. 0);
  843. spin_lock(&chip->reg_lock);
  844. #ifdef WIN9X
  845. /* FIXME: enable playback/recording??? */
  846. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  847. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  848. /* start playback again */
  849. /* FIXME: what is this value (0x0010)??? */
  850. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  851. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  852. #else /* NT4 */
  853. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  854. 0x0000);
  855. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  856. DMA_PLAY_SOMETHING1);
  857. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  858. DMA_PLAY_SOMETHING1 |
  859. DMA_PLAY_SOMETHING2);
  860. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  861. DMA_RESUME |
  862. SOMETHING_ALMOST_ALWAYS_SET |
  863. DMA_EPILOGUE_SOMETHING |
  864. DMA_SOMETHING_ELSE);
  865. #endif
  866. spin_unlock(&chip->reg_lock);
  867. /* now unmute WaveOut */
  868. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  869. chip->is_playing = 1;
  870. snd_azf3328_dbgplay("STARTED PLAYBACK\n");
  871. break;
  872. case SNDRV_PCM_TRIGGER_RESUME:
  873. snd_azf3328_dbgplay("RESUME PLAYBACK\n");
  874. /* resume playback if we were active */
  875. if (chip->is_playing)
  876. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  877. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) | DMA_RESUME);
  878. break;
  879. case SNDRV_PCM_TRIGGER_STOP:
  880. snd_azf3328_dbgplay("STOP PLAYBACK\n");
  881. /* mute WaveOut */
  882. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  883. spin_lock(&chip->reg_lock);
  884. /* stop playback */
  885. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  886. status1 &= ~DMA_RESUME;
  887. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  888. /* hmm, is this really required? we're resetting the same bit
  889. * immediately thereafter... */
  890. status1 |= DMA_PLAY_SOMETHING1;
  891. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  892. status1 &= ~DMA_PLAY_SOMETHING1;
  893. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  894. spin_unlock(&chip->reg_lock);
  895. /* now unmute WaveOut */
  896. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  897. chip->is_playing = 0;
  898. snd_azf3328_dbgplay("STOPPED PLAYBACK\n");
  899. break;
  900. case SNDRV_PCM_TRIGGER_SUSPEND:
  901. snd_azf3328_dbgplay("SUSPEND PLAYBACK\n");
  902. /* make sure playback is stopped */
  903. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  904. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) & ~DMA_RESUME);
  905. break;
  906. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  907. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  908. break;
  909. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  910. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  911. break;
  912. default:
  913. printk(KERN_ERR "FIXME: unknown trigger mode!\n");
  914. return -EINVAL;
  915. }
  916. snd_azf3328_dbgcallleave();
  917. return result;
  918. }
  919. /* this is just analogous to playback; I'm not quite sure whether recording
  920. * should actually be triggered like that */
  921. static int
  922. snd_azf3328_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  923. {
  924. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  925. struct snd_pcm_runtime *runtime = substream->runtime;
  926. int result = 0;
  927. unsigned int status1;
  928. snd_azf3328_dbgcalls("snd_azf3328_capture_trigger cmd %d\n", cmd);
  929. switch (cmd) {
  930. case SNDRV_PCM_TRIGGER_START:
  931. snd_azf3328_dbgplay("START CAPTURE\n");
  932. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  933. runtime->rate,
  934. snd_pcm_format_width(runtime->format),
  935. runtime->channels);
  936. spin_lock(&chip->reg_lock);
  937. /* stop recording */
  938. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  939. status1 &= ~DMA_RESUME;
  940. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  941. /* FIXME: clear interrupts or what??? */
  942. snd_azf3328_codec_outw(chip, IDX_IO_REC_IRQTYPE, 0xffff);
  943. spin_unlock(&chip->reg_lock);
  944. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  945. snd_pcm_lib_period_bytes(substream),
  946. snd_pcm_lib_buffer_bytes(substream),
  947. 1);
  948. spin_lock(&chip->reg_lock);
  949. #ifdef WIN9X
  950. /* FIXME: enable playback/recording??? */
  951. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  952. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  953. /* start capture again */
  954. /* FIXME: what is this value (0x0010)??? */
  955. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  956. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  957. #else
  958. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  959. 0x0000);
  960. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  961. DMA_PLAY_SOMETHING1);
  962. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  963. DMA_PLAY_SOMETHING1 |
  964. DMA_PLAY_SOMETHING2);
  965. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  966. DMA_RESUME |
  967. SOMETHING_ALMOST_ALWAYS_SET |
  968. DMA_EPILOGUE_SOMETHING |
  969. DMA_SOMETHING_ELSE);
  970. #endif
  971. spin_unlock(&chip->reg_lock);
  972. chip->is_recording = 1;
  973. snd_azf3328_dbgplay("STARTED CAPTURE\n");
  974. break;
  975. case SNDRV_PCM_TRIGGER_RESUME:
  976. snd_azf3328_dbgplay("RESUME CAPTURE\n");
  977. /* resume recording if we were active */
  978. if (chip->is_recording)
  979. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  980. snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) | DMA_RESUME);
  981. break;
  982. case SNDRV_PCM_TRIGGER_STOP:
  983. snd_azf3328_dbgplay("STOP CAPTURE\n");
  984. spin_lock(&chip->reg_lock);
  985. /* stop recording */
  986. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  987. status1 &= ~DMA_RESUME;
  988. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  989. status1 |= DMA_PLAY_SOMETHING1;
  990. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  991. status1 &= ~DMA_PLAY_SOMETHING1;
  992. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  993. spin_unlock(&chip->reg_lock);
  994. chip->is_recording = 0;
  995. snd_azf3328_dbgplay("STOPPED CAPTURE\n");
  996. break;
  997. case SNDRV_PCM_TRIGGER_SUSPEND:
  998. snd_azf3328_dbgplay("SUSPEND CAPTURE\n");
  999. /* make sure recording is stopped */
  1000. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  1001. snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) & ~DMA_RESUME);
  1002. break;
  1003. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1004. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  1005. break;
  1006. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1007. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  1008. break;
  1009. default:
  1010. printk(KERN_ERR "FIXME: unknown trigger mode!\n");
  1011. return -EINVAL;
  1012. }
  1013. snd_azf3328_dbgcallleave();
  1014. return result;
  1015. }
  1016. static snd_pcm_uframes_t
  1017. snd_azf3328_playback_pointer(struct snd_pcm_substream *substream)
  1018. {
  1019. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1020. unsigned long bufptr, result;
  1021. snd_pcm_uframes_t frmres;
  1022. #ifdef QUERY_HARDWARE
  1023. bufptr = inl(chip->codec_port+IDX_IO_PLAY_DMA_START_1);
  1024. #else
  1025. bufptr = substream->runtime->dma_addr;
  1026. #endif
  1027. result = inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS);
  1028. /* calculate offset */
  1029. result -= bufptr;
  1030. frmres = bytes_to_frames( substream->runtime, result);
  1031. snd_azf3328_dbgplay("PLAY @ 0x%8lx, frames %8ld\n", result, frmres);
  1032. return frmres;
  1033. }
  1034. static snd_pcm_uframes_t
  1035. snd_azf3328_capture_pointer(struct snd_pcm_substream *substream)
  1036. {
  1037. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1038. unsigned long bufptr, result;
  1039. snd_pcm_uframes_t frmres;
  1040. #ifdef QUERY_HARDWARE
  1041. bufptr = inl(chip->codec_port+IDX_IO_REC_DMA_START_1);
  1042. #else
  1043. bufptr = substream->runtime->dma_addr;
  1044. #endif
  1045. result = inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS);
  1046. /* calculate offset */
  1047. result -= bufptr;
  1048. frmres = bytes_to_frames( substream->runtime, result);
  1049. snd_azf3328_dbgplay("REC @ 0x%8lx, frames %8ld\n", result, frmres);
  1050. return frmres;
  1051. }
  1052. static irqreturn_t
  1053. snd_azf3328_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  1054. {
  1055. struct snd_azf3328 *chip = dev_id;
  1056. u8 status, which;
  1057. static unsigned long irq_count;
  1058. status = snd_azf3328_codec_inb(chip, IDX_IO_IRQSTATUS);
  1059. /* fast path out, to ease interrupt sharing */
  1060. if (!(status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_MPU401|IRQ_TIMER)))
  1061. return IRQ_NONE; /* must be interrupt for another device */
  1062. snd_azf3328_dbgplay("Interrupt %ld!\nIDX_IO_PLAY_FLAGS %04x, IDX_IO_PLAY_IRQTYPE %04x, IDX_IO_IRQSTATUS %04x\n",
  1063. irq_count,
  1064. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS),
  1065. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_IRQTYPE),
  1066. status);
  1067. if (status & IRQ_TIMER)
  1068. {
  1069. /* snd_azf3328_dbgplay("timer %ld\n", inl(chip->codec_port+IDX_IO_TIMER_VALUE) & TIMER_VALUE_MASK); */
  1070. if (chip->timer)
  1071. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1072. /* ACK timer */
  1073. spin_lock(&chip->reg_lock);
  1074. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
  1075. spin_unlock(&chip->reg_lock);
  1076. snd_azf3328_dbgplay("azt3328: timer IRQ\n");
  1077. }
  1078. if (status & IRQ_PLAYBACK)
  1079. {
  1080. spin_lock(&chip->reg_lock);
  1081. which = snd_azf3328_codec_inb(chip, IDX_IO_PLAY_IRQTYPE);
  1082. /* ack all IRQ types immediately */
  1083. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_IRQTYPE, which);
  1084. spin_unlock(&chip->reg_lock);
  1085. if (chip->pcm && chip->playback_substream)
  1086. {
  1087. snd_pcm_period_elapsed(chip->playback_substream);
  1088. snd_azf3328_dbgplay("PLAY period done (#%x), @ %x\n",
  1089. which,
  1090. inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS));
  1091. }
  1092. else
  1093. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1094. if (which & IRQ_PLAY_SOMETHING)
  1095. snd_azf3328_dbgplay("azt3328: unknown play IRQ type occurred, please report!\n");
  1096. }
  1097. if (status & IRQ_RECORDING)
  1098. {
  1099. spin_lock(&chip->reg_lock);
  1100. which = snd_azf3328_codec_inb(chip, IDX_IO_REC_IRQTYPE);
  1101. /* ack all IRQ types immediately */
  1102. snd_azf3328_codec_outb(chip, IDX_IO_REC_IRQTYPE, which);
  1103. spin_unlock(&chip->reg_lock);
  1104. if (chip->pcm && chip->capture_substream)
  1105. {
  1106. snd_pcm_period_elapsed(chip->capture_substream);
  1107. snd_azf3328_dbgplay("REC period done (#%x), @ %x\n",
  1108. which,
  1109. inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS));
  1110. }
  1111. else
  1112. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1113. if (which & IRQ_REC_SOMETHING)
  1114. snd_azf3328_dbgplay("azt3328: unknown rec IRQ type occurred, please report!\n");
  1115. }
  1116. /* MPU401 has less critical IRQ requirements
  1117. * than timer and playback/recording, right? */
  1118. if (status & IRQ_MPU401)
  1119. {
  1120. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
  1121. /* hmm, do we have to ack the IRQ here somehow?
  1122. * If so, then I don't know how... */
  1123. snd_azf3328_dbgplay("azt3328: MPU401 IRQ\n");
  1124. }
  1125. irq_count++;
  1126. return IRQ_HANDLED;
  1127. }
  1128. /*****************************************************************/
  1129. static const struct snd_pcm_hardware snd_azf3328_playback =
  1130. {
  1131. /* FIXME!! Correct? */
  1132. .info = SNDRV_PCM_INFO_MMAP |
  1133. SNDRV_PCM_INFO_INTERLEAVED |
  1134. SNDRV_PCM_INFO_MMAP_VALID,
  1135. .formats = SNDRV_PCM_FMTBIT_S8 |
  1136. SNDRV_PCM_FMTBIT_U8 |
  1137. SNDRV_PCM_FMTBIT_S16_LE |
  1138. SNDRV_PCM_FMTBIT_U16_LE,
  1139. .rates = SNDRV_PCM_RATE_5512 |
  1140. SNDRV_PCM_RATE_8000_48000 |
  1141. SNDRV_PCM_RATE_KNOT,
  1142. .rate_min = 4000,
  1143. .rate_max = 66200,
  1144. .channels_min = 1,
  1145. .channels_max = 2,
  1146. .buffer_bytes_max = 65536,
  1147. .period_bytes_min = 64,
  1148. .period_bytes_max = 65536,
  1149. .periods_min = 1,
  1150. .periods_max = 1024,
  1151. /* FIXME: maybe that card actually has a FIFO?
  1152. * Hmm, it seems newer revisions do have one, but we still don't know
  1153. * its size... */
  1154. .fifo_size = 0,
  1155. };
  1156. static const struct snd_pcm_hardware snd_azf3328_capture =
  1157. {
  1158. /* FIXME */
  1159. .info = SNDRV_PCM_INFO_MMAP |
  1160. SNDRV_PCM_INFO_INTERLEAVED |
  1161. SNDRV_PCM_INFO_MMAP_VALID,
  1162. .formats = SNDRV_PCM_FMTBIT_S8 |
  1163. SNDRV_PCM_FMTBIT_U8 |
  1164. SNDRV_PCM_FMTBIT_S16_LE |
  1165. SNDRV_PCM_FMTBIT_U16_LE,
  1166. .rates = SNDRV_PCM_RATE_5512 |
  1167. SNDRV_PCM_RATE_8000_48000 |
  1168. SNDRV_PCM_RATE_KNOT,
  1169. .rate_min = 4000,
  1170. .rate_max = 66200,
  1171. .channels_min = 1,
  1172. .channels_max = 2,
  1173. .buffer_bytes_max = 65536,
  1174. .period_bytes_min = 64,
  1175. .period_bytes_max = 65536,
  1176. .periods_min = 1,
  1177. .periods_max = 1024,
  1178. .fifo_size = 0,
  1179. };
  1180. static unsigned int snd_azf3328_fixed_rates[] = {
  1181. 4000, 4800, 5512, 6620, 8000, 9600, 11025, 13240, 16000, 22050, 32000,
  1182. 44100, 48000, 66200 };
  1183. static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
  1184. .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
  1185. .list = snd_azf3328_fixed_rates,
  1186. .mask = 0,
  1187. };
  1188. /*****************************************************************/
  1189. static int
  1190. snd_azf3328_playback_open(struct snd_pcm_substream *substream)
  1191. {
  1192. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1193. struct snd_pcm_runtime *runtime = substream->runtime;
  1194. snd_azf3328_dbgcallenter();
  1195. chip->playback_substream = substream;
  1196. runtime->hw = snd_azf3328_playback;
  1197. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1198. &snd_azf3328_hw_constraints_rates);
  1199. snd_azf3328_dbgcallleave();
  1200. return 0;
  1201. }
  1202. static int
  1203. snd_azf3328_capture_open(struct snd_pcm_substream *substream)
  1204. {
  1205. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1206. struct snd_pcm_runtime *runtime = substream->runtime;
  1207. snd_azf3328_dbgcallenter();
  1208. chip->capture_substream = substream;
  1209. runtime->hw = snd_azf3328_capture;
  1210. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1211. &snd_azf3328_hw_constraints_rates);
  1212. snd_azf3328_dbgcallleave();
  1213. return 0;
  1214. }
  1215. static int
  1216. snd_azf3328_playback_close(struct snd_pcm_substream *substream)
  1217. {
  1218. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1219. snd_azf3328_dbgcallenter();
  1220. chip->playback_substream = NULL;
  1221. snd_azf3328_dbgcallleave();
  1222. return 0;
  1223. }
  1224. static int
  1225. snd_azf3328_capture_close(struct snd_pcm_substream *substream)
  1226. {
  1227. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1228. snd_azf3328_dbgcallenter();
  1229. chip->capture_substream = NULL;
  1230. snd_azf3328_dbgcallleave();
  1231. return 0;
  1232. }
  1233. /******************************************************************/
  1234. static struct snd_pcm_ops snd_azf3328_playback_ops = {
  1235. .open = snd_azf3328_playback_open,
  1236. .close = snd_azf3328_playback_close,
  1237. .ioctl = snd_pcm_lib_ioctl,
  1238. .hw_params = snd_azf3328_hw_params,
  1239. .hw_free = snd_azf3328_hw_free,
  1240. .prepare = snd_azf3328_playback_prepare,
  1241. .trigger = snd_azf3328_playback_trigger,
  1242. .pointer = snd_azf3328_playback_pointer
  1243. };
  1244. static struct snd_pcm_ops snd_azf3328_capture_ops = {
  1245. .open = snd_azf3328_capture_open,
  1246. .close = snd_azf3328_capture_close,
  1247. .ioctl = snd_pcm_lib_ioctl,
  1248. .hw_params = snd_azf3328_hw_params,
  1249. .hw_free = snd_azf3328_hw_free,
  1250. .prepare = snd_azf3328_capture_prepare,
  1251. .trigger = snd_azf3328_capture_trigger,
  1252. .pointer = snd_azf3328_capture_pointer
  1253. };
  1254. static int __devinit
  1255. snd_azf3328_pcm(struct snd_azf3328 *chip, int device)
  1256. {
  1257. struct snd_pcm *pcm;
  1258. int err;
  1259. snd_azf3328_dbgcallenter();
  1260. if ((err = snd_pcm_new(chip->card, "AZF3328 DSP", device, 1, 1, &pcm)) < 0)
  1261. return err;
  1262. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_azf3328_playback_ops);
  1263. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_azf3328_capture_ops);
  1264. pcm->private_data = chip;
  1265. pcm->info_flags = 0;
  1266. strcpy(pcm->name, chip->card->shortname);
  1267. chip->pcm = pcm;
  1268. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1269. snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
  1270. snd_azf3328_dbgcallleave();
  1271. return 0;
  1272. }
  1273. /******************************************************************/
  1274. #ifdef SUPPORT_JOYSTICK
  1275. static int __devinit
  1276. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev)
  1277. {
  1278. struct gameport *gp;
  1279. struct resource *r;
  1280. if (!joystick[dev])
  1281. return -ENODEV;
  1282. if (!(r = request_region(0x200, 8, "AZF3328 gameport"))) {
  1283. printk(KERN_WARNING "azt3328: cannot reserve joystick ports\n");
  1284. return -EBUSY;
  1285. }
  1286. chip->gameport = gp = gameport_allocate_port();
  1287. if (!gp) {
  1288. printk(KERN_ERR "azt3328: cannot allocate memory for gameport\n");
  1289. release_and_free_resource(r);
  1290. return -ENOMEM;
  1291. }
  1292. gameport_set_name(gp, "AZF3328 Gameport");
  1293. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1294. gameport_set_dev_parent(gp, &chip->pci->dev);
  1295. gp->io = 0x200;
  1296. gameport_set_port_data(gp, r);
  1297. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1298. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) | LEGACY_JOY);
  1299. gameport_register_port(chip->gameport);
  1300. return 0;
  1301. }
  1302. static void
  1303. snd_azf3328_free_joystick(struct snd_azf3328 *chip)
  1304. {
  1305. if (chip->gameport) {
  1306. struct resource *r = gameport_get_port_data(chip->gameport);
  1307. gameport_unregister_port(chip->gameport);
  1308. chip->gameport = NULL;
  1309. /* disable gameport */
  1310. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1311. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1312. release_and_free_resource(r);
  1313. }
  1314. }
  1315. #else
  1316. static inline int
  1317. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
  1318. static inline void
  1319. snd_azf3328_free_joystick(struct snd_azf3328 *chip) { }
  1320. #endif
  1321. /******************************************************************/
  1322. static int
  1323. snd_azf3328_free(struct snd_azf3328 *chip)
  1324. {
  1325. if (chip->irq < 0)
  1326. goto __end_hw;
  1327. /* reset (close) mixer */
  1328. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1); /* first mute master volume */
  1329. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  1330. /* interrupt setup - mask everything (FIXME!) */
  1331. /* well, at least we know how to disable the timer IRQ */
  1332. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00);
  1333. synchronize_irq(chip->irq);
  1334. __end_hw:
  1335. snd_azf3328_free_joystick(chip);
  1336. if (chip->irq >= 0)
  1337. free_irq(chip->irq, (void *)chip);
  1338. pci_release_regions(chip->pci);
  1339. pci_disable_device(chip->pci);
  1340. kfree(chip);
  1341. return 0;
  1342. }
  1343. static int
  1344. snd_azf3328_dev_free(struct snd_device *device)
  1345. {
  1346. struct snd_azf3328 *chip = device->device_data;
  1347. return snd_azf3328_free(chip);
  1348. }
  1349. /******************************************************************/
  1350. /*** NOTE: the physical timer resolution actually is 1024000 ticks per second,
  1351. *** but announcing those attributes to user-space would make programs
  1352. *** configure the timer to a 1 tick value, resulting in an absolutely fatal
  1353. *** timer IRQ storm.
  1354. *** Thus I chose to announce a down-scaled virtual timer to the outside and
  1355. *** calculate real timer countdown values internally.
  1356. *** (the scale factor can be set via module parameter "seqtimer_scaling").
  1357. ***/
  1358. static int
  1359. snd_azf3328_timer_start(struct snd_timer *timer)
  1360. {
  1361. struct snd_azf3328 *chip;
  1362. unsigned long flags;
  1363. unsigned int delay;
  1364. snd_azf3328_dbgcallenter();
  1365. chip = snd_timer_chip(timer);
  1366. delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
  1367. if (delay < 49)
  1368. {
  1369. /* uhoh, that's not good, since user-space won't know about
  1370. * this timing tweak
  1371. * (we need to do it to avoid a lockup, though) */
  1372. snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay);
  1373. delay = 49; /* minimum time is 49 ticks */
  1374. }
  1375. snd_azf3328_dbgtimer("setting timer countdown value %d, add COUNTDOWN|IRQ\n", delay);
  1376. delay |= TIMER_ENABLE_COUNTDOWN | TIMER_ENABLE_IRQ;
  1377. spin_lock_irqsave(&chip->reg_lock, flags);
  1378. snd_azf3328_codec_outl(chip, IDX_IO_TIMER_VALUE, delay);
  1379. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1380. snd_azf3328_dbgcallleave();
  1381. return 0;
  1382. }
  1383. static int
  1384. snd_azf3328_timer_stop(struct snd_timer *timer)
  1385. {
  1386. struct snd_azf3328 *chip;
  1387. unsigned long flags;
  1388. snd_azf3328_dbgcallenter();
  1389. chip = snd_timer_chip(timer);
  1390. spin_lock_irqsave(&chip->reg_lock, flags);
  1391. /* disable timer countdown and interrupt */
  1392. /* FIXME: should we write TIMER_ACK_IRQ here? */
  1393. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0);
  1394. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1395. snd_azf3328_dbgcallleave();
  1396. return 0;
  1397. }
  1398. static int
  1399. snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
  1400. unsigned long *num, unsigned long *den)
  1401. {
  1402. snd_azf3328_dbgcallenter();
  1403. *num = 1;
  1404. *den = 1024000 / seqtimer_scaling;
  1405. snd_azf3328_dbgcallleave();
  1406. return 0;
  1407. }
  1408. static struct snd_timer_hardware snd_azf3328_timer_hw = {
  1409. .flags = SNDRV_TIMER_HW_AUTO,
  1410. .resolution = 977, /* 1000000/1024000 = 0.9765625us */
  1411. .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
  1412. .start = snd_azf3328_timer_start,
  1413. .stop = snd_azf3328_timer_stop,
  1414. .precise_resolution = snd_azf3328_timer_precise_resolution,
  1415. };
  1416. static int __devinit
  1417. snd_azf3328_timer(struct snd_azf3328 *chip, int device)
  1418. {
  1419. struct snd_timer *timer = NULL;
  1420. struct snd_timer_id tid;
  1421. int err;
  1422. snd_azf3328_dbgcallenter();
  1423. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1424. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1425. tid.card = chip->card->number;
  1426. tid.device = device;
  1427. tid.subdevice = 0;
  1428. snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
  1429. snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
  1430. if ((err = snd_timer_new(chip->card, "AZF3328", &tid, &timer)) < 0) {
  1431. goto out;
  1432. }
  1433. strcpy(timer->name, "AZF3328 timer");
  1434. timer->private_data = chip;
  1435. timer->hw = snd_azf3328_timer_hw;
  1436. chip->timer = timer;
  1437. err = 0;
  1438. out:
  1439. snd_azf3328_dbgcallleave();
  1440. return err;
  1441. }
  1442. /******************************************************************/
  1443. #if 0
  1444. /* check whether a bit can be modified */
  1445. static void
  1446. snd_azf3328_test_bit(unsigned int reg, int bit)
  1447. {
  1448. unsigned char val, valoff, valon;
  1449. val = inb(reg);
  1450. outb(val & ~(1 << bit), reg);
  1451. valoff = inb(reg);
  1452. outb(val|(1 << bit), reg);
  1453. valon = inb(reg);
  1454. outb(val, reg);
  1455. printk(KERN_ERR "reg %04x bit %d: %02x %02x %02x\n", reg, bit, val, valoff, valon);
  1456. }
  1457. #endif
  1458. static void
  1459. snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
  1460. {
  1461. #if DEBUG_MISC
  1462. u16 tmp;
  1463. snd_azf3328_dbgmisc("codec_port 0x%lx, io2_port 0x%lx, mpu_port 0x%lx, synth_port 0x%lx, mixer_port 0x%lx, irq %d\n", chip->codec_port, chip->io2_port, chip->mpu_port, chip->synth_port, chip->mixer_port, chip->irq);
  1464. snd_azf3328_dbgmisc("io2 %02x %02x %02x %02x %02x %02x\n", snd_azf3328_io2_inb(chip, 0), snd_azf3328_io2_inb(chip, 1), snd_azf3328_io2_inb(chip, 2), snd_azf3328_io2_inb(chip, 3), snd_azf3328_io2_inb(chip, 4), snd_azf3328_io2_inb(chip, 5));
  1465. for (tmp=0; tmp <= 0x01; tmp += 1)
  1466. snd_azf3328_dbgmisc("0x%02x: opl 0x%04x, mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, mpu330 0x%04x\n", tmp, inb(0x388 + tmp), inb(0x300 + tmp), inb(0x310 + tmp), inb(0x320 + tmp), inb(0x330 + tmp));
  1467. for (tmp = 0; tmp <= 0x6E; tmp += 2)
  1468. snd_azf3328_dbgmisc("0x%02x: 0x%04x\n", tmp, snd_azf3328_codec_inb(chip, tmp));
  1469. #endif
  1470. }
  1471. static int __devinit
  1472. snd_azf3328_create(struct snd_card *card,
  1473. struct pci_dev *pci,
  1474. unsigned long device_type,
  1475. struct snd_azf3328 ** rchip)
  1476. {
  1477. struct snd_azf3328 *chip;
  1478. int err;
  1479. static struct snd_device_ops ops = {
  1480. .dev_free = snd_azf3328_dev_free,
  1481. };
  1482. u16 tmp;
  1483. *rchip = NULL;
  1484. if ((err = pci_enable_device(pci)) < 0)
  1485. return err;
  1486. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1487. if (chip == NULL) {
  1488. err = -ENOMEM;
  1489. goto out_err;
  1490. }
  1491. spin_lock_init(&chip->reg_lock);
  1492. chip->card = card;
  1493. chip->pci = pci;
  1494. chip->irq = -1;
  1495. /* check if we can restrict PCI DMA transfers to 24 bits */
  1496. if (pci_set_dma_mask(pci, DMA_24BIT_MASK) < 0 ||
  1497. pci_set_consistent_dma_mask(pci, DMA_24BIT_MASK) < 0) {
  1498. snd_printk(KERN_ERR "architecture does not support 24bit PCI busmaster DMA\n");
  1499. err = -ENXIO;
  1500. goto out_err;
  1501. }
  1502. if ((err = pci_request_regions(pci, "Aztech AZF3328")) < 0) {
  1503. goto out_err;
  1504. }
  1505. chip->codec_port = pci_resource_start(pci, 0);
  1506. chip->io2_port = pci_resource_start(pci, 1);
  1507. chip->mpu_port = pci_resource_start(pci, 2);
  1508. chip->synth_port = pci_resource_start(pci, 3);
  1509. chip->mixer_port = pci_resource_start(pci, 4);
  1510. if (request_irq(pci->irq, snd_azf3328_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
  1511. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1512. err = -EBUSY;
  1513. goto out_err;
  1514. }
  1515. chip->irq = pci->irq;
  1516. pci_set_master(pci);
  1517. synchronize_irq(chip->irq);
  1518. snd_azf3328_debug_show_ports(chip);
  1519. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1520. goto out_err;
  1521. }
  1522. /* create mixer interface & switches */
  1523. if ((err = snd_azf3328_mixer_new(chip)) < 0)
  1524. goto out_err;
  1525. #if 0
  1526. /* set very low bitrate to reduce noise and power consumption? */
  1527. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT, 5512, 8, 1);
  1528. #endif
  1529. /* standard chip init stuff */
  1530. /* default IRQ init value */
  1531. tmp = DMA_PLAY_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
  1532. spin_lock_irq(&chip->reg_lock);
  1533. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_FLAGS, tmp);
  1534. snd_azf3328_codec_outb(chip, IDX_IO_REC_FLAGS, tmp);
  1535. snd_azf3328_codec_outb(chip, IDX_IO_SOMETHING_FLAGS, tmp);
  1536. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00); /* disable timer */
  1537. spin_unlock_irq(&chip->reg_lock);
  1538. snd_card_set_dev(card, &pci->dev);
  1539. *rchip = chip;
  1540. err = 0;
  1541. goto out;
  1542. out_err:
  1543. if (chip)
  1544. snd_azf3328_free(chip);
  1545. pci_disable_device(pci);
  1546. out:
  1547. return err;
  1548. }
  1549. static int __devinit
  1550. snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1551. {
  1552. static int dev;
  1553. struct snd_card *card;
  1554. struct snd_azf3328 *chip;
  1555. struct snd_opl3 *opl3;
  1556. int err;
  1557. snd_azf3328_dbgcallenter();
  1558. if (dev >= SNDRV_CARDS)
  1559. return -ENODEV;
  1560. if (!enable[dev]) {
  1561. dev++;
  1562. return -ENOENT;
  1563. }
  1564. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0 );
  1565. if (card == NULL)
  1566. return -ENOMEM;
  1567. strcpy(card->driver, "AZF3328");
  1568. strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
  1569. if ((err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip)) < 0) {
  1570. goto out_err;
  1571. }
  1572. card->private_data = chip;
  1573. if ((err = snd_mpu401_uart_new( card, 0, MPU401_HW_MPU401,
  1574. chip->mpu_port, 1, pci->irq, 0,
  1575. &chip->rmidi)) < 0) {
  1576. snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n", chip->mpu_port);
  1577. goto out_err;
  1578. }
  1579. if ((err = snd_azf3328_timer(chip, 0)) < 0) {
  1580. goto out_err;
  1581. }
  1582. if ((err = snd_azf3328_pcm(chip, 0)) < 0) {
  1583. goto out_err;
  1584. }
  1585. if (snd_opl3_create(card, chip->synth_port, chip->synth_port+2,
  1586. OPL3_HW_AUTO, 1, &opl3) < 0) {
  1587. snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n",
  1588. chip->synth_port, chip->synth_port+2 );
  1589. } else {
  1590. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1591. goto out_err;
  1592. }
  1593. }
  1594. opl3->private_data = chip;
  1595. sprintf(card->longname, "%s at 0x%lx, irq %i",
  1596. card->shortname, chip->codec_port, chip->irq);
  1597. if ((err = snd_card_register(card)) < 0) {
  1598. goto out_err;
  1599. }
  1600. #ifdef MODULE
  1601. printk(
  1602. "azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168\n"
  1603. "azt3328: (hardware was completely undocumented - ZERO support from Aztech).\n"
  1604. "azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
  1605. "azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
  1606. 1024000 / seqtimer_scaling, seqtimer_scaling);
  1607. #endif
  1608. if (snd_azf3328_config_joystick(chip, dev) < 0)
  1609. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1610. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1611. pci_set_drvdata(pci, card);
  1612. dev++;
  1613. err = 0;
  1614. goto out;
  1615. out_err:
  1616. snd_card_free(card);
  1617. out:
  1618. snd_azf3328_dbgcallleave();
  1619. return err;
  1620. }
  1621. static void __devexit
  1622. snd_azf3328_remove(struct pci_dev *pci)
  1623. {
  1624. snd_azf3328_dbgcallenter();
  1625. snd_card_free(pci_get_drvdata(pci));
  1626. pci_set_drvdata(pci, NULL);
  1627. snd_azf3328_dbgcallleave();
  1628. }
  1629. #ifdef CONFIG_PM
  1630. static int
  1631. snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
  1632. {
  1633. struct snd_card *card = pci_get_drvdata(pci);
  1634. struct snd_azf3328 *chip = card->private_data;
  1635. int reg;
  1636. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1637. snd_pcm_suspend_all(chip->pcm);
  1638. for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++)
  1639. chip->saved_regs_mixer[reg] = inw(chip->mixer_port + reg * 2);
  1640. /* make sure to disable master volume etc. to prevent looping sound */
  1641. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
  1642. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  1643. for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++)
  1644. chip->saved_regs_codec[reg] = inw(chip->codec_port + reg * 2);
  1645. for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++)
  1646. chip->saved_regs_io2[reg] = inw(chip->io2_port + reg * 2);
  1647. for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++)
  1648. chip->saved_regs_mpu[reg] = inw(chip->mpu_port + reg * 2);
  1649. for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++)
  1650. chip->saved_regs_synth[reg] = inw(chip->synth_port + reg * 2);
  1651. pci_set_power_state(pci, PCI_D3hot);
  1652. pci_disable_device(pci);
  1653. pci_save_state(pci);
  1654. return 0;
  1655. }
  1656. static int
  1657. snd_azf3328_resume(struct pci_dev *pci)
  1658. {
  1659. struct snd_card *card = pci_get_drvdata(pci);
  1660. struct snd_azf3328 *chip = card->private_data;
  1661. int reg;
  1662. pci_restore_state(pci);
  1663. pci_enable_device(pci);
  1664. pci_set_power_state(pci, PCI_D0);
  1665. pci_set_master(pci);
  1666. for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++)
  1667. outw(chip->saved_regs_io2[reg], chip->io2_port + reg * 2);
  1668. for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++)
  1669. outw(chip->saved_regs_mpu[reg], chip->mpu_port + reg * 2);
  1670. for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++)
  1671. outw(chip->saved_regs_synth[reg], chip->synth_port + reg * 2);
  1672. for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++)
  1673. outw(chip->saved_regs_mixer[reg], chip->mixer_port + reg * 2);
  1674. for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++)
  1675. outw(chip->saved_regs_codec[reg], chip->codec_port + reg * 2);
  1676. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1677. return 0;
  1678. }
  1679. #endif
  1680. static struct pci_driver driver = {
  1681. .name = "AZF3328",
  1682. .id_table = snd_azf3328_ids,
  1683. .probe = snd_azf3328_probe,
  1684. .remove = __devexit_p(snd_azf3328_remove),
  1685. #ifdef CONFIG_PM
  1686. .suspend = snd_azf3328_suspend,
  1687. .resume = snd_azf3328_resume,
  1688. #endif
  1689. };
  1690. static int __init
  1691. alsa_card_azf3328_init(void)
  1692. {
  1693. int err;
  1694. snd_azf3328_dbgcallenter();
  1695. err = pci_register_driver(&driver);
  1696. snd_azf3328_dbgcallleave();
  1697. return err;
  1698. }
  1699. static void __exit
  1700. alsa_card_azf3328_exit(void)
  1701. {
  1702. snd_azf3328_dbgcallenter();
  1703. pci_unregister_driver(&driver);
  1704. snd_azf3328_dbgcallleave();
  1705. }
  1706. module_init(alsa_card_azf3328_init)
  1707. module_exit(alsa_card_azf3328_exit)