pinctrl.c 8.5 KB

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  1. /*
  2. * SuperH Pin Function Controller pinmux support.
  3. *
  4. * Copyright (C) 2012 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/sh_pfc.h>
  14. #include <linux/err.h>
  15. #include <linux/slab.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pinctrl/consumer.h>
  18. #include <linux/pinctrl/pinctrl.h>
  19. #include <linux/pinctrl/pinconf.h>
  20. #include <linux/pinctrl/pinmux.h>
  21. #include <linux/pinctrl/pinconf-generic.h>
  22. struct sh_pfc_pinctrl {
  23. struct pinctrl_dev *pctl;
  24. struct sh_pfc *pfc;
  25. struct pinctrl_pin_desc *pads;
  26. unsigned int nr_pads;
  27. };
  28. static struct sh_pfc_pinctrl *sh_pfc_pmx;
  29. /*
  30. * No group support yet
  31. */
  32. static int sh_pfc_get_noop_count(struct pinctrl_dev *pctldev)
  33. {
  34. return 0;
  35. }
  36. static const char *sh_pfc_get_noop_name(struct pinctrl_dev *pctldev,
  37. unsigned selector)
  38. {
  39. return NULL;
  40. }
  41. static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
  42. const unsigned **pins, unsigned *num_pins)
  43. {
  44. return -ENOTSUPP;
  45. }
  46. static struct pinctrl_ops sh_pfc_pinctrl_ops = {
  47. .get_groups_count = sh_pfc_get_noop_count,
  48. .get_group_name = sh_pfc_get_noop_name,
  49. .get_group_pins = sh_pfc_get_group_pins,
  50. };
  51. /*
  52. * No function support yet
  53. */
  54. static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
  55. const char * const **groups,
  56. unsigned * const num_groups)
  57. {
  58. return 0;
  59. }
  60. static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
  61. unsigned group)
  62. {
  63. return 0;
  64. }
  65. static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
  66. unsigned group)
  67. {
  68. }
  69. static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
  70. struct pinctrl_gpio_range *range,
  71. unsigned offset)
  72. {
  73. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  74. struct sh_pfc *pfc = pmx->pfc;
  75. struct pinmux_data_reg *dummy;
  76. unsigned long flags;
  77. int i, ret, pinmux_type;
  78. ret = -EINVAL;
  79. spin_lock_irqsave(&pfc->lock, flags);
  80. if ((pfc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
  81. goto err;
  82. /* setup pin function here if no data is associated with pin */
  83. if (sh_pfc_get_data_reg(pfc, offset, &dummy, &i) != 0) {
  84. pinmux_type = PINMUX_TYPE_FUNCTION;
  85. if (sh_pfc_config_gpio(pfc, offset,
  86. pinmux_type,
  87. GPIO_CFG_DRYRUN) != 0)
  88. goto err;
  89. if (sh_pfc_config_gpio(pfc, offset,
  90. pinmux_type,
  91. GPIO_CFG_REQ) != 0)
  92. goto err;
  93. } else
  94. pinmux_type = PINMUX_TYPE_GPIO;
  95. pfc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
  96. pfc->gpios[offset].flags |= pinmux_type;
  97. ret = 0;
  98. err:
  99. spin_unlock_irqrestore(&pfc->lock, flags);
  100. return ret;
  101. }
  102. static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
  103. struct pinctrl_gpio_range *range,
  104. unsigned offset)
  105. {
  106. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  107. struct sh_pfc *pfc = pmx->pfc;
  108. unsigned long flags;
  109. int pinmux_type;
  110. spin_lock_irqsave(&pfc->lock, flags);
  111. pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
  112. sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
  113. pfc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
  114. pfc->gpios[offset].flags |= PINMUX_TYPE_NONE;
  115. spin_unlock_irqrestore(&pfc->lock, flags);
  116. }
  117. static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
  118. struct pinctrl_gpio_range *range,
  119. unsigned offset, bool input)
  120. {
  121. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  122. struct sh_pfc *pfc = pmx->pfc;
  123. unsigned long flags;
  124. int pinmux_type, new_pinmux_type;
  125. int ret = -EINVAL;
  126. new_pinmux_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
  127. spin_lock_irqsave(&pfc->lock, flags);
  128. pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
  129. switch (pinmux_type) {
  130. case PINMUX_TYPE_GPIO:
  131. break;
  132. case PINMUX_TYPE_OUTPUT:
  133. case PINMUX_TYPE_INPUT:
  134. case PINMUX_TYPE_INPUT_PULLUP:
  135. case PINMUX_TYPE_INPUT_PULLDOWN:
  136. sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
  137. break;
  138. default:
  139. goto err;
  140. }
  141. if (sh_pfc_config_gpio(pfc, offset,
  142. new_pinmux_type,
  143. GPIO_CFG_DRYRUN) != 0)
  144. goto err;
  145. if (sh_pfc_config_gpio(pfc, offset,
  146. new_pinmux_type,
  147. GPIO_CFG_REQ) != 0)
  148. BUG();
  149. pfc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
  150. pfc->gpios[offset].flags |= new_pinmux_type;
  151. ret = 0;
  152. err:
  153. spin_unlock_irqrestore(&pfc->lock, flags);
  154. return ret;
  155. }
  156. static struct pinmux_ops sh_pfc_pinmux_ops = {
  157. .get_functions_count = sh_pfc_get_noop_count,
  158. .get_function_name = sh_pfc_get_noop_name,
  159. .get_function_groups = sh_pfc_get_function_groups,
  160. .enable = sh_pfc_noop_enable,
  161. .disable = sh_pfc_noop_disable,
  162. .gpio_request_enable = sh_pfc_gpio_request_enable,
  163. .gpio_disable_free = sh_pfc_gpio_disable_free,
  164. .gpio_set_direction = sh_pfc_gpio_set_direction,
  165. };
  166. static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
  167. unsigned long *config)
  168. {
  169. return -ENOTSUPP;
  170. }
  171. static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
  172. unsigned long config)
  173. {
  174. return -EINVAL;
  175. }
  176. static struct pinconf_ops sh_pfc_pinconf_ops = {
  177. .is_generic = true,
  178. .pin_config_get = sh_pfc_pinconf_get,
  179. .pin_config_set = sh_pfc_pinconf_set,
  180. };
  181. static struct pinctrl_gpio_range sh_pfc_gpio_range = {
  182. .name = KBUILD_MODNAME,
  183. .id = 0,
  184. };
  185. static struct pinctrl_desc sh_pfc_pinctrl_desc = {
  186. .name = KBUILD_MODNAME,
  187. .owner = THIS_MODULE,
  188. .pctlops = &sh_pfc_pinctrl_ops,
  189. .pmxops = &sh_pfc_pinmux_ops,
  190. .confops = &sh_pfc_pinconf_ops,
  191. };
  192. int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
  193. {
  194. sh_pfc_pmx = kmalloc(sizeof(struct sh_pfc_pinctrl), GFP_KERNEL);
  195. if (unlikely(!sh_pfc_pmx))
  196. return -ENOMEM;
  197. sh_pfc_pmx->pfc = pfc;
  198. return 0;
  199. }
  200. /* pinmux ranges -> pinctrl pin descs */
  201. static int __devinit sh_pfc_map_gpios(struct sh_pfc *pfc,
  202. struct sh_pfc_pinctrl *pmx)
  203. {
  204. int i;
  205. pmx->nr_pads = pfc->last_gpio - pfc->first_gpio + 1;
  206. pmx->pads = kmalloc(sizeof(struct pinctrl_pin_desc) * pmx->nr_pads,
  207. GFP_KERNEL);
  208. if (unlikely(!pmx->pads)) {
  209. pmx->nr_pads = 0;
  210. return -ENOMEM;
  211. }
  212. /*
  213. * We don't necessarily have a 1:1 mapping between pin and linux
  214. * GPIO number, as the latter maps to the associated enum_id.
  215. * Care needs to be taken to translate back to pin space when
  216. * dealing with any pin configurations.
  217. */
  218. for (i = 0; i < pmx->nr_pads; i++) {
  219. struct pinctrl_pin_desc *pin = pmx->pads + i;
  220. struct pinmux_gpio *gpio = pfc->gpios + i;
  221. pin->number = pfc->first_gpio + i;
  222. pin->name = gpio->name;
  223. }
  224. sh_pfc_pinctrl_desc.pins = pmx->pads;
  225. sh_pfc_pinctrl_desc.npins = pmx->nr_pads;
  226. return 0;
  227. }
  228. static int __devinit sh_pfc_pinctrl_probe(struct platform_device *pdev)
  229. {
  230. struct sh_pfc *pfc;
  231. int ret;
  232. if (unlikely(!sh_pfc_pmx))
  233. return -ENODEV;
  234. pfc = sh_pfc_pmx->pfc;
  235. ret = sh_pfc_map_gpios(pfc, sh_pfc_pmx);
  236. if (unlikely(ret != 0))
  237. return ret;
  238. sh_pfc_pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, &pdev->dev,
  239. sh_pfc_pmx);
  240. if (IS_ERR(sh_pfc_pmx->pctl)) {
  241. ret = PTR_ERR(sh_pfc_pmx->pctl);
  242. goto out;
  243. }
  244. sh_pfc_gpio_range.npins = pfc->last_gpio - pfc->first_gpio + 1;
  245. sh_pfc_gpio_range.base = pfc->first_gpio;
  246. sh_pfc_gpio_range.pin_base = pfc->first_gpio;
  247. pinctrl_add_gpio_range(sh_pfc_pmx->pctl, &sh_pfc_gpio_range);
  248. platform_set_drvdata(pdev, sh_pfc_pmx);
  249. return 0;
  250. out:
  251. kfree(sh_pfc_pmx->pads);
  252. kfree(sh_pfc_pmx);
  253. return ret;
  254. }
  255. static int __devexit sh_pfc_pinctrl_remove(struct platform_device *pdev)
  256. {
  257. struct sh_pfc_pinctrl *pmx = platform_get_drvdata(pdev);
  258. pinctrl_remove_gpio_range(pmx->pctl, &sh_pfc_gpio_range);
  259. pinctrl_unregister(pmx->pctl);
  260. platform_set_drvdata(pdev, NULL);
  261. kfree(sh_pfc_pmx->pads);
  262. kfree(sh_pfc_pmx);
  263. return 0;
  264. }
  265. static struct platform_driver sh_pfc_pinctrl_driver = {
  266. .probe = sh_pfc_pinctrl_probe,
  267. .remove = __devexit_p(sh_pfc_pinctrl_remove),
  268. .driver = {
  269. .name = KBUILD_MODNAME,
  270. .owner = THIS_MODULE,
  271. },
  272. };
  273. static struct platform_device sh_pfc_pinctrl_device = {
  274. .name = KBUILD_MODNAME,
  275. .id = -1,
  276. };
  277. static int __init sh_pfc_pinctrl_init(void)
  278. {
  279. int rc;
  280. rc = platform_driver_register(&sh_pfc_pinctrl_driver);
  281. if (likely(!rc)) {
  282. rc = platform_device_register(&sh_pfc_pinctrl_device);
  283. if (unlikely(rc))
  284. platform_driver_unregister(&sh_pfc_pinctrl_driver);
  285. }
  286. return rc;
  287. }
  288. static void __exit sh_pfc_pinctrl_exit(void)
  289. {
  290. platform_driver_unregister(&sh_pfc_pinctrl_driver);
  291. }
  292. subsys_initcall(sh_pfc_pinctrl_init);
  293. module_exit(sh_pfc_pinctrl_exit);