nouveau_dma.c 6.3 KB

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  1. /*
  2. * Copyright (C) 2007 Ben Skeggs.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #include "drmP.h"
  27. #include "drm.h"
  28. #include "nouveau_drv.h"
  29. #include "nouveau_dma.h"
  30. int
  31. nouveau_dma_init(struct nouveau_channel *chan)
  32. {
  33. struct drm_device *dev = chan->dev;
  34. struct drm_nouveau_private *dev_priv = dev->dev_private;
  35. struct nouveau_gpuobj *m2mf = NULL;
  36. struct nouveau_gpuobj *nvsw = NULL;
  37. int ret, i;
  38. /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
  39. ret = nouveau_gpuobj_gr_new(chan, dev_priv->card_type < NV_50 ?
  40. 0x0039 : 0x5039, &m2mf);
  41. if (ret)
  42. return ret;
  43. ret = nouveau_gpuobj_ref_add(dev, chan, NvM2MF, m2mf, NULL);
  44. if (ret)
  45. return ret;
  46. /* Create an NV_SW object for various sync purposes */
  47. ret = nouveau_gpuobj_sw_new(chan, NV_SW, &nvsw);
  48. if (ret)
  49. return ret;
  50. ret = nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL);
  51. if (ret)
  52. return ret;
  53. /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
  54. ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
  55. if (ret)
  56. return ret;
  57. /* Map push buffer */
  58. ret = nouveau_bo_map(chan->pushbuf_bo);
  59. if (ret)
  60. return ret;
  61. /* Map M2MF notifier object - fbcon. */
  62. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  63. ret = nouveau_bo_map(chan->notifier_bo);
  64. if (ret)
  65. return ret;
  66. }
  67. /* Initialise DMA vars */
  68. chan->dma.max = (chan->pushbuf_bo->bo.mem.size >> 2) - 2;
  69. chan->dma.put = 0;
  70. chan->dma.cur = chan->dma.put;
  71. chan->dma.free = chan->dma.max - chan->dma.cur;
  72. /* Insert NOPS for NOUVEAU_DMA_SKIPS */
  73. ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
  74. if (ret)
  75. return ret;
  76. for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
  77. OUT_RING(chan, 0);
  78. /* Initialise NV_MEMORY_TO_MEMORY_FORMAT */
  79. ret = RING_SPACE(chan, 4);
  80. if (ret)
  81. return ret;
  82. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
  83. OUT_RING(chan, NvM2MF);
  84. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
  85. OUT_RING(chan, NvNotify0);
  86. /* Initialise NV_SW */
  87. ret = RING_SPACE(chan, 2);
  88. if (ret)
  89. return ret;
  90. BEGIN_RING(chan, NvSubSw, 0, 1);
  91. OUT_RING(chan, NvSw);
  92. /* Sit back and pray the channel works.. */
  93. FIRE_RING(chan);
  94. return 0;
  95. }
  96. void
  97. OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
  98. {
  99. bool is_iomem;
  100. u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
  101. mem = &mem[chan->dma.cur];
  102. if (is_iomem)
  103. memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
  104. else
  105. memcpy(mem, data, nr_dwords * 4);
  106. chan->dma.cur += nr_dwords;
  107. }
  108. static inline bool
  109. READ_GET(struct nouveau_channel *chan, uint32_t *get)
  110. {
  111. uint32_t val;
  112. val = nvchan_rd32(chan, chan->user_get);
  113. if (val < chan->pushbuf_base ||
  114. val >= chan->pushbuf_base + chan->pushbuf_bo->bo.mem.size) {
  115. /* meaningless to dma_wait() except to know whether the
  116. * GPU has stalled or not
  117. */
  118. *get = val;
  119. return false;
  120. }
  121. *get = (val - chan->pushbuf_base) >> 2;
  122. return true;
  123. }
  124. int
  125. nouveau_dma_wait(struct nouveau_channel *chan, int size)
  126. {
  127. uint32_t get, prev_get = 0, cnt = 0;
  128. bool get_valid;
  129. while (chan->dma.free < size) {
  130. /* reset counter as long as GET is still advancing, this is
  131. * to avoid misdetecting a GPU lockup if the GPU happens to
  132. * just be processing an operation that takes a long time
  133. */
  134. get_valid = READ_GET(chan, &get);
  135. if (get != prev_get) {
  136. prev_get = get;
  137. cnt = 0;
  138. }
  139. if ((++cnt & 0xff) == 0) {
  140. DRM_UDELAY(1);
  141. if (cnt > 100000)
  142. return -EBUSY;
  143. }
  144. /* loop until we have a usable GET pointer. the value
  145. * we read from the GPU may be outside the main ring if
  146. * PFIFO is processing a buffer called from the main ring,
  147. * discard these values until something sensible is seen.
  148. *
  149. * the other case we discard GET is while the GPU is fetching
  150. * from the SKIPS area, so the code below doesn't have to deal
  151. * with some fun corner cases.
  152. */
  153. if (!get_valid || get < NOUVEAU_DMA_SKIPS)
  154. continue;
  155. if (get <= chan->dma.cur) {
  156. /* engine is fetching behind us, or is completely
  157. * idle (GET == PUT) so we have free space up until
  158. * the end of the push buffer
  159. *
  160. * we can only hit that path once per call due to
  161. * looping back to the beginning of the push buffer,
  162. * we'll hit the fetching-ahead-of-us path from that
  163. * point on.
  164. *
  165. * the *one* exception to that rule is if we read
  166. * GET==PUT, in which case the below conditional will
  167. * always succeed and break us out of the wait loop.
  168. */
  169. chan->dma.free = chan->dma.max - chan->dma.cur;
  170. if (chan->dma.free >= size)
  171. break;
  172. /* not enough space left at the end of the push buffer,
  173. * instruct the GPU to jump back to the start right
  174. * after processing the currently pending commands.
  175. */
  176. OUT_RING(chan, chan->pushbuf_base | 0x20000000);
  177. WRITE_PUT(NOUVEAU_DMA_SKIPS);
  178. /* we're now submitting commands at the start of
  179. * the push buffer.
  180. */
  181. chan->dma.cur =
  182. chan->dma.put = NOUVEAU_DMA_SKIPS;
  183. }
  184. /* engine fetching ahead of us, we have space up until the
  185. * current GET pointer. the "- 1" is to ensure there's
  186. * space left to emit a jump back to the beginning of the
  187. * push buffer if we require it. we can never get GET == PUT
  188. * here, so this is safe.
  189. */
  190. chan->dma.free = get - chan->dma.cur - 1;
  191. }
  192. return 0;
  193. }