events.c 37 KB

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  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is recieved, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/pci.h>
  39. #include <asm/xen/hypercall.h>
  40. #include <asm/xen/hypervisor.h>
  41. #include <xen/xen.h>
  42. #include <xen/hvm.h>
  43. #include <xen/xen-ops.h>
  44. #include <xen/events.h>
  45. #include <xen/interface/xen.h>
  46. #include <xen/interface/event_channel.h>
  47. #include <xen/interface/hvm/hvm_op.h>
  48. #include <xen/interface/hvm/params.h>
  49. /*
  50. * This lock protects updates to the following mapping and reference-count
  51. * arrays. The lock does not need to be acquired to read the mapping tables.
  52. */
  53. static DEFINE_SPINLOCK(irq_mapping_update_lock);
  54. /* IRQ <-> VIRQ mapping. */
  55. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  56. /* IRQ <-> IPI mapping */
  57. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  58. /* Interrupt types. */
  59. enum xen_irq_type {
  60. IRQT_UNBOUND = 0,
  61. IRQT_PIRQ,
  62. IRQT_VIRQ,
  63. IRQT_IPI,
  64. IRQT_EVTCHN
  65. };
  66. /*
  67. * Packed IRQ information:
  68. * type - enum xen_irq_type
  69. * event channel - irq->event channel mapping
  70. * cpu - cpu this event channel is bound to
  71. * index - type-specific information:
  72. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  73. * guest, or GSI (real passthrough IRQ) of the device.
  74. * VIRQ - virq number
  75. * IPI - IPI vector
  76. * EVTCHN -
  77. */
  78. struct irq_info
  79. {
  80. enum xen_irq_type type; /* type */
  81. unsigned short evtchn; /* event channel */
  82. unsigned short cpu; /* cpu bound */
  83. union {
  84. unsigned short virq;
  85. enum ipi_vector ipi;
  86. struct {
  87. unsigned short pirq;
  88. unsigned short gsi;
  89. unsigned char vector;
  90. unsigned char flags;
  91. } pirq;
  92. } u;
  93. };
  94. #define PIRQ_NEEDS_EOI (1 << 0)
  95. #define PIRQ_SHAREABLE (1 << 1)
  96. static struct irq_info *irq_info;
  97. static int *pirq_to_irq;
  98. static int *evtchn_to_irq;
  99. struct cpu_evtchn_s {
  100. unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
  101. };
  102. static __initdata struct cpu_evtchn_s init_evtchn_mask = {
  103. .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
  104. };
  105. static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
  106. static inline unsigned long *cpu_evtchn_mask(int cpu)
  107. {
  108. return cpu_evtchn_mask_p[cpu].bits;
  109. }
  110. /* Xen will never allocate port zero for any purpose. */
  111. #define VALID_EVTCHN(chn) ((chn) != 0)
  112. static struct irq_chip xen_dynamic_chip;
  113. static struct irq_chip xen_percpu_chip;
  114. static struct irq_chip xen_pirq_chip;
  115. /* Constructor for packed IRQ information. */
  116. static struct irq_info mk_unbound_info(void)
  117. {
  118. return (struct irq_info) { .type = IRQT_UNBOUND };
  119. }
  120. static struct irq_info mk_evtchn_info(unsigned short evtchn)
  121. {
  122. return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
  123. .cpu = 0 };
  124. }
  125. static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
  126. {
  127. return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
  128. .cpu = 0, .u.ipi = ipi };
  129. }
  130. static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
  131. {
  132. return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
  133. .cpu = 0, .u.virq = virq };
  134. }
  135. static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
  136. unsigned short gsi, unsigned short vector)
  137. {
  138. return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
  139. .cpu = 0,
  140. .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
  141. }
  142. /*
  143. * Accessors for packed IRQ information.
  144. */
  145. static struct irq_info *info_for_irq(unsigned irq)
  146. {
  147. return &irq_info[irq];
  148. }
  149. static unsigned int evtchn_from_irq(unsigned irq)
  150. {
  151. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  152. return 0;
  153. return info_for_irq(irq)->evtchn;
  154. }
  155. unsigned irq_from_evtchn(unsigned int evtchn)
  156. {
  157. return evtchn_to_irq[evtchn];
  158. }
  159. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  160. static enum ipi_vector ipi_from_irq(unsigned irq)
  161. {
  162. struct irq_info *info = info_for_irq(irq);
  163. BUG_ON(info == NULL);
  164. BUG_ON(info->type != IRQT_IPI);
  165. return info->u.ipi;
  166. }
  167. static unsigned virq_from_irq(unsigned irq)
  168. {
  169. struct irq_info *info = info_for_irq(irq);
  170. BUG_ON(info == NULL);
  171. BUG_ON(info->type != IRQT_VIRQ);
  172. return info->u.virq;
  173. }
  174. static unsigned pirq_from_irq(unsigned irq)
  175. {
  176. struct irq_info *info = info_for_irq(irq);
  177. BUG_ON(info == NULL);
  178. BUG_ON(info->type != IRQT_PIRQ);
  179. return info->u.pirq.pirq;
  180. }
  181. static unsigned gsi_from_irq(unsigned irq)
  182. {
  183. struct irq_info *info = info_for_irq(irq);
  184. BUG_ON(info == NULL);
  185. BUG_ON(info->type != IRQT_PIRQ);
  186. return info->u.pirq.gsi;
  187. }
  188. static unsigned vector_from_irq(unsigned irq)
  189. {
  190. struct irq_info *info = info_for_irq(irq);
  191. BUG_ON(info == NULL);
  192. BUG_ON(info->type != IRQT_PIRQ);
  193. return info->u.pirq.vector;
  194. }
  195. static enum xen_irq_type type_from_irq(unsigned irq)
  196. {
  197. return info_for_irq(irq)->type;
  198. }
  199. static unsigned cpu_from_irq(unsigned irq)
  200. {
  201. return info_for_irq(irq)->cpu;
  202. }
  203. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  204. {
  205. int irq = evtchn_to_irq[evtchn];
  206. unsigned ret = 0;
  207. if (irq != -1)
  208. ret = cpu_from_irq(irq);
  209. return ret;
  210. }
  211. static bool pirq_needs_eoi(unsigned irq)
  212. {
  213. struct irq_info *info = info_for_irq(irq);
  214. BUG_ON(info->type != IRQT_PIRQ);
  215. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  216. }
  217. static inline unsigned long active_evtchns(unsigned int cpu,
  218. struct shared_info *sh,
  219. unsigned int idx)
  220. {
  221. return (sh->evtchn_pending[idx] &
  222. cpu_evtchn_mask(cpu)[idx] &
  223. ~sh->evtchn_mask[idx]);
  224. }
  225. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  226. {
  227. int irq = evtchn_to_irq[chn];
  228. BUG_ON(irq == -1);
  229. #ifdef CONFIG_SMP
  230. cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu));
  231. #endif
  232. clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
  233. set_bit(chn, cpu_evtchn_mask(cpu));
  234. irq_info[irq].cpu = cpu;
  235. }
  236. static void init_evtchn_cpu_bindings(void)
  237. {
  238. int i;
  239. #ifdef CONFIG_SMP
  240. struct irq_desc *desc;
  241. /* By default all event channels notify CPU#0. */
  242. for_each_irq_desc(i, desc) {
  243. cpumask_copy(desc->affinity, cpumask_of(0));
  244. }
  245. #endif
  246. for_each_possible_cpu(i)
  247. memset(cpu_evtchn_mask(i),
  248. (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
  249. }
  250. static inline void clear_evtchn(int port)
  251. {
  252. struct shared_info *s = HYPERVISOR_shared_info;
  253. sync_clear_bit(port, &s->evtchn_pending[0]);
  254. }
  255. static inline void set_evtchn(int port)
  256. {
  257. struct shared_info *s = HYPERVISOR_shared_info;
  258. sync_set_bit(port, &s->evtchn_pending[0]);
  259. }
  260. static inline int test_evtchn(int port)
  261. {
  262. struct shared_info *s = HYPERVISOR_shared_info;
  263. return sync_test_bit(port, &s->evtchn_pending[0]);
  264. }
  265. /**
  266. * notify_remote_via_irq - send event to remote end of event channel via irq
  267. * @irq: irq of event channel to send event to
  268. *
  269. * Unlike notify_remote_via_evtchn(), this is safe to use across
  270. * save/restore. Notifications on a broken connection are silently
  271. * dropped.
  272. */
  273. void notify_remote_via_irq(int irq)
  274. {
  275. int evtchn = evtchn_from_irq(irq);
  276. if (VALID_EVTCHN(evtchn))
  277. notify_remote_via_evtchn(evtchn);
  278. }
  279. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  280. static void mask_evtchn(int port)
  281. {
  282. struct shared_info *s = HYPERVISOR_shared_info;
  283. sync_set_bit(port, &s->evtchn_mask[0]);
  284. }
  285. static void unmask_evtchn(int port)
  286. {
  287. struct shared_info *s = HYPERVISOR_shared_info;
  288. unsigned int cpu = get_cpu();
  289. BUG_ON(!irqs_disabled());
  290. /* Slow path (hypercall) if this is a non-local port. */
  291. if (unlikely(cpu != cpu_from_evtchn(port))) {
  292. struct evtchn_unmask unmask = { .port = port };
  293. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  294. } else {
  295. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  296. sync_clear_bit(port, &s->evtchn_mask[0]);
  297. /*
  298. * The following is basically the equivalent of
  299. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  300. * the interrupt edge' if the channel is masked.
  301. */
  302. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  303. !sync_test_and_set_bit(port / BITS_PER_LONG,
  304. &vcpu_info->evtchn_pending_sel))
  305. vcpu_info->evtchn_upcall_pending = 1;
  306. }
  307. put_cpu();
  308. }
  309. static int get_nr_hw_irqs(void)
  310. {
  311. int ret = 1;
  312. #ifdef CONFIG_X86_IO_APIC
  313. ret = get_nr_irqs_gsi();
  314. #endif
  315. return ret;
  316. }
  317. static int xen_allocate_irq_dynamic(void)
  318. {
  319. struct irq_data *data;
  320. int irq, res;
  321. int bottom = get_nr_hw_irqs();
  322. int top = nr_irqs-1;
  323. if (bottom == nr_irqs)
  324. goto no_irqs;
  325. /* This loop starts from the top of IRQ space and goes down.
  326. * We need this b/c if we have a PCI device in a Xen PV guest
  327. * we do not have an IO-APIC (though the backend might have them)
  328. * mapped in. To not have a collision of physical IRQs with the Xen
  329. * event channels start at the top of the IRQ space for virtual IRQs.
  330. */
  331. for (irq = top; irq > bottom; irq--) {
  332. data = irq_get_irq_data(irq);
  333. /* only 15->0 have init'd desc; handle irq > 16 */
  334. if (!data)
  335. break;
  336. if (data->chip == &no_irq_chip)
  337. break;
  338. if (data->chip != &xen_dynamic_chip)
  339. continue;
  340. if (irq_info[irq].type == IRQT_UNBOUND)
  341. return irq;
  342. }
  343. if (irq == bottom)
  344. goto no_irqs;
  345. res = irq_alloc_desc_at(irq, -1);
  346. if (WARN_ON(res != irq))
  347. return -1;
  348. return irq;
  349. no_irqs:
  350. panic("No available IRQ to bind to: increase nr_irqs!\n");
  351. }
  352. static bool identity_mapped_irq(unsigned irq)
  353. {
  354. /* identity map all the hardware irqs */
  355. return irq < get_nr_hw_irqs();
  356. }
  357. static int xen_allocate_irq_gsi(unsigned gsi)
  358. {
  359. int irq;
  360. if (!identity_mapped_irq(gsi) &&
  361. (xen_initial_domain() || !xen_pv_domain()))
  362. return xen_allocate_irq_dynamic();
  363. /* Legacy IRQ descriptors are already allocated by the arch. */
  364. if (gsi < NR_IRQS_LEGACY)
  365. return gsi;
  366. irq = irq_alloc_desc_at(gsi, -1);
  367. if (irq < 0)
  368. panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
  369. return irq;
  370. }
  371. static void xen_free_irq(unsigned irq)
  372. {
  373. irq_free_desc(irq);
  374. }
  375. static void pirq_unmask_notify(int irq)
  376. {
  377. struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
  378. if (unlikely(pirq_needs_eoi(irq))) {
  379. int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  380. WARN_ON(rc);
  381. }
  382. }
  383. static void pirq_query_unmask(int irq)
  384. {
  385. struct physdev_irq_status_query irq_status;
  386. struct irq_info *info = info_for_irq(irq);
  387. BUG_ON(info->type != IRQT_PIRQ);
  388. irq_status.irq = pirq_from_irq(irq);
  389. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  390. irq_status.flags = 0;
  391. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  392. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  393. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  394. }
  395. static bool probing_irq(int irq)
  396. {
  397. struct irq_desc *desc = irq_to_desc(irq);
  398. return desc && desc->action == NULL;
  399. }
  400. static unsigned int startup_pirq(unsigned int irq)
  401. {
  402. struct evtchn_bind_pirq bind_pirq;
  403. struct irq_info *info = info_for_irq(irq);
  404. int evtchn = evtchn_from_irq(irq);
  405. int rc;
  406. BUG_ON(info->type != IRQT_PIRQ);
  407. if (VALID_EVTCHN(evtchn))
  408. goto out;
  409. bind_pirq.pirq = pirq_from_irq(irq);
  410. /* NB. We are happy to share unless we are probing. */
  411. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  412. BIND_PIRQ__WILL_SHARE : 0;
  413. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  414. if (rc != 0) {
  415. if (!probing_irq(irq))
  416. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  417. irq);
  418. return 0;
  419. }
  420. evtchn = bind_pirq.port;
  421. pirq_query_unmask(irq);
  422. evtchn_to_irq[evtchn] = irq;
  423. bind_evtchn_to_cpu(evtchn, 0);
  424. info->evtchn = evtchn;
  425. out:
  426. unmask_evtchn(evtchn);
  427. pirq_unmask_notify(irq);
  428. return 0;
  429. }
  430. static void shutdown_pirq(unsigned int irq)
  431. {
  432. struct evtchn_close close;
  433. struct irq_info *info = info_for_irq(irq);
  434. int evtchn = evtchn_from_irq(irq);
  435. BUG_ON(info->type != IRQT_PIRQ);
  436. if (!VALID_EVTCHN(evtchn))
  437. return;
  438. mask_evtchn(evtchn);
  439. close.port = evtchn;
  440. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  441. BUG();
  442. bind_evtchn_to_cpu(evtchn, 0);
  443. evtchn_to_irq[evtchn] = -1;
  444. info->evtchn = 0;
  445. }
  446. static void enable_pirq(unsigned int irq)
  447. {
  448. startup_pirq(irq);
  449. }
  450. static void disable_pirq(unsigned int irq)
  451. {
  452. }
  453. static void ack_pirq(unsigned int irq)
  454. {
  455. int evtchn = evtchn_from_irq(irq);
  456. move_native_irq(irq);
  457. if (VALID_EVTCHN(evtchn)) {
  458. mask_evtchn(evtchn);
  459. clear_evtchn(evtchn);
  460. }
  461. }
  462. static void end_pirq(unsigned int irq)
  463. {
  464. int evtchn = evtchn_from_irq(irq);
  465. struct irq_desc *desc = irq_to_desc(irq);
  466. if (WARN_ON(!desc))
  467. return;
  468. if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) ==
  469. (IRQ_DISABLED|IRQ_PENDING)) {
  470. shutdown_pirq(irq);
  471. } else if (VALID_EVTCHN(evtchn)) {
  472. unmask_evtchn(evtchn);
  473. pirq_unmask_notify(irq);
  474. }
  475. }
  476. static int find_irq_by_gsi(unsigned gsi)
  477. {
  478. int irq;
  479. for (irq = 0; irq < nr_irqs; irq++) {
  480. struct irq_info *info = info_for_irq(irq);
  481. if (info == NULL || info->type != IRQT_PIRQ)
  482. continue;
  483. if (gsi_from_irq(irq) == gsi)
  484. return irq;
  485. }
  486. return -1;
  487. }
  488. int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
  489. {
  490. return xen_map_pirq_gsi(gsi, gsi, shareable, name);
  491. }
  492. /* xen_map_pirq_gsi might allocate irqs from the top down, as a
  493. * consequence don't assume that the irq number returned has a low value
  494. * or can be used as a pirq number unless you know otherwise.
  495. *
  496. * One notable exception is when xen_map_pirq_gsi is called passing an
  497. * hardware gsi as argument, in that case the irq number returned
  498. * matches the gsi number passed as second argument.
  499. *
  500. * Note: We don't assign an event channel until the irq actually started
  501. * up. Return an existing irq if we've already got one for the gsi.
  502. */
  503. int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
  504. {
  505. int irq = 0;
  506. struct physdev_irq irq_op;
  507. spin_lock(&irq_mapping_update_lock);
  508. if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
  509. printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
  510. pirq > nr_irqs ? "pirq" :"",
  511. gsi > nr_irqs ? "gsi" : "");
  512. goto out;
  513. }
  514. irq = find_irq_by_gsi(gsi);
  515. if (irq != -1) {
  516. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  517. irq, gsi);
  518. goto out; /* XXX need refcount? */
  519. }
  520. irq = xen_allocate_irq_gsi(gsi);
  521. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  522. handle_level_irq, name);
  523. irq_op.irq = irq;
  524. irq_op.vector = 0;
  525. /* Only the privileged domain can do this. For non-priv, the pcifront
  526. * driver provides a PCI bus that does the call to do exactly
  527. * this in the priv domain. */
  528. if (xen_initial_domain() &&
  529. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  530. xen_free_irq(irq);
  531. irq = -ENOSPC;
  532. goto out;
  533. }
  534. irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
  535. irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
  536. pirq_to_irq[pirq] = irq;
  537. out:
  538. spin_unlock(&irq_mapping_update_lock);
  539. return irq;
  540. }
  541. #ifdef CONFIG_PCI_MSI
  542. #include <linux/msi.h>
  543. #include "../pci/msi.h"
  544. static int find_unbound_pirq(int type)
  545. {
  546. int rc, i;
  547. struct physdev_get_free_pirq op_get_free_pirq;
  548. op_get_free_pirq.type = type;
  549. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  550. if (!rc)
  551. return op_get_free_pirq.pirq;
  552. for (i = 0; i < nr_irqs; i++) {
  553. if (pirq_to_irq[i] < 0)
  554. return i;
  555. }
  556. return -1;
  557. }
  558. void xen_allocate_pirq_msi(char *name, int *irq, int *pirq, int alloc)
  559. {
  560. spin_lock(&irq_mapping_update_lock);
  561. if (alloc & XEN_ALLOC_IRQ) {
  562. *irq = xen_allocate_irq_dynamic();
  563. if (*irq == -1)
  564. goto out;
  565. }
  566. if (alloc & XEN_ALLOC_PIRQ) {
  567. *pirq = find_unbound_pirq(MAP_PIRQ_TYPE_MSI);
  568. if (*pirq == -1)
  569. goto out;
  570. }
  571. set_irq_chip_and_handler_name(*irq, &xen_pirq_chip,
  572. handle_level_irq, name);
  573. irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0);
  574. pirq_to_irq[*pirq] = *irq;
  575. out:
  576. spin_unlock(&irq_mapping_update_lock);
  577. }
  578. int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
  579. {
  580. int irq = -1;
  581. struct physdev_map_pirq map_irq;
  582. int rc;
  583. int pos;
  584. u32 table_offset, bir;
  585. memset(&map_irq, 0, sizeof(map_irq));
  586. map_irq.domid = DOMID_SELF;
  587. map_irq.type = MAP_PIRQ_TYPE_MSI;
  588. map_irq.index = -1;
  589. map_irq.pirq = -1;
  590. map_irq.bus = dev->bus->number;
  591. map_irq.devfn = dev->devfn;
  592. if (type == PCI_CAP_ID_MSIX) {
  593. pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  594. pci_read_config_dword(dev, msix_table_offset_reg(pos),
  595. &table_offset);
  596. bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
  597. map_irq.table_base = pci_resource_start(dev, bir);
  598. map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
  599. }
  600. spin_lock(&irq_mapping_update_lock);
  601. irq = xen_allocate_irq_dynamic();
  602. if (irq == -1)
  603. goto out;
  604. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  605. if (rc) {
  606. printk(KERN_WARNING "xen map irq failed %d\n", rc);
  607. xen_free_irq(irq);
  608. irq = -1;
  609. goto out;
  610. }
  611. irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
  612. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  613. handle_level_irq,
  614. (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
  615. out:
  616. spin_unlock(&irq_mapping_update_lock);
  617. return irq;
  618. }
  619. #endif
  620. int xen_destroy_irq(int irq)
  621. {
  622. struct irq_desc *desc;
  623. struct physdev_unmap_pirq unmap_irq;
  624. struct irq_info *info = info_for_irq(irq);
  625. int rc = -ENOENT;
  626. spin_lock(&irq_mapping_update_lock);
  627. desc = irq_to_desc(irq);
  628. if (!desc)
  629. goto out;
  630. if (xen_initial_domain()) {
  631. unmap_irq.pirq = info->u.pirq.pirq;
  632. unmap_irq.domid = DOMID_SELF;
  633. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  634. if (rc) {
  635. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  636. goto out;
  637. }
  638. pirq_to_irq[info->u.pirq.pirq] = -1;
  639. }
  640. irq_info[irq] = mk_unbound_info();
  641. xen_free_irq(irq);
  642. out:
  643. spin_unlock(&irq_mapping_update_lock);
  644. return rc;
  645. }
  646. int xen_vector_from_irq(unsigned irq)
  647. {
  648. return vector_from_irq(irq);
  649. }
  650. int xen_gsi_from_irq(unsigned irq)
  651. {
  652. return gsi_from_irq(irq);
  653. }
  654. int xen_irq_from_pirq(unsigned pirq)
  655. {
  656. return pirq_to_irq[pirq];
  657. }
  658. int bind_evtchn_to_irq(unsigned int evtchn)
  659. {
  660. int irq;
  661. spin_lock(&irq_mapping_update_lock);
  662. irq = evtchn_to_irq[evtchn];
  663. if (irq == -1) {
  664. irq = xen_allocate_irq_dynamic();
  665. set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
  666. handle_fasteoi_irq, "event");
  667. evtchn_to_irq[evtchn] = irq;
  668. irq_info[irq] = mk_evtchn_info(evtchn);
  669. }
  670. spin_unlock(&irq_mapping_update_lock);
  671. return irq;
  672. }
  673. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  674. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  675. {
  676. struct evtchn_bind_ipi bind_ipi;
  677. int evtchn, irq;
  678. spin_lock(&irq_mapping_update_lock);
  679. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  680. if (irq == -1) {
  681. irq = xen_allocate_irq_dynamic();
  682. if (irq < 0)
  683. goto out;
  684. set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
  685. handle_percpu_irq, "ipi");
  686. bind_ipi.vcpu = cpu;
  687. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  688. &bind_ipi) != 0)
  689. BUG();
  690. evtchn = bind_ipi.port;
  691. evtchn_to_irq[evtchn] = irq;
  692. irq_info[irq] = mk_ipi_info(evtchn, ipi);
  693. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  694. bind_evtchn_to_cpu(evtchn, cpu);
  695. }
  696. out:
  697. spin_unlock(&irq_mapping_update_lock);
  698. return irq;
  699. }
  700. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  701. {
  702. struct evtchn_bind_virq bind_virq;
  703. int evtchn, irq;
  704. spin_lock(&irq_mapping_update_lock);
  705. irq = per_cpu(virq_to_irq, cpu)[virq];
  706. if (irq == -1) {
  707. irq = xen_allocate_irq_dynamic();
  708. set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
  709. handle_percpu_irq, "virq");
  710. bind_virq.virq = virq;
  711. bind_virq.vcpu = cpu;
  712. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  713. &bind_virq) != 0)
  714. BUG();
  715. evtchn = bind_virq.port;
  716. evtchn_to_irq[evtchn] = irq;
  717. irq_info[irq] = mk_virq_info(evtchn, virq);
  718. per_cpu(virq_to_irq, cpu)[virq] = irq;
  719. bind_evtchn_to_cpu(evtchn, cpu);
  720. }
  721. spin_unlock(&irq_mapping_update_lock);
  722. return irq;
  723. }
  724. static void unbind_from_irq(unsigned int irq)
  725. {
  726. struct evtchn_close close;
  727. int evtchn = evtchn_from_irq(irq);
  728. spin_lock(&irq_mapping_update_lock);
  729. if (VALID_EVTCHN(evtchn)) {
  730. close.port = evtchn;
  731. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  732. BUG();
  733. switch (type_from_irq(irq)) {
  734. case IRQT_VIRQ:
  735. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  736. [virq_from_irq(irq)] = -1;
  737. break;
  738. case IRQT_IPI:
  739. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  740. [ipi_from_irq(irq)] = -1;
  741. break;
  742. default:
  743. break;
  744. }
  745. /* Closed ports are implicitly re-bound to VCPU0. */
  746. bind_evtchn_to_cpu(evtchn, 0);
  747. evtchn_to_irq[evtchn] = -1;
  748. }
  749. if (irq_info[irq].type != IRQT_UNBOUND) {
  750. irq_info[irq] = mk_unbound_info();
  751. xen_free_irq(irq);
  752. }
  753. spin_unlock(&irq_mapping_update_lock);
  754. }
  755. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  756. irq_handler_t handler,
  757. unsigned long irqflags,
  758. const char *devname, void *dev_id)
  759. {
  760. unsigned int irq;
  761. int retval;
  762. irq = bind_evtchn_to_irq(evtchn);
  763. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  764. if (retval != 0) {
  765. unbind_from_irq(irq);
  766. return retval;
  767. }
  768. return irq;
  769. }
  770. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  771. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  772. irq_handler_t handler,
  773. unsigned long irqflags, const char *devname, void *dev_id)
  774. {
  775. unsigned int irq;
  776. int retval;
  777. irq = bind_virq_to_irq(virq, cpu);
  778. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  779. if (retval != 0) {
  780. unbind_from_irq(irq);
  781. return retval;
  782. }
  783. return irq;
  784. }
  785. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  786. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  787. unsigned int cpu,
  788. irq_handler_t handler,
  789. unsigned long irqflags,
  790. const char *devname,
  791. void *dev_id)
  792. {
  793. int irq, retval;
  794. irq = bind_ipi_to_irq(ipi, cpu);
  795. if (irq < 0)
  796. return irq;
  797. irqflags |= IRQF_NO_SUSPEND;
  798. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  799. if (retval != 0) {
  800. unbind_from_irq(irq);
  801. return retval;
  802. }
  803. return irq;
  804. }
  805. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  806. {
  807. free_irq(irq, dev_id);
  808. unbind_from_irq(irq);
  809. }
  810. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  811. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  812. {
  813. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  814. BUG_ON(irq < 0);
  815. notify_remote_via_irq(irq);
  816. }
  817. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  818. {
  819. struct shared_info *sh = HYPERVISOR_shared_info;
  820. int cpu = smp_processor_id();
  821. unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
  822. int i;
  823. unsigned long flags;
  824. static DEFINE_SPINLOCK(debug_lock);
  825. struct vcpu_info *v;
  826. spin_lock_irqsave(&debug_lock, flags);
  827. printk("\nvcpu %d\n ", cpu);
  828. for_each_online_cpu(i) {
  829. int pending;
  830. v = per_cpu(xen_vcpu, i);
  831. pending = (get_irq_regs() && i == cpu)
  832. ? xen_irqs_disabled(get_irq_regs())
  833. : v->evtchn_upcall_mask;
  834. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  835. pending, v->evtchn_upcall_pending,
  836. (int)(sizeof(v->evtchn_pending_sel)*2),
  837. v->evtchn_pending_sel);
  838. }
  839. v = per_cpu(xen_vcpu, cpu);
  840. printk("\npending:\n ");
  841. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  842. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  843. sh->evtchn_pending[i],
  844. i % 8 == 0 ? "\n " : " ");
  845. printk("\nglobal mask:\n ");
  846. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  847. printk("%0*lx%s",
  848. (int)(sizeof(sh->evtchn_mask[0])*2),
  849. sh->evtchn_mask[i],
  850. i % 8 == 0 ? "\n " : " ");
  851. printk("\nglobally unmasked:\n ");
  852. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  853. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  854. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  855. i % 8 == 0 ? "\n " : " ");
  856. printk("\nlocal cpu%d mask:\n ", cpu);
  857. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  858. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  859. cpu_evtchn[i],
  860. i % 8 == 0 ? "\n " : " ");
  861. printk("\nlocally unmasked:\n ");
  862. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  863. unsigned long pending = sh->evtchn_pending[i]
  864. & ~sh->evtchn_mask[i]
  865. & cpu_evtchn[i];
  866. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  867. pending, i % 8 == 0 ? "\n " : " ");
  868. }
  869. printk("\npending list:\n");
  870. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  871. if (sync_test_bit(i, sh->evtchn_pending)) {
  872. int word_idx = i / BITS_PER_LONG;
  873. printk(" %d: event %d -> irq %d%s%s%s\n",
  874. cpu_from_evtchn(i), i,
  875. evtchn_to_irq[i],
  876. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  877. ? "" : " l2-clear",
  878. !sync_test_bit(i, sh->evtchn_mask)
  879. ? "" : " globally-masked",
  880. sync_test_bit(i, cpu_evtchn)
  881. ? "" : " locally-masked");
  882. }
  883. }
  884. spin_unlock_irqrestore(&debug_lock, flags);
  885. return IRQ_HANDLED;
  886. }
  887. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  888. /*
  889. * Search the CPUs pending events bitmasks. For each one found, map
  890. * the event number to an irq, and feed it into do_IRQ() for
  891. * handling.
  892. *
  893. * Xen uses a two-level bitmap to speed searching. The first level is
  894. * a bitset of words which contain pending event bits. The second
  895. * level is a bitset of pending events themselves.
  896. */
  897. static void __xen_evtchn_do_upcall(void)
  898. {
  899. int cpu = get_cpu();
  900. struct shared_info *s = HYPERVISOR_shared_info;
  901. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  902. unsigned count;
  903. do {
  904. unsigned long pending_words;
  905. vcpu_info->evtchn_upcall_pending = 0;
  906. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  907. goto out;
  908. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  909. /* Clear master flag /before/ clearing selector flag. */
  910. wmb();
  911. #endif
  912. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  913. while (pending_words != 0) {
  914. unsigned long pending_bits;
  915. int word_idx = __ffs(pending_words);
  916. pending_words &= ~(1UL << word_idx);
  917. while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
  918. int bit_idx = __ffs(pending_bits);
  919. int port = (word_idx * BITS_PER_LONG) + bit_idx;
  920. int irq = evtchn_to_irq[port];
  921. struct irq_desc *desc;
  922. mask_evtchn(port);
  923. clear_evtchn(port);
  924. if (irq != -1) {
  925. desc = irq_to_desc(irq);
  926. if (desc)
  927. generic_handle_irq_desc(irq, desc);
  928. }
  929. }
  930. }
  931. BUG_ON(!irqs_disabled());
  932. count = __this_cpu_read(xed_nesting_count);
  933. __this_cpu_write(xed_nesting_count, 0);
  934. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  935. out:
  936. put_cpu();
  937. }
  938. void xen_evtchn_do_upcall(struct pt_regs *regs)
  939. {
  940. struct pt_regs *old_regs = set_irq_regs(regs);
  941. exit_idle();
  942. irq_enter();
  943. __xen_evtchn_do_upcall();
  944. irq_exit();
  945. set_irq_regs(old_regs);
  946. }
  947. void xen_hvm_evtchn_do_upcall(void)
  948. {
  949. __xen_evtchn_do_upcall();
  950. }
  951. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  952. /* Rebind a new event channel to an existing irq. */
  953. void rebind_evtchn_irq(int evtchn, int irq)
  954. {
  955. struct irq_info *info = info_for_irq(irq);
  956. /* Make sure the irq is masked, since the new event channel
  957. will also be masked. */
  958. disable_irq(irq);
  959. spin_lock(&irq_mapping_update_lock);
  960. /* After resume the irq<->evtchn mappings are all cleared out */
  961. BUG_ON(evtchn_to_irq[evtchn] != -1);
  962. /* Expect irq to have been bound before,
  963. so there should be a proper type */
  964. BUG_ON(info->type == IRQT_UNBOUND);
  965. evtchn_to_irq[evtchn] = irq;
  966. irq_info[irq] = mk_evtchn_info(evtchn);
  967. spin_unlock(&irq_mapping_update_lock);
  968. /* new event channels are always bound to cpu 0 */
  969. irq_set_affinity(irq, cpumask_of(0));
  970. /* Unmask the event channel. */
  971. enable_irq(irq);
  972. }
  973. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  974. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  975. {
  976. struct evtchn_bind_vcpu bind_vcpu;
  977. int evtchn = evtchn_from_irq(irq);
  978. /* events delivered via platform PCI interrupts are always
  979. * routed to vcpu 0 */
  980. if (!VALID_EVTCHN(evtchn) ||
  981. (xen_hvm_domain() && !xen_have_vector_callback))
  982. return -1;
  983. /* Send future instances of this interrupt to other vcpu. */
  984. bind_vcpu.port = evtchn;
  985. bind_vcpu.vcpu = tcpu;
  986. /*
  987. * If this fails, it usually just indicates that we're dealing with a
  988. * virq or IPI channel, which don't actually need to be rebound. Ignore
  989. * it, but don't do the xenlinux-level rebind in that case.
  990. */
  991. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  992. bind_evtchn_to_cpu(evtchn, tcpu);
  993. return 0;
  994. }
  995. static int set_affinity_irq(unsigned irq, const struct cpumask *dest)
  996. {
  997. unsigned tcpu = cpumask_first(dest);
  998. return rebind_irq_to_cpu(irq, tcpu);
  999. }
  1000. int resend_irq_on_evtchn(unsigned int irq)
  1001. {
  1002. int masked, evtchn = evtchn_from_irq(irq);
  1003. struct shared_info *s = HYPERVISOR_shared_info;
  1004. if (!VALID_EVTCHN(evtchn))
  1005. return 1;
  1006. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  1007. sync_set_bit(evtchn, s->evtchn_pending);
  1008. if (!masked)
  1009. unmask_evtchn(evtchn);
  1010. return 1;
  1011. }
  1012. static void enable_dynirq(unsigned int irq)
  1013. {
  1014. int evtchn = evtchn_from_irq(irq);
  1015. if (VALID_EVTCHN(evtchn))
  1016. unmask_evtchn(evtchn);
  1017. }
  1018. static void disable_dynirq(unsigned int irq)
  1019. {
  1020. int evtchn = evtchn_from_irq(irq);
  1021. if (VALID_EVTCHN(evtchn))
  1022. mask_evtchn(evtchn);
  1023. }
  1024. static void ack_dynirq(unsigned int irq)
  1025. {
  1026. int evtchn = evtchn_from_irq(irq);
  1027. move_masked_irq(irq);
  1028. if (VALID_EVTCHN(evtchn))
  1029. unmask_evtchn(evtchn);
  1030. }
  1031. static int retrigger_dynirq(unsigned int irq)
  1032. {
  1033. int evtchn = evtchn_from_irq(irq);
  1034. struct shared_info *sh = HYPERVISOR_shared_info;
  1035. int ret = 0;
  1036. if (VALID_EVTCHN(evtchn)) {
  1037. int masked;
  1038. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  1039. sync_set_bit(evtchn, sh->evtchn_pending);
  1040. if (!masked)
  1041. unmask_evtchn(evtchn);
  1042. ret = 1;
  1043. }
  1044. return ret;
  1045. }
  1046. static void restore_cpu_pirqs(void)
  1047. {
  1048. int pirq, rc, irq, gsi;
  1049. struct physdev_map_pirq map_irq;
  1050. for (pirq = 0; pirq < nr_irqs; pirq++) {
  1051. irq = pirq_to_irq[pirq];
  1052. if (irq == -1)
  1053. continue;
  1054. /* save/restore of PT devices doesn't work, so at this point the
  1055. * only devices present are GSI based emulated devices */
  1056. gsi = gsi_from_irq(irq);
  1057. if (!gsi)
  1058. continue;
  1059. map_irq.domid = DOMID_SELF;
  1060. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1061. map_irq.index = gsi;
  1062. map_irq.pirq = pirq;
  1063. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1064. if (rc) {
  1065. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1066. gsi, irq, pirq, rc);
  1067. irq_info[irq] = mk_unbound_info();
  1068. pirq_to_irq[pirq] = -1;
  1069. continue;
  1070. }
  1071. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1072. startup_pirq(irq);
  1073. }
  1074. }
  1075. static void restore_cpu_virqs(unsigned int cpu)
  1076. {
  1077. struct evtchn_bind_virq bind_virq;
  1078. int virq, irq, evtchn;
  1079. for (virq = 0; virq < NR_VIRQS; virq++) {
  1080. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1081. continue;
  1082. BUG_ON(virq_from_irq(irq) != virq);
  1083. /* Get a new binding from Xen. */
  1084. bind_virq.virq = virq;
  1085. bind_virq.vcpu = cpu;
  1086. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1087. &bind_virq) != 0)
  1088. BUG();
  1089. evtchn = bind_virq.port;
  1090. /* Record the new mapping. */
  1091. evtchn_to_irq[evtchn] = irq;
  1092. irq_info[irq] = mk_virq_info(evtchn, virq);
  1093. bind_evtchn_to_cpu(evtchn, cpu);
  1094. }
  1095. }
  1096. static void restore_cpu_ipis(unsigned int cpu)
  1097. {
  1098. struct evtchn_bind_ipi bind_ipi;
  1099. int ipi, irq, evtchn;
  1100. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1101. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1102. continue;
  1103. BUG_ON(ipi_from_irq(irq) != ipi);
  1104. /* Get a new binding from Xen. */
  1105. bind_ipi.vcpu = cpu;
  1106. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1107. &bind_ipi) != 0)
  1108. BUG();
  1109. evtchn = bind_ipi.port;
  1110. /* Record the new mapping. */
  1111. evtchn_to_irq[evtchn] = irq;
  1112. irq_info[irq] = mk_ipi_info(evtchn, ipi);
  1113. bind_evtchn_to_cpu(evtchn, cpu);
  1114. }
  1115. }
  1116. /* Clear an irq's pending state, in preparation for polling on it */
  1117. void xen_clear_irq_pending(int irq)
  1118. {
  1119. int evtchn = evtchn_from_irq(irq);
  1120. if (VALID_EVTCHN(evtchn))
  1121. clear_evtchn(evtchn);
  1122. }
  1123. EXPORT_SYMBOL(xen_clear_irq_pending);
  1124. void xen_set_irq_pending(int irq)
  1125. {
  1126. int evtchn = evtchn_from_irq(irq);
  1127. if (VALID_EVTCHN(evtchn))
  1128. set_evtchn(evtchn);
  1129. }
  1130. bool xen_test_irq_pending(int irq)
  1131. {
  1132. int evtchn = evtchn_from_irq(irq);
  1133. bool ret = false;
  1134. if (VALID_EVTCHN(evtchn))
  1135. ret = test_evtchn(evtchn);
  1136. return ret;
  1137. }
  1138. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1139. * the irq will be disabled so it won't deliver an interrupt. */
  1140. void xen_poll_irq_timeout(int irq, u64 timeout)
  1141. {
  1142. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1143. if (VALID_EVTCHN(evtchn)) {
  1144. struct sched_poll poll;
  1145. poll.nr_ports = 1;
  1146. poll.timeout = timeout;
  1147. set_xen_guest_handle(poll.ports, &evtchn);
  1148. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1149. BUG();
  1150. }
  1151. }
  1152. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1153. /* Poll waiting for an irq to become pending. In the usual case, the
  1154. * irq will be disabled so it won't deliver an interrupt. */
  1155. void xen_poll_irq(int irq)
  1156. {
  1157. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1158. }
  1159. void xen_irq_resume(void)
  1160. {
  1161. unsigned int cpu, irq, evtchn;
  1162. struct irq_desc *desc;
  1163. init_evtchn_cpu_bindings();
  1164. /* New event-channel space is not 'live' yet. */
  1165. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1166. mask_evtchn(evtchn);
  1167. /* No IRQ <-> event-channel mappings. */
  1168. for (irq = 0; irq < nr_irqs; irq++)
  1169. irq_info[irq].evtchn = 0; /* zap event-channel binding */
  1170. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1171. evtchn_to_irq[evtchn] = -1;
  1172. for_each_possible_cpu(cpu) {
  1173. restore_cpu_virqs(cpu);
  1174. restore_cpu_ipis(cpu);
  1175. }
  1176. /*
  1177. * Unmask any IRQF_NO_SUSPEND IRQs which are enabled. These
  1178. * are not handled by the IRQ core.
  1179. */
  1180. for_each_irq_desc(irq, desc) {
  1181. if (!desc->action || !(desc->action->flags & IRQF_NO_SUSPEND))
  1182. continue;
  1183. if (desc->status & IRQ_DISABLED)
  1184. continue;
  1185. evtchn = evtchn_from_irq(irq);
  1186. if (evtchn == -1)
  1187. continue;
  1188. unmask_evtchn(evtchn);
  1189. }
  1190. restore_cpu_pirqs();
  1191. }
  1192. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1193. .name = "xen-dyn",
  1194. .disable = disable_dynirq,
  1195. .mask = disable_dynirq,
  1196. .unmask = enable_dynirq,
  1197. .eoi = ack_dynirq,
  1198. .set_affinity = set_affinity_irq,
  1199. .retrigger = retrigger_dynirq,
  1200. };
  1201. static struct irq_chip xen_pirq_chip __read_mostly = {
  1202. .name = "xen-pirq",
  1203. .startup = startup_pirq,
  1204. .shutdown = shutdown_pirq,
  1205. .enable = enable_pirq,
  1206. .unmask = enable_pirq,
  1207. .disable = disable_pirq,
  1208. .mask = disable_pirq,
  1209. .ack = ack_pirq,
  1210. .end = end_pirq,
  1211. .set_affinity = set_affinity_irq,
  1212. .retrigger = retrigger_dynirq,
  1213. };
  1214. static struct irq_chip xen_percpu_chip __read_mostly = {
  1215. .name = "xen-percpu",
  1216. .disable = disable_dynirq,
  1217. .mask = disable_dynirq,
  1218. .unmask = enable_dynirq,
  1219. .ack = ack_dynirq,
  1220. };
  1221. int xen_set_callback_via(uint64_t via)
  1222. {
  1223. struct xen_hvm_param a;
  1224. a.domid = DOMID_SELF;
  1225. a.index = HVM_PARAM_CALLBACK_IRQ;
  1226. a.value = via;
  1227. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1228. }
  1229. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1230. #ifdef CONFIG_XEN_PVHVM
  1231. /* Vector callbacks are better than PCI interrupts to receive event
  1232. * channel notifications because we can receive vector callbacks on any
  1233. * vcpu and we don't need PCI support or APIC interactions. */
  1234. void xen_callback_vector(void)
  1235. {
  1236. int rc;
  1237. uint64_t callback_via;
  1238. if (xen_have_vector_callback) {
  1239. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1240. rc = xen_set_callback_via(callback_via);
  1241. if (rc) {
  1242. printk(KERN_ERR "Request for Xen HVM callback vector"
  1243. " failed.\n");
  1244. xen_have_vector_callback = 0;
  1245. return;
  1246. }
  1247. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1248. "enabled\n");
  1249. /* in the restore case the vector has already been allocated */
  1250. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1251. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1252. }
  1253. }
  1254. #else
  1255. void xen_callback_vector(void) {}
  1256. #endif
  1257. void __init xen_init_IRQ(void)
  1258. {
  1259. int i;
  1260. cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
  1261. GFP_KERNEL);
  1262. irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
  1263. /* We are using nr_irqs as the maximum number of pirq available but
  1264. * that number is actually chosen by Xen and we don't know exactly
  1265. * what it is. Be careful choosing high pirq numbers. */
  1266. pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
  1267. for (i = 0; i < nr_irqs; i++)
  1268. pirq_to_irq[i] = -1;
  1269. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1270. GFP_KERNEL);
  1271. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1272. evtchn_to_irq[i] = -1;
  1273. init_evtchn_cpu_bindings();
  1274. /* No event channels are 'live' right now. */
  1275. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1276. mask_evtchn(i);
  1277. if (xen_hvm_domain()) {
  1278. xen_callback_vector();
  1279. native_init_IRQ();
  1280. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1281. * __acpi_register_gsi can point at the right function */
  1282. pci_xen_hvm_init();
  1283. } else {
  1284. irq_ctx_init(smp_processor_id());
  1285. if (xen_initial_domain())
  1286. xen_setup_pirqs();
  1287. }
  1288. }