at91sam9n12.dtsi 12 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. #include "skeleton.dtsi"
  10. #include <dt-bindings/pinctrl/at91.h>
  11. #include <dt-bindings/gpio/gpio.h>
  12. / {
  13. model = "Atmel AT91SAM9N12 SoC";
  14. compatible = "atmel,at91sam9n12";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. tcb0 = &tcb0;
  27. tcb1 = &tcb1;
  28. i2c0 = &i2c0;
  29. i2c1 = &i2c1;
  30. ssc0 = &ssc0;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x20000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. };
  56. ramc0: ramc@ffffe800 {
  57. compatible = "atmel,at91sam9g45-ddramc";
  58. reg = <0xffffe800 0x200>;
  59. };
  60. pmc: pmc@fffffc00 {
  61. compatible = "atmel,at91rm9200-pmc";
  62. reg = <0xfffffc00 0x100>;
  63. };
  64. rstc@fffffe00 {
  65. compatible = "atmel,at91sam9g45-rstc";
  66. reg = <0xfffffe00 0x10>;
  67. };
  68. pit: timer@fffffe30 {
  69. compatible = "atmel,at91sam9260-pit";
  70. reg = <0xfffffe30 0xf>;
  71. interrupts = <1 4 7>;
  72. };
  73. shdwc@fffffe10 {
  74. compatible = "atmel,at91sam9x5-shdwc";
  75. reg = <0xfffffe10 0x10>;
  76. };
  77. mmc0: mmc@f0008000 {
  78. compatible = "atmel,hsmci";
  79. reg = <0xf0008000 0x600>;
  80. interrupts = <12 4 0>;
  81. dmas = <&dma 1 0>;
  82. dma-names = "rxtx";
  83. #address-cells = <1>;
  84. #size-cells = <0>;
  85. status = "disabled";
  86. };
  87. tcb0: timer@f8008000 {
  88. compatible = "atmel,at91sam9x5-tcb";
  89. reg = <0xf8008000 0x100>;
  90. interrupts = <17 4 0>;
  91. };
  92. tcb1: timer@f800c000 {
  93. compatible = "atmel,at91sam9x5-tcb";
  94. reg = <0xf800c000 0x100>;
  95. interrupts = <17 4 0>;
  96. };
  97. dma: dma-controller@ffffec00 {
  98. compatible = "atmel,at91sam9g45-dma";
  99. reg = <0xffffec00 0x200>;
  100. interrupts = <20 4 0>;
  101. #dma-cells = <2>;
  102. };
  103. pinctrl@fffff400 {
  104. #address-cells = <1>;
  105. #size-cells = <1>;
  106. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  107. ranges = <0xfffff400 0xfffff400 0x800>;
  108. atmel,mux-mask = <
  109. /* A B C */
  110. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  111. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  112. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  113. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  114. >;
  115. /* shared pinctrl settings */
  116. dbgu {
  117. pinctrl_dbgu: dbgu-0 {
  118. atmel,pins =
  119. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
  120. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
  121. };
  122. };
  123. usart0 {
  124. pinctrl_usart0: usart0-0 {
  125. atmel,pins =
  126. <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
  127. AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
  128. };
  129. pinctrl_usart0_rts: usart0_rts-0 {
  130. atmel,pins =
  131. <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
  132. };
  133. pinctrl_usart0_cts: usart0_cts-0 {
  134. atmel,pins =
  135. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
  136. };
  137. };
  138. usart1 {
  139. pinctrl_usart1: usart1-0 {
  140. atmel,pins =
  141. <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
  142. AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
  143. };
  144. };
  145. usart2 {
  146. pinctrl_usart2: usart2-0 {
  147. atmel,pins =
  148. <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
  149. AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
  150. };
  151. pinctrl_usart2_rts: usart2_rts-0 {
  152. atmel,pins =
  153. <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
  154. };
  155. pinctrl_usart2_cts: usart2_cts-0 {
  156. atmel,pins =
  157. <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
  158. };
  159. };
  160. usart3 {
  161. pinctrl_usart3: usart3-0 {
  162. atmel,pins =
  163. <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
  164. AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
  165. };
  166. pinctrl_usart3_rts: usart3_rts-0 {
  167. atmel,pins =
  168. <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
  169. };
  170. pinctrl_usart3_cts: usart3_cts-0 {
  171. atmel,pins =
  172. <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
  173. };
  174. };
  175. uart0 {
  176. pinctrl_uart0: uart0-0 {
  177. atmel,pins =
  178. <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
  179. AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
  180. };
  181. };
  182. uart1 {
  183. pinctrl_uart1: uart1-0 {
  184. atmel,pins =
  185. <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
  186. AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
  187. };
  188. };
  189. nand {
  190. pinctrl_nand: nand-0 {
  191. atmel,pins =
  192. <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
  193. AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
  194. };
  195. };
  196. mmc0 {
  197. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  198. atmel,pins =
  199. <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  200. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
  201. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
  202. };
  203. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  204. atmel,pins =
  205. <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
  206. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
  207. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
  208. };
  209. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  210. atmel,pins =
  211. <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
  212. AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
  213. AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
  214. AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
  215. };
  216. };
  217. ssc0 {
  218. pinctrl_ssc0_tx: ssc0_tx-0 {
  219. atmel,pins =
  220. <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
  221. AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
  222. AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
  223. };
  224. pinctrl_ssc0_rx: ssc0_rx-0 {
  225. atmel,pins =
  226. <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  227. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  228. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
  229. };
  230. };
  231. spi0 {
  232. pinctrl_spi0: spi0-0 {
  233. atmel,pins =
  234. <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
  235. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
  236. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
  237. };
  238. };
  239. spi1 {
  240. pinctrl_spi1: spi1-0 {
  241. atmel,pins =
  242. <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
  243. AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
  244. AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
  245. };
  246. };
  247. pioA: gpio@fffff400 {
  248. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  249. reg = <0xfffff400 0x200>;
  250. interrupts = <2 4 1>;
  251. #gpio-cells = <2>;
  252. gpio-controller;
  253. interrupt-controller;
  254. #interrupt-cells = <2>;
  255. };
  256. pioB: gpio@fffff600 {
  257. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  258. reg = <0xfffff600 0x200>;
  259. interrupts = <2 4 1>;
  260. #gpio-cells = <2>;
  261. gpio-controller;
  262. interrupt-controller;
  263. #interrupt-cells = <2>;
  264. };
  265. pioC: gpio@fffff800 {
  266. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  267. reg = <0xfffff800 0x200>;
  268. interrupts = <3 4 1>;
  269. #gpio-cells = <2>;
  270. gpio-controller;
  271. interrupt-controller;
  272. #interrupt-cells = <2>;
  273. };
  274. pioD: gpio@fffffa00 {
  275. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  276. reg = <0xfffffa00 0x200>;
  277. interrupts = <3 4 1>;
  278. #gpio-cells = <2>;
  279. gpio-controller;
  280. interrupt-controller;
  281. #interrupt-cells = <2>;
  282. };
  283. };
  284. dbgu: serial@fffff200 {
  285. compatible = "atmel,at91sam9260-usart";
  286. reg = <0xfffff200 0x200>;
  287. interrupts = <1 4 7>;
  288. pinctrl-names = "default";
  289. pinctrl-0 = <&pinctrl_dbgu>;
  290. status = "disabled";
  291. };
  292. ssc0: ssc@f0010000 {
  293. compatible = "atmel,at91sam9g45-ssc";
  294. reg = <0xf0010000 0x4000>;
  295. interrupts = <28 4 5>;
  296. pinctrl-names = "default";
  297. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  298. status = "disabled";
  299. };
  300. usart0: serial@f801c000 {
  301. compatible = "atmel,at91sam9260-usart";
  302. reg = <0xf801c000 0x4000>;
  303. interrupts = <5 4 5>;
  304. pinctrl-names = "default";
  305. pinctrl-0 = <&pinctrl_usart0>;
  306. status = "disabled";
  307. };
  308. usart1: serial@f8020000 {
  309. compatible = "atmel,at91sam9260-usart";
  310. reg = <0xf8020000 0x4000>;
  311. interrupts = <6 4 5>;
  312. pinctrl-names = "default";
  313. pinctrl-0 = <&pinctrl_usart1>;
  314. status = "disabled";
  315. };
  316. usart2: serial@f8024000 {
  317. compatible = "atmel,at91sam9260-usart";
  318. reg = <0xf8024000 0x4000>;
  319. interrupts = <7 4 5>;
  320. pinctrl-names = "default";
  321. pinctrl-0 = <&pinctrl_usart2>;
  322. status = "disabled";
  323. };
  324. usart3: serial@f8028000 {
  325. compatible = "atmel,at91sam9260-usart";
  326. reg = <0xf8028000 0x4000>;
  327. interrupts = <8 4 5>;
  328. pinctrl-names = "default";
  329. pinctrl-0 = <&pinctrl_usart3>;
  330. status = "disabled";
  331. };
  332. i2c0: i2c@f8010000 {
  333. compatible = "atmel,at91sam9x5-i2c";
  334. reg = <0xf8010000 0x100>;
  335. interrupts = <9 4 6>;
  336. dmas = <&dma 1 13>,
  337. <&dma 1 14>;
  338. dma-names = "tx", "rx";
  339. #address-cells = <1>;
  340. #size-cells = <0>;
  341. status = "disabled";
  342. };
  343. i2c1: i2c@f8014000 {
  344. compatible = "atmel,at91sam9x5-i2c";
  345. reg = <0xf8014000 0x100>;
  346. interrupts = <10 4 6>;
  347. dmas = <&dma 1 15>,
  348. <&dma 1 16>;
  349. dma-names = "tx", "rx";
  350. #address-cells = <1>;
  351. #size-cells = <0>;
  352. status = "disabled";
  353. };
  354. spi0: spi@f0000000 {
  355. #address-cells = <1>;
  356. #size-cells = <0>;
  357. compatible = "atmel,at91rm9200-spi";
  358. reg = <0xf0000000 0x100>;
  359. interrupts = <13 4 3>;
  360. pinctrl-names = "default";
  361. pinctrl-0 = <&pinctrl_spi0>;
  362. status = "disabled";
  363. };
  364. spi1: spi@f0004000 {
  365. #address-cells = <1>;
  366. #size-cells = <0>;
  367. compatible = "atmel,at91rm9200-spi";
  368. reg = <0xf0004000 0x100>;
  369. interrupts = <14 4 3>;
  370. pinctrl-names = "default";
  371. pinctrl-0 = <&pinctrl_spi1>;
  372. status = "disabled";
  373. };
  374. };
  375. nand0: nand@40000000 {
  376. compatible = "atmel,at91rm9200-nand";
  377. #address-cells = <1>;
  378. #size-cells = <1>;
  379. reg = < 0x40000000 0x10000000
  380. 0xffffe000 0x00000600
  381. 0xffffe600 0x00000200
  382. 0x00108000 0x00018000
  383. >;
  384. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  385. atmel,nand-addr-offset = <21>;
  386. atmel,nand-cmd-offset = <22>;
  387. pinctrl-names = "default";
  388. pinctrl-0 = <&pinctrl_nand>;
  389. gpios = <&pioD 5 GPIO_ACTIVE_HIGH
  390. &pioD 4 GPIO_ACTIVE_HIGH
  391. 0
  392. >;
  393. status = "disabled";
  394. };
  395. usb0: ohci@00500000 {
  396. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  397. reg = <0x00500000 0x00100000>;
  398. interrupts = <22 4 2>;
  399. status = "disabled";
  400. };
  401. };
  402. i2c@0 {
  403. compatible = "i2c-gpio";
  404. gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
  405. &pioA 31 GPIO_ACTIVE_HIGH /* scl */
  406. >;
  407. i2c-gpio,sda-open-drain;
  408. i2c-gpio,scl-open-drain;
  409. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  410. #address-cells = <1>;
  411. #size-cells = <0>;
  412. status = "disabled";
  413. };
  414. };