at91sam9g45.dtsi 17 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. #include "skeleton.dtsi"
  12. #include <dt-bindings/pinctrl/at91.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. / {
  15. model = "Atmel AT91SAM9G45 family SoC";
  16. compatible = "atmel,at91sam9g45";
  17. interrupt-parent = <&aic>;
  18. aliases {
  19. serial0 = &dbgu;
  20. serial1 = &usart0;
  21. serial2 = &usart1;
  22. serial3 = &usart2;
  23. serial4 = &usart3;
  24. gpio0 = &pioA;
  25. gpio1 = &pioB;
  26. gpio2 = &pioC;
  27. gpio3 = &pioD;
  28. gpio4 = &pioE;
  29. tcb0 = &tcb0;
  30. tcb1 = &tcb1;
  31. i2c0 = &i2c0;
  32. i2c1 = &i2c1;
  33. ssc0 = &ssc0;
  34. ssc1 = &ssc1;
  35. };
  36. cpus {
  37. cpu@0 {
  38. compatible = "arm,arm926ejs";
  39. };
  40. };
  41. memory {
  42. reg = <0x70000000 0x10000000>;
  43. };
  44. ahb {
  45. compatible = "simple-bus";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. ranges;
  49. apb {
  50. compatible = "simple-bus";
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. ranges;
  54. aic: interrupt-controller@fffff000 {
  55. #interrupt-cells = <3>;
  56. compatible = "atmel,at91rm9200-aic";
  57. interrupt-controller;
  58. reg = <0xfffff000 0x200>;
  59. atmel,external-irqs = <31>;
  60. };
  61. ramc0: ramc@ffffe400 {
  62. compatible = "atmel,at91sam9g45-ddramc";
  63. reg = <0xffffe400 0x200
  64. 0xffffe600 0x200>;
  65. };
  66. pmc: pmc@fffffc00 {
  67. compatible = "atmel,at91rm9200-pmc";
  68. reg = <0xfffffc00 0x100>;
  69. };
  70. rstc@fffffd00 {
  71. compatible = "atmel,at91sam9g45-rstc";
  72. reg = <0xfffffd00 0x10>;
  73. };
  74. pit: timer@fffffd30 {
  75. compatible = "atmel,at91sam9260-pit";
  76. reg = <0xfffffd30 0xf>;
  77. interrupts = <1 4 7>;
  78. };
  79. shdwc@fffffd10 {
  80. compatible = "atmel,at91sam9rl-shdwc";
  81. reg = <0xfffffd10 0x10>;
  82. };
  83. tcb0: timer@fff7c000 {
  84. compatible = "atmel,at91rm9200-tcb";
  85. reg = <0xfff7c000 0x100>;
  86. interrupts = <18 4 0>;
  87. };
  88. tcb1: timer@fffd4000 {
  89. compatible = "atmel,at91rm9200-tcb";
  90. reg = <0xfffd4000 0x100>;
  91. interrupts = <18 4 0>;
  92. };
  93. dma: dma-controller@ffffec00 {
  94. compatible = "atmel,at91sam9g45-dma";
  95. reg = <0xffffec00 0x200>;
  96. interrupts = <21 4 0>;
  97. #dma-cells = <2>;
  98. };
  99. pinctrl@fffff200 {
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  103. ranges = <0xfffff200 0xfffff200 0xa00>;
  104. atmel,mux-mask = <
  105. /* A B */
  106. 0xffffffff 0xffc003ff /* pioA */
  107. 0xffffffff 0x800f8f00 /* pioB */
  108. 0xffffffff 0x00000e00 /* pioC */
  109. 0xffffffff 0xff0c1381 /* pioD */
  110. 0xffffffff 0x81ffff81 /* pioE */
  111. >;
  112. /* shared pinctrl settings */
  113. dbgu {
  114. pinctrl_dbgu: dbgu-0 {
  115. atmel,pins =
  116. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
  117. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
  118. };
  119. };
  120. usart0 {
  121. pinctrl_usart0: usart0-0 {
  122. atmel,pins =
  123. <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
  124. AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
  125. };
  126. pinctrl_usart0_rts: usart0_rts-0 {
  127. atmel,pins =
  128. <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
  129. };
  130. pinctrl_usart0_cts: usart0_cts-0 {
  131. atmel,pins =
  132. <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
  133. };
  134. };
  135. uart1 {
  136. pinctrl_usart1: usart1-0 {
  137. atmel,pins =
  138. <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
  139. AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
  140. };
  141. pinctrl_usart1_rts: usart1_rts-0 {
  142. atmel,pins =
  143. <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
  144. };
  145. pinctrl_usart1_cts: usart1_cts-0 {
  146. atmel,pins =
  147. <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
  148. };
  149. };
  150. usart2 {
  151. pinctrl_usart2: usart2-0 {
  152. atmel,pins =
  153. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
  154. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
  155. };
  156. pinctrl_usart2_rts: usart2_rts-0 {
  157. atmel,pins =
  158. <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
  159. };
  160. pinctrl_usart2_cts: usart2_cts-0 {
  161. atmel,pins =
  162. <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
  163. };
  164. };
  165. usart3 {
  166. pinctrl_usart3: usart3-0 {
  167. atmel,pins =
  168. <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
  169. AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
  170. };
  171. pinctrl_usart3_rts: usart3_rts-0 {
  172. atmel,pins =
  173. <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
  174. };
  175. pinctrl_usart3_cts: usart3_cts-0 {
  176. atmel,pins =
  177. <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
  178. };
  179. };
  180. nand {
  181. pinctrl_nand: nand-0 {
  182. atmel,pins =
  183. <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
  184. AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
  185. };
  186. };
  187. macb {
  188. pinctrl_macb_rmii: macb_rmii-0 {
  189. atmel,pins =
  190. <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
  191. AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
  192. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
  193. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
  194. AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
  195. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
  196. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
  197. AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  198. AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
  199. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
  200. };
  201. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  202. atmel,pins =
  203. <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
  204. AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
  205. AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
  206. AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
  207. AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  208. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  209. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
  210. AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
  211. };
  212. };
  213. mmc0 {
  214. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  215. atmel,pins =
  216. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
  217. AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
  218. AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
  219. };
  220. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  221. atmel,pins =
  222. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
  223. AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
  224. AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
  225. };
  226. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  227. atmel,pins =
  228. <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
  229. AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
  230. AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
  231. AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
  232. };
  233. };
  234. mmc1 {
  235. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  236. atmel,pins =
  237. <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
  238. AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
  239. AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
  240. };
  241. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  242. atmel,pins =
  243. <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
  244. AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
  245. AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
  246. };
  247. pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
  248. atmel,pins =
  249. <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
  250. AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
  251. AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
  252. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
  253. };
  254. };
  255. ssc0 {
  256. pinctrl_ssc0_tx: ssc0_tx-0 {
  257. atmel,pins =
  258. <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
  259. AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
  260. AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
  261. };
  262. pinctrl_ssc0_rx: ssc0_rx-0 {
  263. atmel,pins =
  264. <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
  265. AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
  266. AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
  267. };
  268. };
  269. ssc1 {
  270. pinctrl_ssc1_tx: ssc1_tx-0 {
  271. atmel,pins =
  272. <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
  273. AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
  274. AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
  275. };
  276. pinctrl_ssc1_rx: ssc1_rx-0 {
  277. atmel,pins =
  278. <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
  279. AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
  280. AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
  281. };
  282. };
  283. spi0 {
  284. pinctrl_spi0: spi0-0 {
  285. atmel,pins =
  286. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
  287. AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
  288. AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
  289. };
  290. };
  291. spi1 {
  292. pinctrl_spi1: spi1-0 {
  293. atmel,pins =
  294. <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
  295. AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
  296. AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
  297. };
  298. };
  299. pioA: gpio@fffff200 {
  300. compatible = "atmel,at91rm9200-gpio";
  301. reg = <0xfffff200 0x200>;
  302. interrupts = <2 4 1>;
  303. #gpio-cells = <2>;
  304. gpio-controller;
  305. interrupt-controller;
  306. #interrupt-cells = <2>;
  307. };
  308. pioB: gpio@fffff400 {
  309. compatible = "atmel,at91rm9200-gpio";
  310. reg = <0xfffff400 0x200>;
  311. interrupts = <3 4 1>;
  312. #gpio-cells = <2>;
  313. gpio-controller;
  314. interrupt-controller;
  315. #interrupt-cells = <2>;
  316. };
  317. pioC: gpio@fffff600 {
  318. compatible = "atmel,at91rm9200-gpio";
  319. reg = <0xfffff600 0x200>;
  320. interrupts = <4 4 1>;
  321. #gpio-cells = <2>;
  322. gpio-controller;
  323. interrupt-controller;
  324. #interrupt-cells = <2>;
  325. };
  326. pioD: gpio@fffff800 {
  327. compatible = "atmel,at91rm9200-gpio";
  328. reg = <0xfffff800 0x200>;
  329. interrupts = <5 4 1>;
  330. #gpio-cells = <2>;
  331. gpio-controller;
  332. interrupt-controller;
  333. #interrupt-cells = <2>;
  334. };
  335. pioE: gpio@fffffa00 {
  336. compatible = "atmel,at91rm9200-gpio";
  337. reg = <0xfffffa00 0x200>;
  338. interrupts = <5 4 1>;
  339. #gpio-cells = <2>;
  340. gpio-controller;
  341. interrupt-controller;
  342. #interrupt-cells = <2>;
  343. };
  344. };
  345. dbgu: serial@ffffee00 {
  346. compatible = "atmel,at91sam9260-usart";
  347. reg = <0xffffee00 0x200>;
  348. interrupts = <1 4 7>;
  349. pinctrl-names = "default";
  350. pinctrl-0 = <&pinctrl_dbgu>;
  351. status = "disabled";
  352. };
  353. usart0: serial@fff8c000 {
  354. compatible = "atmel,at91sam9260-usart";
  355. reg = <0xfff8c000 0x200>;
  356. interrupts = <7 4 5>;
  357. atmel,use-dma-rx;
  358. atmel,use-dma-tx;
  359. pinctrl-names = "default";
  360. pinctrl-0 = <&pinctrl_usart0>;
  361. status = "disabled";
  362. };
  363. usart1: serial@fff90000 {
  364. compatible = "atmel,at91sam9260-usart";
  365. reg = <0xfff90000 0x200>;
  366. interrupts = <8 4 5>;
  367. atmel,use-dma-rx;
  368. atmel,use-dma-tx;
  369. pinctrl-names = "default";
  370. pinctrl-0 = <&pinctrl_usart1>;
  371. status = "disabled";
  372. };
  373. usart2: serial@fff94000 {
  374. compatible = "atmel,at91sam9260-usart";
  375. reg = <0xfff94000 0x200>;
  376. interrupts = <9 4 5>;
  377. atmel,use-dma-rx;
  378. atmel,use-dma-tx;
  379. pinctrl-names = "default";
  380. pinctrl-0 = <&pinctrl_usart2>;
  381. status = "disabled";
  382. };
  383. usart3: serial@fff98000 {
  384. compatible = "atmel,at91sam9260-usart";
  385. reg = <0xfff98000 0x200>;
  386. interrupts = <10 4 5>;
  387. atmel,use-dma-rx;
  388. atmel,use-dma-tx;
  389. pinctrl-names = "default";
  390. pinctrl-0 = <&pinctrl_usart3>;
  391. status = "disabled";
  392. };
  393. macb0: ethernet@fffbc000 {
  394. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  395. reg = <0xfffbc000 0x100>;
  396. interrupts = <25 4 3>;
  397. pinctrl-names = "default";
  398. pinctrl-0 = <&pinctrl_macb_rmii>;
  399. status = "disabled";
  400. };
  401. i2c0: i2c@fff84000 {
  402. compatible = "atmel,at91sam9g10-i2c";
  403. reg = <0xfff84000 0x100>;
  404. interrupts = <12 4 6>;
  405. #address-cells = <1>;
  406. #size-cells = <0>;
  407. status = "disabled";
  408. };
  409. i2c1: i2c@fff88000 {
  410. compatible = "atmel,at91sam9g10-i2c";
  411. reg = <0xfff88000 0x100>;
  412. interrupts = <13 4 6>;
  413. #address-cells = <1>;
  414. #size-cells = <0>;
  415. status = "disabled";
  416. };
  417. ssc0: ssc@fff9c000 {
  418. compatible = "atmel,at91sam9g45-ssc";
  419. reg = <0xfff9c000 0x4000>;
  420. interrupts = <16 4 5>;
  421. pinctrl-names = "default";
  422. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  423. status = "disabled";
  424. };
  425. ssc1: ssc@fffa0000 {
  426. compatible = "atmel,at91sam9g45-ssc";
  427. reg = <0xfffa0000 0x4000>;
  428. interrupts = <17 4 5>;
  429. pinctrl-names = "default";
  430. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  431. status = "disabled";
  432. };
  433. adc0: adc@fffb0000 {
  434. compatible = "atmel,at91sam9260-adc";
  435. reg = <0xfffb0000 0x100>;
  436. interrupts = <20 4 0>;
  437. atmel,adc-use-external-triggers;
  438. atmel,adc-channels-used = <0xff>;
  439. atmel,adc-vref = <3300>;
  440. atmel,adc-num-channels = <8>;
  441. atmel,adc-startup-time = <40>;
  442. atmel,adc-channel-base = <0x30>;
  443. atmel,adc-drdy-mask = <0x10000>;
  444. atmel,adc-status-register = <0x1c>;
  445. atmel,adc-trigger-register = <0x08>;
  446. atmel,adc-res = <8 10>;
  447. atmel,adc-res-names = "lowres", "highres";
  448. atmel,adc-use-res = "highres";
  449. trigger@0 {
  450. trigger-name = "external-rising";
  451. trigger-value = <0x1>;
  452. trigger-external;
  453. };
  454. trigger@1 {
  455. trigger-name = "external-falling";
  456. trigger-value = <0x2>;
  457. trigger-external;
  458. };
  459. trigger@2 {
  460. trigger-name = "external-any";
  461. trigger-value = <0x3>;
  462. trigger-external;
  463. };
  464. trigger@3 {
  465. trigger-name = "continuous";
  466. trigger-value = <0x6>;
  467. };
  468. };
  469. mmc0: mmc@fff80000 {
  470. compatible = "atmel,hsmci";
  471. reg = <0xfff80000 0x600>;
  472. interrupts = <11 4 0>;
  473. dmas = <&dma 1 0>;
  474. dma-names = "rxtx";
  475. #address-cells = <1>;
  476. #size-cells = <0>;
  477. status = "disabled";
  478. };
  479. mmc1: mmc@fffd0000 {
  480. compatible = "atmel,hsmci";
  481. reg = <0xfffd0000 0x600>;
  482. interrupts = <29 4 0>;
  483. dmas = <&dma 1 13>;
  484. dma-names = "rxtx";
  485. #address-cells = <1>;
  486. #size-cells = <0>;
  487. status = "disabled";
  488. };
  489. watchdog@fffffd40 {
  490. compatible = "atmel,at91sam9260-wdt";
  491. reg = <0xfffffd40 0x10>;
  492. status = "disabled";
  493. };
  494. spi0: spi@fffa4000 {
  495. #address-cells = <1>;
  496. #size-cells = <0>;
  497. compatible = "atmel,at91rm9200-spi";
  498. reg = <0xfffa4000 0x200>;
  499. interrupts = <14 4 3>;
  500. pinctrl-names = "default";
  501. pinctrl-0 = <&pinctrl_spi0>;
  502. status = "disabled";
  503. };
  504. spi1: spi@fffa8000 {
  505. #address-cells = <1>;
  506. #size-cells = <0>;
  507. compatible = "atmel,at91rm9200-spi";
  508. reg = <0xfffa8000 0x200>;
  509. interrupts = <15 4 3>;
  510. pinctrl-names = "default";
  511. pinctrl-0 = <&pinctrl_spi1>;
  512. status = "disabled";
  513. };
  514. };
  515. nand0: nand@40000000 {
  516. compatible = "atmel,at91rm9200-nand";
  517. #address-cells = <1>;
  518. #size-cells = <1>;
  519. reg = <0x40000000 0x10000000
  520. 0xffffe200 0x200
  521. >;
  522. atmel,nand-addr-offset = <21>;
  523. atmel,nand-cmd-offset = <22>;
  524. pinctrl-names = "default";
  525. pinctrl-0 = <&pinctrl_nand>;
  526. gpios = <&pioC 8 GPIO_ACTIVE_HIGH
  527. &pioC 14 GPIO_ACTIVE_HIGH
  528. 0
  529. >;
  530. status = "disabled";
  531. };
  532. usb0: ohci@00700000 {
  533. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  534. reg = <0x00700000 0x100000>;
  535. interrupts = <22 4 2>;
  536. status = "disabled";
  537. };
  538. usb1: ehci@00800000 {
  539. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  540. reg = <0x00800000 0x100000>;
  541. interrupts = <22 4 2>;
  542. status = "disabled";
  543. };
  544. };
  545. i2c@0 {
  546. compatible = "i2c-gpio";
  547. gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
  548. &pioA 21 GPIO_ACTIVE_HIGH /* scl */
  549. >;
  550. i2c-gpio,sda-open-drain;
  551. i2c-gpio,scl-open-drain;
  552. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  553. #address-cells = <1>;
  554. #size-cells = <0>;
  555. status = "disabled";
  556. };
  557. };