at91rm9200.dtsi 15 KB

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  1. /*
  2. * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2012 Joachim Eastwood <manabian@gmail.com>
  7. *
  8. * Based on at91sam9260.dtsi
  9. *
  10. * Licensed under GPLv2 or later.
  11. */
  12. #include "skeleton.dtsi"
  13. #include <dt-bindings/pinctrl/at91.h>
  14. #include <dt-bindings/gpio/gpio.h>
  15. / {
  16. model = "Atmel AT91RM9200 family SoC";
  17. compatible = "atmel,at91rm9200";
  18. interrupt-parent = <&aic>;
  19. aliases {
  20. serial0 = &dbgu;
  21. serial1 = &usart0;
  22. serial2 = &usart1;
  23. serial3 = &usart2;
  24. serial4 = &usart3;
  25. gpio0 = &pioA;
  26. gpio1 = &pioB;
  27. gpio2 = &pioC;
  28. gpio3 = &pioD;
  29. tcb0 = &tcb0;
  30. tcb1 = &tcb1;
  31. i2c0 = &i2c0;
  32. ssc0 = &ssc0;
  33. ssc1 = &ssc1;
  34. ssc2 = &ssc2;
  35. };
  36. cpus {
  37. cpu@0 {
  38. compatible = "arm,arm920t";
  39. };
  40. };
  41. memory {
  42. reg = <0x20000000 0x04000000>;
  43. };
  44. ahb {
  45. compatible = "simple-bus";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. ranges;
  49. apb {
  50. compatible = "simple-bus";
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. ranges;
  54. aic: interrupt-controller@fffff000 {
  55. #interrupt-cells = <3>;
  56. compatible = "atmel,at91rm9200-aic";
  57. interrupt-controller;
  58. reg = <0xfffff000 0x200>;
  59. atmel,external-irqs = <25 26 27 28 29 30 31>;
  60. };
  61. ramc0: ramc@ffffff00 {
  62. compatible = "atmel,at91rm9200-sdramc";
  63. reg = <0xffffff00 0x100>;
  64. };
  65. pmc: pmc@fffffc00 {
  66. compatible = "atmel,at91rm9200-pmc";
  67. reg = <0xfffffc00 0x100>;
  68. };
  69. st: timer@fffffd00 {
  70. compatible = "atmel,at91rm9200-st";
  71. reg = <0xfffffd00 0x100>;
  72. interrupts = <1 4 7>;
  73. };
  74. tcb0: timer@fffa0000 {
  75. compatible = "atmel,at91rm9200-tcb";
  76. reg = <0xfffa0000 0x100>;
  77. interrupts = <17 4 0 18 4 0 19 4 0>;
  78. };
  79. tcb1: timer@fffa4000 {
  80. compatible = "atmel,at91rm9200-tcb";
  81. reg = <0xfffa4000 0x100>;
  82. interrupts = <20 4 0 21 4 0 22 4 0>;
  83. };
  84. i2c0: i2c@fffb8000 {
  85. compatible = "atmel,at91rm9200-i2c";
  86. reg = <0xfffb8000 0x4000>;
  87. interrupts = <12 4 6>;
  88. pinctrl-names = "default";
  89. pinctrl-0 = <&pinctrl_twi>;
  90. #address-cells = <1>;
  91. #size-cells = <0>;
  92. status = "disabled";
  93. };
  94. mmc0: mmc@fffb4000 {
  95. compatible = "atmel,hsmci";
  96. reg = <0xfffb4000 0x4000>;
  97. interrupts = <10 4 0>;
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. status = "disabled";
  101. };
  102. ssc0: ssc@fffd0000 {
  103. compatible = "atmel,at91rm9200-ssc";
  104. reg = <0xfffd0000 0x4000>;
  105. interrupts = <14 4 5>;
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  108. status = "disable";
  109. };
  110. ssc1: ssc@fffd4000 {
  111. compatible = "atmel,at91rm9200-ssc";
  112. reg = <0xfffd4000 0x4000>;
  113. interrupts = <15 4 5>;
  114. pinctrl-names = "default";
  115. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  116. status = "disable";
  117. };
  118. ssc2: ssc@fffd8000 {
  119. compatible = "atmel,at91rm9200-ssc";
  120. reg = <0xfffd8000 0x4000>;
  121. interrupts = <16 4 5>;
  122. pinctrl-names = "default";
  123. pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
  124. status = "disable";
  125. };
  126. macb0: ethernet@fffbc000 {
  127. compatible = "cdns,at91rm9200-emac", "cdns,emac";
  128. reg = <0xfffbc000 0x4000>;
  129. interrupts = <24 4 3>;
  130. phy-mode = "rmii";
  131. pinctrl-names = "default";
  132. pinctrl-0 = <&pinctrl_macb_rmii>;
  133. status = "disabled";
  134. };
  135. pinctrl@fffff400 {
  136. #address-cells = <1>;
  137. #size-cells = <1>;
  138. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  139. ranges = <0xfffff400 0xfffff400 0x800>;
  140. atmel,mux-mask = <
  141. /* A B */
  142. 0xffffffff 0xffffffff /* pioA */
  143. 0xffffffff 0x083fffff /* pioB */
  144. 0xffff3fff 0x00000000 /* pioC */
  145. 0x03ff87ff 0x0fffff80 /* pioD */
  146. >;
  147. /* shared pinctrl settings */
  148. dbgu {
  149. pinctrl_dbgu: dbgu-0 {
  150. atmel,pins =
  151. <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */
  152. AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */
  153. };
  154. };
  155. uart0 {
  156. pinctrl_uart0: uart0-0 {
  157. atmel,pins =
  158. <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  159. AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
  160. };
  161. pinctrl_uart0_rts: uart0_rts-0 {
  162. atmel,pins =
  163. <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
  164. };
  165. pinctrl_uart0_cts: uart0_cts-0 {
  166. atmel,pins =
  167. <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
  168. };
  169. };
  170. uart1 {
  171. pinctrl_uart1: uart1-0 {
  172. atmel,pins =
  173. <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */
  174. AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
  175. };
  176. pinctrl_uart1_rts: uart1_rts-0 {
  177. atmel,pins =
  178. <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */
  179. };
  180. pinctrl_uart1_cts: uart1_cts-0 {
  181. atmel,pins =
  182. <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
  183. };
  184. pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
  185. atmel,pins =
  186. <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
  187. AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
  188. };
  189. pinctrl_uart1_dcd: uart1_dcd-0 {
  190. atmel,pins =
  191. <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
  192. };
  193. pinctrl_uart1_ri: uart1_ri-0 {
  194. atmel,pins =
  195. <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
  196. };
  197. };
  198. uart2 {
  199. pinctrl_uart2: uart2-0 {
  200. atmel,pins =
  201. <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */
  202. AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
  203. };
  204. pinctrl_uart2_rts: uart2_rts-0 {
  205. atmel,pins =
  206. <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
  207. };
  208. pinctrl_uart2_cts: uart2_cts-0 {
  209. atmel,pins =
  210. <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */
  211. };
  212. };
  213. uart3 {
  214. pinctrl_uart3: uart3-0 {
  215. atmel,pins =
  216. <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
  217. AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */
  218. };
  219. pinctrl_uart3_rts: uart3_rts-0 {
  220. atmel,pins =
  221. <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
  222. };
  223. pinctrl_uart3_cts: uart3_cts-0 {
  224. atmel,pins =
  225. <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
  226. };
  227. };
  228. nand {
  229. pinctrl_nand: nand-0 {
  230. atmel,pins =
  231. <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */
  232. AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */
  233. };
  234. };
  235. macb {
  236. pinctrl_macb_rmii: macb_rmii-0 {
  237. atmel,pins =
  238. <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */
  239. AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */
  240. AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
  241. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
  242. AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
  243. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
  244. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
  245. AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
  246. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
  247. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */
  248. };
  249. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  250. atmel,pins =
  251. <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */
  252. AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */
  253. AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */
  254. AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */
  255. AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */
  256. AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */
  257. AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */
  258. AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */
  259. };
  260. };
  261. mmc0 {
  262. pinctrl_mmc0_clk: mmc0_clk-0 {
  263. atmel,pins =
  264. <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
  265. };
  266. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  267. atmel,pins =
  268. <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
  269. AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */
  270. };
  271. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  272. atmel,pins =
  273. <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */
  274. AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */
  275. AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */
  276. };
  277. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  278. atmel,pins =
  279. <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */
  280. AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */
  281. };
  282. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  283. atmel,pins =
  284. <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */
  285. AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
  286. AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */
  287. };
  288. };
  289. ssc0 {
  290. pinctrl_ssc0_tx: ssc0_tx-0 {
  291. atmel,pins =
  292. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
  293. AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
  294. AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */
  295. };
  296. pinctrl_ssc0_rx: ssc0_rx-0 {
  297. atmel,pins =
  298. <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
  299. AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
  300. AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
  301. };
  302. };
  303. ssc1 {
  304. pinctrl_ssc1_tx: ssc1_tx-0 {
  305. atmel,pins =
  306. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
  307. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
  308. AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
  309. };
  310. pinctrl_ssc1_rx: ssc1_rx-0 {
  311. atmel,pins =
  312. <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
  313. AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
  314. AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
  315. };
  316. };
  317. ssc2 {
  318. pinctrl_ssc2_tx: ssc2_tx-0 {
  319. atmel,pins =
  320. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
  321. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
  322. AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */
  323. };
  324. pinctrl_ssc2_rx: ssc2_rx-0 {
  325. atmel,pins =
  326. <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
  327. AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
  328. AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
  329. };
  330. };
  331. twi {
  332. pinctrl_twi: twi-0 {
  333. atmel,pins =
  334. <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */
  335. AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */
  336. };
  337. pinctrl_twi_gpio: twi_gpio-0 {
  338. atmel,pins =
  339. <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */
  340. AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */
  341. };
  342. };
  343. pioA: gpio@fffff400 {
  344. compatible = "atmel,at91rm9200-gpio";
  345. reg = <0xfffff400 0x200>;
  346. interrupts = <2 4 1>;
  347. #gpio-cells = <2>;
  348. gpio-controller;
  349. interrupt-controller;
  350. #interrupt-cells = <2>;
  351. };
  352. pioB: gpio@fffff600 {
  353. compatible = "atmel,at91rm9200-gpio";
  354. reg = <0xfffff600 0x200>;
  355. interrupts = <3 4 1>;
  356. #gpio-cells = <2>;
  357. gpio-controller;
  358. interrupt-controller;
  359. #interrupt-cells = <2>;
  360. };
  361. pioC: gpio@fffff800 {
  362. compatible = "atmel,at91rm9200-gpio";
  363. reg = <0xfffff800 0x200>;
  364. interrupts = <4 4 1>;
  365. #gpio-cells = <2>;
  366. gpio-controller;
  367. interrupt-controller;
  368. #interrupt-cells = <2>;
  369. };
  370. pioD: gpio@fffffa00 {
  371. compatible = "atmel,at91rm9200-gpio";
  372. reg = <0xfffffa00 0x200>;
  373. interrupts = <5 4 1>;
  374. #gpio-cells = <2>;
  375. gpio-controller;
  376. interrupt-controller;
  377. #interrupt-cells = <2>;
  378. };
  379. };
  380. dbgu: serial@fffff200 {
  381. compatible = "atmel,at91rm9200-usart";
  382. reg = <0xfffff200 0x200>;
  383. interrupts = <1 4 7>;
  384. pinctrl-names = "default";
  385. pinctrl-0 = <&pinctrl_dbgu>;
  386. status = "disabled";
  387. };
  388. usart0: serial@fffc0000 {
  389. compatible = "atmel,at91rm9200-usart";
  390. reg = <0xfffc0000 0x200>;
  391. interrupts = <6 4 5>;
  392. atmel,use-dma-rx;
  393. atmel,use-dma-tx;
  394. pinctrl-names = "default";
  395. pinctrl-0 = <&pinctrl_uart0>;
  396. status = "disabled";
  397. };
  398. usart1: serial@fffc4000 {
  399. compatible = "atmel,at91rm9200-usart";
  400. reg = <0xfffc4000 0x200>;
  401. interrupts = <7 4 5>;
  402. atmel,use-dma-rx;
  403. atmel,use-dma-tx;
  404. pinctrl-names = "default";
  405. pinctrl-0 = <&pinctrl_uart1>;
  406. status = "disabled";
  407. };
  408. usart2: serial@fffc8000 {
  409. compatible = "atmel,at91rm9200-usart";
  410. reg = <0xfffc8000 0x200>;
  411. interrupts = <8 4 5>;
  412. atmel,use-dma-rx;
  413. atmel,use-dma-tx;
  414. pinctrl-names = "default";
  415. pinctrl-0 = <&pinctrl_uart2>;
  416. status = "disabled";
  417. };
  418. usart3: serial@fffcc000 {
  419. compatible = "atmel,at91rm9200-usart";
  420. reg = <0xfffcc000 0x200>;
  421. interrupts = <23 4 5>;
  422. atmel,use-dma-rx;
  423. atmel,use-dma-tx;
  424. pinctrl-names = "default";
  425. pinctrl-0 = <&pinctrl_uart3>;
  426. status = "disabled";
  427. };
  428. usb1: gadget@fffb0000 {
  429. compatible = "atmel,at91rm9200-udc";
  430. reg = <0xfffb0000 0x4000>;
  431. interrupts = <11 4 2>;
  432. status = "disabled";
  433. };
  434. };
  435. nand0: nand@40000000 {
  436. compatible = "atmel,at91rm9200-nand";
  437. #address-cells = <1>;
  438. #size-cells = <1>;
  439. reg = <0x40000000 0x10000000>;
  440. atmel,nand-addr-offset = <21>;
  441. atmel,nand-cmd-offset = <22>;
  442. pinctrl-names = "default";
  443. pinctrl-0 = <&pinctrl_nand>;
  444. nand-ecc-mode = "soft";
  445. gpios = <&pioC 2 GPIO_ACTIVE_HIGH
  446. 0
  447. &pioB 1 GPIO_ACTIVE_HIGH
  448. >;
  449. status = "disabled";
  450. };
  451. usb0: ohci@00300000 {
  452. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  453. reg = <0x00300000 0x100000>;
  454. interrupts = <23 4 2>;
  455. status = "disabled";
  456. };
  457. };
  458. i2c@0 {
  459. compatible = "i2c-gpio";
  460. gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
  461. &pioA 26 GPIO_ACTIVE_HIGH /* scl */
  462. >;
  463. i2c-gpio,sda-open-drain;
  464. i2c-gpio,scl-open-drain;
  465. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  466. pinctrl-names = "default";
  467. pinctrl-0 = <&pinctrl_twi_gpio>;
  468. #address-cells = <1>;
  469. #size-cells = <0>;
  470. status = "disabled";
  471. };
  472. };