mce_intel_64.c 2.1 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091
  1. /*
  2. * Intel specific MCE features.
  3. * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
  4. */
  5. #include <linux/init.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/percpu.h>
  8. #include <asm/processor.h>
  9. #include <asm/apic.h>
  10. #include <asm/msr.h>
  11. #include <asm/mce.h>
  12. #include <asm/hw_irq.h>
  13. #include <asm/idle.h>
  14. #include <asm/therm_throt.h>
  15. asmlinkage void smp_thermal_interrupt(void)
  16. {
  17. __u64 msr_val;
  18. ack_APIC_irq();
  19. exit_idle();
  20. irq_enter();
  21. rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  22. if (therm_throt_process(msr_val & 1))
  23. mce_log_therm_throt_event(smp_processor_id(), msr_val);
  24. inc_irq_stat(irq_thermal_count);
  25. irq_exit();
  26. }
  27. static void intel_init_thermal(struct cpuinfo_x86 *c)
  28. {
  29. u32 l, h;
  30. int tm2 = 0;
  31. unsigned int cpu = smp_processor_id();
  32. if (!cpu_has(c, X86_FEATURE_ACPI))
  33. return;
  34. if (!cpu_has(c, X86_FEATURE_ACC))
  35. return;
  36. /* first check if TM1 is already enabled by the BIOS, in which
  37. * case there might be some SMM goo which handles it, so we can't even
  38. * put a handler since it might be delivered via SMI already.
  39. */
  40. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  41. h = apic_read(APIC_LVTTHMR);
  42. if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
  43. printk(KERN_DEBUG
  44. "CPU%d: Thermal monitoring handled by SMI\n", cpu);
  45. return;
  46. }
  47. if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
  48. tm2 = 1;
  49. if (h & APIC_VECTOR_MASK) {
  50. printk(KERN_DEBUG
  51. "CPU%d: Thermal LVT vector (%#x) already "
  52. "installed\n", cpu, (h & APIC_VECTOR_MASK));
  53. return;
  54. }
  55. h = THERMAL_APIC_VECTOR;
  56. h |= (APIC_DM_FIXED | APIC_LVT_MASKED);
  57. apic_write(APIC_LVTTHMR, h);
  58. rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
  59. wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
  60. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  61. wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
  62. l = apic_read(APIC_LVTTHMR);
  63. apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
  64. printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
  65. cpu, tm2 ? "TM2" : "TM1");
  66. /* enable thermal throttle processing */
  67. atomic_set(&therm_throt_en, 1);
  68. return;
  69. }
  70. void mce_intel_feature_init(struct cpuinfo_x86 *c)
  71. {
  72. intel_init_thermal(c);
  73. }