oxygen_lib.c 12 KB

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  1. /*
  2. * C-Media CMI8788 driver - main driver module
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/delay.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/mutex.h>
  22. #include <linux/pci.h>
  23. #include <sound/ac97_codec.h>
  24. #include <sound/asoundef.h>
  25. #include <sound/core.h>
  26. #include <sound/info.h>
  27. #include <sound/mpu401.h>
  28. #include <sound/pcm.h>
  29. #include "oxygen.h"
  30. MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  31. MODULE_DESCRIPTION("C-Media CMI8788 helper library");
  32. MODULE_LICENSE("GPL");
  33. static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
  34. {
  35. struct oxygen *chip = dev_id;
  36. unsigned int status, clear, elapsed_streams, i;
  37. status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
  38. if (!status)
  39. return IRQ_NONE;
  40. spin_lock(&chip->reg_lock);
  41. clear = status & (OXYGEN_CHANNEL_A |
  42. OXYGEN_CHANNEL_B |
  43. OXYGEN_CHANNEL_C |
  44. OXYGEN_CHANNEL_SPDIF |
  45. OXYGEN_CHANNEL_MULTICH |
  46. OXYGEN_CHANNEL_AC97 |
  47. OXYGEN_INT_SPDIF_IN_DETECT |
  48. OXYGEN_INT_GPIO);
  49. if (clear) {
  50. if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
  51. chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
  52. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  53. chip->interrupt_mask & ~clear);
  54. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  55. chip->interrupt_mask);
  56. }
  57. elapsed_streams = status & chip->pcm_running;
  58. spin_unlock(&chip->reg_lock);
  59. for (i = 0; i < PCM_COUNT; ++i)
  60. if ((elapsed_streams & (1 << i)) && chip->streams[i])
  61. snd_pcm_period_elapsed(chip->streams[i]);
  62. if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
  63. spin_lock(&chip->reg_lock);
  64. i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
  65. if (i & OXYGEN_SPDIF_RATE_INT) {
  66. oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
  67. schedule_work(&chip->spdif_input_bits_work);
  68. }
  69. spin_unlock(&chip->reg_lock);
  70. }
  71. if (status & OXYGEN_INT_GPIO)
  72. ;
  73. if ((status & OXYGEN_INT_MIDI) && chip->midi)
  74. snd_mpu401_uart_interrupt(0, chip->midi->private_data);
  75. return IRQ_HANDLED;
  76. }
  77. static void oxygen_spdif_input_bits_changed(struct work_struct *work)
  78. {
  79. struct oxygen *chip = container_of(work, struct oxygen,
  80. spdif_input_bits_work);
  81. spin_lock_irq(&chip->reg_lock);
  82. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  83. OXYGEN_SPDIF_IN_CLOCK_96,
  84. OXYGEN_SPDIF_IN_CLOCK_MASK);
  85. spin_unlock_irq(&chip->reg_lock);
  86. msleep(1);
  87. if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
  88. & OXYGEN_SPDIF_LOCK_STATUS)) {
  89. spin_lock_irq(&chip->reg_lock);
  90. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  91. OXYGEN_SPDIF_IN_CLOCK_192,
  92. OXYGEN_SPDIF_IN_CLOCK_MASK);
  93. spin_unlock_irq(&chip->reg_lock);
  94. msleep(1);
  95. if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
  96. & OXYGEN_SPDIF_LOCK_STATUS)) {
  97. spin_lock_irq(&chip->reg_lock);
  98. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  99. OXYGEN_SPDIF_IN_CLOCK_96,
  100. OXYGEN_SPDIF_IN_CLOCK_MASK);
  101. spin_unlock_irq(&chip->reg_lock);
  102. }
  103. }
  104. if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
  105. spin_lock_irq(&chip->reg_lock);
  106. chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
  107. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  108. chip->interrupt_mask);
  109. spin_unlock_irq(&chip->reg_lock);
  110. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  111. &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
  112. }
  113. }
  114. #ifdef CONFIG_PROC_FS
  115. static void oxygen_proc_read(struct snd_info_entry *entry,
  116. struct snd_info_buffer *buffer)
  117. {
  118. struct oxygen *chip = entry->private_data;
  119. int i, j;
  120. snd_iprintf(buffer, "CMI8788\n\n");
  121. for (i = 0; i < 0x100; i += 0x10) {
  122. snd_iprintf(buffer, "%02x:", i);
  123. for (j = 0; j < 0x10; ++j)
  124. snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
  125. snd_iprintf(buffer, "\n");
  126. }
  127. if (mutex_lock_interruptible(&chip->mutex) < 0)
  128. return;
  129. if (chip->has_ac97_0) {
  130. snd_iprintf(buffer, "\nAC97\n");
  131. for (i = 0; i < 0x80; i += 0x10) {
  132. snd_iprintf(buffer, "%02x:", i);
  133. for (j = 0; j < 0x10; j += 2)
  134. snd_iprintf(buffer, " %04x",
  135. oxygen_read_ac97(chip, 0, i + j));
  136. snd_iprintf(buffer, "\n");
  137. }
  138. }
  139. if (chip->has_ac97_1) {
  140. snd_iprintf(buffer, "\nAC97 2\n");
  141. for (i = 0; i < 0x80; i += 0x10) {
  142. snd_iprintf(buffer, "%02x:", i);
  143. for (j = 0; j < 0x10; j += 2)
  144. snd_iprintf(buffer, " %04x",
  145. oxygen_read_ac97(chip, 1, i + j));
  146. snd_iprintf(buffer, "\n");
  147. }
  148. }
  149. mutex_unlock(&chip->mutex);
  150. }
  151. static void __devinit oxygen_proc_init(struct oxygen *chip)
  152. {
  153. struct snd_info_entry *entry;
  154. if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
  155. snd_info_set_text_ops(entry, chip, oxygen_proc_read);
  156. }
  157. #else
  158. #define oxygen_proc_init(chip)
  159. #endif
  160. static void __devinit oxygen_init(struct oxygen *chip)
  161. {
  162. unsigned int i;
  163. chip->dac_routing = 1;
  164. for (i = 0; i < 8; ++i)
  165. chip->dac_volume[i] = 0xff;
  166. chip->spdif_playback_enable = 1;
  167. chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
  168. (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
  169. chip->spdif_pcm_bits = chip->spdif_bits;
  170. if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
  171. chip->revision = 2;
  172. else
  173. chip->revision = 1;
  174. if (chip->revision == 1)
  175. oxygen_set_bits8(chip, OXYGEN_MISC,
  176. OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
  177. i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
  178. chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
  179. chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
  180. oxygen_set_bits8(chip, OXYGEN_FUNCTION,
  181. OXYGEN_FUNCTION_RESET_CODEC |
  182. chip->model->function_flags);
  183. oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
  184. OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
  185. OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
  186. OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
  187. oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
  188. OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
  189. OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
  190. OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
  191. oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
  192. OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
  193. OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
  194. OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
  195. oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
  196. OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
  197. OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
  198. OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
  199. oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_RATE_MASK);
  200. oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
  201. oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
  202. OXYGEN_PLAY_MULTICH_I2S_DAC | OXYGEN_PLAY_SPDIF_SPDIF |
  203. (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
  204. (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
  205. (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
  206. (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
  207. oxygen_write8(chip, OXYGEN_REC_ROUTING,
  208. OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
  209. OXYGEN_REC_B_ROUTE_AC97_1 |
  210. OXYGEN_REC_C_ROUTE_SPDIF);
  211. oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
  212. oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
  213. (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
  214. (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
  215. (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
  216. (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
  217. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
  218. oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
  219. oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
  220. if (chip->has_ac97_0) {
  221. oxygen_clear_bits16(chip, OXYGEN_AC97_OUT_CONFIG,
  222. OXYGEN_AC97_CODEC0_FRONTL |
  223. OXYGEN_AC97_CODEC0_FRONTR |
  224. OXYGEN_AC97_CODEC0_SIDEL |
  225. OXYGEN_AC97_CODEC0_SIDER |
  226. OXYGEN_AC97_CODEC0_CENTER |
  227. OXYGEN_AC97_CODEC0_BASE |
  228. OXYGEN_AC97_CODEC0_REARL |
  229. OXYGEN_AC97_CODEC0_REARR);
  230. oxygen_set_bits16(chip, OXYGEN_AC97_IN_CONFIG,
  231. OXYGEN_AC97_CODEC0_LINEL |
  232. OXYGEN_AC97_CODEC0_LINER);
  233. oxygen_write_ac97(chip, 0, AC97_RESET, 0);
  234. msleep(1);
  235. oxygen_ac97_set_bits(chip, 0, 0x70, 0x0300);
  236. oxygen_ac97_set_bits(chip, 0, 0x64, 0x8043);
  237. oxygen_ac97_set_bits(chip, 0, 0x62, 0x180f);
  238. oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
  239. oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
  240. oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
  241. oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
  242. oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
  243. oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
  244. oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
  245. oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
  246. oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
  247. oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
  248. oxygen_ac97_clear_bits(chip, 0, 0x72, 0x0001);
  249. /* power down unused ADCs and DACs */
  250. oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
  251. AC97_PD_PR0 | AC97_PD_PR1);
  252. oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
  253. AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
  254. }
  255. }
  256. static void oxygen_card_free(struct snd_card *card)
  257. {
  258. struct oxygen *chip = card->private_data;
  259. spin_lock_irq(&chip->reg_lock);
  260. chip->interrupt_mask = 0;
  261. chip->pcm_running = 0;
  262. oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
  263. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
  264. spin_unlock_irq(&chip->reg_lock);
  265. if (chip->irq >= 0) {
  266. free_irq(chip->irq, chip);
  267. synchronize_irq(chip->irq);
  268. }
  269. flush_scheduled_work();
  270. chip->model->cleanup(chip);
  271. mutex_destroy(&chip->mutex);
  272. pci_release_regions(chip->pci);
  273. pci_disable_device(chip->pci);
  274. }
  275. int __devinit oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
  276. const struct oxygen_model *model)
  277. {
  278. struct snd_card *card;
  279. struct oxygen *chip;
  280. int err;
  281. card = snd_card_new(index, id, model->owner, sizeof *chip);
  282. if (!card)
  283. return -ENOMEM;
  284. chip = card->private_data;
  285. chip->card = card;
  286. chip->pci = pci;
  287. chip->irq = -1;
  288. chip->model = model;
  289. spin_lock_init(&chip->reg_lock);
  290. mutex_init(&chip->mutex);
  291. INIT_WORK(&chip->spdif_input_bits_work,
  292. oxygen_spdif_input_bits_changed);
  293. err = pci_enable_device(pci);
  294. if (err < 0)
  295. goto err_card;
  296. err = pci_request_regions(pci, model->chip);
  297. if (err < 0) {
  298. snd_printk(KERN_ERR "cannot reserve PCI resources\n");
  299. goto err_pci_enable;
  300. }
  301. if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
  302. pci_resource_len(pci, 0) < 0x100) {
  303. snd_printk(KERN_ERR "invalid PCI I/O range\n");
  304. err = -ENXIO;
  305. goto err_pci_regions;
  306. }
  307. chip->addr = pci_resource_start(pci, 0);
  308. pci_set_master(pci);
  309. snd_card_set_dev(card, &pci->dev);
  310. card->private_free = oxygen_card_free;
  311. oxygen_init(chip);
  312. model->init(chip);
  313. err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
  314. model->chip, chip);
  315. if (err < 0) {
  316. snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
  317. goto err_card;
  318. }
  319. chip->irq = pci->irq;
  320. strcpy(card->driver, model->chip);
  321. strcpy(card->shortname, model->shortname);
  322. sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
  323. model->longname, chip->revision, chip->addr, chip->irq);
  324. strcpy(card->mixername, model->chip);
  325. snd_component_add(card, model->chip);
  326. err = oxygen_pcm_init(chip);
  327. if (err < 0)
  328. goto err_card;
  329. err = oxygen_mixer_init(chip);
  330. if (err < 0)
  331. goto err_card;
  332. if (oxygen_read8(chip, OXYGEN_MISC) & OXYGEN_MISC_MIDI) {
  333. err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
  334. chip->addr + OXYGEN_MPU401,
  335. MPU401_INFO_INTEGRATED, 0, 0,
  336. &chip->midi);
  337. if (err < 0)
  338. goto err_card;
  339. }
  340. oxygen_proc_init(chip);
  341. spin_lock_irq(&chip->reg_lock);
  342. chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
  343. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  344. spin_unlock_irq(&chip->reg_lock);
  345. err = snd_card_register(card);
  346. if (err < 0)
  347. goto err_card;
  348. pci_set_drvdata(pci, card);
  349. return 0;
  350. err_pci_regions:
  351. pci_release_regions(pci);
  352. err_pci_enable:
  353. pci_disable_device(pci);
  354. err_card:
  355. snd_card_free(card);
  356. return err;
  357. }
  358. EXPORT_SYMBOL(oxygen_pci_probe);
  359. void __devexit oxygen_pci_remove(struct pci_dev *pci)
  360. {
  361. snd_card_free(pci_get_drvdata(pci));
  362. pci_set_drvdata(pci, NULL);
  363. }
  364. EXPORT_SYMBOL(oxygen_pci_remove);