intel_display.c 181 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966596759685969597059715972597359745975597659775978597959805981598259835984598559865987598859895990599159925993599459955996599759985999600060016002600360046005600660076008600960106011601260136014601560166017601860196020602160226023602460256026602760286029603060316032603360346035603660376038603960406041604260436044604560466047604860496050605160526053605460556056605760586059606060616062606360646065606660676068606960706071607260736074607560766077607860796080608160826083608460856086608760886089609060916092609360946095609660976098609961006101610261036104610561066107610861096110611161126113611461156116611761186119612061216122612361246125612661276128612961306131613261336134613561366137613861396140614161426143614461456146614761486149615061516152615361546155615661576158615961606161616261636164616561666167616861696170617161726173617461756176617761786179618061816182618361846185618661876188618961906191619261936194619561966197619861996200620162026203620462056206620762086209621062116212621362146215621662176218621962206221622262236224622562266227622862296230623162326233623462356236623762386239624062416242624362446245624662476248
  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/module.h>
  27. #include <linux/input.h>
  28. #include <linux/i2c.h>
  29. #include <linux/kernel.h>
  30. #include <linux/slab.h>
  31. #include <linux/vgaarb.h>
  32. #include "drmP.h"
  33. #include "intel_drv.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #include "i915_trace.h"
  37. #include "drm_dp_helper.h"
  38. #include "drm_crtc_helper.h"
  39. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  41. static void intel_update_watermarks(struct drm_device *dev);
  42. static void intel_increase_pllclock(struct drm_crtc *crtc);
  43. static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  44. typedef struct {
  45. /* given values */
  46. int n;
  47. int m1, m2;
  48. int p1, p2;
  49. /* derived values */
  50. int dot;
  51. int vco;
  52. int m;
  53. int p;
  54. } intel_clock_t;
  55. typedef struct {
  56. int min, max;
  57. } intel_range_t;
  58. typedef struct {
  59. int dot_limit;
  60. int p2_slow, p2_fast;
  61. } intel_p2_t;
  62. #define INTEL_P2_NUM 2
  63. typedef struct intel_limit intel_limit_t;
  64. struct intel_limit {
  65. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  66. intel_p2_t p2;
  67. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  68. int, int, intel_clock_t *);
  69. };
  70. #define I8XX_DOT_MIN 25000
  71. #define I8XX_DOT_MAX 350000
  72. #define I8XX_VCO_MIN 930000
  73. #define I8XX_VCO_MAX 1400000
  74. #define I8XX_N_MIN 3
  75. #define I8XX_N_MAX 16
  76. #define I8XX_M_MIN 96
  77. #define I8XX_M_MAX 140
  78. #define I8XX_M1_MIN 18
  79. #define I8XX_M1_MAX 26
  80. #define I8XX_M2_MIN 6
  81. #define I8XX_M2_MAX 16
  82. #define I8XX_P_MIN 4
  83. #define I8XX_P_MAX 128
  84. #define I8XX_P1_MIN 2
  85. #define I8XX_P1_MAX 33
  86. #define I8XX_P1_LVDS_MIN 1
  87. #define I8XX_P1_LVDS_MAX 6
  88. #define I8XX_P2_SLOW 4
  89. #define I8XX_P2_FAST 2
  90. #define I8XX_P2_LVDS_SLOW 14
  91. #define I8XX_P2_LVDS_FAST 7
  92. #define I8XX_P2_SLOW_LIMIT 165000
  93. #define I9XX_DOT_MIN 20000
  94. #define I9XX_DOT_MAX 400000
  95. #define I9XX_VCO_MIN 1400000
  96. #define I9XX_VCO_MAX 2800000
  97. #define PINEVIEW_VCO_MIN 1700000
  98. #define PINEVIEW_VCO_MAX 3500000
  99. #define I9XX_N_MIN 1
  100. #define I9XX_N_MAX 6
  101. /* Pineview's Ncounter is a ring counter */
  102. #define PINEVIEW_N_MIN 3
  103. #define PINEVIEW_N_MAX 6
  104. #define I9XX_M_MIN 70
  105. #define I9XX_M_MAX 120
  106. #define PINEVIEW_M_MIN 2
  107. #define PINEVIEW_M_MAX 256
  108. #define I9XX_M1_MIN 10
  109. #define I9XX_M1_MAX 22
  110. #define I9XX_M2_MIN 5
  111. #define I9XX_M2_MAX 9
  112. /* Pineview M1 is reserved, and must be 0 */
  113. #define PINEVIEW_M1_MIN 0
  114. #define PINEVIEW_M1_MAX 0
  115. #define PINEVIEW_M2_MIN 0
  116. #define PINEVIEW_M2_MAX 254
  117. #define I9XX_P_SDVO_DAC_MIN 5
  118. #define I9XX_P_SDVO_DAC_MAX 80
  119. #define I9XX_P_LVDS_MIN 7
  120. #define I9XX_P_LVDS_MAX 98
  121. #define PINEVIEW_P_LVDS_MIN 7
  122. #define PINEVIEW_P_LVDS_MAX 112
  123. #define I9XX_P1_MIN 1
  124. #define I9XX_P1_MAX 8
  125. #define I9XX_P2_SDVO_DAC_SLOW 10
  126. #define I9XX_P2_SDVO_DAC_FAST 5
  127. #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
  128. #define I9XX_P2_LVDS_SLOW 14
  129. #define I9XX_P2_LVDS_FAST 7
  130. #define I9XX_P2_LVDS_SLOW_LIMIT 112000
  131. /*The parameter is for SDVO on G4x platform*/
  132. #define G4X_DOT_SDVO_MIN 25000
  133. #define G4X_DOT_SDVO_MAX 270000
  134. #define G4X_VCO_MIN 1750000
  135. #define G4X_VCO_MAX 3500000
  136. #define G4X_N_SDVO_MIN 1
  137. #define G4X_N_SDVO_MAX 4
  138. #define G4X_M_SDVO_MIN 104
  139. #define G4X_M_SDVO_MAX 138
  140. #define G4X_M1_SDVO_MIN 17
  141. #define G4X_M1_SDVO_MAX 23
  142. #define G4X_M2_SDVO_MIN 5
  143. #define G4X_M2_SDVO_MAX 11
  144. #define G4X_P_SDVO_MIN 10
  145. #define G4X_P_SDVO_MAX 30
  146. #define G4X_P1_SDVO_MIN 1
  147. #define G4X_P1_SDVO_MAX 3
  148. #define G4X_P2_SDVO_SLOW 10
  149. #define G4X_P2_SDVO_FAST 10
  150. #define G4X_P2_SDVO_LIMIT 270000
  151. /*The parameter is for HDMI_DAC on G4x platform*/
  152. #define G4X_DOT_HDMI_DAC_MIN 22000
  153. #define G4X_DOT_HDMI_DAC_MAX 400000
  154. #define G4X_N_HDMI_DAC_MIN 1
  155. #define G4X_N_HDMI_DAC_MAX 4
  156. #define G4X_M_HDMI_DAC_MIN 104
  157. #define G4X_M_HDMI_DAC_MAX 138
  158. #define G4X_M1_HDMI_DAC_MIN 16
  159. #define G4X_M1_HDMI_DAC_MAX 23
  160. #define G4X_M2_HDMI_DAC_MIN 5
  161. #define G4X_M2_HDMI_DAC_MAX 11
  162. #define G4X_P_HDMI_DAC_MIN 5
  163. #define G4X_P_HDMI_DAC_MAX 80
  164. #define G4X_P1_HDMI_DAC_MIN 1
  165. #define G4X_P1_HDMI_DAC_MAX 8
  166. #define G4X_P2_HDMI_DAC_SLOW 10
  167. #define G4X_P2_HDMI_DAC_FAST 5
  168. #define G4X_P2_HDMI_DAC_LIMIT 165000
  169. /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
  170. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
  171. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
  172. #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
  173. #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
  174. #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
  175. #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
  176. #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
  177. #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
  178. #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
  179. #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
  180. #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
  181. #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
  182. #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
  183. #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
  184. #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
  185. #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
  186. #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
  187. /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
  188. #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
  189. #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
  190. #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
  191. #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
  192. #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
  193. #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
  194. #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
  195. #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
  196. #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
  197. #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
  198. #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
  199. #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
  200. #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
  201. #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
  202. #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
  203. #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
  204. #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
  205. /*The parameter is for DISPLAY PORT on G4x platform*/
  206. #define G4X_DOT_DISPLAY_PORT_MIN 161670
  207. #define G4X_DOT_DISPLAY_PORT_MAX 227000
  208. #define G4X_N_DISPLAY_PORT_MIN 1
  209. #define G4X_N_DISPLAY_PORT_MAX 2
  210. #define G4X_M_DISPLAY_PORT_MIN 97
  211. #define G4X_M_DISPLAY_PORT_MAX 108
  212. #define G4X_M1_DISPLAY_PORT_MIN 0x10
  213. #define G4X_M1_DISPLAY_PORT_MAX 0x12
  214. #define G4X_M2_DISPLAY_PORT_MIN 0x05
  215. #define G4X_M2_DISPLAY_PORT_MAX 0x06
  216. #define G4X_P_DISPLAY_PORT_MIN 10
  217. #define G4X_P_DISPLAY_PORT_MAX 20
  218. #define G4X_P1_DISPLAY_PORT_MIN 1
  219. #define G4X_P1_DISPLAY_PORT_MAX 2
  220. #define G4X_P2_DISPLAY_PORT_SLOW 10
  221. #define G4X_P2_DISPLAY_PORT_FAST 10
  222. #define G4X_P2_DISPLAY_PORT_LIMIT 0
  223. /* Ironlake / Sandybridge */
  224. /* as we calculate clock using (register_value + 2) for
  225. N/M1/M2, so here the range value for them is (actual_value-2).
  226. */
  227. #define IRONLAKE_DOT_MIN 25000
  228. #define IRONLAKE_DOT_MAX 350000
  229. #define IRONLAKE_VCO_MIN 1760000
  230. #define IRONLAKE_VCO_MAX 3510000
  231. #define IRONLAKE_M1_MIN 12
  232. #define IRONLAKE_M1_MAX 22
  233. #define IRONLAKE_M2_MIN 5
  234. #define IRONLAKE_M2_MAX 9
  235. #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
  236. /* We have parameter ranges for different type of outputs. */
  237. /* DAC & HDMI Refclk 120Mhz */
  238. #define IRONLAKE_DAC_N_MIN 1
  239. #define IRONLAKE_DAC_N_MAX 5
  240. #define IRONLAKE_DAC_M_MIN 79
  241. #define IRONLAKE_DAC_M_MAX 127
  242. #define IRONLAKE_DAC_P_MIN 5
  243. #define IRONLAKE_DAC_P_MAX 80
  244. #define IRONLAKE_DAC_P1_MIN 1
  245. #define IRONLAKE_DAC_P1_MAX 8
  246. #define IRONLAKE_DAC_P2_SLOW 10
  247. #define IRONLAKE_DAC_P2_FAST 5
  248. /* LVDS single-channel 120Mhz refclk */
  249. #define IRONLAKE_LVDS_S_N_MIN 1
  250. #define IRONLAKE_LVDS_S_N_MAX 3
  251. #define IRONLAKE_LVDS_S_M_MIN 79
  252. #define IRONLAKE_LVDS_S_M_MAX 118
  253. #define IRONLAKE_LVDS_S_P_MIN 28
  254. #define IRONLAKE_LVDS_S_P_MAX 112
  255. #define IRONLAKE_LVDS_S_P1_MIN 2
  256. #define IRONLAKE_LVDS_S_P1_MAX 8
  257. #define IRONLAKE_LVDS_S_P2_SLOW 14
  258. #define IRONLAKE_LVDS_S_P2_FAST 14
  259. /* LVDS dual-channel 120Mhz refclk */
  260. #define IRONLAKE_LVDS_D_N_MIN 1
  261. #define IRONLAKE_LVDS_D_N_MAX 3
  262. #define IRONLAKE_LVDS_D_M_MIN 79
  263. #define IRONLAKE_LVDS_D_M_MAX 127
  264. #define IRONLAKE_LVDS_D_P_MIN 14
  265. #define IRONLAKE_LVDS_D_P_MAX 56
  266. #define IRONLAKE_LVDS_D_P1_MIN 2
  267. #define IRONLAKE_LVDS_D_P1_MAX 8
  268. #define IRONLAKE_LVDS_D_P2_SLOW 7
  269. #define IRONLAKE_LVDS_D_P2_FAST 7
  270. /* LVDS single-channel 100Mhz refclk */
  271. #define IRONLAKE_LVDS_S_SSC_N_MIN 1
  272. #define IRONLAKE_LVDS_S_SSC_N_MAX 2
  273. #define IRONLAKE_LVDS_S_SSC_M_MIN 79
  274. #define IRONLAKE_LVDS_S_SSC_M_MAX 126
  275. #define IRONLAKE_LVDS_S_SSC_P_MIN 28
  276. #define IRONLAKE_LVDS_S_SSC_P_MAX 112
  277. #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
  278. #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
  279. #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
  280. #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
  281. /* LVDS dual-channel 100Mhz refclk */
  282. #define IRONLAKE_LVDS_D_SSC_N_MIN 1
  283. #define IRONLAKE_LVDS_D_SSC_N_MAX 3
  284. #define IRONLAKE_LVDS_D_SSC_M_MIN 79
  285. #define IRONLAKE_LVDS_D_SSC_M_MAX 126
  286. #define IRONLAKE_LVDS_D_SSC_P_MIN 14
  287. #define IRONLAKE_LVDS_D_SSC_P_MAX 42
  288. #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
  289. #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
  290. #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
  291. #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
  292. /* DisplayPort */
  293. #define IRONLAKE_DP_N_MIN 1
  294. #define IRONLAKE_DP_N_MAX 2
  295. #define IRONLAKE_DP_M_MIN 81
  296. #define IRONLAKE_DP_M_MAX 90
  297. #define IRONLAKE_DP_P_MIN 10
  298. #define IRONLAKE_DP_P_MAX 20
  299. #define IRONLAKE_DP_P2_FAST 10
  300. #define IRONLAKE_DP_P2_SLOW 10
  301. #define IRONLAKE_DP_P2_LIMIT 0
  302. #define IRONLAKE_DP_P1_MIN 1
  303. #define IRONLAKE_DP_P1_MAX 2
  304. /* FDI */
  305. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  306. static bool
  307. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  308. int target, int refclk, intel_clock_t *best_clock);
  309. static bool
  310. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  311. int target, int refclk, intel_clock_t *best_clock);
  312. static bool
  313. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  314. int target, int refclk, intel_clock_t *best_clock);
  315. static bool
  316. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  317. int target, int refclk, intel_clock_t *best_clock);
  318. static const intel_limit_t intel_limits_i8xx_dvo = {
  319. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  320. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  321. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  322. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  323. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  324. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  325. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  326. .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
  327. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  328. .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
  329. .find_pll = intel_find_best_PLL,
  330. };
  331. static const intel_limit_t intel_limits_i8xx_lvds = {
  332. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  333. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  334. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  335. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  336. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  337. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  338. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  339. .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
  340. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  341. .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
  342. .find_pll = intel_find_best_PLL,
  343. };
  344. static const intel_limit_t intel_limits_i9xx_sdvo = {
  345. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  346. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  347. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  348. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  349. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  350. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  351. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  352. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  353. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  354. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  355. .find_pll = intel_find_best_PLL,
  356. };
  357. static const intel_limit_t intel_limits_i9xx_lvds = {
  358. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  359. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  360. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  361. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  362. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  363. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  364. .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
  365. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  366. /* The single-channel range is 25-112Mhz, and dual-channel
  367. * is 80-224Mhz. Prefer single channel as much as possible.
  368. */
  369. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  370. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
  371. .find_pll = intel_find_best_PLL,
  372. };
  373. /* below parameter and function is for G4X Chipset Family*/
  374. static const intel_limit_t intel_limits_g4x_sdvo = {
  375. .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
  376. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  377. .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
  378. .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
  379. .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
  380. .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
  381. .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
  382. .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
  383. .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
  384. .p2_slow = G4X_P2_SDVO_SLOW,
  385. .p2_fast = G4X_P2_SDVO_FAST
  386. },
  387. .find_pll = intel_g4x_find_best_PLL,
  388. };
  389. static const intel_limit_t intel_limits_g4x_hdmi = {
  390. .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
  391. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  392. .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
  393. .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
  394. .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
  395. .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
  396. .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
  397. .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
  398. .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
  399. .p2_slow = G4X_P2_HDMI_DAC_SLOW,
  400. .p2_fast = G4X_P2_HDMI_DAC_FAST
  401. },
  402. .find_pll = intel_g4x_find_best_PLL,
  403. };
  404. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  405. .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
  406. .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
  407. .vco = { .min = G4X_VCO_MIN,
  408. .max = G4X_VCO_MAX },
  409. .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
  410. .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
  411. .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
  412. .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
  413. .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
  414. .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
  415. .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
  416. .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
  417. .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
  418. .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
  419. .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
  420. .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
  421. .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
  422. .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
  423. .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
  424. },
  425. .find_pll = intel_g4x_find_best_PLL,
  426. };
  427. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  428. .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
  429. .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
  430. .vco = { .min = G4X_VCO_MIN,
  431. .max = G4X_VCO_MAX },
  432. .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
  433. .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
  434. .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
  435. .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
  436. .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
  437. .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
  438. .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
  439. .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
  440. .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
  441. .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
  442. .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
  443. .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
  444. .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
  445. .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
  446. .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
  447. },
  448. .find_pll = intel_g4x_find_best_PLL,
  449. };
  450. static const intel_limit_t intel_limits_g4x_display_port = {
  451. .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
  452. .max = G4X_DOT_DISPLAY_PORT_MAX },
  453. .vco = { .min = G4X_VCO_MIN,
  454. .max = G4X_VCO_MAX},
  455. .n = { .min = G4X_N_DISPLAY_PORT_MIN,
  456. .max = G4X_N_DISPLAY_PORT_MAX },
  457. .m = { .min = G4X_M_DISPLAY_PORT_MIN,
  458. .max = G4X_M_DISPLAY_PORT_MAX },
  459. .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
  460. .max = G4X_M1_DISPLAY_PORT_MAX },
  461. .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
  462. .max = G4X_M2_DISPLAY_PORT_MAX },
  463. .p = { .min = G4X_P_DISPLAY_PORT_MIN,
  464. .max = G4X_P_DISPLAY_PORT_MAX },
  465. .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
  466. .max = G4X_P1_DISPLAY_PORT_MAX},
  467. .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
  468. .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
  469. .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
  470. .find_pll = intel_find_pll_g4x_dp,
  471. };
  472. static const intel_limit_t intel_limits_pineview_sdvo = {
  473. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
  474. .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
  475. .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
  476. .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
  477. .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
  478. .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
  479. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  480. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  481. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  482. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  483. .find_pll = intel_find_best_PLL,
  484. };
  485. static const intel_limit_t intel_limits_pineview_lvds = {
  486. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  487. .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
  488. .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
  489. .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
  490. .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
  491. .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
  492. .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
  493. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  494. /* Pineview only supports single-channel mode. */
  495. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  496. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
  497. .find_pll = intel_find_best_PLL,
  498. };
  499. static const intel_limit_t intel_limits_ironlake_dac = {
  500. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  501. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  502. .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
  503. .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
  504. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  505. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  506. .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
  507. .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
  508. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  509. .p2_slow = IRONLAKE_DAC_P2_SLOW,
  510. .p2_fast = IRONLAKE_DAC_P2_FAST },
  511. .find_pll = intel_g4x_find_best_PLL,
  512. };
  513. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  514. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  515. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  516. .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
  517. .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
  518. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  519. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  520. .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
  521. .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
  522. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  523. .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
  524. .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
  525. .find_pll = intel_g4x_find_best_PLL,
  526. };
  527. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  528. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  529. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  530. .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
  531. .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
  532. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  533. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  534. .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
  535. .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
  536. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  537. .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
  538. .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
  539. .find_pll = intel_g4x_find_best_PLL,
  540. };
  541. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  542. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  543. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  544. .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
  545. .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
  546. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  547. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  548. .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
  549. .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
  550. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  551. .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
  552. .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
  553. .find_pll = intel_g4x_find_best_PLL,
  554. };
  555. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  556. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  557. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  558. .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
  559. .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
  560. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  561. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  562. .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
  563. .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
  564. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  565. .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
  566. .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
  567. .find_pll = intel_g4x_find_best_PLL,
  568. };
  569. static const intel_limit_t intel_limits_ironlake_display_port = {
  570. .dot = { .min = IRONLAKE_DOT_MIN,
  571. .max = IRONLAKE_DOT_MAX },
  572. .vco = { .min = IRONLAKE_VCO_MIN,
  573. .max = IRONLAKE_VCO_MAX},
  574. .n = { .min = IRONLAKE_DP_N_MIN,
  575. .max = IRONLAKE_DP_N_MAX },
  576. .m = { .min = IRONLAKE_DP_M_MIN,
  577. .max = IRONLAKE_DP_M_MAX },
  578. .m1 = { .min = IRONLAKE_M1_MIN,
  579. .max = IRONLAKE_M1_MAX },
  580. .m2 = { .min = IRONLAKE_M2_MIN,
  581. .max = IRONLAKE_M2_MAX },
  582. .p = { .min = IRONLAKE_DP_P_MIN,
  583. .max = IRONLAKE_DP_P_MAX },
  584. .p1 = { .min = IRONLAKE_DP_P1_MIN,
  585. .max = IRONLAKE_DP_P1_MAX},
  586. .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
  587. .p2_slow = IRONLAKE_DP_P2_SLOW,
  588. .p2_fast = IRONLAKE_DP_P2_FAST },
  589. .find_pll = intel_find_pll_ironlake_dp,
  590. };
  591. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
  592. {
  593. struct drm_device *dev = crtc->dev;
  594. struct drm_i915_private *dev_priv = dev->dev_private;
  595. const intel_limit_t *limit;
  596. int refclk = 120;
  597. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  598. if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
  599. refclk = 100;
  600. if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  601. LVDS_CLKB_POWER_UP) {
  602. /* LVDS dual channel */
  603. if (refclk == 100)
  604. limit = &intel_limits_ironlake_dual_lvds_100m;
  605. else
  606. limit = &intel_limits_ironlake_dual_lvds;
  607. } else {
  608. if (refclk == 100)
  609. limit = &intel_limits_ironlake_single_lvds_100m;
  610. else
  611. limit = &intel_limits_ironlake_single_lvds;
  612. }
  613. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  614. HAS_eDP)
  615. limit = &intel_limits_ironlake_display_port;
  616. else
  617. limit = &intel_limits_ironlake_dac;
  618. return limit;
  619. }
  620. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  621. {
  622. struct drm_device *dev = crtc->dev;
  623. struct drm_i915_private *dev_priv = dev->dev_private;
  624. const intel_limit_t *limit;
  625. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  626. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  627. LVDS_CLKB_POWER_UP)
  628. /* LVDS with dual channel */
  629. limit = &intel_limits_g4x_dual_channel_lvds;
  630. else
  631. /* LVDS with dual channel */
  632. limit = &intel_limits_g4x_single_channel_lvds;
  633. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  634. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  635. limit = &intel_limits_g4x_hdmi;
  636. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  637. limit = &intel_limits_g4x_sdvo;
  638. } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  639. limit = &intel_limits_g4x_display_port;
  640. } else /* The option is for other outputs */
  641. limit = &intel_limits_i9xx_sdvo;
  642. return limit;
  643. }
  644. static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
  645. {
  646. struct drm_device *dev = crtc->dev;
  647. const intel_limit_t *limit;
  648. if (HAS_PCH_SPLIT(dev))
  649. limit = intel_ironlake_limit(crtc);
  650. else if (IS_G4X(dev)) {
  651. limit = intel_g4x_limit(crtc);
  652. } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
  653. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  654. limit = &intel_limits_i9xx_lvds;
  655. else
  656. limit = &intel_limits_i9xx_sdvo;
  657. } else if (IS_PINEVIEW(dev)) {
  658. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  659. limit = &intel_limits_pineview_lvds;
  660. else
  661. limit = &intel_limits_pineview_sdvo;
  662. } else {
  663. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  664. limit = &intel_limits_i8xx_lvds;
  665. else
  666. limit = &intel_limits_i8xx_dvo;
  667. }
  668. return limit;
  669. }
  670. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  671. static void pineview_clock(int refclk, intel_clock_t *clock)
  672. {
  673. clock->m = clock->m2 + 2;
  674. clock->p = clock->p1 * clock->p2;
  675. clock->vco = refclk * clock->m / clock->n;
  676. clock->dot = clock->vco / clock->p;
  677. }
  678. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  679. {
  680. if (IS_PINEVIEW(dev)) {
  681. pineview_clock(refclk, clock);
  682. return;
  683. }
  684. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  685. clock->p = clock->p1 * clock->p2;
  686. clock->vco = refclk * clock->m / (clock->n + 2);
  687. clock->dot = clock->vco / clock->p;
  688. }
  689. /**
  690. * Returns whether any output on the specified pipe is of the specified type
  691. */
  692. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  693. {
  694. struct drm_device *dev = crtc->dev;
  695. struct drm_mode_config *mode_config = &dev->mode_config;
  696. struct intel_encoder *encoder;
  697. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  698. if (encoder->base.crtc == crtc && encoder->type == type)
  699. return true;
  700. return false;
  701. }
  702. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  703. /**
  704. * Returns whether the given set of divisors are valid for a given refclk with
  705. * the given connectors.
  706. */
  707. static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
  708. {
  709. const intel_limit_t *limit = intel_limit (crtc);
  710. struct drm_device *dev = crtc->dev;
  711. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  712. INTELPllInvalid ("p1 out of range\n");
  713. if (clock->p < limit->p.min || limit->p.max < clock->p)
  714. INTELPllInvalid ("p out of range\n");
  715. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  716. INTELPllInvalid ("m2 out of range\n");
  717. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  718. INTELPllInvalid ("m1 out of range\n");
  719. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  720. INTELPllInvalid ("m1 <= m2\n");
  721. if (clock->m < limit->m.min || limit->m.max < clock->m)
  722. INTELPllInvalid ("m out of range\n");
  723. if (clock->n < limit->n.min || limit->n.max < clock->n)
  724. INTELPllInvalid ("n out of range\n");
  725. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  726. INTELPllInvalid ("vco out of range\n");
  727. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  728. * connector, etc., rather than just a single range.
  729. */
  730. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  731. INTELPllInvalid ("dot out of range\n");
  732. return true;
  733. }
  734. static bool
  735. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  736. int target, int refclk, intel_clock_t *best_clock)
  737. {
  738. struct drm_device *dev = crtc->dev;
  739. struct drm_i915_private *dev_priv = dev->dev_private;
  740. intel_clock_t clock;
  741. int err = target;
  742. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  743. (I915_READ(LVDS)) != 0) {
  744. /*
  745. * For LVDS, if the panel is on, just rely on its current
  746. * settings for dual-channel. We haven't figured out how to
  747. * reliably set up different single/dual channel state, if we
  748. * even can.
  749. */
  750. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  751. LVDS_CLKB_POWER_UP)
  752. clock.p2 = limit->p2.p2_fast;
  753. else
  754. clock.p2 = limit->p2.p2_slow;
  755. } else {
  756. if (target < limit->p2.dot_limit)
  757. clock.p2 = limit->p2.p2_slow;
  758. else
  759. clock.p2 = limit->p2.p2_fast;
  760. }
  761. memset (best_clock, 0, sizeof (*best_clock));
  762. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  763. clock.m1++) {
  764. for (clock.m2 = limit->m2.min;
  765. clock.m2 <= limit->m2.max; clock.m2++) {
  766. /* m1 is always 0 in Pineview */
  767. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  768. break;
  769. for (clock.n = limit->n.min;
  770. clock.n <= limit->n.max; clock.n++) {
  771. for (clock.p1 = limit->p1.min;
  772. clock.p1 <= limit->p1.max; clock.p1++) {
  773. int this_err;
  774. intel_clock(dev, refclk, &clock);
  775. if (!intel_PLL_is_valid(crtc, &clock))
  776. continue;
  777. this_err = abs(clock.dot - target);
  778. if (this_err < err) {
  779. *best_clock = clock;
  780. err = this_err;
  781. }
  782. }
  783. }
  784. }
  785. }
  786. return (err != target);
  787. }
  788. static bool
  789. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  790. int target, int refclk, intel_clock_t *best_clock)
  791. {
  792. struct drm_device *dev = crtc->dev;
  793. struct drm_i915_private *dev_priv = dev->dev_private;
  794. intel_clock_t clock;
  795. int max_n;
  796. bool found;
  797. /* approximately equals target * 0.00585 */
  798. int err_most = (target >> 8) + (target >> 9);
  799. found = false;
  800. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  801. int lvds_reg;
  802. if (HAS_PCH_SPLIT(dev))
  803. lvds_reg = PCH_LVDS;
  804. else
  805. lvds_reg = LVDS;
  806. if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  807. LVDS_CLKB_POWER_UP)
  808. clock.p2 = limit->p2.p2_fast;
  809. else
  810. clock.p2 = limit->p2.p2_slow;
  811. } else {
  812. if (target < limit->p2.dot_limit)
  813. clock.p2 = limit->p2.p2_slow;
  814. else
  815. clock.p2 = limit->p2.p2_fast;
  816. }
  817. memset(best_clock, 0, sizeof(*best_clock));
  818. max_n = limit->n.max;
  819. /* based on hardware requirement, prefer smaller n to precision */
  820. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  821. /* based on hardware requirement, prefere larger m1,m2 */
  822. for (clock.m1 = limit->m1.max;
  823. clock.m1 >= limit->m1.min; clock.m1--) {
  824. for (clock.m2 = limit->m2.max;
  825. clock.m2 >= limit->m2.min; clock.m2--) {
  826. for (clock.p1 = limit->p1.max;
  827. clock.p1 >= limit->p1.min; clock.p1--) {
  828. int this_err;
  829. intel_clock(dev, refclk, &clock);
  830. if (!intel_PLL_is_valid(crtc, &clock))
  831. continue;
  832. this_err = abs(clock.dot - target) ;
  833. if (this_err < err_most) {
  834. *best_clock = clock;
  835. err_most = this_err;
  836. max_n = clock.n;
  837. found = true;
  838. }
  839. }
  840. }
  841. }
  842. }
  843. return found;
  844. }
  845. static bool
  846. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  847. int target, int refclk, intel_clock_t *best_clock)
  848. {
  849. struct drm_device *dev = crtc->dev;
  850. intel_clock_t clock;
  851. /* return directly when it is eDP */
  852. if (HAS_eDP)
  853. return true;
  854. if (target < 200000) {
  855. clock.n = 1;
  856. clock.p1 = 2;
  857. clock.p2 = 10;
  858. clock.m1 = 12;
  859. clock.m2 = 9;
  860. } else {
  861. clock.n = 2;
  862. clock.p1 = 1;
  863. clock.p2 = 10;
  864. clock.m1 = 14;
  865. clock.m2 = 8;
  866. }
  867. intel_clock(dev, refclk, &clock);
  868. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  869. return true;
  870. }
  871. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  872. static bool
  873. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  874. int target, int refclk, intel_clock_t *best_clock)
  875. {
  876. intel_clock_t clock;
  877. if (target < 200000) {
  878. clock.p1 = 2;
  879. clock.p2 = 10;
  880. clock.n = 2;
  881. clock.m1 = 23;
  882. clock.m2 = 8;
  883. } else {
  884. clock.p1 = 1;
  885. clock.p2 = 10;
  886. clock.n = 1;
  887. clock.m1 = 14;
  888. clock.m2 = 2;
  889. }
  890. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  891. clock.p = (clock.p1 * clock.p2);
  892. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  893. clock.vco = 0;
  894. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  895. return true;
  896. }
  897. /**
  898. * intel_wait_for_vblank - wait for vblank on a given pipe
  899. * @dev: drm device
  900. * @pipe: pipe to wait for
  901. *
  902. * Wait for vblank to occur on a given pipe. Needed for various bits of
  903. * mode setting code.
  904. */
  905. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  906. {
  907. struct drm_i915_private *dev_priv = dev->dev_private;
  908. int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
  909. /* Clear existing vblank status. Note this will clear any other
  910. * sticky status fields as well.
  911. *
  912. * This races with i915_driver_irq_handler() with the result
  913. * that either function could miss a vblank event. Here it is not
  914. * fatal, as we will either wait upon the next vblank interrupt or
  915. * timeout. Generally speaking intel_wait_for_vblank() is only
  916. * called during modeset at which time the GPU should be idle and
  917. * should *not* be performing page flips and thus not waiting on
  918. * vblanks...
  919. * Currently, the result of us stealing a vblank from the irq
  920. * handler is that a single frame will be skipped during swapbuffers.
  921. */
  922. I915_WRITE(pipestat_reg,
  923. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  924. /* Wait for vblank interrupt bit to set */
  925. if (wait_for(I915_READ(pipestat_reg) &
  926. PIPE_VBLANK_INTERRUPT_STATUS,
  927. 50))
  928. DRM_DEBUG_KMS("vblank wait timed out\n");
  929. }
  930. /**
  931. * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
  932. * @dev: drm device
  933. * @pipe: pipe to wait for
  934. *
  935. * After disabling a pipe, we can't wait for vblank in the usual way,
  936. * spinning on the vblank interrupt status bit, since we won't actually
  937. * see an interrupt when the pipe is disabled.
  938. *
  939. * So this function waits for the display line value to settle (it
  940. * usually ends up stopping at the start of the next frame).
  941. */
  942. void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
  943. {
  944. struct drm_i915_private *dev_priv = dev->dev_private;
  945. int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
  946. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  947. u32 last_line;
  948. /* Wait for the display line to settle */
  949. do {
  950. last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
  951. mdelay(5);
  952. } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
  953. time_after(timeout, jiffies));
  954. if (time_after(jiffies, timeout))
  955. DRM_DEBUG_KMS("vblank wait timed out\n");
  956. }
  957. /* Parameters have changed, update FBC info */
  958. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  959. {
  960. struct drm_device *dev = crtc->dev;
  961. struct drm_i915_private *dev_priv = dev->dev_private;
  962. struct drm_framebuffer *fb = crtc->fb;
  963. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  964. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  965. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  966. int plane, i;
  967. u32 fbc_ctl, fbc_ctl2;
  968. dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  969. if (fb->pitch < dev_priv->cfb_pitch)
  970. dev_priv->cfb_pitch = fb->pitch;
  971. /* FBC_CTL wants 64B units */
  972. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  973. dev_priv->cfb_fence = obj_priv->fence_reg;
  974. dev_priv->cfb_plane = intel_crtc->plane;
  975. plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  976. /* Clear old tags */
  977. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  978. I915_WRITE(FBC_TAG + (i * 4), 0);
  979. /* Set it up... */
  980. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
  981. if (obj_priv->tiling_mode != I915_TILING_NONE)
  982. fbc_ctl2 |= FBC_CTL_CPU_FENCE;
  983. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  984. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  985. /* enable it... */
  986. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  987. if (IS_I945GM(dev))
  988. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  989. fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  990. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  991. if (obj_priv->tiling_mode != I915_TILING_NONE)
  992. fbc_ctl |= dev_priv->cfb_fence;
  993. I915_WRITE(FBC_CONTROL, fbc_ctl);
  994. DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
  995. dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
  996. }
  997. void i8xx_disable_fbc(struct drm_device *dev)
  998. {
  999. struct drm_i915_private *dev_priv = dev->dev_private;
  1000. u32 fbc_ctl;
  1001. if (!I915_HAS_FBC(dev))
  1002. return;
  1003. if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
  1004. return; /* Already off, just return */
  1005. /* Disable compression */
  1006. fbc_ctl = I915_READ(FBC_CONTROL);
  1007. fbc_ctl &= ~FBC_CTL_EN;
  1008. I915_WRITE(FBC_CONTROL, fbc_ctl);
  1009. /* Wait for compressing bit to clear */
  1010. if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  1011. DRM_DEBUG_KMS("FBC idle timed out\n");
  1012. return;
  1013. }
  1014. DRM_DEBUG_KMS("disabled FBC\n");
  1015. }
  1016. static bool i8xx_fbc_enabled(struct drm_device *dev)
  1017. {
  1018. struct drm_i915_private *dev_priv = dev->dev_private;
  1019. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  1020. }
  1021. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1022. {
  1023. struct drm_device *dev = crtc->dev;
  1024. struct drm_i915_private *dev_priv = dev->dev_private;
  1025. struct drm_framebuffer *fb = crtc->fb;
  1026. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1027. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  1028. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1029. int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
  1030. DPFC_CTL_PLANEB);
  1031. unsigned long stall_watermark = 200;
  1032. u32 dpfc_ctl;
  1033. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  1034. dev_priv->cfb_fence = obj_priv->fence_reg;
  1035. dev_priv->cfb_plane = intel_crtc->plane;
  1036. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  1037. if (obj_priv->tiling_mode != I915_TILING_NONE) {
  1038. dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
  1039. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  1040. } else {
  1041. I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  1042. }
  1043. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  1044. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1045. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1046. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1047. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  1048. /* enable it... */
  1049. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  1050. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1051. }
  1052. void g4x_disable_fbc(struct drm_device *dev)
  1053. {
  1054. struct drm_i915_private *dev_priv = dev->dev_private;
  1055. u32 dpfc_ctl;
  1056. /* Disable compression */
  1057. dpfc_ctl = I915_READ(DPFC_CONTROL);
  1058. dpfc_ctl &= ~DPFC_CTL_EN;
  1059. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  1060. DRM_DEBUG_KMS("disabled FBC\n");
  1061. }
  1062. static bool g4x_fbc_enabled(struct drm_device *dev)
  1063. {
  1064. struct drm_i915_private *dev_priv = dev->dev_private;
  1065. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  1066. }
  1067. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1068. {
  1069. struct drm_device *dev = crtc->dev;
  1070. struct drm_i915_private *dev_priv = dev->dev_private;
  1071. struct drm_framebuffer *fb = crtc->fb;
  1072. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1073. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  1074. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1075. int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
  1076. DPFC_CTL_PLANEB;
  1077. unsigned long stall_watermark = 200;
  1078. u32 dpfc_ctl;
  1079. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  1080. dev_priv->cfb_fence = obj_priv->fence_reg;
  1081. dev_priv->cfb_plane = intel_crtc->plane;
  1082. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1083. dpfc_ctl &= DPFC_RESERVED;
  1084. dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  1085. if (obj_priv->tiling_mode != I915_TILING_NONE) {
  1086. dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
  1087. I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  1088. } else {
  1089. I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  1090. }
  1091. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  1092. I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1093. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1094. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1095. I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  1096. I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
  1097. /* enable it... */
  1098. I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
  1099. DPFC_CTL_EN);
  1100. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1101. }
  1102. void ironlake_disable_fbc(struct drm_device *dev)
  1103. {
  1104. struct drm_i915_private *dev_priv = dev->dev_private;
  1105. u32 dpfc_ctl;
  1106. /* Disable compression */
  1107. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1108. dpfc_ctl &= ~DPFC_CTL_EN;
  1109. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  1110. DRM_DEBUG_KMS("disabled FBC\n");
  1111. }
  1112. static bool ironlake_fbc_enabled(struct drm_device *dev)
  1113. {
  1114. struct drm_i915_private *dev_priv = dev->dev_private;
  1115. return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  1116. }
  1117. bool intel_fbc_enabled(struct drm_device *dev)
  1118. {
  1119. struct drm_i915_private *dev_priv = dev->dev_private;
  1120. if (!dev_priv->display.fbc_enabled)
  1121. return false;
  1122. return dev_priv->display.fbc_enabled(dev);
  1123. }
  1124. void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1125. {
  1126. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  1127. if (!dev_priv->display.enable_fbc)
  1128. return;
  1129. dev_priv->display.enable_fbc(crtc, interval);
  1130. }
  1131. void intel_disable_fbc(struct drm_device *dev)
  1132. {
  1133. struct drm_i915_private *dev_priv = dev->dev_private;
  1134. if (!dev_priv->display.disable_fbc)
  1135. return;
  1136. dev_priv->display.disable_fbc(dev);
  1137. }
  1138. /**
  1139. * intel_update_fbc - enable/disable FBC as needed
  1140. * @crtc: CRTC to point the compressor at
  1141. * @mode: mode in use
  1142. *
  1143. * Set up the framebuffer compression hardware at mode set time. We
  1144. * enable it if possible:
  1145. * - plane A only (on pre-965)
  1146. * - no pixel mulitply/line duplication
  1147. * - no alpha buffer discard
  1148. * - no dual wide
  1149. * - framebuffer <= 2048 in width, 1536 in height
  1150. *
  1151. * We can't assume that any compression will take place (worst case),
  1152. * so the compressed buffer has to be the same size as the uncompressed
  1153. * one. It also must reside (along with the line length buffer) in
  1154. * stolen memory.
  1155. *
  1156. * We need to enable/disable FBC on a global basis.
  1157. */
  1158. static void intel_update_fbc(struct drm_crtc *crtc,
  1159. struct drm_display_mode *mode)
  1160. {
  1161. struct drm_device *dev = crtc->dev;
  1162. struct drm_i915_private *dev_priv = dev->dev_private;
  1163. struct drm_framebuffer *fb = crtc->fb;
  1164. struct intel_framebuffer *intel_fb;
  1165. struct drm_i915_gem_object *obj_priv;
  1166. struct drm_crtc *tmp_crtc;
  1167. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1168. int plane = intel_crtc->plane;
  1169. int crtcs_enabled = 0;
  1170. DRM_DEBUG_KMS("\n");
  1171. if (!i915_powersave)
  1172. return;
  1173. if (!I915_HAS_FBC(dev))
  1174. return;
  1175. if (!crtc->fb)
  1176. return;
  1177. intel_fb = to_intel_framebuffer(fb);
  1178. obj_priv = to_intel_bo(intel_fb->obj);
  1179. /*
  1180. * If FBC is already on, we just have to verify that we can
  1181. * keep it that way...
  1182. * Need to disable if:
  1183. * - more than one pipe is active
  1184. * - changing FBC params (stride, fence, mode)
  1185. * - new fb is too large to fit in compressed buffer
  1186. * - going to an unsupported config (interlace, pixel multiply, etc.)
  1187. */
  1188. list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  1189. if (tmp_crtc->enabled)
  1190. crtcs_enabled++;
  1191. }
  1192. DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
  1193. if (crtcs_enabled > 1) {
  1194. DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  1195. dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
  1196. goto out_disable;
  1197. }
  1198. if (intel_fb->obj->size > dev_priv->cfb_size) {
  1199. DRM_DEBUG_KMS("framebuffer too large, disabling "
  1200. "compression\n");
  1201. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1202. goto out_disable;
  1203. }
  1204. if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
  1205. (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
  1206. DRM_DEBUG_KMS("mode incompatible with compression, "
  1207. "disabling\n");
  1208. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  1209. goto out_disable;
  1210. }
  1211. if ((mode->hdisplay > 2048) ||
  1212. (mode->vdisplay > 1536)) {
  1213. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  1214. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  1215. goto out_disable;
  1216. }
  1217. if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
  1218. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  1219. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  1220. goto out_disable;
  1221. }
  1222. if (obj_priv->tiling_mode != I915_TILING_X) {
  1223. DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
  1224. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  1225. goto out_disable;
  1226. }
  1227. /* If the kernel debugger is active, always disable compression */
  1228. if (in_dbg_master())
  1229. goto out_disable;
  1230. if (intel_fbc_enabled(dev)) {
  1231. /* We can re-enable it in this case, but need to update pitch */
  1232. if ((fb->pitch > dev_priv->cfb_pitch) ||
  1233. (obj_priv->fence_reg != dev_priv->cfb_fence) ||
  1234. (plane != dev_priv->cfb_plane))
  1235. intel_disable_fbc(dev);
  1236. }
  1237. /* Now try to turn it back on if possible */
  1238. if (!intel_fbc_enabled(dev))
  1239. intel_enable_fbc(crtc, 500);
  1240. return;
  1241. out_disable:
  1242. /* Multiple disables should be harmless */
  1243. if (intel_fbc_enabled(dev)) {
  1244. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  1245. intel_disable_fbc(dev);
  1246. }
  1247. }
  1248. int
  1249. intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
  1250. {
  1251. struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
  1252. u32 alignment;
  1253. int ret;
  1254. switch (obj_priv->tiling_mode) {
  1255. case I915_TILING_NONE:
  1256. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1257. alignment = 128 * 1024;
  1258. else if (IS_I965G(dev))
  1259. alignment = 4 * 1024;
  1260. else
  1261. alignment = 64 * 1024;
  1262. break;
  1263. case I915_TILING_X:
  1264. /* pin() will align the object as required by fence */
  1265. alignment = 0;
  1266. break;
  1267. case I915_TILING_Y:
  1268. /* FIXME: Is this true? */
  1269. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1270. return -EINVAL;
  1271. default:
  1272. BUG();
  1273. }
  1274. ret = i915_gem_object_pin(obj, alignment);
  1275. if (ret != 0)
  1276. return ret;
  1277. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1278. * fence, whereas 965+ only requires a fence if using
  1279. * framebuffer compression. For simplicity, we always install
  1280. * a fence as the cost is not that onerous.
  1281. */
  1282. if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
  1283. obj_priv->tiling_mode != I915_TILING_NONE) {
  1284. ret = i915_gem_object_get_fence_reg(obj);
  1285. if (ret != 0) {
  1286. i915_gem_object_unpin(obj);
  1287. return ret;
  1288. }
  1289. }
  1290. return 0;
  1291. }
  1292. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1293. static int
  1294. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1295. int x, int y)
  1296. {
  1297. struct drm_device *dev = crtc->dev;
  1298. struct drm_i915_private *dev_priv = dev->dev_private;
  1299. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1300. struct intel_framebuffer *intel_fb;
  1301. struct drm_i915_gem_object *obj_priv;
  1302. struct drm_gem_object *obj;
  1303. int plane = intel_crtc->plane;
  1304. unsigned long Start, Offset;
  1305. int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
  1306. int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
  1307. int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
  1308. int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
  1309. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1310. u32 dspcntr;
  1311. switch (plane) {
  1312. case 0:
  1313. case 1:
  1314. break;
  1315. default:
  1316. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1317. return -EINVAL;
  1318. }
  1319. intel_fb = to_intel_framebuffer(fb);
  1320. obj = intel_fb->obj;
  1321. obj_priv = to_intel_bo(obj);
  1322. dspcntr = I915_READ(dspcntr_reg);
  1323. /* Mask out pixel format bits in case we change it */
  1324. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1325. switch (fb->bits_per_pixel) {
  1326. case 8:
  1327. dspcntr |= DISPPLANE_8BPP;
  1328. break;
  1329. case 16:
  1330. if (fb->depth == 15)
  1331. dspcntr |= DISPPLANE_15_16BPP;
  1332. else
  1333. dspcntr |= DISPPLANE_16BPP;
  1334. break;
  1335. case 24:
  1336. case 32:
  1337. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1338. break;
  1339. default:
  1340. DRM_ERROR("Unknown color depth\n");
  1341. return -EINVAL;
  1342. }
  1343. if (IS_I965G(dev)) {
  1344. if (obj_priv->tiling_mode != I915_TILING_NONE)
  1345. dspcntr |= DISPPLANE_TILED;
  1346. else
  1347. dspcntr &= ~DISPPLANE_TILED;
  1348. }
  1349. if (HAS_PCH_SPLIT(dev))
  1350. /* must disable */
  1351. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1352. I915_WRITE(dspcntr_reg, dspcntr);
  1353. Start = obj_priv->gtt_offset;
  1354. Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
  1355. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1356. Start, Offset, x, y, fb->pitch);
  1357. I915_WRITE(dspstride, fb->pitch);
  1358. if (IS_I965G(dev)) {
  1359. I915_WRITE(dspsurf, Start);
  1360. I915_WRITE(dsptileoff, (y << 16) | x);
  1361. I915_WRITE(dspbase, Offset);
  1362. } else {
  1363. I915_WRITE(dspbase, Start + Offset);
  1364. }
  1365. POSTING_READ(dspbase);
  1366. if (IS_I965G(dev) || plane == 0)
  1367. intel_update_fbc(crtc, &crtc->mode);
  1368. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1369. intel_increase_pllclock(crtc);
  1370. return 0;
  1371. }
  1372. static int
  1373. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1374. struct drm_framebuffer *old_fb)
  1375. {
  1376. struct drm_device *dev = crtc->dev;
  1377. struct drm_i915_master_private *master_priv;
  1378. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1379. struct intel_framebuffer *intel_fb;
  1380. struct drm_i915_gem_object *obj_priv;
  1381. struct drm_gem_object *obj;
  1382. int pipe = intel_crtc->pipe;
  1383. int plane = intel_crtc->plane;
  1384. int ret;
  1385. /* no fb bound */
  1386. if (!crtc->fb) {
  1387. DRM_DEBUG_KMS("No FB bound\n");
  1388. return 0;
  1389. }
  1390. switch (plane) {
  1391. case 0:
  1392. case 1:
  1393. break;
  1394. default:
  1395. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1396. return -EINVAL;
  1397. }
  1398. intel_fb = to_intel_framebuffer(crtc->fb);
  1399. obj = intel_fb->obj;
  1400. obj_priv = to_intel_bo(obj);
  1401. mutex_lock(&dev->struct_mutex);
  1402. ret = intel_pin_and_fence_fb_obj(dev, obj);
  1403. if (ret != 0) {
  1404. mutex_unlock(&dev->struct_mutex);
  1405. return ret;
  1406. }
  1407. ret = i915_gem_object_set_to_display_plane(obj);
  1408. if (ret != 0) {
  1409. i915_gem_object_unpin(obj);
  1410. mutex_unlock(&dev->struct_mutex);
  1411. return ret;
  1412. }
  1413. ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
  1414. if (ret) {
  1415. i915_gem_object_unpin(obj);
  1416. mutex_unlock(&dev->struct_mutex);
  1417. return ret;
  1418. }
  1419. if (old_fb) {
  1420. intel_fb = to_intel_framebuffer(old_fb);
  1421. obj_priv = to_intel_bo(intel_fb->obj);
  1422. i915_gem_object_unpin(intel_fb->obj);
  1423. }
  1424. mutex_unlock(&dev->struct_mutex);
  1425. if (!dev->primary->master)
  1426. return 0;
  1427. master_priv = dev->primary->master->driver_priv;
  1428. if (!master_priv->sarea_priv)
  1429. return 0;
  1430. if (pipe) {
  1431. master_priv->sarea_priv->pipeB_x = x;
  1432. master_priv->sarea_priv->pipeB_y = y;
  1433. } else {
  1434. master_priv->sarea_priv->pipeA_x = x;
  1435. master_priv->sarea_priv->pipeA_y = y;
  1436. }
  1437. return 0;
  1438. }
  1439. static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
  1440. {
  1441. struct drm_device *dev = crtc->dev;
  1442. struct drm_i915_private *dev_priv = dev->dev_private;
  1443. u32 dpa_ctl;
  1444. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  1445. dpa_ctl = I915_READ(DP_A);
  1446. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  1447. if (clock < 200000) {
  1448. u32 temp;
  1449. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  1450. /* workaround for 160Mhz:
  1451. 1) program 0x4600c bits 15:0 = 0x8124
  1452. 2) program 0x46010 bit 0 = 1
  1453. 3) program 0x46034 bit 24 = 1
  1454. 4) program 0x64000 bit 14 = 1
  1455. */
  1456. temp = I915_READ(0x4600c);
  1457. temp &= 0xffff0000;
  1458. I915_WRITE(0x4600c, temp | 0x8124);
  1459. temp = I915_READ(0x46010);
  1460. I915_WRITE(0x46010, temp | 1);
  1461. temp = I915_READ(0x46034);
  1462. I915_WRITE(0x46034, temp | (1 << 24));
  1463. } else {
  1464. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  1465. }
  1466. I915_WRITE(DP_A, dpa_ctl);
  1467. udelay(500);
  1468. }
  1469. /* The FDI link training functions for ILK/Ibexpeak. */
  1470. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  1471. {
  1472. struct drm_device *dev = crtc->dev;
  1473. struct drm_i915_private *dev_priv = dev->dev_private;
  1474. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1475. int pipe = intel_crtc->pipe;
  1476. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1477. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1478. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  1479. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  1480. u32 temp, tries = 0;
  1481. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1482. for train result */
  1483. temp = I915_READ(fdi_rx_imr_reg);
  1484. temp &= ~FDI_RX_SYMBOL_LOCK;
  1485. temp &= ~FDI_RX_BIT_LOCK;
  1486. I915_WRITE(fdi_rx_imr_reg, temp);
  1487. I915_READ(fdi_rx_imr_reg);
  1488. udelay(150);
  1489. /* enable CPU FDI TX and PCH FDI RX */
  1490. temp = I915_READ(fdi_tx_reg);
  1491. temp |= FDI_TX_ENABLE;
  1492. temp &= ~(7 << 19);
  1493. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1494. temp &= ~FDI_LINK_TRAIN_NONE;
  1495. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1496. I915_WRITE(fdi_tx_reg, temp);
  1497. I915_READ(fdi_tx_reg);
  1498. temp = I915_READ(fdi_rx_reg);
  1499. temp &= ~FDI_LINK_TRAIN_NONE;
  1500. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1501. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1502. I915_READ(fdi_rx_reg);
  1503. udelay(150);
  1504. for (tries = 0; tries < 5; tries++) {
  1505. temp = I915_READ(fdi_rx_iir_reg);
  1506. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1507. if ((temp & FDI_RX_BIT_LOCK)) {
  1508. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1509. I915_WRITE(fdi_rx_iir_reg,
  1510. temp | FDI_RX_BIT_LOCK);
  1511. break;
  1512. }
  1513. }
  1514. if (tries == 5)
  1515. DRM_DEBUG_KMS("FDI train 1 fail!\n");
  1516. /* Train 2 */
  1517. temp = I915_READ(fdi_tx_reg);
  1518. temp &= ~FDI_LINK_TRAIN_NONE;
  1519. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1520. I915_WRITE(fdi_tx_reg, temp);
  1521. temp = I915_READ(fdi_rx_reg);
  1522. temp &= ~FDI_LINK_TRAIN_NONE;
  1523. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1524. I915_WRITE(fdi_rx_reg, temp);
  1525. udelay(150);
  1526. tries = 0;
  1527. for (tries = 0; tries < 5; tries++) {
  1528. temp = I915_READ(fdi_rx_iir_reg);
  1529. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1530. if (temp & FDI_RX_SYMBOL_LOCK) {
  1531. I915_WRITE(fdi_rx_iir_reg,
  1532. temp | FDI_RX_SYMBOL_LOCK);
  1533. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1534. break;
  1535. }
  1536. }
  1537. if (tries == 5)
  1538. DRM_DEBUG_KMS("FDI train 2 fail!\n");
  1539. DRM_DEBUG_KMS("FDI train done\n");
  1540. }
  1541. static int snb_b_fdi_train_param [] = {
  1542. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  1543. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  1544. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  1545. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  1546. };
  1547. /* The FDI link training functions for SNB/Cougarpoint. */
  1548. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  1549. {
  1550. struct drm_device *dev = crtc->dev;
  1551. struct drm_i915_private *dev_priv = dev->dev_private;
  1552. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1553. int pipe = intel_crtc->pipe;
  1554. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1555. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1556. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  1557. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  1558. u32 temp, i;
  1559. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1560. for train result */
  1561. temp = I915_READ(fdi_rx_imr_reg);
  1562. temp &= ~FDI_RX_SYMBOL_LOCK;
  1563. temp &= ~FDI_RX_BIT_LOCK;
  1564. I915_WRITE(fdi_rx_imr_reg, temp);
  1565. I915_READ(fdi_rx_imr_reg);
  1566. udelay(150);
  1567. /* enable CPU FDI TX and PCH FDI RX */
  1568. temp = I915_READ(fdi_tx_reg);
  1569. temp |= FDI_TX_ENABLE;
  1570. temp &= ~(7 << 19);
  1571. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1572. temp &= ~FDI_LINK_TRAIN_NONE;
  1573. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1574. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1575. /* SNB-B */
  1576. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1577. I915_WRITE(fdi_tx_reg, temp);
  1578. I915_READ(fdi_tx_reg);
  1579. temp = I915_READ(fdi_rx_reg);
  1580. if (HAS_PCH_CPT(dev)) {
  1581. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1582. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1583. } else {
  1584. temp &= ~FDI_LINK_TRAIN_NONE;
  1585. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1586. }
  1587. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1588. I915_READ(fdi_rx_reg);
  1589. udelay(150);
  1590. for (i = 0; i < 4; i++ ) {
  1591. temp = I915_READ(fdi_tx_reg);
  1592. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1593. temp |= snb_b_fdi_train_param[i];
  1594. I915_WRITE(fdi_tx_reg, temp);
  1595. udelay(500);
  1596. temp = I915_READ(fdi_rx_iir_reg);
  1597. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1598. if (temp & FDI_RX_BIT_LOCK) {
  1599. I915_WRITE(fdi_rx_iir_reg,
  1600. temp | FDI_RX_BIT_LOCK);
  1601. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1602. break;
  1603. }
  1604. }
  1605. if (i == 4)
  1606. DRM_DEBUG_KMS("FDI train 1 fail!\n");
  1607. /* Train 2 */
  1608. temp = I915_READ(fdi_tx_reg);
  1609. temp &= ~FDI_LINK_TRAIN_NONE;
  1610. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1611. if (IS_GEN6(dev)) {
  1612. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1613. /* SNB-B */
  1614. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1615. }
  1616. I915_WRITE(fdi_tx_reg, temp);
  1617. temp = I915_READ(fdi_rx_reg);
  1618. if (HAS_PCH_CPT(dev)) {
  1619. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1620. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  1621. } else {
  1622. temp &= ~FDI_LINK_TRAIN_NONE;
  1623. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1624. }
  1625. I915_WRITE(fdi_rx_reg, temp);
  1626. udelay(150);
  1627. for (i = 0; i < 4; i++ ) {
  1628. temp = I915_READ(fdi_tx_reg);
  1629. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1630. temp |= snb_b_fdi_train_param[i];
  1631. I915_WRITE(fdi_tx_reg, temp);
  1632. udelay(500);
  1633. temp = I915_READ(fdi_rx_iir_reg);
  1634. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1635. if (temp & FDI_RX_SYMBOL_LOCK) {
  1636. I915_WRITE(fdi_rx_iir_reg,
  1637. temp | FDI_RX_SYMBOL_LOCK);
  1638. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1639. break;
  1640. }
  1641. }
  1642. if (i == 4)
  1643. DRM_DEBUG_KMS("FDI train 2 fail!\n");
  1644. DRM_DEBUG_KMS("FDI train done.\n");
  1645. }
  1646. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  1647. {
  1648. struct drm_device *dev = crtc->dev;
  1649. struct drm_i915_private *dev_priv = dev->dev_private;
  1650. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1651. int pipe = intel_crtc->pipe;
  1652. int plane = intel_crtc->plane;
  1653. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  1654. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1655. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1656. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1657. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1658. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1659. int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
  1660. int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  1661. int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  1662. int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  1663. int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  1664. int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  1665. int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  1666. int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
  1667. int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
  1668. int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
  1669. int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
  1670. int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
  1671. int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
  1672. int trans_dpll_sel = (pipe == 0) ? 0 : 1;
  1673. u32 temp;
  1674. u32 pipe_bpc;
  1675. temp = I915_READ(pipeconf_reg);
  1676. pipe_bpc = temp & PIPE_BPC_MASK;
  1677. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1678. temp = I915_READ(PCH_LVDS);
  1679. if ((temp & LVDS_PORT_EN) == 0) {
  1680. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  1681. POSTING_READ(PCH_LVDS);
  1682. }
  1683. }
  1684. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  1685. temp = I915_READ(fdi_rx_reg);
  1686. /*
  1687. * make the BPC in FDI Rx be consistent with that in
  1688. * pipeconf reg.
  1689. */
  1690. temp &= ~(0x7 << 16);
  1691. temp |= (pipe_bpc << 11);
  1692. temp &= ~(7 << 19);
  1693. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1694. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  1695. I915_READ(fdi_rx_reg);
  1696. udelay(200);
  1697. /* Switch from Rawclk to PCDclk */
  1698. temp = I915_READ(fdi_rx_reg);
  1699. I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
  1700. I915_READ(fdi_rx_reg);
  1701. udelay(200);
  1702. /* Enable CPU FDI TX PLL, always on for Ironlake */
  1703. temp = I915_READ(fdi_tx_reg);
  1704. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  1705. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  1706. I915_READ(fdi_tx_reg);
  1707. udelay(100);
  1708. }
  1709. /* Enable panel fitting for LVDS */
  1710. if (dev_priv->pch_pf_size &&
  1711. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
  1712. || HAS_eDP || intel_pch_has_edp(crtc))) {
  1713. /* Force use of hard-coded filter coefficients
  1714. * as some pre-programmed values are broken,
  1715. * e.g. x201.
  1716. */
  1717. I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
  1718. PF_ENABLE | PF_FILTER_MED_3x3);
  1719. I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
  1720. dev_priv->pch_pf_pos);
  1721. I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
  1722. dev_priv->pch_pf_size);
  1723. }
  1724. /* Enable CPU pipe */
  1725. temp = I915_READ(pipeconf_reg);
  1726. if ((temp & PIPEACONF_ENABLE) == 0) {
  1727. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1728. I915_READ(pipeconf_reg);
  1729. udelay(100);
  1730. }
  1731. /* configure and enable CPU plane */
  1732. temp = I915_READ(dspcntr_reg);
  1733. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1734. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1735. /* Flush the plane changes */
  1736. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1737. }
  1738. /* For PCH output, training FDI link */
  1739. if (IS_GEN6(dev))
  1740. gen6_fdi_link_train(crtc);
  1741. else
  1742. ironlake_fdi_link_train(crtc);
  1743. /* enable PCH DPLL */
  1744. temp = I915_READ(pch_dpll_reg);
  1745. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1746. I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
  1747. I915_READ(pch_dpll_reg);
  1748. }
  1749. udelay(200);
  1750. if (HAS_PCH_CPT(dev)) {
  1751. /* Be sure PCH DPLL SEL is set */
  1752. temp = I915_READ(PCH_DPLL_SEL);
  1753. if (trans_dpll_sel == 0 &&
  1754. (temp & TRANSA_DPLL_ENABLE) == 0)
  1755. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  1756. else if (trans_dpll_sel == 1 &&
  1757. (temp & TRANSB_DPLL_ENABLE) == 0)
  1758. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  1759. I915_WRITE(PCH_DPLL_SEL, temp);
  1760. I915_READ(PCH_DPLL_SEL);
  1761. }
  1762. /* set transcoder timing */
  1763. I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
  1764. I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
  1765. I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
  1766. I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
  1767. I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
  1768. I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
  1769. /* enable normal train */
  1770. temp = I915_READ(fdi_tx_reg);
  1771. temp &= ~FDI_LINK_TRAIN_NONE;
  1772. I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
  1773. FDI_TX_ENHANCE_FRAME_ENABLE);
  1774. I915_READ(fdi_tx_reg);
  1775. temp = I915_READ(fdi_rx_reg);
  1776. if (HAS_PCH_CPT(dev)) {
  1777. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1778. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  1779. } else {
  1780. temp &= ~FDI_LINK_TRAIN_NONE;
  1781. temp |= FDI_LINK_TRAIN_NONE;
  1782. }
  1783. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  1784. I915_READ(fdi_rx_reg);
  1785. /* wait one idle pattern time */
  1786. udelay(100);
  1787. /* For PCH DP, enable TRANS_DP_CTL */
  1788. if (HAS_PCH_CPT(dev) &&
  1789. intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  1790. int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
  1791. int reg;
  1792. reg = I915_READ(trans_dp_ctl);
  1793. reg &= ~(TRANS_DP_PORT_SEL_MASK |
  1794. TRANS_DP_SYNC_MASK);
  1795. reg |= (TRANS_DP_OUTPUT_ENABLE |
  1796. TRANS_DP_ENH_FRAMING);
  1797. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  1798. reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  1799. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  1800. reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  1801. switch (intel_trans_dp_port_sel(crtc)) {
  1802. case PCH_DP_B:
  1803. reg |= TRANS_DP_PORT_SEL_B;
  1804. break;
  1805. case PCH_DP_C:
  1806. reg |= TRANS_DP_PORT_SEL_C;
  1807. break;
  1808. case PCH_DP_D:
  1809. reg |= TRANS_DP_PORT_SEL_D;
  1810. break;
  1811. default:
  1812. DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
  1813. reg |= TRANS_DP_PORT_SEL_B;
  1814. break;
  1815. }
  1816. I915_WRITE(trans_dp_ctl, reg);
  1817. POSTING_READ(trans_dp_ctl);
  1818. }
  1819. /* enable PCH transcoder */
  1820. temp = I915_READ(transconf_reg);
  1821. /*
  1822. * make the BPC in transcoder be consistent with
  1823. * that in pipeconf reg.
  1824. */
  1825. temp &= ~PIPE_BPC_MASK;
  1826. temp |= pipe_bpc;
  1827. I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
  1828. I915_READ(transconf_reg);
  1829. if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100))
  1830. DRM_ERROR("failed to enable transcoder\n");
  1831. intel_crtc_load_lut(crtc);
  1832. intel_update_fbc(crtc, &crtc->mode);
  1833. }
  1834. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  1835. {
  1836. struct drm_device *dev = crtc->dev;
  1837. struct drm_i915_private *dev_priv = dev->dev_private;
  1838. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1839. int pipe = intel_crtc->pipe;
  1840. int plane = intel_crtc->plane;
  1841. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  1842. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1843. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1844. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1845. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1846. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1847. int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
  1848. int trans_dpll_sel = (pipe == 0) ? 0 : 1;
  1849. u32 temp;
  1850. u32 pipe_bpc;
  1851. temp = I915_READ(pipeconf_reg);
  1852. pipe_bpc = temp & PIPE_BPC_MASK;
  1853. drm_vblank_off(dev, pipe);
  1854. /* Disable display plane */
  1855. temp = I915_READ(dspcntr_reg);
  1856. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1857. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1858. /* Flush the plane changes */
  1859. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1860. I915_READ(dspbase_reg);
  1861. }
  1862. if (dev_priv->cfb_plane == plane &&
  1863. dev_priv->display.disable_fbc)
  1864. dev_priv->display.disable_fbc(dev);
  1865. /* disable cpu pipe, disable after all planes disabled */
  1866. temp = I915_READ(pipeconf_reg);
  1867. if ((temp & PIPEACONF_ENABLE) != 0) {
  1868. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1869. /* wait for cpu pipe off, pipe state */
  1870. if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50))
  1871. DRM_ERROR("failed to turn off cpu pipe\n");
  1872. } else
  1873. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  1874. udelay(100);
  1875. /* Disable PF */
  1876. I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
  1877. I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
  1878. /* disable CPU FDI tx and PCH FDI rx */
  1879. temp = I915_READ(fdi_tx_reg);
  1880. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
  1881. I915_READ(fdi_tx_reg);
  1882. temp = I915_READ(fdi_rx_reg);
  1883. /* BPC in FDI rx is consistent with that in pipeconf */
  1884. temp &= ~(0x07 << 16);
  1885. temp |= (pipe_bpc << 11);
  1886. I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
  1887. I915_READ(fdi_rx_reg);
  1888. udelay(100);
  1889. /* still set train pattern 1 */
  1890. temp = I915_READ(fdi_tx_reg);
  1891. temp &= ~FDI_LINK_TRAIN_NONE;
  1892. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1893. I915_WRITE(fdi_tx_reg, temp);
  1894. POSTING_READ(fdi_tx_reg);
  1895. temp = I915_READ(fdi_rx_reg);
  1896. if (HAS_PCH_CPT(dev)) {
  1897. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1898. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1899. } else {
  1900. temp &= ~FDI_LINK_TRAIN_NONE;
  1901. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1902. }
  1903. I915_WRITE(fdi_rx_reg, temp);
  1904. POSTING_READ(fdi_rx_reg);
  1905. udelay(100);
  1906. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1907. temp = I915_READ(PCH_LVDS);
  1908. I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
  1909. I915_READ(PCH_LVDS);
  1910. udelay(100);
  1911. }
  1912. /* disable PCH transcoder */
  1913. temp = I915_READ(transconf_reg);
  1914. if ((temp & TRANS_ENABLE) != 0) {
  1915. I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
  1916. /* wait for PCH transcoder off, transcoder state */
  1917. if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50))
  1918. DRM_ERROR("failed to disable transcoder\n");
  1919. }
  1920. temp = I915_READ(transconf_reg);
  1921. /* BPC in transcoder is consistent with that in pipeconf */
  1922. temp &= ~PIPE_BPC_MASK;
  1923. temp |= pipe_bpc;
  1924. I915_WRITE(transconf_reg, temp);
  1925. I915_READ(transconf_reg);
  1926. udelay(100);
  1927. if (HAS_PCH_CPT(dev)) {
  1928. /* disable TRANS_DP_CTL */
  1929. int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
  1930. int reg;
  1931. reg = I915_READ(trans_dp_ctl);
  1932. reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  1933. I915_WRITE(trans_dp_ctl, reg);
  1934. POSTING_READ(trans_dp_ctl);
  1935. /* disable DPLL_SEL */
  1936. temp = I915_READ(PCH_DPLL_SEL);
  1937. if (trans_dpll_sel == 0)
  1938. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
  1939. else
  1940. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  1941. I915_WRITE(PCH_DPLL_SEL, temp);
  1942. I915_READ(PCH_DPLL_SEL);
  1943. }
  1944. /* disable PCH DPLL */
  1945. temp = I915_READ(pch_dpll_reg);
  1946. I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1947. I915_READ(pch_dpll_reg);
  1948. /* Switch from PCDclk to Rawclk */
  1949. temp = I915_READ(fdi_rx_reg);
  1950. temp &= ~FDI_SEL_PCDCLK;
  1951. I915_WRITE(fdi_rx_reg, temp);
  1952. I915_READ(fdi_rx_reg);
  1953. /* Disable CPU FDI TX PLL */
  1954. temp = I915_READ(fdi_tx_reg);
  1955. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
  1956. I915_READ(fdi_tx_reg);
  1957. udelay(100);
  1958. temp = I915_READ(fdi_rx_reg);
  1959. temp &= ~FDI_RX_PLL_ENABLE;
  1960. I915_WRITE(fdi_rx_reg, temp);
  1961. I915_READ(fdi_rx_reg);
  1962. /* Wait for the clocks to turn off. */
  1963. udelay(100);
  1964. }
  1965. static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
  1966. {
  1967. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1968. int pipe = intel_crtc->pipe;
  1969. int plane = intel_crtc->plane;
  1970. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1971. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1972. */
  1973. switch (mode) {
  1974. case DRM_MODE_DPMS_ON:
  1975. case DRM_MODE_DPMS_STANDBY:
  1976. case DRM_MODE_DPMS_SUSPEND:
  1977. DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
  1978. ironlake_crtc_enable(crtc);
  1979. break;
  1980. case DRM_MODE_DPMS_OFF:
  1981. DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
  1982. ironlake_crtc_disable(crtc);
  1983. break;
  1984. }
  1985. }
  1986. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  1987. {
  1988. if (!enable && intel_crtc->overlay) {
  1989. struct drm_device *dev = intel_crtc->base.dev;
  1990. mutex_lock(&dev->struct_mutex);
  1991. (void) intel_overlay_switch_off(intel_crtc->overlay, false);
  1992. mutex_unlock(&dev->struct_mutex);
  1993. }
  1994. /* Let userspace switch the overlay on again. In most cases userspace
  1995. * has to recompute where to put it anyway.
  1996. */
  1997. }
  1998. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  1999. {
  2000. struct drm_device *dev = crtc->dev;
  2001. struct drm_i915_private *dev_priv = dev->dev_private;
  2002. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2003. int pipe = intel_crtc->pipe;
  2004. int plane = intel_crtc->plane;
  2005. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  2006. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  2007. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  2008. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  2009. u32 temp;
  2010. /* Enable the DPLL */
  2011. temp = I915_READ(dpll_reg);
  2012. if ((temp & DPLL_VCO_ENABLE) == 0) {
  2013. I915_WRITE(dpll_reg, temp);
  2014. I915_READ(dpll_reg);
  2015. /* Wait for the clocks to stabilize. */
  2016. udelay(150);
  2017. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  2018. I915_READ(dpll_reg);
  2019. /* Wait for the clocks to stabilize. */
  2020. udelay(150);
  2021. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  2022. I915_READ(dpll_reg);
  2023. /* Wait for the clocks to stabilize. */
  2024. udelay(150);
  2025. }
  2026. /* Enable the pipe */
  2027. temp = I915_READ(pipeconf_reg);
  2028. if ((temp & PIPEACONF_ENABLE) == 0)
  2029. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  2030. /* Enable the plane */
  2031. temp = I915_READ(dspcntr_reg);
  2032. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  2033. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  2034. /* Flush the plane changes */
  2035. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  2036. }
  2037. intel_crtc_load_lut(crtc);
  2038. if ((IS_I965G(dev) || plane == 0))
  2039. intel_update_fbc(crtc, &crtc->mode);
  2040. /* Give the overlay scaler a chance to enable if it's on this pipe */
  2041. intel_crtc_dpms_overlay(intel_crtc, true);
  2042. }
  2043. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  2044. {
  2045. struct drm_device *dev = crtc->dev;
  2046. struct drm_i915_private *dev_priv = dev->dev_private;
  2047. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2048. int pipe = intel_crtc->pipe;
  2049. int plane = intel_crtc->plane;
  2050. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  2051. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  2052. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  2053. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  2054. u32 temp;
  2055. /* Give the overlay scaler a chance to disable if it's on this pipe */
  2056. intel_crtc_dpms_overlay(intel_crtc, false);
  2057. drm_vblank_off(dev, pipe);
  2058. if (dev_priv->cfb_plane == plane &&
  2059. dev_priv->display.disable_fbc)
  2060. dev_priv->display.disable_fbc(dev);
  2061. /* Disable display plane */
  2062. temp = I915_READ(dspcntr_reg);
  2063. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  2064. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  2065. /* Flush the plane changes */
  2066. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  2067. I915_READ(dspbase_reg);
  2068. }
  2069. if (!IS_I9XX(dev)) {
  2070. /* Wait for vblank for the disable to take effect */
  2071. intel_wait_for_vblank_off(dev, pipe);
  2072. }
  2073. /* Don't disable pipe A or pipe A PLLs if needed */
  2074. if (pipeconf_reg == PIPEACONF &&
  2075. (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  2076. goto skip_pipe_off;
  2077. /* Next, disable display pipes */
  2078. temp = I915_READ(pipeconf_reg);
  2079. if ((temp & PIPEACONF_ENABLE) != 0) {
  2080. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  2081. I915_READ(pipeconf_reg);
  2082. }
  2083. /* Wait for vblank for the disable to take effect. */
  2084. intel_wait_for_vblank_off(dev, pipe);
  2085. temp = I915_READ(dpll_reg);
  2086. if ((temp & DPLL_VCO_ENABLE) != 0) {
  2087. I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
  2088. I915_READ(dpll_reg);
  2089. }
  2090. skip_pipe_off:
  2091. /* Wait for the clocks to turn off. */
  2092. udelay(150);
  2093. }
  2094. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  2095. {
  2096. /* XXX: When our outputs are all unaware of DPMS modes other than off
  2097. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  2098. */
  2099. switch (mode) {
  2100. case DRM_MODE_DPMS_ON:
  2101. case DRM_MODE_DPMS_STANDBY:
  2102. case DRM_MODE_DPMS_SUSPEND:
  2103. i9xx_crtc_enable(crtc);
  2104. break;
  2105. case DRM_MODE_DPMS_OFF:
  2106. i9xx_crtc_disable(crtc);
  2107. break;
  2108. }
  2109. }
  2110. /*
  2111. * When we disable a pipe, we need to clear any pending scanline wait events
  2112. * to avoid hanging the ring, which we assume we are waiting on.
  2113. */
  2114. static void intel_clear_scanline_wait(struct drm_device *dev)
  2115. {
  2116. struct drm_i915_private *dev_priv = dev->dev_private;
  2117. u32 tmp;
  2118. if (IS_GEN2(dev))
  2119. /* Can't break the hang on i8xx */
  2120. return;
  2121. tmp = I915_READ(PRB0_CTL);
  2122. if (tmp & RING_WAIT) {
  2123. I915_WRITE(PRB0_CTL, tmp);
  2124. POSTING_READ(PRB0_CTL);
  2125. }
  2126. }
  2127. /**
  2128. * Sets the power management mode of the pipe and plane.
  2129. */
  2130. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  2131. {
  2132. struct drm_device *dev = crtc->dev;
  2133. struct drm_i915_private *dev_priv = dev->dev_private;
  2134. struct drm_i915_master_private *master_priv;
  2135. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2136. int pipe = intel_crtc->pipe;
  2137. bool enabled;
  2138. if (intel_crtc->dpms_mode == mode)
  2139. return;
  2140. intel_crtc->dpms_mode = mode;
  2141. intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
  2142. /* When switching on the display, ensure that SR is disabled
  2143. * with multiple pipes prior to enabling to new pipe.
  2144. *
  2145. * When switching off the display, make sure the cursor is
  2146. * properly hidden and there are no pending waits prior to
  2147. * disabling the pipe.
  2148. */
  2149. if (mode == DRM_MODE_DPMS_ON)
  2150. intel_update_watermarks(dev);
  2151. else
  2152. intel_crtc_update_cursor(crtc);
  2153. dev_priv->display.dpms(crtc, mode);
  2154. if (mode == DRM_MODE_DPMS_ON)
  2155. intel_crtc_update_cursor(crtc);
  2156. else {
  2157. /* XXX Note that this is not a complete solution, but a hack
  2158. * to avoid the most frequently hit hang.
  2159. */
  2160. intel_clear_scanline_wait(dev);
  2161. intel_update_watermarks(dev);
  2162. }
  2163. if (!dev->primary->master)
  2164. return;
  2165. master_priv = dev->primary->master->driver_priv;
  2166. if (!master_priv->sarea_priv)
  2167. return;
  2168. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  2169. switch (pipe) {
  2170. case 0:
  2171. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  2172. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  2173. break;
  2174. case 1:
  2175. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  2176. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  2177. break;
  2178. default:
  2179. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  2180. break;
  2181. }
  2182. }
  2183. /* Prepare for a mode set.
  2184. *
  2185. * Note we could be a lot smarter here. We need to figure out which outputs
  2186. * will be enabled, which disabled (in short, how the config will changes)
  2187. * and perform the minimum necessary steps to accomplish that, e.g. updating
  2188. * watermarks, FBC configuration, making sure PLLs are programmed correctly,
  2189. * panel fitting is in the proper state, etc.
  2190. */
  2191. static void i9xx_crtc_prepare(struct drm_crtc *crtc)
  2192. {
  2193. struct drm_device *dev = crtc->dev;
  2194. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2195. intel_crtc->cursor_on = false;
  2196. intel_crtc_update_cursor(crtc);
  2197. i9xx_crtc_disable(crtc);
  2198. intel_clear_scanline_wait(dev);
  2199. }
  2200. static void i9xx_crtc_commit(struct drm_crtc *crtc)
  2201. {
  2202. struct drm_device *dev = crtc->dev;
  2203. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2204. intel_update_watermarks(dev);
  2205. i9xx_crtc_enable(crtc);
  2206. intel_crtc->cursor_on = true;
  2207. intel_crtc_update_cursor(crtc);
  2208. }
  2209. static void ironlake_crtc_prepare(struct drm_crtc *crtc)
  2210. {
  2211. struct drm_device *dev = crtc->dev;
  2212. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2213. intel_crtc->cursor_on = false;
  2214. intel_crtc_update_cursor(crtc);
  2215. ironlake_crtc_disable(crtc);
  2216. intel_clear_scanline_wait(dev);
  2217. }
  2218. static void ironlake_crtc_commit(struct drm_crtc *crtc)
  2219. {
  2220. struct drm_device *dev = crtc->dev;
  2221. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2222. intel_update_watermarks(dev);
  2223. ironlake_crtc_enable(crtc);
  2224. intel_crtc->cursor_on = true;
  2225. intel_crtc_update_cursor(crtc);
  2226. }
  2227. void intel_encoder_prepare (struct drm_encoder *encoder)
  2228. {
  2229. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2230. /* lvds has its own version of prepare see intel_lvds_prepare */
  2231. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  2232. }
  2233. void intel_encoder_commit (struct drm_encoder *encoder)
  2234. {
  2235. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2236. /* lvds has its own version of commit see intel_lvds_commit */
  2237. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  2238. }
  2239. void intel_encoder_destroy(struct drm_encoder *encoder)
  2240. {
  2241. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  2242. if (intel_encoder->ddc_bus)
  2243. intel_i2c_destroy(intel_encoder->ddc_bus);
  2244. if (intel_encoder->i2c_bus)
  2245. intel_i2c_destroy(intel_encoder->i2c_bus);
  2246. drm_encoder_cleanup(encoder);
  2247. kfree(intel_encoder);
  2248. }
  2249. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  2250. struct drm_display_mode *mode,
  2251. struct drm_display_mode *adjusted_mode)
  2252. {
  2253. struct drm_device *dev = crtc->dev;
  2254. if (HAS_PCH_SPLIT(dev)) {
  2255. /* FDI link clock is fixed at 2.7G */
  2256. if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
  2257. return false;
  2258. }
  2259. return true;
  2260. }
  2261. static int i945_get_display_clock_speed(struct drm_device *dev)
  2262. {
  2263. return 400000;
  2264. }
  2265. static int i915_get_display_clock_speed(struct drm_device *dev)
  2266. {
  2267. return 333000;
  2268. }
  2269. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  2270. {
  2271. return 200000;
  2272. }
  2273. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  2274. {
  2275. u16 gcfgc = 0;
  2276. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  2277. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  2278. return 133000;
  2279. else {
  2280. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  2281. case GC_DISPLAY_CLOCK_333_MHZ:
  2282. return 333000;
  2283. default:
  2284. case GC_DISPLAY_CLOCK_190_200_MHZ:
  2285. return 190000;
  2286. }
  2287. }
  2288. }
  2289. static int i865_get_display_clock_speed(struct drm_device *dev)
  2290. {
  2291. return 266000;
  2292. }
  2293. static int i855_get_display_clock_speed(struct drm_device *dev)
  2294. {
  2295. u16 hpllcc = 0;
  2296. /* Assume that the hardware is in the high speed state. This
  2297. * should be the default.
  2298. */
  2299. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  2300. case GC_CLOCK_133_200:
  2301. case GC_CLOCK_100_200:
  2302. return 200000;
  2303. case GC_CLOCK_166_250:
  2304. return 250000;
  2305. case GC_CLOCK_100_133:
  2306. return 133000;
  2307. }
  2308. /* Shouldn't happen */
  2309. return 0;
  2310. }
  2311. static int i830_get_display_clock_speed(struct drm_device *dev)
  2312. {
  2313. return 133000;
  2314. }
  2315. /**
  2316. * Return the pipe currently connected to the panel fitter,
  2317. * or -1 if the panel fitter is not present or not in use
  2318. */
  2319. int intel_panel_fitter_pipe (struct drm_device *dev)
  2320. {
  2321. struct drm_i915_private *dev_priv = dev->dev_private;
  2322. u32 pfit_control;
  2323. /* i830 doesn't have a panel fitter */
  2324. if (IS_I830(dev))
  2325. return -1;
  2326. pfit_control = I915_READ(PFIT_CONTROL);
  2327. /* See if the panel fitter is in use */
  2328. if ((pfit_control & PFIT_ENABLE) == 0)
  2329. return -1;
  2330. /* 965 can place panel fitter on either pipe */
  2331. if (IS_I965G(dev))
  2332. return (pfit_control >> 29) & 0x3;
  2333. /* older chips can only use pipe 1 */
  2334. return 1;
  2335. }
  2336. struct fdi_m_n {
  2337. u32 tu;
  2338. u32 gmch_m;
  2339. u32 gmch_n;
  2340. u32 link_m;
  2341. u32 link_n;
  2342. };
  2343. static void
  2344. fdi_reduce_ratio(u32 *num, u32 *den)
  2345. {
  2346. while (*num > 0xffffff || *den > 0xffffff) {
  2347. *num >>= 1;
  2348. *den >>= 1;
  2349. }
  2350. }
  2351. #define DATA_N 0x800000
  2352. #define LINK_N 0x80000
  2353. static void
  2354. ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
  2355. int link_clock, struct fdi_m_n *m_n)
  2356. {
  2357. u64 temp;
  2358. m_n->tu = 64; /* default size */
  2359. temp = (u64) DATA_N * pixel_clock;
  2360. temp = div_u64(temp, link_clock);
  2361. m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
  2362. m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
  2363. m_n->gmch_n = DATA_N;
  2364. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  2365. temp = (u64) LINK_N * pixel_clock;
  2366. m_n->link_m = div_u64(temp, link_clock);
  2367. m_n->link_n = LINK_N;
  2368. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  2369. }
  2370. struct intel_watermark_params {
  2371. unsigned long fifo_size;
  2372. unsigned long max_wm;
  2373. unsigned long default_wm;
  2374. unsigned long guard_size;
  2375. unsigned long cacheline_size;
  2376. };
  2377. /* Pineview has different values for various configs */
  2378. static struct intel_watermark_params pineview_display_wm = {
  2379. PINEVIEW_DISPLAY_FIFO,
  2380. PINEVIEW_MAX_WM,
  2381. PINEVIEW_DFT_WM,
  2382. PINEVIEW_GUARD_WM,
  2383. PINEVIEW_FIFO_LINE_SIZE
  2384. };
  2385. static struct intel_watermark_params pineview_display_hplloff_wm = {
  2386. PINEVIEW_DISPLAY_FIFO,
  2387. PINEVIEW_MAX_WM,
  2388. PINEVIEW_DFT_HPLLOFF_WM,
  2389. PINEVIEW_GUARD_WM,
  2390. PINEVIEW_FIFO_LINE_SIZE
  2391. };
  2392. static struct intel_watermark_params pineview_cursor_wm = {
  2393. PINEVIEW_CURSOR_FIFO,
  2394. PINEVIEW_CURSOR_MAX_WM,
  2395. PINEVIEW_CURSOR_DFT_WM,
  2396. PINEVIEW_CURSOR_GUARD_WM,
  2397. PINEVIEW_FIFO_LINE_SIZE,
  2398. };
  2399. static struct intel_watermark_params pineview_cursor_hplloff_wm = {
  2400. PINEVIEW_CURSOR_FIFO,
  2401. PINEVIEW_CURSOR_MAX_WM,
  2402. PINEVIEW_CURSOR_DFT_WM,
  2403. PINEVIEW_CURSOR_GUARD_WM,
  2404. PINEVIEW_FIFO_LINE_SIZE
  2405. };
  2406. static struct intel_watermark_params g4x_wm_info = {
  2407. G4X_FIFO_SIZE,
  2408. G4X_MAX_WM,
  2409. G4X_MAX_WM,
  2410. 2,
  2411. G4X_FIFO_LINE_SIZE,
  2412. };
  2413. static struct intel_watermark_params g4x_cursor_wm_info = {
  2414. I965_CURSOR_FIFO,
  2415. I965_CURSOR_MAX_WM,
  2416. I965_CURSOR_DFT_WM,
  2417. 2,
  2418. G4X_FIFO_LINE_SIZE,
  2419. };
  2420. static struct intel_watermark_params i965_cursor_wm_info = {
  2421. I965_CURSOR_FIFO,
  2422. I965_CURSOR_MAX_WM,
  2423. I965_CURSOR_DFT_WM,
  2424. 2,
  2425. I915_FIFO_LINE_SIZE,
  2426. };
  2427. static struct intel_watermark_params i945_wm_info = {
  2428. I945_FIFO_SIZE,
  2429. I915_MAX_WM,
  2430. 1,
  2431. 2,
  2432. I915_FIFO_LINE_SIZE
  2433. };
  2434. static struct intel_watermark_params i915_wm_info = {
  2435. I915_FIFO_SIZE,
  2436. I915_MAX_WM,
  2437. 1,
  2438. 2,
  2439. I915_FIFO_LINE_SIZE
  2440. };
  2441. static struct intel_watermark_params i855_wm_info = {
  2442. I855GM_FIFO_SIZE,
  2443. I915_MAX_WM,
  2444. 1,
  2445. 2,
  2446. I830_FIFO_LINE_SIZE
  2447. };
  2448. static struct intel_watermark_params i830_wm_info = {
  2449. I830_FIFO_SIZE,
  2450. I915_MAX_WM,
  2451. 1,
  2452. 2,
  2453. I830_FIFO_LINE_SIZE
  2454. };
  2455. static struct intel_watermark_params ironlake_display_wm_info = {
  2456. ILK_DISPLAY_FIFO,
  2457. ILK_DISPLAY_MAXWM,
  2458. ILK_DISPLAY_DFTWM,
  2459. 2,
  2460. ILK_FIFO_LINE_SIZE
  2461. };
  2462. static struct intel_watermark_params ironlake_cursor_wm_info = {
  2463. ILK_CURSOR_FIFO,
  2464. ILK_CURSOR_MAXWM,
  2465. ILK_CURSOR_DFTWM,
  2466. 2,
  2467. ILK_FIFO_LINE_SIZE
  2468. };
  2469. static struct intel_watermark_params ironlake_display_srwm_info = {
  2470. ILK_DISPLAY_SR_FIFO,
  2471. ILK_DISPLAY_MAX_SRWM,
  2472. ILK_DISPLAY_DFT_SRWM,
  2473. 2,
  2474. ILK_FIFO_LINE_SIZE
  2475. };
  2476. static struct intel_watermark_params ironlake_cursor_srwm_info = {
  2477. ILK_CURSOR_SR_FIFO,
  2478. ILK_CURSOR_MAX_SRWM,
  2479. ILK_CURSOR_DFT_SRWM,
  2480. 2,
  2481. ILK_FIFO_LINE_SIZE
  2482. };
  2483. /**
  2484. * intel_calculate_wm - calculate watermark level
  2485. * @clock_in_khz: pixel clock
  2486. * @wm: chip FIFO params
  2487. * @pixel_size: display pixel size
  2488. * @latency_ns: memory latency for the platform
  2489. *
  2490. * Calculate the watermark level (the level at which the display plane will
  2491. * start fetching from memory again). Each chip has a different display
  2492. * FIFO size and allocation, so the caller needs to figure that out and pass
  2493. * in the correct intel_watermark_params structure.
  2494. *
  2495. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  2496. * on the pixel size. When it reaches the watermark level, it'll start
  2497. * fetching FIFO line sized based chunks from memory until the FIFO fills
  2498. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  2499. * will occur, and a display engine hang could result.
  2500. */
  2501. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  2502. struct intel_watermark_params *wm,
  2503. int pixel_size,
  2504. unsigned long latency_ns)
  2505. {
  2506. long entries_required, wm_size;
  2507. /*
  2508. * Note: we need to make sure we don't overflow for various clock &
  2509. * latency values.
  2510. * clocks go from a few thousand to several hundred thousand.
  2511. * latency is usually a few thousand
  2512. */
  2513. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  2514. 1000;
  2515. entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  2516. DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
  2517. wm_size = wm->fifo_size - (entries_required + wm->guard_size);
  2518. DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
  2519. /* Don't promote wm_size to unsigned... */
  2520. if (wm_size > (long)wm->max_wm)
  2521. wm_size = wm->max_wm;
  2522. if (wm_size <= 0)
  2523. wm_size = wm->default_wm;
  2524. return wm_size;
  2525. }
  2526. struct cxsr_latency {
  2527. int is_desktop;
  2528. int is_ddr3;
  2529. unsigned long fsb_freq;
  2530. unsigned long mem_freq;
  2531. unsigned long display_sr;
  2532. unsigned long display_hpll_disable;
  2533. unsigned long cursor_sr;
  2534. unsigned long cursor_hpll_disable;
  2535. };
  2536. static const struct cxsr_latency cxsr_latency_table[] = {
  2537. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  2538. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  2539. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  2540. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  2541. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  2542. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  2543. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  2544. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  2545. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  2546. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  2547. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  2548. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  2549. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  2550. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  2551. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  2552. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  2553. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  2554. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  2555. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  2556. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  2557. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  2558. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  2559. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  2560. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  2561. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  2562. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  2563. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  2564. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  2565. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  2566. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  2567. };
  2568. static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
  2569. int is_ddr3,
  2570. int fsb,
  2571. int mem)
  2572. {
  2573. const struct cxsr_latency *latency;
  2574. int i;
  2575. if (fsb == 0 || mem == 0)
  2576. return NULL;
  2577. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  2578. latency = &cxsr_latency_table[i];
  2579. if (is_desktop == latency->is_desktop &&
  2580. is_ddr3 == latency->is_ddr3 &&
  2581. fsb == latency->fsb_freq && mem == latency->mem_freq)
  2582. return latency;
  2583. }
  2584. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2585. return NULL;
  2586. }
  2587. static void pineview_disable_cxsr(struct drm_device *dev)
  2588. {
  2589. struct drm_i915_private *dev_priv = dev->dev_private;
  2590. /* deactivate cxsr */
  2591. I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
  2592. }
  2593. /*
  2594. * Latency for FIFO fetches is dependent on several factors:
  2595. * - memory configuration (speed, channels)
  2596. * - chipset
  2597. * - current MCH state
  2598. * It can be fairly high in some situations, so here we assume a fairly
  2599. * pessimal value. It's a tradeoff between extra memory fetches (if we
  2600. * set this value too high, the FIFO will fetch frequently to stay full)
  2601. * and power consumption (set it too low to save power and we might see
  2602. * FIFO underruns and display "flicker").
  2603. *
  2604. * A value of 5us seems to be a good balance; safe for very low end
  2605. * platforms but not overly aggressive on lower latency configs.
  2606. */
  2607. static const int latency_ns = 5000;
  2608. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  2609. {
  2610. struct drm_i915_private *dev_priv = dev->dev_private;
  2611. uint32_t dsparb = I915_READ(DSPARB);
  2612. int size;
  2613. size = dsparb & 0x7f;
  2614. if (plane)
  2615. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  2616. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2617. plane ? "B" : "A", size);
  2618. return size;
  2619. }
  2620. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  2621. {
  2622. struct drm_i915_private *dev_priv = dev->dev_private;
  2623. uint32_t dsparb = I915_READ(DSPARB);
  2624. int size;
  2625. size = dsparb & 0x1ff;
  2626. if (plane)
  2627. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  2628. size >>= 1; /* Convert to cachelines */
  2629. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2630. plane ? "B" : "A", size);
  2631. return size;
  2632. }
  2633. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  2634. {
  2635. struct drm_i915_private *dev_priv = dev->dev_private;
  2636. uint32_t dsparb = I915_READ(DSPARB);
  2637. int size;
  2638. size = dsparb & 0x7f;
  2639. size >>= 2; /* Convert to cachelines */
  2640. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2641. plane ? "B" : "A",
  2642. size);
  2643. return size;
  2644. }
  2645. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  2646. {
  2647. struct drm_i915_private *dev_priv = dev->dev_private;
  2648. uint32_t dsparb = I915_READ(DSPARB);
  2649. int size;
  2650. size = dsparb & 0x7f;
  2651. size >>= 1; /* Convert to cachelines */
  2652. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2653. plane ? "B" : "A", size);
  2654. return size;
  2655. }
  2656. static void pineview_update_wm(struct drm_device *dev, int planea_clock,
  2657. int planeb_clock, int sr_hdisplay, int unused,
  2658. int pixel_size)
  2659. {
  2660. struct drm_i915_private *dev_priv = dev->dev_private;
  2661. const struct cxsr_latency *latency;
  2662. u32 reg;
  2663. unsigned long wm;
  2664. int sr_clock;
  2665. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  2666. dev_priv->fsb_freq, dev_priv->mem_freq);
  2667. if (!latency) {
  2668. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2669. pineview_disable_cxsr(dev);
  2670. return;
  2671. }
  2672. if (!planea_clock || !planeb_clock) {
  2673. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2674. /* Display SR */
  2675. wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
  2676. pixel_size, latency->display_sr);
  2677. reg = I915_READ(DSPFW1);
  2678. reg &= ~DSPFW_SR_MASK;
  2679. reg |= wm << DSPFW_SR_SHIFT;
  2680. I915_WRITE(DSPFW1, reg);
  2681. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  2682. /* cursor SR */
  2683. wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
  2684. pixel_size, latency->cursor_sr);
  2685. reg = I915_READ(DSPFW3);
  2686. reg &= ~DSPFW_CURSOR_SR_MASK;
  2687. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  2688. I915_WRITE(DSPFW3, reg);
  2689. /* Display HPLL off SR */
  2690. wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
  2691. pixel_size, latency->display_hpll_disable);
  2692. reg = I915_READ(DSPFW3);
  2693. reg &= ~DSPFW_HPLL_SR_MASK;
  2694. reg |= wm & DSPFW_HPLL_SR_MASK;
  2695. I915_WRITE(DSPFW3, reg);
  2696. /* cursor HPLL off SR */
  2697. wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
  2698. pixel_size, latency->cursor_hpll_disable);
  2699. reg = I915_READ(DSPFW3);
  2700. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  2701. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  2702. I915_WRITE(DSPFW3, reg);
  2703. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  2704. /* activate cxsr */
  2705. I915_WRITE(DSPFW3,
  2706. I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
  2707. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  2708. } else {
  2709. pineview_disable_cxsr(dev);
  2710. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  2711. }
  2712. }
  2713. static void g4x_update_wm(struct drm_device *dev, int planea_clock,
  2714. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2715. int pixel_size)
  2716. {
  2717. struct drm_i915_private *dev_priv = dev->dev_private;
  2718. int total_size, cacheline_size;
  2719. int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
  2720. struct intel_watermark_params planea_params, planeb_params;
  2721. unsigned long line_time_us;
  2722. int sr_clock, sr_entries = 0, entries_required;
  2723. /* Create copies of the base settings for each pipe */
  2724. planea_params = planeb_params = g4x_wm_info;
  2725. /* Grab a couple of global values before we overwrite them */
  2726. total_size = planea_params.fifo_size;
  2727. cacheline_size = planea_params.cacheline_size;
  2728. /*
  2729. * Note: we need to make sure we don't overflow for various clock &
  2730. * latency values.
  2731. * clocks go from a few thousand to several hundred thousand.
  2732. * latency is usually a few thousand
  2733. */
  2734. entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
  2735. 1000;
  2736. entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
  2737. planea_wm = entries_required + planea_params.guard_size;
  2738. entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
  2739. 1000;
  2740. entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
  2741. planeb_wm = entries_required + planeb_params.guard_size;
  2742. cursora_wm = cursorb_wm = 16;
  2743. cursor_sr = 32;
  2744. DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2745. /* Calc sr entries for one plane configs */
  2746. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2747. /* self-refresh has much higher latency */
  2748. static const int sr_latency_ns = 12000;
  2749. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2750. line_time_us = ((sr_htotal * 1000) / sr_clock);
  2751. /* Use ns/us then divide to preserve precision */
  2752. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2753. pixel_size * sr_hdisplay;
  2754. sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
  2755. entries_required = (((sr_latency_ns / line_time_us) +
  2756. 1000) / 1000) * pixel_size * 64;
  2757. entries_required = DIV_ROUND_UP(entries_required,
  2758. g4x_cursor_wm_info.cacheline_size);
  2759. cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
  2760. if (cursor_sr > g4x_cursor_wm_info.max_wm)
  2761. cursor_sr = g4x_cursor_wm_info.max_wm;
  2762. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  2763. "cursor %d\n", sr_entries, cursor_sr);
  2764. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2765. } else {
  2766. /* Turn off self refresh if both pipes are enabled */
  2767. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2768. & ~FW_BLC_SELF_EN);
  2769. }
  2770. DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
  2771. planea_wm, planeb_wm, sr_entries);
  2772. planea_wm &= 0x3f;
  2773. planeb_wm &= 0x3f;
  2774. I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
  2775. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  2776. (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
  2777. I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  2778. (cursora_wm << DSPFW_CURSORA_SHIFT));
  2779. /* HPLL off in SR has some issues on G4x... disable it */
  2780. I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  2781. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  2782. }
  2783. static void i965_update_wm(struct drm_device *dev, int planea_clock,
  2784. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2785. int pixel_size)
  2786. {
  2787. struct drm_i915_private *dev_priv = dev->dev_private;
  2788. unsigned long line_time_us;
  2789. int sr_clock, sr_entries, srwm = 1;
  2790. int cursor_sr = 16;
  2791. /* Calc sr entries for one plane configs */
  2792. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2793. /* self-refresh has much higher latency */
  2794. static const int sr_latency_ns = 12000;
  2795. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2796. line_time_us = ((sr_htotal * 1000) / sr_clock);
  2797. /* Use ns/us then divide to preserve precision */
  2798. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2799. pixel_size * sr_hdisplay;
  2800. sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
  2801. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2802. srwm = I965_FIFO_SIZE - sr_entries;
  2803. if (srwm < 0)
  2804. srwm = 1;
  2805. srwm &= 0x1ff;
  2806. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2807. pixel_size * 64;
  2808. sr_entries = DIV_ROUND_UP(sr_entries,
  2809. i965_cursor_wm_info.cacheline_size);
  2810. cursor_sr = i965_cursor_wm_info.fifo_size -
  2811. (sr_entries + i965_cursor_wm_info.guard_size);
  2812. if (cursor_sr > i965_cursor_wm_info.max_wm)
  2813. cursor_sr = i965_cursor_wm_info.max_wm;
  2814. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  2815. "cursor %d\n", srwm, cursor_sr);
  2816. if (IS_I965GM(dev))
  2817. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2818. } else {
  2819. /* Turn off self refresh if both pipes are enabled */
  2820. if (IS_I965GM(dev))
  2821. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2822. & ~FW_BLC_SELF_EN);
  2823. }
  2824. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  2825. srwm);
  2826. /* 965 has limitations... */
  2827. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
  2828. (8 << 0));
  2829. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  2830. /* update cursor SR watermark */
  2831. I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  2832. }
  2833. static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
  2834. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2835. int pixel_size)
  2836. {
  2837. struct drm_i915_private *dev_priv = dev->dev_private;
  2838. uint32_t fwater_lo;
  2839. uint32_t fwater_hi;
  2840. int total_size, cacheline_size, cwm, srwm = 1;
  2841. int planea_wm, planeb_wm;
  2842. struct intel_watermark_params planea_params, planeb_params;
  2843. unsigned long line_time_us;
  2844. int sr_clock, sr_entries = 0;
  2845. /* Create copies of the base settings for each pipe */
  2846. if (IS_I965GM(dev) || IS_I945GM(dev))
  2847. planea_params = planeb_params = i945_wm_info;
  2848. else if (IS_I9XX(dev))
  2849. planea_params = planeb_params = i915_wm_info;
  2850. else
  2851. planea_params = planeb_params = i855_wm_info;
  2852. /* Grab a couple of global values before we overwrite them */
  2853. total_size = planea_params.fifo_size;
  2854. cacheline_size = planea_params.cacheline_size;
  2855. /* Update per-plane FIFO sizes */
  2856. planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2857. planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  2858. planea_wm = intel_calculate_wm(planea_clock, &planea_params,
  2859. pixel_size, latency_ns);
  2860. planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
  2861. pixel_size, latency_ns);
  2862. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2863. /*
  2864. * Overlay gets an aggressive default since video jitter is bad.
  2865. */
  2866. cwm = 2;
  2867. /* Calc sr entries for one plane configs */
  2868. if (HAS_FW_BLC(dev) && sr_hdisplay &&
  2869. (!planea_clock || !planeb_clock)) {
  2870. /* self-refresh has much higher latency */
  2871. static const int sr_latency_ns = 6000;
  2872. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2873. line_time_us = ((sr_htotal * 1000) / sr_clock);
  2874. /* Use ns/us then divide to preserve precision */
  2875. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2876. pixel_size * sr_hdisplay;
  2877. sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
  2878. DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
  2879. srwm = total_size - sr_entries;
  2880. if (srwm < 0)
  2881. srwm = 1;
  2882. if (IS_I945G(dev) || IS_I945GM(dev))
  2883. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  2884. else if (IS_I915GM(dev)) {
  2885. /* 915M has a smaller SRWM field */
  2886. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  2887. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  2888. }
  2889. } else {
  2890. /* Turn off self refresh if both pipes are enabled */
  2891. if (IS_I945G(dev) || IS_I945GM(dev)) {
  2892. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2893. & ~FW_BLC_SELF_EN);
  2894. } else if (IS_I915GM(dev)) {
  2895. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  2896. }
  2897. }
  2898. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  2899. planea_wm, planeb_wm, cwm, srwm);
  2900. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  2901. fwater_hi = (cwm & 0x1f);
  2902. /* Set request length to 8 cachelines per fetch */
  2903. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  2904. fwater_hi = fwater_hi | (1 << 8);
  2905. I915_WRITE(FW_BLC, fwater_lo);
  2906. I915_WRITE(FW_BLC2, fwater_hi);
  2907. }
  2908. static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
  2909. int unused2, int unused3, int pixel_size)
  2910. {
  2911. struct drm_i915_private *dev_priv = dev->dev_private;
  2912. uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  2913. int planea_wm;
  2914. i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2915. planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
  2916. pixel_size, latency_ns);
  2917. fwater_lo |= (3<<8) | planea_wm;
  2918. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  2919. I915_WRITE(FW_BLC, fwater_lo);
  2920. }
  2921. #define ILK_LP0_PLANE_LATENCY 700
  2922. #define ILK_LP0_CURSOR_LATENCY 1300
  2923. static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
  2924. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2925. int pixel_size)
  2926. {
  2927. struct drm_i915_private *dev_priv = dev->dev_private;
  2928. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  2929. int sr_wm, cursor_wm;
  2930. unsigned long line_time_us;
  2931. int sr_clock, entries_required;
  2932. u32 reg_value;
  2933. int line_count;
  2934. int planea_htotal = 0, planeb_htotal = 0;
  2935. struct drm_crtc *crtc;
  2936. /* Need htotal for all active display plane */
  2937. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2938. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2939. if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
  2940. if (intel_crtc->plane == 0)
  2941. planea_htotal = crtc->mode.htotal;
  2942. else
  2943. planeb_htotal = crtc->mode.htotal;
  2944. }
  2945. }
  2946. /* Calculate and update the watermark for plane A */
  2947. if (planea_clock) {
  2948. entries_required = ((planea_clock / 1000) * pixel_size *
  2949. ILK_LP0_PLANE_LATENCY) / 1000;
  2950. entries_required = DIV_ROUND_UP(entries_required,
  2951. ironlake_display_wm_info.cacheline_size);
  2952. planea_wm = entries_required +
  2953. ironlake_display_wm_info.guard_size;
  2954. if (planea_wm > (int)ironlake_display_wm_info.max_wm)
  2955. planea_wm = ironlake_display_wm_info.max_wm;
  2956. /* Use the large buffer method to calculate cursor watermark */
  2957. line_time_us = (planea_htotal * 1000) / planea_clock;
  2958. /* Use ns/us then divide to preserve precision */
  2959. line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
  2960. /* calculate the cursor watermark for cursor A */
  2961. entries_required = line_count * 64 * pixel_size;
  2962. entries_required = DIV_ROUND_UP(entries_required,
  2963. ironlake_cursor_wm_info.cacheline_size);
  2964. cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
  2965. if (cursora_wm > ironlake_cursor_wm_info.max_wm)
  2966. cursora_wm = ironlake_cursor_wm_info.max_wm;
  2967. reg_value = I915_READ(WM0_PIPEA_ILK);
  2968. reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  2969. reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
  2970. (cursora_wm & WM0_PIPE_CURSOR_MASK);
  2971. I915_WRITE(WM0_PIPEA_ILK, reg_value);
  2972. DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
  2973. "cursor: %d\n", planea_wm, cursora_wm);
  2974. }
  2975. /* Calculate and update the watermark for plane B */
  2976. if (planeb_clock) {
  2977. entries_required = ((planeb_clock / 1000) * pixel_size *
  2978. ILK_LP0_PLANE_LATENCY) / 1000;
  2979. entries_required = DIV_ROUND_UP(entries_required,
  2980. ironlake_display_wm_info.cacheline_size);
  2981. planeb_wm = entries_required +
  2982. ironlake_display_wm_info.guard_size;
  2983. if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
  2984. planeb_wm = ironlake_display_wm_info.max_wm;
  2985. /* Use the large buffer method to calculate cursor watermark */
  2986. line_time_us = (planeb_htotal * 1000) / planeb_clock;
  2987. /* Use ns/us then divide to preserve precision */
  2988. line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
  2989. /* calculate the cursor watermark for cursor B */
  2990. entries_required = line_count * 64 * pixel_size;
  2991. entries_required = DIV_ROUND_UP(entries_required,
  2992. ironlake_cursor_wm_info.cacheline_size);
  2993. cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
  2994. if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
  2995. cursorb_wm = ironlake_cursor_wm_info.max_wm;
  2996. reg_value = I915_READ(WM0_PIPEB_ILK);
  2997. reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  2998. reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
  2999. (cursorb_wm & WM0_PIPE_CURSOR_MASK);
  3000. I915_WRITE(WM0_PIPEB_ILK, reg_value);
  3001. DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
  3002. "cursor: %d\n", planeb_wm, cursorb_wm);
  3003. }
  3004. /*
  3005. * Calculate and update the self-refresh watermark only when one
  3006. * display plane is used.
  3007. */
  3008. if (!planea_clock || !planeb_clock) {
  3009. /* Read the self-refresh latency. The unit is 0.5us */
  3010. int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
  3011. sr_clock = planea_clock ? planea_clock : planeb_clock;
  3012. line_time_us = ((sr_htotal * 1000) / sr_clock);
  3013. /* Use ns/us then divide to preserve precision */
  3014. line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
  3015. / 1000;
  3016. /* calculate the self-refresh watermark for display plane */
  3017. entries_required = line_count * sr_hdisplay * pixel_size;
  3018. entries_required = DIV_ROUND_UP(entries_required,
  3019. ironlake_display_srwm_info.cacheline_size);
  3020. sr_wm = entries_required +
  3021. ironlake_display_srwm_info.guard_size;
  3022. /* calculate the self-refresh watermark for display cursor */
  3023. entries_required = line_count * pixel_size * 64;
  3024. entries_required = DIV_ROUND_UP(entries_required,
  3025. ironlake_cursor_srwm_info.cacheline_size);
  3026. cursor_wm = entries_required +
  3027. ironlake_cursor_srwm_info.guard_size;
  3028. /* configure watermark and enable self-refresh */
  3029. reg_value = I915_READ(WM1_LP_ILK);
  3030. reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
  3031. WM1_LP_CURSOR_MASK);
  3032. reg_value |= WM1_LP_SR_EN |
  3033. (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
  3034. (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
  3035. I915_WRITE(WM1_LP_ILK, reg_value);
  3036. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  3037. "cursor %d\n", sr_wm, cursor_wm);
  3038. } else {
  3039. /* Turn off self refresh if both pipes are enabled */
  3040. I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
  3041. }
  3042. }
  3043. /**
  3044. * intel_update_watermarks - update FIFO watermark values based on current modes
  3045. *
  3046. * Calculate watermark values for the various WM regs based on current mode
  3047. * and plane configuration.
  3048. *
  3049. * There are several cases to deal with here:
  3050. * - normal (i.e. non-self-refresh)
  3051. * - self-refresh (SR) mode
  3052. * - lines are large relative to FIFO size (buffer can hold up to 2)
  3053. * - lines are small relative to FIFO size (buffer can hold more than 2
  3054. * lines), so need to account for TLB latency
  3055. *
  3056. * The normal calculation is:
  3057. * watermark = dotclock * bytes per pixel * latency
  3058. * where latency is platform & configuration dependent (we assume pessimal
  3059. * values here).
  3060. *
  3061. * The SR calculation is:
  3062. * watermark = (trunc(latency/line time)+1) * surface width *
  3063. * bytes per pixel
  3064. * where
  3065. * line time = htotal / dotclock
  3066. * surface width = hdisplay for normal plane and 64 for cursor
  3067. * and latency is assumed to be high, as above.
  3068. *
  3069. * The final value programmed to the register should always be rounded up,
  3070. * and include an extra 2 entries to account for clock crossings.
  3071. *
  3072. * We don't use the sprite, so we can ignore that. And on Crestline we have
  3073. * to set the non-SR watermarks to 8.
  3074. */
  3075. static void intel_update_watermarks(struct drm_device *dev)
  3076. {
  3077. struct drm_i915_private *dev_priv = dev->dev_private;
  3078. struct drm_crtc *crtc;
  3079. int sr_hdisplay = 0;
  3080. unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
  3081. int enabled = 0, pixel_size = 0;
  3082. int sr_htotal = 0;
  3083. if (!dev_priv->display.update_wm)
  3084. return;
  3085. /* Get the clock config from both planes */
  3086. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3087. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3088. if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
  3089. enabled++;
  3090. if (intel_crtc->plane == 0) {
  3091. DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
  3092. intel_crtc->pipe, crtc->mode.clock);
  3093. planea_clock = crtc->mode.clock;
  3094. } else {
  3095. DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
  3096. intel_crtc->pipe, crtc->mode.clock);
  3097. planeb_clock = crtc->mode.clock;
  3098. }
  3099. sr_hdisplay = crtc->mode.hdisplay;
  3100. sr_clock = crtc->mode.clock;
  3101. sr_htotal = crtc->mode.htotal;
  3102. if (crtc->fb)
  3103. pixel_size = crtc->fb->bits_per_pixel / 8;
  3104. else
  3105. pixel_size = 4; /* by default */
  3106. }
  3107. }
  3108. if (enabled <= 0)
  3109. return;
  3110. dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
  3111. sr_hdisplay, sr_htotal, pixel_size);
  3112. }
  3113. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  3114. struct drm_display_mode *mode,
  3115. struct drm_display_mode *adjusted_mode,
  3116. int x, int y,
  3117. struct drm_framebuffer *old_fb)
  3118. {
  3119. struct drm_device *dev = crtc->dev;
  3120. struct drm_i915_private *dev_priv = dev->dev_private;
  3121. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3122. int pipe = intel_crtc->pipe;
  3123. int plane = intel_crtc->plane;
  3124. int fp_reg = (pipe == 0) ? FPA0 : FPB0;
  3125. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  3126. int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
  3127. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  3128. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  3129. int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  3130. int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  3131. int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  3132. int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  3133. int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  3134. int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  3135. int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
  3136. int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
  3137. int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
  3138. int refclk, num_connectors = 0;
  3139. intel_clock_t clock, reduced_clock;
  3140. u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
  3141. bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  3142. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  3143. struct intel_encoder *has_edp_encoder = NULL;
  3144. struct drm_mode_config *mode_config = &dev->mode_config;
  3145. struct drm_encoder *encoder;
  3146. const intel_limit_t *limit;
  3147. int ret;
  3148. struct fdi_m_n m_n = {0};
  3149. int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
  3150. int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
  3151. int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
  3152. int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
  3153. int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
  3154. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  3155. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  3156. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  3157. int trans_dpll_sel = (pipe == 0) ? 0 : 1;
  3158. int lvds_reg = LVDS;
  3159. u32 temp;
  3160. int target_clock;
  3161. drm_vblank_pre_modeset(dev, pipe);
  3162. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  3163. struct intel_encoder *intel_encoder;
  3164. if (encoder->crtc != crtc)
  3165. continue;
  3166. intel_encoder = to_intel_encoder(encoder);
  3167. switch (intel_encoder->type) {
  3168. case INTEL_OUTPUT_LVDS:
  3169. is_lvds = true;
  3170. break;
  3171. case INTEL_OUTPUT_SDVO:
  3172. case INTEL_OUTPUT_HDMI:
  3173. is_sdvo = true;
  3174. if (intel_encoder->needs_tv_clock)
  3175. is_tv = true;
  3176. break;
  3177. case INTEL_OUTPUT_DVO:
  3178. is_dvo = true;
  3179. break;
  3180. case INTEL_OUTPUT_TVOUT:
  3181. is_tv = true;
  3182. break;
  3183. case INTEL_OUTPUT_ANALOG:
  3184. is_crt = true;
  3185. break;
  3186. case INTEL_OUTPUT_DISPLAYPORT:
  3187. is_dp = true;
  3188. break;
  3189. case INTEL_OUTPUT_EDP:
  3190. has_edp_encoder = intel_encoder;
  3191. break;
  3192. }
  3193. num_connectors++;
  3194. }
  3195. if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
  3196. refclk = dev_priv->lvds_ssc_freq * 1000;
  3197. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3198. refclk / 1000);
  3199. } else if (IS_I9XX(dev)) {
  3200. refclk = 96000;
  3201. if (HAS_PCH_SPLIT(dev))
  3202. refclk = 120000; /* 120Mhz refclk */
  3203. } else {
  3204. refclk = 48000;
  3205. }
  3206. /*
  3207. * Returns a set of divisors for the desired target clock with the given
  3208. * refclk, or FALSE. The returned values represent the clock equation:
  3209. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  3210. */
  3211. limit = intel_limit(crtc);
  3212. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  3213. if (!ok) {
  3214. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  3215. drm_vblank_post_modeset(dev, pipe);
  3216. return -EINVAL;
  3217. }
  3218. /* Ensure that the cursor is valid for the new mode before changing... */
  3219. intel_crtc_update_cursor(crtc);
  3220. if (is_lvds && dev_priv->lvds_downclock_avail) {
  3221. has_reduced_clock = limit->find_pll(limit, crtc,
  3222. dev_priv->lvds_downclock,
  3223. refclk,
  3224. &reduced_clock);
  3225. if (has_reduced_clock && (clock.p != reduced_clock.p)) {
  3226. /*
  3227. * If the different P is found, it means that we can't
  3228. * switch the display clock by using the FP0/FP1.
  3229. * In such case we will disable the LVDS downclock
  3230. * feature.
  3231. */
  3232. DRM_DEBUG_KMS("Different P is found for "
  3233. "LVDS clock/downclock\n");
  3234. has_reduced_clock = 0;
  3235. }
  3236. }
  3237. /* SDVO TV has fixed PLL values depend on its clock range,
  3238. this mirrors vbios setting. */
  3239. if (is_sdvo && is_tv) {
  3240. if (adjusted_mode->clock >= 100000
  3241. && adjusted_mode->clock < 140500) {
  3242. clock.p1 = 2;
  3243. clock.p2 = 10;
  3244. clock.n = 3;
  3245. clock.m1 = 16;
  3246. clock.m2 = 8;
  3247. } else if (adjusted_mode->clock >= 140500
  3248. && adjusted_mode->clock <= 200000) {
  3249. clock.p1 = 1;
  3250. clock.p2 = 10;
  3251. clock.n = 6;
  3252. clock.m1 = 12;
  3253. clock.m2 = 8;
  3254. }
  3255. }
  3256. /* FDI link */
  3257. if (HAS_PCH_SPLIT(dev)) {
  3258. int lane = 0, link_bw, bpp;
  3259. /* eDP doesn't require FDI link, so just set DP M/N
  3260. according to current link config */
  3261. if (has_edp_encoder) {
  3262. target_clock = mode->clock;
  3263. intel_edp_link_config(has_edp_encoder,
  3264. &lane, &link_bw);
  3265. } else {
  3266. /* DP over FDI requires target mode clock
  3267. instead of link clock */
  3268. if (is_dp)
  3269. target_clock = mode->clock;
  3270. else
  3271. target_clock = adjusted_mode->clock;
  3272. link_bw = 270000;
  3273. }
  3274. /* determine panel color depth */
  3275. temp = I915_READ(pipeconf_reg);
  3276. temp &= ~PIPE_BPC_MASK;
  3277. if (is_lvds) {
  3278. int lvds_reg = I915_READ(PCH_LVDS);
  3279. /* the BPC will be 6 if it is 18-bit LVDS panel */
  3280. if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
  3281. temp |= PIPE_8BPC;
  3282. else
  3283. temp |= PIPE_6BPC;
  3284. } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
  3285. switch (dev_priv->edp_bpp/3) {
  3286. case 8:
  3287. temp |= PIPE_8BPC;
  3288. break;
  3289. case 10:
  3290. temp |= PIPE_10BPC;
  3291. break;
  3292. case 6:
  3293. temp |= PIPE_6BPC;
  3294. break;
  3295. case 12:
  3296. temp |= PIPE_12BPC;
  3297. break;
  3298. }
  3299. } else
  3300. temp |= PIPE_8BPC;
  3301. I915_WRITE(pipeconf_reg, temp);
  3302. I915_READ(pipeconf_reg);
  3303. switch (temp & PIPE_BPC_MASK) {
  3304. case PIPE_8BPC:
  3305. bpp = 24;
  3306. break;
  3307. case PIPE_10BPC:
  3308. bpp = 30;
  3309. break;
  3310. case PIPE_6BPC:
  3311. bpp = 18;
  3312. break;
  3313. case PIPE_12BPC:
  3314. bpp = 36;
  3315. break;
  3316. default:
  3317. DRM_ERROR("unknown pipe bpc value\n");
  3318. bpp = 24;
  3319. }
  3320. if (!lane) {
  3321. /*
  3322. * Account for spread spectrum to avoid
  3323. * oversubscribing the link. Max center spread
  3324. * is 2.5%; use 5% for safety's sake.
  3325. */
  3326. u32 bps = target_clock * bpp * 21 / 20;
  3327. lane = bps / (link_bw * 8) + 1;
  3328. }
  3329. intel_crtc->fdi_lanes = lane;
  3330. ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
  3331. }
  3332. /* Ironlake: try to setup display ref clock before DPLL
  3333. * enabling. This is only under driver's control after
  3334. * PCH B stepping, previous chipset stepping should be
  3335. * ignoring this setting.
  3336. */
  3337. if (HAS_PCH_SPLIT(dev)) {
  3338. temp = I915_READ(PCH_DREF_CONTROL);
  3339. /* Always enable nonspread source */
  3340. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  3341. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  3342. I915_WRITE(PCH_DREF_CONTROL, temp);
  3343. POSTING_READ(PCH_DREF_CONTROL);
  3344. temp &= ~DREF_SSC_SOURCE_MASK;
  3345. temp |= DREF_SSC_SOURCE_ENABLE;
  3346. I915_WRITE(PCH_DREF_CONTROL, temp);
  3347. POSTING_READ(PCH_DREF_CONTROL);
  3348. udelay(200);
  3349. if (has_edp_encoder) {
  3350. if (dev_priv->lvds_use_ssc) {
  3351. temp |= DREF_SSC1_ENABLE;
  3352. I915_WRITE(PCH_DREF_CONTROL, temp);
  3353. POSTING_READ(PCH_DREF_CONTROL);
  3354. udelay(200);
  3355. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  3356. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  3357. I915_WRITE(PCH_DREF_CONTROL, temp);
  3358. POSTING_READ(PCH_DREF_CONTROL);
  3359. } else {
  3360. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  3361. I915_WRITE(PCH_DREF_CONTROL, temp);
  3362. POSTING_READ(PCH_DREF_CONTROL);
  3363. }
  3364. }
  3365. }
  3366. if (IS_PINEVIEW(dev)) {
  3367. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  3368. if (has_reduced_clock)
  3369. fp2 = (1 << reduced_clock.n) << 16 |
  3370. reduced_clock.m1 << 8 | reduced_clock.m2;
  3371. } else {
  3372. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  3373. if (has_reduced_clock)
  3374. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  3375. reduced_clock.m2;
  3376. }
  3377. if (!HAS_PCH_SPLIT(dev))
  3378. dpll = DPLL_VGA_MODE_DIS;
  3379. if (IS_I9XX(dev)) {
  3380. if (is_lvds)
  3381. dpll |= DPLLB_MODE_LVDS;
  3382. else
  3383. dpll |= DPLLB_MODE_DAC_SERIAL;
  3384. if (is_sdvo) {
  3385. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  3386. if (pixel_multiplier > 1) {
  3387. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  3388. dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  3389. else if (HAS_PCH_SPLIT(dev))
  3390. dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  3391. }
  3392. dpll |= DPLL_DVO_HIGH_SPEED;
  3393. }
  3394. if (is_dp)
  3395. dpll |= DPLL_DVO_HIGH_SPEED;
  3396. /* compute bitmask from p1 value */
  3397. if (IS_PINEVIEW(dev))
  3398. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3399. else {
  3400. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3401. /* also FPA1 */
  3402. if (HAS_PCH_SPLIT(dev))
  3403. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3404. if (IS_G4X(dev) && has_reduced_clock)
  3405. dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3406. }
  3407. switch (clock.p2) {
  3408. case 5:
  3409. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3410. break;
  3411. case 7:
  3412. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3413. break;
  3414. case 10:
  3415. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3416. break;
  3417. case 14:
  3418. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3419. break;
  3420. }
  3421. if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
  3422. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3423. } else {
  3424. if (is_lvds) {
  3425. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3426. } else {
  3427. if (clock.p1 == 2)
  3428. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3429. else
  3430. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3431. if (clock.p2 == 4)
  3432. dpll |= PLL_P2_DIVIDE_BY_4;
  3433. }
  3434. }
  3435. if (is_sdvo && is_tv)
  3436. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3437. else if (is_tv)
  3438. /* XXX: just matching BIOS for now */
  3439. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3440. dpll |= 3;
  3441. else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
  3442. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3443. else
  3444. dpll |= PLL_REF_INPUT_DREFCLK;
  3445. /* setup pipeconf */
  3446. pipeconf = I915_READ(pipeconf_reg);
  3447. /* Set up the display plane register */
  3448. dspcntr = DISPPLANE_GAMMA_ENABLE;
  3449. /* Ironlake's plane is forced to pipe, bit 24 is to
  3450. enable color space conversion */
  3451. if (!HAS_PCH_SPLIT(dev)) {
  3452. if (pipe == 0)
  3453. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  3454. else
  3455. dspcntr |= DISPPLANE_SEL_PIPE_B;
  3456. }
  3457. if (pipe == 0 && !IS_I965G(dev)) {
  3458. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  3459. * core speed.
  3460. *
  3461. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  3462. * pipe == 0 check?
  3463. */
  3464. if (mode->clock >
  3465. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  3466. pipeconf |= PIPEACONF_DOUBLE_WIDE;
  3467. else
  3468. pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
  3469. }
  3470. dspcntr |= DISPLAY_PLANE_ENABLE;
  3471. pipeconf |= PIPEACONF_ENABLE;
  3472. dpll |= DPLL_VCO_ENABLE;
  3473. /* Disable the panel fitter if it was on our pipe */
  3474. if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
  3475. I915_WRITE(PFIT_CONTROL, 0);
  3476. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  3477. drm_mode_debug_printmodeline(mode);
  3478. /* assign to Ironlake registers */
  3479. if (HAS_PCH_SPLIT(dev)) {
  3480. fp_reg = pch_fp_reg;
  3481. dpll_reg = pch_dpll_reg;
  3482. }
  3483. if (!has_edp_encoder) {
  3484. I915_WRITE(fp_reg, fp);
  3485. I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
  3486. I915_READ(dpll_reg);
  3487. udelay(150);
  3488. }
  3489. /* enable transcoder DPLL */
  3490. if (HAS_PCH_CPT(dev)) {
  3491. temp = I915_READ(PCH_DPLL_SEL);
  3492. if (trans_dpll_sel == 0)
  3493. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  3494. else
  3495. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  3496. I915_WRITE(PCH_DPLL_SEL, temp);
  3497. I915_READ(PCH_DPLL_SEL);
  3498. udelay(150);
  3499. }
  3500. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  3501. * This is an exception to the general rule that mode_set doesn't turn
  3502. * things on.
  3503. */
  3504. if (is_lvds) {
  3505. u32 lvds;
  3506. if (HAS_PCH_SPLIT(dev))
  3507. lvds_reg = PCH_LVDS;
  3508. lvds = I915_READ(lvds_reg);
  3509. lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  3510. if (pipe == 1) {
  3511. if (HAS_PCH_CPT(dev))
  3512. lvds |= PORT_TRANS_B_SEL_CPT;
  3513. else
  3514. lvds |= LVDS_PIPEB_SELECT;
  3515. } else {
  3516. if (HAS_PCH_CPT(dev))
  3517. lvds &= ~PORT_TRANS_SEL_MASK;
  3518. else
  3519. lvds &= ~LVDS_PIPEB_SELECT;
  3520. }
  3521. /* set the corresponsding LVDS_BORDER bit */
  3522. lvds |= dev_priv->lvds_border_bits;
  3523. /* Set the B0-B3 data pairs corresponding to whether we're going to
  3524. * set the DPLLs for dual-channel mode or not.
  3525. */
  3526. if (clock.p2 == 7)
  3527. lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  3528. else
  3529. lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  3530. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  3531. * appropriately here, but we need to look more thoroughly into how
  3532. * panels behave in the two modes.
  3533. */
  3534. /* set the dithering flag on non-PCH LVDS as needed */
  3535. if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
  3536. if (dev_priv->lvds_dither)
  3537. lvds |= LVDS_ENABLE_DITHER;
  3538. else
  3539. lvds &= ~LVDS_ENABLE_DITHER;
  3540. }
  3541. I915_WRITE(lvds_reg, lvds);
  3542. I915_READ(lvds_reg);
  3543. }
  3544. /* set the dithering flag and clear for anything other than a panel. */
  3545. if (HAS_PCH_SPLIT(dev)) {
  3546. pipeconf &= ~PIPECONF_DITHER_EN;
  3547. pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
  3548. if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
  3549. pipeconf |= PIPECONF_DITHER_EN;
  3550. pipeconf |= PIPECONF_DITHER_TYPE_ST1;
  3551. }
  3552. }
  3553. if (is_dp)
  3554. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  3555. else if (HAS_PCH_SPLIT(dev)) {
  3556. /* For non-DP output, clear any trans DP clock recovery setting.*/
  3557. if (pipe == 0) {
  3558. I915_WRITE(TRANSA_DATA_M1, 0);
  3559. I915_WRITE(TRANSA_DATA_N1, 0);
  3560. I915_WRITE(TRANSA_DP_LINK_M1, 0);
  3561. I915_WRITE(TRANSA_DP_LINK_N1, 0);
  3562. } else {
  3563. I915_WRITE(TRANSB_DATA_M1, 0);
  3564. I915_WRITE(TRANSB_DATA_N1, 0);
  3565. I915_WRITE(TRANSB_DP_LINK_M1, 0);
  3566. I915_WRITE(TRANSB_DP_LINK_N1, 0);
  3567. }
  3568. }
  3569. if (!has_edp_encoder) {
  3570. I915_WRITE(fp_reg, fp);
  3571. I915_WRITE(dpll_reg, dpll);
  3572. I915_READ(dpll_reg);
  3573. /* Wait for the clocks to stabilize. */
  3574. udelay(150);
  3575. if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
  3576. if (is_sdvo) {
  3577. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  3578. if (pixel_multiplier > 1)
  3579. pixel_multiplier = (pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3580. else
  3581. pixel_multiplier = 0;
  3582. I915_WRITE(dpll_md_reg,
  3583. (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
  3584. pixel_multiplier);
  3585. } else
  3586. I915_WRITE(dpll_md_reg, 0);
  3587. } else {
  3588. /* write it again -- the BIOS does, after all */
  3589. I915_WRITE(dpll_reg, dpll);
  3590. }
  3591. I915_READ(dpll_reg);
  3592. /* Wait for the clocks to stabilize. */
  3593. udelay(150);
  3594. }
  3595. if (is_lvds && has_reduced_clock && i915_powersave) {
  3596. I915_WRITE(fp_reg + 4, fp2);
  3597. intel_crtc->lowfreq_avail = true;
  3598. if (HAS_PIPE_CXSR(dev)) {
  3599. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  3600. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  3601. }
  3602. } else {
  3603. I915_WRITE(fp_reg + 4, fp);
  3604. intel_crtc->lowfreq_avail = false;
  3605. if (HAS_PIPE_CXSR(dev)) {
  3606. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  3607. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  3608. }
  3609. }
  3610. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  3611. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  3612. /* the chip adds 2 halflines automatically */
  3613. adjusted_mode->crtc_vdisplay -= 1;
  3614. adjusted_mode->crtc_vtotal -= 1;
  3615. adjusted_mode->crtc_vblank_start -= 1;
  3616. adjusted_mode->crtc_vblank_end -= 1;
  3617. adjusted_mode->crtc_vsync_end -= 1;
  3618. adjusted_mode->crtc_vsync_start -= 1;
  3619. } else
  3620. pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
  3621. I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
  3622. ((adjusted_mode->crtc_htotal - 1) << 16));
  3623. I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
  3624. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  3625. I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
  3626. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  3627. I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
  3628. ((adjusted_mode->crtc_vtotal - 1) << 16));
  3629. I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
  3630. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  3631. I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
  3632. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  3633. /* pipesrc and dspsize control the size that is scaled from, which should
  3634. * always be the user's requested size.
  3635. */
  3636. if (!HAS_PCH_SPLIT(dev)) {
  3637. I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
  3638. (mode->hdisplay - 1));
  3639. I915_WRITE(dsppos_reg, 0);
  3640. }
  3641. I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  3642. if (HAS_PCH_SPLIT(dev)) {
  3643. I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
  3644. I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
  3645. I915_WRITE(link_m1_reg, m_n.link_m);
  3646. I915_WRITE(link_n1_reg, m_n.link_n);
  3647. if (has_edp_encoder) {
  3648. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  3649. } else {
  3650. /* enable FDI RX PLL too */
  3651. temp = I915_READ(fdi_rx_reg);
  3652. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  3653. I915_READ(fdi_rx_reg);
  3654. udelay(200);
  3655. /* enable FDI TX PLL too */
  3656. temp = I915_READ(fdi_tx_reg);
  3657. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  3658. I915_READ(fdi_tx_reg);
  3659. /* enable FDI RX PCDCLK */
  3660. temp = I915_READ(fdi_rx_reg);
  3661. I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
  3662. I915_READ(fdi_rx_reg);
  3663. udelay(200);
  3664. }
  3665. }
  3666. I915_WRITE(pipeconf_reg, pipeconf);
  3667. I915_READ(pipeconf_reg);
  3668. intel_wait_for_vblank(dev, pipe);
  3669. if (IS_IRONLAKE(dev)) {
  3670. /* enable address swizzle for tiling buffer */
  3671. temp = I915_READ(DISP_ARB_CTL);
  3672. I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
  3673. }
  3674. I915_WRITE(dspcntr_reg, dspcntr);
  3675. /* Flush the plane changes */
  3676. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  3677. intel_update_watermarks(dev);
  3678. drm_vblank_post_modeset(dev, pipe);
  3679. return ret;
  3680. }
  3681. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  3682. void intel_crtc_load_lut(struct drm_crtc *crtc)
  3683. {
  3684. struct drm_device *dev = crtc->dev;
  3685. struct drm_i915_private *dev_priv = dev->dev_private;
  3686. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3687. int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
  3688. int i;
  3689. /* The clocks have to be on to load the palette. */
  3690. if (!crtc->enabled)
  3691. return;
  3692. /* use legacy palette for Ironlake */
  3693. if (HAS_PCH_SPLIT(dev))
  3694. palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
  3695. LGC_PALETTE_B;
  3696. for (i = 0; i < 256; i++) {
  3697. I915_WRITE(palreg + 4 * i,
  3698. (intel_crtc->lut_r[i] << 16) |
  3699. (intel_crtc->lut_g[i] << 8) |
  3700. intel_crtc->lut_b[i]);
  3701. }
  3702. }
  3703. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  3704. {
  3705. struct drm_device *dev = crtc->dev;
  3706. struct drm_i915_private *dev_priv = dev->dev_private;
  3707. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3708. bool visible = base != 0;
  3709. u32 cntl;
  3710. if (intel_crtc->cursor_visible == visible)
  3711. return;
  3712. cntl = I915_READ(CURACNTR);
  3713. if (visible) {
  3714. /* On these chipsets we can only modify the base whilst
  3715. * the cursor is disabled.
  3716. */
  3717. I915_WRITE(CURABASE, base);
  3718. cntl &= ~(CURSOR_FORMAT_MASK);
  3719. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  3720. cntl |= CURSOR_ENABLE |
  3721. CURSOR_GAMMA_ENABLE |
  3722. CURSOR_FORMAT_ARGB;
  3723. } else
  3724. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  3725. I915_WRITE(CURACNTR, cntl);
  3726. intel_crtc->cursor_visible = visible;
  3727. }
  3728. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  3729. {
  3730. struct drm_device *dev = crtc->dev;
  3731. struct drm_i915_private *dev_priv = dev->dev_private;
  3732. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3733. int pipe = intel_crtc->pipe;
  3734. bool visible = base != 0;
  3735. if (intel_crtc->cursor_visible != visible) {
  3736. uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
  3737. if (base) {
  3738. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  3739. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  3740. cntl |= pipe << 28; /* Connect to correct pipe */
  3741. } else {
  3742. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  3743. cntl |= CURSOR_MODE_DISABLE;
  3744. }
  3745. I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
  3746. intel_crtc->cursor_visible = visible;
  3747. }
  3748. /* and commit changes on next vblank */
  3749. I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
  3750. }
  3751. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  3752. static void intel_crtc_update_cursor(struct drm_crtc *crtc)
  3753. {
  3754. struct drm_device *dev = crtc->dev;
  3755. struct drm_i915_private *dev_priv = dev->dev_private;
  3756. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3757. int pipe = intel_crtc->pipe;
  3758. int x = intel_crtc->cursor_x;
  3759. int y = intel_crtc->cursor_y;
  3760. u32 base, pos;
  3761. bool visible;
  3762. pos = 0;
  3763. if (intel_crtc->cursor_on && crtc->fb) {
  3764. base = intel_crtc->cursor_addr;
  3765. if (x > (int) crtc->fb->width)
  3766. base = 0;
  3767. if (y > (int) crtc->fb->height)
  3768. base = 0;
  3769. } else
  3770. base = 0;
  3771. if (x < 0) {
  3772. if (x + intel_crtc->cursor_width < 0)
  3773. base = 0;
  3774. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  3775. x = -x;
  3776. }
  3777. pos |= x << CURSOR_X_SHIFT;
  3778. if (y < 0) {
  3779. if (y + intel_crtc->cursor_height < 0)
  3780. base = 0;
  3781. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  3782. y = -y;
  3783. }
  3784. pos |= y << CURSOR_Y_SHIFT;
  3785. visible = base != 0;
  3786. if (!visible && !intel_crtc->cursor_visible)
  3787. return;
  3788. I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
  3789. if (IS_845G(dev) || IS_I865G(dev))
  3790. i845_update_cursor(crtc, base);
  3791. else
  3792. i9xx_update_cursor(crtc, base);
  3793. if (visible)
  3794. intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
  3795. }
  3796. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  3797. struct drm_file *file_priv,
  3798. uint32_t handle,
  3799. uint32_t width, uint32_t height)
  3800. {
  3801. struct drm_device *dev = crtc->dev;
  3802. struct drm_i915_private *dev_priv = dev->dev_private;
  3803. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3804. struct drm_gem_object *bo;
  3805. struct drm_i915_gem_object *obj_priv;
  3806. uint32_t addr;
  3807. int ret;
  3808. DRM_DEBUG_KMS("\n");
  3809. /* if we want to turn off the cursor ignore width and height */
  3810. if (!handle) {
  3811. DRM_DEBUG_KMS("cursor off\n");
  3812. addr = 0;
  3813. bo = NULL;
  3814. mutex_lock(&dev->struct_mutex);
  3815. goto finish;
  3816. }
  3817. /* Currently we only support 64x64 cursors */
  3818. if (width != 64 || height != 64) {
  3819. DRM_ERROR("we currently only support 64x64 cursors\n");
  3820. return -EINVAL;
  3821. }
  3822. bo = drm_gem_object_lookup(dev, file_priv, handle);
  3823. if (!bo)
  3824. return -ENOENT;
  3825. obj_priv = to_intel_bo(bo);
  3826. if (bo->size < width * height * 4) {
  3827. DRM_ERROR("buffer is to small\n");
  3828. ret = -ENOMEM;
  3829. goto fail;
  3830. }
  3831. /* we only need to pin inside GTT if cursor is non-phy */
  3832. mutex_lock(&dev->struct_mutex);
  3833. if (!dev_priv->info->cursor_needs_physical) {
  3834. ret = i915_gem_object_pin(bo, PAGE_SIZE);
  3835. if (ret) {
  3836. DRM_ERROR("failed to pin cursor bo\n");
  3837. goto fail_locked;
  3838. }
  3839. ret = i915_gem_object_set_to_gtt_domain(bo, 0);
  3840. if (ret) {
  3841. DRM_ERROR("failed to move cursor bo into the GTT\n");
  3842. goto fail_unpin;
  3843. }
  3844. addr = obj_priv->gtt_offset;
  3845. } else {
  3846. int align = IS_I830(dev) ? 16 * 1024 : 256;
  3847. ret = i915_gem_attach_phys_object(dev, bo,
  3848. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  3849. align);
  3850. if (ret) {
  3851. DRM_ERROR("failed to attach phys object\n");
  3852. goto fail_locked;
  3853. }
  3854. addr = obj_priv->phys_obj->handle->busaddr;
  3855. }
  3856. if (!IS_I9XX(dev))
  3857. I915_WRITE(CURSIZE, (height << 12) | width);
  3858. finish:
  3859. if (intel_crtc->cursor_bo) {
  3860. if (dev_priv->info->cursor_needs_physical) {
  3861. if (intel_crtc->cursor_bo != bo)
  3862. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  3863. } else
  3864. i915_gem_object_unpin(intel_crtc->cursor_bo);
  3865. drm_gem_object_unreference(intel_crtc->cursor_bo);
  3866. }
  3867. mutex_unlock(&dev->struct_mutex);
  3868. intel_crtc->cursor_addr = addr;
  3869. intel_crtc->cursor_bo = bo;
  3870. intel_crtc->cursor_width = width;
  3871. intel_crtc->cursor_height = height;
  3872. intel_crtc_update_cursor(crtc);
  3873. return 0;
  3874. fail_unpin:
  3875. i915_gem_object_unpin(bo);
  3876. fail_locked:
  3877. mutex_unlock(&dev->struct_mutex);
  3878. fail:
  3879. drm_gem_object_unreference_unlocked(bo);
  3880. return ret;
  3881. }
  3882. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  3883. {
  3884. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3885. intel_crtc->cursor_x = x;
  3886. intel_crtc->cursor_y = y;
  3887. intel_crtc_update_cursor(crtc);
  3888. return 0;
  3889. }
  3890. /** Sets the color ramps on behalf of RandR */
  3891. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  3892. u16 blue, int regno)
  3893. {
  3894. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3895. intel_crtc->lut_r[regno] = red >> 8;
  3896. intel_crtc->lut_g[regno] = green >> 8;
  3897. intel_crtc->lut_b[regno] = blue >> 8;
  3898. }
  3899. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  3900. u16 *blue, int regno)
  3901. {
  3902. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3903. *red = intel_crtc->lut_r[regno] << 8;
  3904. *green = intel_crtc->lut_g[regno] << 8;
  3905. *blue = intel_crtc->lut_b[regno] << 8;
  3906. }
  3907. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  3908. u16 *blue, uint32_t start, uint32_t size)
  3909. {
  3910. int end = (start + size > 256) ? 256 : start + size, i;
  3911. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3912. for (i = start; i < end; i++) {
  3913. intel_crtc->lut_r[i] = red[i] >> 8;
  3914. intel_crtc->lut_g[i] = green[i] >> 8;
  3915. intel_crtc->lut_b[i] = blue[i] >> 8;
  3916. }
  3917. intel_crtc_load_lut(crtc);
  3918. }
  3919. /**
  3920. * Get a pipe with a simple mode set on it for doing load-based monitor
  3921. * detection.
  3922. *
  3923. * It will be up to the load-detect code to adjust the pipe as appropriate for
  3924. * its requirements. The pipe will be connected to no other encoders.
  3925. *
  3926. * Currently this code will only succeed if there is a pipe with no encoders
  3927. * configured for it. In the future, it could choose to temporarily disable
  3928. * some outputs to free up a pipe for its use.
  3929. *
  3930. * \return crtc, or NULL if no pipes are available.
  3931. */
  3932. /* VESA 640x480x72Hz mode to set on the pipe */
  3933. static struct drm_display_mode load_detect_mode = {
  3934. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  3935. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  3936. };
  3937. struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
  3938. struct drm_connector *connector,
  3939. struct drm_display_mode *mode,
  3940. int *dpms_mode)
  3941. {
  3942. struct intel_crtc *intel_crtc;
  3943. struct drm_crtc *possible_crtc;
  3944. struct drm_crtc *supported_crtc =NULL;
  3945. struct drm_encoder *encoder = &intel_encoder->base;
  3946. struct drm_crtc *crtc = NULL;
  3947. struct drm_device *dev = encoder->dev;
  3948. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3949. struct drm_crtc_helper_funcs *crtc_funcs;
  3950. int i = -1;
  3951. /*
  3952. * Algorithm gets a little messy:
  3953. * - if the connector already has an assigned crtc, use it (but make
  3954. * sure it's on first)
  3955. * - try to find the first unused crtc that can drive this connector,
  3956. * and use that if we find one
  3957. * - if there are no unused crtcs available, try to use the first
  3958. * one we found that supports the connector
  3959. */
  3960. /* See if we already have a CRTC for this connector */
  3961. if (encoder->crtc) {
  3962. crtc = encoder->crtc;
  3963. /* Make sure the crtc and connector are running */
  3964. intel_crtc = to_intel_crtc(crtc);
  3965. *dpms_mode = intel_crtc->dpms_mode;
  3966. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3967. crtc_funcs = crtc->helper_private;
  3968. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3969. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  3970. }
  3971. return crtc;
  3972. }
  3973. /* Find an unused one (if possible) */
  3974. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  3975. i++;
  3976. if (!(encoder->possible_crtcs & (1 << i)))
  3977. continue;
  3978. if (!possible_crtc->enabled) {
  3979. crtc = possible_crtc;
  3980. break;
  3981. }
  3982. if (!supported_crtc)
  3983. supported_crtc = possible_crtc;
  3984. }
  3985. /*
  3986. * If we didn't find an unused CRTC, don't use any.
  3987. */
  3988. if (!crtc) {
  3989. return NULL;
  3990. }
  3991. encoder->crtc = crtc;
  3992. connector->encoder = encoder;
  3993. intel_encoder->load_detect_temp = true;
  3994. intel_crtc = to_intel_crtc(crtc);
  3995. *dpms_mode = intel_crtc->dpms_mode;
  3996. if (!crtc->enabled) {
  3997. if (!mode)
  3998. mode = &load_detect_mode;
  3999. drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
  4000. } else {
  4001. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  4002. crtc_funcs = crtc->helper_private;
  4003. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  4004. }
  4005. /* Add this connector to the crtc */
  4006. encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
  4007. encoder_funcs->commit(encoder);
  4008. }
  4009. /* let the connector get through one full cycle before testing */
  4010. intel_wait_for_vblank(dev, intel_crtc->pipe);
  4011. return crtc;
  4012. }
  4013. void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
  4014. struct drm_connector *connector, int dpms_mode)
  4015. {
  4016. struct drm_encoder *encoder = &intel_encoder->base;
  4017. struct drm_device *dev = encoder->dev;
  4018. struct drm_crtc *crtc = encoder->crtc;
  4019. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  4020. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  4021. if (intel_encoder->load_detect_temp) {
  4022. encoder->crtc = NULL;
  4023. connector->encoder = NULL;
  4024. intel_encoder->load_detect_temp = false;
  4025. crtc->enabled = drm_helper_crtc_in_use(crtc);
  4026. drm_helper_disable_unused_functions(dev);
  4027. }
  4028. /* Switch crtc and encoder back off if necessary */
  4029. if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
  4030. if (encoder->crtc == crtc)
  4031. encoder_funcs->dpms(encoder, dpms_mode);
  4032. crtc_funcs->dpms(crtc, dpms_mode);
  4033. }
  4034. }
  4035. /* Returns the clock of the currently programmed mode of the given pipe. */
  4036. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  4037. {
  4038. struct drm_i915_private *dev_priv = dev->dev_private;
  4039. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4040. int pipe = intel_crtc->pipe;
  4041. u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
  4042. u32 fp;
  4043. intel_clock_t clock;
  4044. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  4045. fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
  4046. else
  4047. fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
  4048. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  4049. if (IS_PINEVIEW(dev)) {
  4050. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  4051. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  4052. } else {
  4053. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  4054. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  4055. }
  4056. if (IS_I9XX(dev)) {
  4057. if (IS_PINEVIEW(dev))
  4058. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  4059. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  4060. else
  4061. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  4062. DPLL_FPA01_P1_POST_DIV_SHIFT);
  4063. switch (dpll & DPLL_MODE_MASK) {
  4064. case DPLLB_MODE_DAC_SERIAL:
  4065. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  4066. 5 : 10;
  4067. break;
  4068. case DPLLB_MODE_LVDS:
  4069. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  4070. 7 : 14;
  4071. break;
  4072. default:
  4073. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  4074. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  4075. return 0;
  4076. }
  4077. /* XXX: Handle the 100Mhz refclk */
  4078. intel_clock(dev, 96000, &clock);
  4079. } else {
  4080. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  4081. if (is_lvds) {
  4082. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  4083. DPLL_FPA01_P1_POST_DIV_SHIFT);
  4084. clock.p2 = 14;
  4085. if ((dpll & PLL_REF_INPUT_MASK) ==
  4086. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  4087. /* XXX: might not be 66MHz */
  4088. intel_clock(dev, 66000, &clock);
  4089. } else
  4090. intel_clock(dev, 48000, &clock);
  4091. } else {
  4092. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  4093. clock.p1 = 2;
  4094. else {
  4095. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  4096. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  4097. }
  4098. if (dpll & PLL_P2_DIVIDE_BY_4)
  4099. clock.p2 = 4;
  4100. else
  4101. clock.p2 = 2;
  4102. intel_clock(dev, 48000, &clock);
  4103. }
  4104. }
  4105. /* XXX: It would be nice to validate the clocks, but we can't reuse
  4106. * i830PllIsValid() because it relies on the xf86_config connector
  4107. * configuration being accurate, which it isn't necessarily.
  4108. */
  4109. return clock.dot;
  4110. }
  4111. /** Returns the currently programmed mode of the given pipe. */
  4112. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  4113. struct drm_crtc *crtc)
  4114. {
  4115. struct drm_i915_private *dev_priv = dev->dev_private;
  4116. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4117. int pipe = intel_crtc->pipe;
  4118. struct drm_display_mode *mode;
  4119. int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
  4120. int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
  4121. int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
  4122. int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
  4123. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  4124. if (!mode)
  4125. return NULL;
  4126. mode->clock = intel_crtc_clock_get(dev, crtc);
  4127. mode->hdisplay = (htot & 0xffff) + 1;
  4128. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  4129. mode->hsync_start = (hsync & 0xffff) + 1;
  4130. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  4131. mode->vdisplay = (vtot & 0xffff) + 1;
  4132. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  4133. mode->vsync_start = (vsync & 0xffff) + 1;
  4134. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  4135. drm_mode_set_name(mode);
  4136. drm_mode_set_crtcinfo(mode, 0);
  4137. return mode;
  4138. }
  4139. #define GPU_IDLE_TIMEOUT 500 /* ms */
  4140. /* When this timer fires, we've been idle for awhile */
  4141. static void intel_gpu_idle_timer(unsigned long arg)
  4142. {
  4143. struct drm_device *dev = (struct drm_device *)arg;
  4144. drm_i915_private_t *dev_priv = dev->dev_private;
  4145. DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
  4146. dev_priv->busy = false;
  4147. queue_work(dev_priv->wq, &dev_priv->idle_work);
  4148. }
  4149. #define CRTC_IDLE_TIMEOUT 1000 /* ms */
  4150. static void intel_crtc_idle_timer(unsigned long arg)
  4151. {
  4152. struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
  4153. struct drm_crtc *crtc = &intel_crtc->base;
  4154. drm_i915_private_t *dev_priv = crtc->dev->dev_private;
  4155. DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
  4156. intel_crtc->busy = false;
  4157. queue_work(dev_priv->wq, &dev_priv->idle_work);
  4158. }
  4159. static void intel_increase_pllclock(struct drm_crtc *crtc)
  4160. {
  4161. struct drm_device *dev = crtc->dev;
  4162. drm_i915_private_t *dev_priv = dev->dev_private;
  4163. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4164. int pipe = intel_crtc->pipe;
  4165. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  4166. int dpll = I915_READ(dpll_reg);
  4167. if (HAS_PCH_SPLIT(dev))
  4168. return;
  4169. if (!dev_priv->lvds_downclock_avail)
  4170. return;
  4171. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  4172. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  4173. /* Unlock panel regs */
  4174. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
  4175. PANEL_UNLOCK_REGS);
  4176. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  4177. I915_WRITE(dpll_reg, dpll);
  4178. dpll = I915_READ(dpll_reg);
  4179. intel_wait_for_vblank(dev, pipe);
  4180. dpll = I915_READ(dpll_reg);
  4181. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  4182. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  4183. /* ...and lock them again */
  4184. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  4185. }
  4186. /* Schedule downclock */
  4187. mod_timer(&intel_crtc->idle_timer, jiffies +
  4188. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  4189. }
  4190. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  4191. {
  4192. struct drm_device *dev = crtc->dev;
  4193. drm_i915_private_t *dev_priv = dev->dev_private;
  4194. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4195. int pipe = intel_crtc->pipe;
  4196. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  4197. int dpll = I915_READ(dpll_reg);
  4198. if (HAS_PCH_SPLIT(dev))
  4199. return;
  4200. if (!dev_priv->lvds_downclock_avail)
  4201. return;
  4202. /*
  4203. * Since this is called by a timer, we should never get here in
  4204. * the manual case.
  4205. */
  4206. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  4207. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  4208. /* Unlock panel regs */
  4209. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
  4210. PANEL_UNLOCK_REGS);
  4211. dpll |= DISPLAY_RATE_SELECT_FPA1;
  4212. I915_WRITE(dpll_reg, dpll);
  4213. dpll = I915_READ(dpll_reg);
  4214. intel_wait_for_vblank(dev, pipe);
  4215. dpll = I915_READ(dpll_reg);
  4216. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  4217. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  4218. /* ...and lock them again */
  4219. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  4220. }
  4221. }
  4222. /**
  4223. * intel_idle_update - adjust clocks for idleness
  4224. * @work: work struct
  4225. *
  4226. * Either the GPU or display (or both) went idle. Check the busy status
  4227. * here and adjust the CRTC and GPU clocks as necessary.
  4228. */
  4229. static void intel_idle_update(struct work_struct *work)
  4230. {
  4231. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  4232. idle_work);
  4233. struct drm_device *dev = dev_priv->dev;
  4234. struct drm_crtc *crtc;
  4235. struct intel_crtc *intel_crtc;
  4236. int enabled = 0;
  4237. if (!i915_powersave)
  4238. return;
  4239. mutex_lock(&dev->struct_mutex);
  4240. i915_update_gfx_val(dev_priv);
  4241. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4242. /* Skip inactive CRTCs */
  4243. if (!crtc->fb)
  4244. continue;
  4245. enabled++;
  4246. intel_crtc = to_intel_crtc(crtc);
  4247. if (!intel_crtc->busy)
  4248. intel_decrease_pllclock(crtc);
  4249. }
  4250. if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
  4251. DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
  4252. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  4253. }
  4254. mutex_unlock(&dev->struct_mutex);
  4255. }
  4256. /**
  4257. * intel_mark_busy - mark the GPU and possibly the display busy
  4258. * @dev: drm device
  4259. * @obj: object we're operating on
  4260. *
  4261. * Callers can use this function to indicate that the GPU is busy processing
  4262. * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
  4263. * buffer), we'll also mark the display as busy, so we know to increase its
  4264. * clock frequency.
  4265. */
  4266. void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
  4267. {
  4268. drm_i915_private_t *dev_priv = dev->dev_private;
  4269. struct drm_crtc *crtc = NULL;
  4270. struct intel_framebuffer *intel_fb;
  4271. struct intel_crtc *intel_crtc;
  4272. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  4273. return;
  4274. if (!dev_priv->busy) {
  4275. if (IS_I945G(dev) || IS_I945GM(dev)) {
  4276. u32 fw_blc_self;
  4277. DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
  4278. fw_blc_self = I915_READ(FW_BLC_SELF);
  4279. fw_blc_self &= ~FW_BLC_SELF_EN;
  4280. I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
  4281. }
  4282. dev_priv->busy = true;
  4283. } else
  4284. mod_timer(&dev_priv->idle_timer, jiffies +
  4285. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  4286. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4287. if (!crtc->fb)
  4288. continue;
  4289. intel_crtc = to_intel_crtc(crtc);
  4290. intel_fb = to_intel_framebuffer(crtc->fb);
  4291. if (intel_fb->obj == obj) {
  4292. if (!intel_crtc->busy) {
  4293. if (IS_I945G(dev) || IS_I945GM(dev)) {
  4294. u32 fw_blc_self;
  4295. DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
  4296. fw_blc_self = I915_READ(FW_BLC_SELF);
  4297. fw_blc_self &= ~FW_BLC_SELF_EN;
  4298. I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
  4299. }
  4300. /* Non-busy -> busy, upclock */
  4301. intel_increase_pllclock(crtc);
  4302. intel_crtc->busy = true;
  4303. } else {
  4304. /* Busy -> busy, put off timer */
  4305. mod_timer(&intel_crtc->idle_timer, jiffies +
  4306. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  4307. }
  4308. }
  4309. }
  4310. }
  4311. static void intel_crtc_destroy(struct drm_crtc *crtc)
  4312. {
  4313. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4314. struct drm_device *dev = crtc->dev;
  4315. struct intel_unpin_work *work;
  4316. unsigned long flags;
  4317. spin_lock_irqsave(&dev->event_lock, flags);
  4318. work = intel_crtc->unpin_work;
  4319. intel_crtc->unpin_work = NULL;
  4320. spin_unlock_irqrestore(&dev->event_lock, flags);
  4321. if (work) {
  4322. cancel_work_sync(&work->work);
  4323. kfree(work);
  4324. }
  4325. drm_crtc_cleanup(crtc);
  4326. kfree(intel_crtc);
  4327. }
  4328. static void intel_unpin_work_fn(struct work_struct *__work)
  4329. {
  4330. struct intel_unpin_work *work =
  4331. container_of(__work, struct intel_unpin_work, work);
  4332. mutex_lock(&work->dev->struct_mutex);
  4333. i915_gem_object_unpin(work->old_fb_obj);
  4334. drm_gem_object_unreference(work->pending_flip_obj);
  4335. drm_gem_object_unreference(work->old_fb_obj);
  4336. mutex_unlock(&work->dev->struct_mutex);
  4337. kfree(work);
  4338. }
  4339. static void do_intel_finish_page_flip(struct drm_device *dev,
  4340. struct drm_crtc *crtc)
  4341. {
  4342. drm_i915_private_t *dev_priv = dev->dev_private;
  4343. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4344. struct intel_unpin_work *work;
  4345. struct drm_i915_gem_object *obj_priv;
  4346. struct drm_pending_vblank_event *e;
  4347. struct timeval now;
  4348. unsigned long flags;
  4349. /* Ignore early vblank irqs */
  4350. if (intel_crtc == NULL)
  4351. return;
  4352. spin_lock_irqsave(&dev->event_lock, flags);
  4353. work = intel_crtc->unpin_work;
  4354. if (work == NULL || !work->pending) {
  4355. spin_unlock_irqrestore(&dev->event_lock, flags);
  4356. return;
  4357. }
  4358. intel_crtc->unpin_work = NULL;
  4359. drm_vblank_put(dev, intel_crtc->pipe);
  4360. if (work->event) {
  4361. e = work->event;
  4362. do_gettimeofday(&now);
  4363. e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
  4364. e->event.tv_sec = now.tv_sec;
  4365. e->event.tv_usec = now.tv_usec;
  4366. list_add_tail(&e->base.link,
  4367. &e->base.file_priv->event_list);
  4368. wake_up_interruptible(&e->base.file_priv->event_wait);
  4369. }
  4370. spin_unlock_irqrestore(&dev->event_lock, flags);
  4371. obj_priv = to_intel_bo(work->pending_flip_obj);
  4372. /* Initial scanout buffer will have a 0 pending flip count */
  4373. if ((atomic_read(&obj_priv->pending_flip) == 0) ||
  4374. atomic_dec_and_test(&obj_priv->pending_flip))
  4375. DRM_WAKEUP(&dev_priv->pending_flip_queue);
  4376. schedule_work(&work->work);
  4377. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  4378. }
  4379. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  4380. {
  4381. drm_i915_private_t *dev_priv = dev->dev_private;
  4382. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  4383. do_intel_finish_page_flip(dev, crtc);
  4384. }
  4385. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  4386. {
  4387. drm_i915_private_t *dev_priv = dev->dev_private;
  4388. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  4389. do_intel_finish_page_flip(dev, crtc);
  4390. }
  4391. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  4392. {
  4393. drm_i915_private_t *dev_priv = dev->dev_private;
  4394. struct intel_crtc *intel_crtc =
  4395. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  4396. unsigned long flags;
  4397. spin_lock_irqsave(&dev->event_lock, flags);
  4398. if (intel_crtc->unpin_work) {
  4399. if ((++intel_crtc->unpin_work->pending) > 1)
  4400. DRM_ERROR("Prepared flip multiple times\n");
  4401. } else {
  4402. DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
  4403. }
  4404. spin_unlock_irqrestore(&dev->event_lock, flags);
  4405. }
  4406. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  4407. struct drm_framebuffer *fb,
  4408. struct drm_pending_vblank_event *event)
  4409. {
  4410. struct drm_device *dev = crtc->dev;
  4411. struct drm_i915_private *dev_priv = dev->dev_private;
  4412. struct intel_framebuffer *intel_fb;
  4413. struct drm_i915_gem_object *obj_priv;
  4414. struct drm_gem_object *obj;
  4415. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4416. struct intel_unpin_work *work;
  4417. unsigned long flags, offset;
  4418. int pipe = intel_crtc->pipe;
  4419. u32 pf, pipesrc;
  4420. int ret;
  4421. work = kzalloc(sizeof *work, GFP_KERNEL);
  4422. if (work == NULL)
  4423. return -ENOMEM;
  4424. work->event = event;
  4425. work->dev = crtc->dev;
  4426. intel_fb = to_intel_framebuffer(crtc->fb);
  4427. work->old_fb_obj = intel_fb->obj;
  4428. INIT_WORK(&work->work, intel_unpin_work_fn);
  4429. /* We borrow the event spin lock for protecting unpin_work */
  4430. spin_lock_irqsave(&dev->event_lock, flags);
  4431. if (intel_crtc->unpin_work) {
  4432. spin_unlock_irqrestore(&dev->event_lock, flags);
  4433. kfree(work);
  4434. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  4435. return -EBUSY;
  4436. }
  4437. intel_crtc->unpin_work = work;
  4438. spin_unlock_irqrestore(&dev->event_lock, flags);
  4439. intel_fb = to_intel_framebuffer(fb);
  4440. obj = intel_fb->obj;
  4441. mutex_lock(&dev->struct_mutex);
  4442. ret = intel_pin_and_fence_fb_obj(dev, obj);
  4443. if (ret)
  4444. goto cleanup_work;
  4445. /* Reference the objects for the scheduled work. */
  4446. drm_gem_object_reference(work->old_fb_obj);
  4447. drm_gem_object_reference(obj);
  4448. crtc->fb = fb;
  4449. ret = i915_gem_object_flush_write_domain(obj);
  4450. if (ret)
  4451. goto cleanup_objs;
  4452. ret = drm_vblank_get(dev, intel_crtc->pipe);
  4453. if (ret)
  4454. goto cleanup_objs;
  4455. obj_priv = to_intel_bo(obj);
  4456. atomic_inc(&obj_priv->pending_flip);
  4457. work->pending_flip_obj = obj;
  4458. if (IS_GEN3(dev) || IS_GEN2(dev)) {
  4459. u32 flip_mask;
  4460. if (intel_crtc->plane)
  4461. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  4462. else
  4463. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  4464. BEGIN_LP_RING(2);
  4465. OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
  4466. OUT_RING(0);
  4467. ADVANCE_LP_RING();
  4468. }
  4469. work->enable_stall_check = true;
  4470. /* Offset into the new buffer for cases of shared fbs between CRTCs */
  4471. offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
  4472. BEGIN_LP_RING(4);
  4473. switch(INTEL_INFO(dev)->gen) {
  4474. case 2:
  4475. OUT_RING(MI_DISPLAY_FLIP |
  4476. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4477. OUT_RING(fb->pitch);
  4478. OUT_RING(obj_priv->gtt_offset + offset);
  4479. OUT_RING(MI_NOOP);
  4480. break;
  4481. case 3:
  4482. OUT_RING(MI_DISPLAY_FLIP_I915 |
  4483. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4484. OUT_RING(fb->pitch);
  4485. OUT_RING(obj_priv->gtt_offset + offset);
  4486. OUT_RING(MI_NOOP);
  4487. break;
  4488. case 4:
  4489. case 5:
  4490. /* i965+ uses the linear or tiled offsets from the
  4491. * Display Registers (which do not change across a page-flip)
  4492. * so we need only reprogram the base address.
  4493. */
  4494. OUT_RING(MI_DISPLAY_FLIP |
  4495. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4496. OUT_RING(fb->pitch);
  4497. OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
  4498. /* XXX Enabling the panel-fitter across page-flip is so far
  4499. * untested on non-native modes, so ignore it for now.
  4500. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  4501. */
  4502. pf = 0;
  4503. pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
  4504. OUT_RING(pf | pipesrc);
  4505. break;
  4506. case 6:
  4507. OUT_RING(MI_DISPLAY_FLIP |
  4508. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4509. OUT_RING(fb->pitch | obj_priv->tiling_mode);
  4510. OUT_RING(obj_priv->gtt_offset);
  4511. pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  4512. pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
  4513. OUT_RING(pf | pipesrc);
  4514. break;
  4515. }
  4516. ADVANCE_LP_RING();
  4517. mutex_unlock(&dev->struct_mutex);
  4518. trace_i915_flip_request(intel_crtc->plane, obj);
  4519. return 0;
  4520. cleanup_objs:
  4521. drm_gem_object_unreference(work->old_fb_obj);
  4522. drm_gem_object_unreference(obj);
  4523. cleanup_work:
  4524. mutex_unlock(&dev->struct_mutex);
  4525. spin_lock_irqsave(&dev->event_lock, flags);
  4526. intel_crtc->unpin_work = NULL;
  4527. spin_unlock_irqrestore(&dev->event_lock, flags);
  4528. kfree(work);
  4529. return ret;
  4530. }
  4531. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  4532. .dpms = intel_crtc_dpms,
  4533. .mode_fixup = intel_crtc_mode_fixup,
  4534. .mode_set = intel_crtc_mode_set,
  4535. .mode_set_base = intel_pipe_set_base,
  4536. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  4537. .load_lut = intel_crtc_load_lut,
  4538. };
  4539. static const struct drm_crtc_funcs intel_crtc_funcs = {
  4540. .cursor_set = intel_crtc_cursor_set,
  4541. .cursor_move = intel_crtc_cursor_move,
  4542. .gamma_set = intel_crtc_gamma_set,
  4543. .set_config = drm_crtc_helper_set_config,
  4544. .destroy = intel_crtc_destroy,
  4545. .page_flip = intel_crtc_page_flip,
  4546. };
  4547. static void intel_crtc_init(struct drm_device *dev, int pipe)
  4548. {
  4549. drm_i915_private_t *dev_priv = dev->dev_private;
  4550. struct intel_crtc *intel_crtc;
  4551. int i;
  4552. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  4553. if (intel_crtc == NULL)
  4554. return;
  4555. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  4556. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  4557. intel_crtc->pipe = pipe;
  4558. intel_crtc->plane = pipe;
  4559. for (i = 0; i < 256; i++) {
  4560. intel_crtc->lut_r[i] = i;
  4561. intel_crtc->lut_g[i] = i;
  4562. intel_crtc->lut_b[i] = i;
  4563. }
  4564. /* Swap pipes & planes for FBC on pre-965 */
  4565. intel_crtc->pipe = pipe;
  4566. intel_crtc->plane = pipe;
  4567. if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
  4568. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  4569. intel_crtc->plane = ((pipe == 0) ? 1 : 0);
  4570. }
  4571. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  4572. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  4573. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  4574. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  4575. intel_crtc->cursor_addr = 0;
  4576. intel_crtc->dpms_mode = -1;
  4577. if (HAS_PCH_SPLIT(dev)) {
  4578. intel_helper_funcs.prepare = ironlake_crtc_prepare;
  4579. intel_helper_funcs.commit = ironlake_crtc_commit;
  4580. } else {
  4581. intel_helper_funcs.prepare = i9xx_crtc_prepare;
  4582. intel_helper_funcs.commit = i9xx_crtc_commit;
  4583. }
  4584. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  4585. intel_crtc->busy = false;
  4586. setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
  4587. (unsigned long)intel_crtc);
  4588. }
  4589. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  4590. struct drm_file *file_priv)
  4591. {
  4592. drm_i915_private_t *dev_priv = dev->dev_private;
  4593. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  4594. struct drm_mode_object *drmmode_obj;
  4595. struct intel_crtc *crtc;
  4596. if (!dev_priv) {
  4597. DRM_ERROR("called with no initialization\n");
  4598. return -EINVAL;
  4599. }
  4600. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  4601. DRM_MODE_OBJECT_CRTC);
  4602. if (!drmmode_obj) {
  4603. DRM_ERROR("no such CRTC id\n");
  4604. return -EINVAL;
  4605. }
  4606. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  4607. pipe_from_crtc_id->pipe = crtc->pipe;
  4608. return 0;
  4609. }
  4610. static int intel_encoder_clones(struct drm_device *dev, int type_mask)
  4611. {
  4612. struct intel_encoder *encoder;
  4613. int index_mask = 0;
  4614. int entry = 0;
  4615. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  4616. if (type_mask & encoder->clone_mask)
  4617. index_mask |= (1 << entry);
  4618. entry++;
  4619. }
  4620. return index_mask;
  4621. }
  4622. static void intel_setup_outputs(struct drm_device *dev)
  4623. {
  4624. struct drm_i915_private *dev_priv = dev->dev_private;
  4625. struct intel_encoder *encoder;
  4626. bool dpd_is_edp = false;
  4627. if (IS_MOBILE(dev) && !IS_I830(dev))
  4628. intel_lvds_init(dev);
  4629. if (HAS_PCH_SPLIT(dev)) {
  4630. dpd_is_edp = intel_dpd_is_edp(dev);
  4631. if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
  4632. intel_dp_init(dev, DP_A);
  4633. if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  4634. intel_dp_init(dev, PCH_DP_D);
  4635. }
  4636. intel_crt_init(dev);
  4637. if (HAS_PCH_SPLIT(dev)) {
  4638. int found;
  4639. if (I915_READ(HDMIB) & PORT_DETECTED) {
  4640. /* PCH SDVOB multiplex with HDMIB */
  4641. found = intel_sdvo_init(dev, PCH_SDVOB);
  4642. if (!found)
  4643. intel_hdmi_init(dev, HDMIB);
  4644. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  4645. intel_dp_init(dev, PCH_DP_B);
  4646. }
  4647. if (I915_READ(HDMIC) & PORT_DETECTED)
  4648. intel_hdmi_init(dev, HDMIC);
  4649. if (I915_READ(HDMID) & PORT_DETECTED)
  4650. intel_hdmi_init(dev, HDMID);
  4651. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  4652. intel_dp_init(dev, PCH_DP_C);
  4653. if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  4654. intel_dp_init(dev, PCH_DP_D);
  4655. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  4656. bool found = false;
  4657. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  4658. DRM_DEBUG_KMS("probing SDVOB\n");
  4659. found = intel_sdvo_init(dev, SDVOB);
  4660. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  4661. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  4662. intel_hdmi_init(dev, SDVOB);
  4663. }
  4664. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  4665. DRM_DEBUG_KMS("probing DP_B\n");
  4666. intel_dp_init(dev, DP_B);
  4667. }
  4668. }
  4669. /* Before G4X SDVOC doesn't have its own detect register */
  4670. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  4671. DRM_DEBUG_KMS("probing SDVOC\n");
  4672. found = intel_sdvo_init(dev, SDVOC);
  4673. }
  4674. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  4675. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  4676. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  4677. intel_hdmi_init(dev, SDVOC);
  4678. }
  4679. if (SUPPORTS_INTEGRATED_DP(dev)) {
  4680. DRM_DEBUG_KMS("probing DP_C\n");
  4681. intel_dp_init(dev, DP_C);
  4682. }
  4683. }
  4684. if (SUPPORTS_INTEGRATED_DP(dev) &&
  4685. (I915_READ(DP_D) & DP_DETECTED)) {
  4686. DRM_DEBUG_KMS("probing DP_D\n");
  4687. intel_dp_init(dev, DP_D);
  4688. }
  4689. } else if (IS_GEN2(dev))
  4690. intel_dvo_init(dev);
  4691. if (SUPPORTS_TV(dev))
  4692. intel_tv_init(dev);
  4693. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  4694. encoder->base.possible_crtcs = encoder->crtc_mask;
  4695. encoder->base.possible_clones =
  4696. intel_encoder_clones(dev, encoder->clone_mask);
  4697. }
  4698. }
  4699. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  4700. {
  4701. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  4702. drm_framebuffer_cleanup(fb);
  4703. drm_gem_object_unreference_unlocked(intel_fb->obj);
  4704. kfree(intel_fb);
  4705. }
  4706. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  4707. struct drm_file *file_priv,
  4708. unsigned int *handle)
  4709. {
  4710. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  4711. struct drm_gem_object *object = intel_fb->obj;
  4712. return drm_gem_handle_create(file_priv, object, handle);
  4713. }
  4714. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  4715. .destroy = intel_user_framebuffer_destroy,
  4716. .create_handle = intel_user_framebuffer_create_handle,
  4717. };
  4718. int intel_framebuffer_init(struct drm_device *dev,
  4719. struct intel_framebuffer *intel_fb,
  4720. struct drm_mode_fb_cmd *mode_cmd,
  4721. struct drm_gem_object *obj)
  4722. {
  4723. struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
  4724. int ret;
  4725. if (obj_priv->tiling_mode == I915_TILING_Y)
  4726. return -EINVAL;
  4727. if (mode_cmd->pitch & 63)
  4728. return -EINVAL;
  4729. switch (mode_cmd->bpp) {
  4730. case 8:
  4731. case 16:
  4732. case 24:
  4733. case 32:
  4734. break;
  4735. default:
  4736. return -EINVAL;
  4737. }
  4738. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  4739. if (ret) {
  4740. DRM_ERROR("framebuffer init failed %d\n", ret);
  4741. return ret;
  4742. }
  4743. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  4744. intel_fb->obj = obj;
  4745. return 0;
  4746. }
  4747. static struct drm_framebuffer *
  4748. intel_user_framebuffer_create(struct drm_device *dev,
  4749. struct drm_file *filp,
  4750. struct drm_mode_fb_cmd *mode_cmd)
  4751. {
  4752. struct drm_gem_object *obj;
  4753. struct intel_framebuffer *intel_fb;
  4754. int ret;
  4755. obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
  4756. if (!obj)
  4757. return ERR_PTR(-ENOENT);
  4758. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  4759. if (!intel_fb)
  4760. return ERR_PTR(-ENOMEM);
  4761. ret = intel_framebuffer_init(dev, intel_fb,
  4762. mode_cmd, obj);
  4763. if (ret) {
  4764. drm_gem_object_unreference_unlocked(obj);
  4765. kfree(intel_fb);
  4766. return ERR_PTR(ret);
  4767. }
  4768. return &intel_fb->base;
  4769. }
  4770. static const struct drm_mode_config_funcs intel_mode_funcs = {
  4771. .fb_create = intel_user_framebuffer_create,
  4772. .output_poll_changed = intel_fb_output_poll_changed,
  4773. };
  4774. static struct drm_gem_object *
  4775. intel_alloc_context_page(struct drm_device *dev)
  4776. {
  4777. struct drm_gem_object *ctx;
  4778. int ret;
  4779. ctx = i915_gem_alloc_object(dev, 4096);
  4780. if (!ctx) {
  4781. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  4782. return NULL;
  4783. }
  4784. mutex_lock(&dev->struct_mutex);
  4785. ret = i915_gem_object_pin(ctx, 4096);
  4786. if (ret) {
  4787. DRM_ERROR("failed to pin power context: %d\n", ret);
  4788. goto err_unref;
  4789. }
  4790. ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
  4791. if (ret) {
  4792. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  4793. goto err_unpin;
  4794. }
  4795. mutex_unlock(&dev->struct_mutex);
  4796. return ctx;
  4797. err_unpin:
  4798. i915_gem_object_unpin(ctx);
  4799. err_unref:
  4800. drm_gem_object_unreference(ctx);
  4801. mutex_unlock(&dev->struct_mutex);
  4802. return NULL;
  4803. }
  4804. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  4805. {
  4806. struct drm_i915_private *dev_priv = dev->dev_private;
  4807. u16 rgvswctl;
  4808. rgvswctl = I915_READ16(MEMSWCTL);
  4809. if (rgvswctl & MEMCTL_CMD_STS) {
  4810. DRM_DEBUG("gpu busy, RCS change rejected\n");
  4811. return false; /* still busy with another command */
  4812. }
  4813. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  4814. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  4815. I915_WRITE16(MEMSWCTL, rgvswctl);
  4816. POSTING_READ16(MEMSWCTL);
  4817. rgvswctl |= MEMCTL_CMD_STS;
  4818. I915_WRITE16(MEMSWCTL, rgvswctl);
  4819. return true;
  4820. }
  4821. void ironlake_enable_drps(struct drm_device *dev)
  4822. {
  4823. struct drm_i915_private *dev_priv = dev->dev_private;
  4824. u32 rgvmodectl = I915_READ(MEMMODECTL);
  4825. u8 fmax, fmin, fstart, vstart;
  4826. /* 100ms RC evaluation intervals */
  4827. I915_WRITE(RCUPEI, 100000);
  4828. I915_WRITE(RCDNEI, 100000);
  4829. /* Set max/min thresholds to 90ms and 80ms respectively */
  4830. I915_WRITE(RCBMAXAVG, 90000);
  4831. I915_WRITE(RCBMINAVG, 80000);
  4832. I915_WRITE(MEMIHYST, 1);
  4833. /* Set up min, max, and cur for interrupt handling */
  4834. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  4835. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  4836. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  4837. MEMMODE_FSTART_SHIFT;
  4838. fstart = fmax;
  4839. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  4840. PXVFREQ_PX_SHIFT;
  4841. dev_priv->fmax = fstart; /* IPS callback will increase this */
  4842. dev_priv->fstart = fstart;
  4843. dev_priv->max_delay = fmax;
  4844. dev_priv->min_delay = fmin;
  4845. dev_priv->cur_delay = fstart;
  4846. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
  4847. fstart);
  4848. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  4849. /*
  4850. * Interrupts will be enabled in ironlake_irq_postinstall
  4851. */
  4852. I915_WRITE(VIDSTART, vstart);
  4853. POSTING_READ(VIDSTART);
  4854. rgvmodectl |= MEMMODE_SWMODE_EN;
  4855. I915_WRITE(MEMMODECTL, rgvmodectl);
  4856. if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
  4857. DRM_ERROR("stuck trying to change perf mode\n");
  4858. msleep(1);
  4859. ironlake_set_drps(dev, fstart);
  4860. dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  4861. I915_READ(0x112e0);
  4862. dev_priv->last_time1 = jiffies_to_msecs(jiffies);
  4863. dev_priv->last_count2 = I915_READ(0x112f4);
  4864. getrawmonotonic(&dev_priv->last_time2);
  4865. }
  4866. void ironlake_disable_drps(struct drm_device *dev)
  4867. {
  4868. struct drm_i915_private *dev_priv = dev->dev_private;
  4869. u16 rgvswctl = I915_READ16(MEMSWCTL);
  4870. /* Ack interrupts, disable EFC interrupt */
  4871. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  4872. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  4873. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  4874. I915_WRITE(DEIIR, DE_PCU_EVENT);
  4875. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  4876. /* Go back to the starting frequency */
  4877. ironlake_set_drps(dev, dev_priv->fstart);
  4878. msleep(1);
  4879. rgvswctl |= MEMCTL_CMD_STS;
  4880. I915_WRITE(MEMSWCTL, rgvswctl);
  4881. msleep(1);
  4882. }
  4883. static unsigned long intel_pxfreq(u32 vidfreq)
  4884. {
  4885. unsigned long freq;
  4886. int div = (vidfreq & 0x3f0000) >> 16;
  4887. int post = (vidfreq & 0x3000) >> 12;
  4888. int pre = (vidfreq & 0x7);
  4889. if (!pre)
  4890. return 0;
  4891. freq = ((div * 133333) / ((1<<post) * pre));
  4892. return freq;
  4893. }
  4894. void intel_init_emon(struct drm_device *dev)
  4895. {
  4896. struct drm_i915_private *dev_priv = dev->dev_private;
  4897. u32 lcfuse;
  4898. u8 pxw[16];
  4899. int i;
  4900. /* Disable to program */
  4901. I915_WRITE(ECR, 0);
  4902. POSTING_READ(ECR);
  4903. /* Program energy weights for various events */
  4904. I915_WRITE(SDEW, 0x15040d00);
  4905. I915_WRITE(CSIEW0, 0x007f0000);
  4906. I915_WRITE(CSIEW1, 0x1e220004);
  4907. I915_WRITE(CSIEW2, 0x04000004);
  4908. for (i = 0; i < 5; i++)
  4909. I915_WRITE(PEW + (i * 4), 0);
  4910. for (i = 0; i < 3; i++)
  4911. I915_WRITE(DEW + (i * 4), 0);
  4912. /* Program P-state weights to account for frequency power adjustment */
  4913. for (i = 0; i < 16; i++) {
  4914. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  4915. unsigned long freq = intel_pxfreq(pxvidfreq);
  4916. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  4917. PXVFREQ_PX_SHIFT;
  4918. unsigned long val;
  4919. val = vid * vid;
  4920. val *= (freq / 1000);
  4921. val *= 255;
  4922. val /= (127*127*900);
  4923. if (val > 0xff)
  4924. DRM_ERROR("bad pxval: %ld\n", val);
  4925. pxw[i] = val;
  4926. }
  4927. /* Render standby states get 0 weight */
  4928. pxw[14] = 0;
  4929. pxw[15] = 0;
  4930. for (i = 0; i < 4; i++) {
  4931. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  4932. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  4933. I915_WRITE(PXW + (i * 4), val);
  4934. }
  4935. /* Adjust magic regs to magic values (more experimental results) */
  4936. I915_WRITE(OGW0, 0);
  4937. I915_WRITE(OGW1, 0);
  4938. I915_WRITE(EG0, 0x00007f00);
  4939. I915_WRITE(EG1, 0x0000000e);
  4940. I915_WRITE(EG2, 0x000e0000);
  4941. I915_WRITE(EG3, 0x68000300);
  4942. I915_WRITE(EG4, 0x42000000);
  4943. I915_WRITE(EG5, 0x00140031);
  4944. I915_WRITE(EG6, 0);
  4945. I915_WRITE(EG7, 0);
  4946. for (i = 0; i < 8; i++)
  4947. I915_WRITE(PXWL + (i * 4), 0);
  4948. /* Enable PMON + select events */
  4949. I915_WRITE(ECR, 0x80000019);
  4950. lcfuse = I915_READ(LCFUSE02);
  4951. dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
  4952. }
  4953. void intel_init_clock_gating(struct drm_device *dev)
  4954. {
  4955. struct drm_i915_private *dev_priv = dev->dev_private;
  4956. /*
  4957. * Disable clock gating reported to work incorrectly according to the
  4958. * specs, but enable as much else as we can.
  4959. */
  4960. if (HAS_PCH_SPLIT(dev)) {
  4961. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  4962. if (IS_IRONLAKE(dev)) {
  4963. /* Required for FBC */
  4964. dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
  4965. /* Required for CxSR */
  4966. dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  4967. I915_WRITE(PCH_3DCGDIS0,
  4968. MARIUNIT_CLOCK_GATE_DISABLE |
  4969. SVSMUNIT_CLOCK_GATE_DISABLE);
  4970. }
  4971. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  4972. /*
  4973. * According to the spec the following bits should be set in
  4974. * order to enable memory self-refresh
  4975. * The bit 22/21 of 0x42004
  4976. * The bit 5 of 0x42020
  4977. * The bit 15 of 0x45000
  4978. */
  4979. if (IS_IRONLAKE(dev)) {
  4980. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  4981. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  4982. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  4983. I915_WRITE(ILK_DSPCLK_GATE,
  4984. (I915_READ(ILK_DSPCLK_GATE) |
  4985. ILK_DPARB_CLK_GATE));
  4986. I915_WRITE(DISP_ARB_CTL,
  4987. (I915_READ(DISP_ARB_CTL) |
  4988. DISP_FBC_WM_DIS));
  4989. }
  4990. /*
  4991. * Based on the document from hardware guys the following bits
  4992. * should be set unconditionally in order to enable FBC.
  4993. * The bit 22 of 0x42000
  4994. * The bit 22 of 0x42004
  4995. * The bit 7,8,9 of 0x42020.
  4996. */
  4997. if (IS_IRONLAKE_M(dev)) {
  4998. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  4999. I915_READ(ILK_DISPLAY_CHICKEN1) |
  5000. ILK_FBCQ_DIS);
  5001. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  5002. I915_READ(ILK_DISPLAY_CHICKEN2) |
  5003. ILK_DPARB_GATE);
  5004. I915_WRITE(ILK_DSPCLK_GATE,
  5005. I915_READ(ILK_DSPCLK_GATE) |
  5006. ILK_DPFC_DIS1 |
  5007. ILK_DPFC_DIS2 |
  5008. ILK_CLK_FBC);
  5009. }
  5010. return;
  5011. } else if (IS_G4X(dev)) {
  5012. uint32_t dspclk_gate;
  5013. I915_WRITE(RENCLK_GATE_D1, 0);
  5014. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  5015. GS_UNIT_CLOCK_GATE_DISABLE |
  5016. CL_UNIT_CLOCK_GATE_DISABLE);
  5017. I915_WRITE(RAMCLK_GATE_D, 0);
  5018. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  5019. OVRUNIT_CLOCK_GATE_DISABLE |
  5020. OVCUNIT_CLOCK_GATE_DISABLE;
  5021. if (IS_GM45(dev))
  5022. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  5023. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  5024. } else if (IS_I965GM(dev)) {
  5025. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  5026. I915_WRITE(RENCLK_GATE_D2, 0);
  5027. I915_WRITE(DSPCLK_GATE_D, 0);
  5028. I915_WRITE(RAMCLK_GATE_D, 0);
  5029. I915_WRITE16(DEUC, 0);
  5030. } else if (IS_I965G(dev)) {
  5031. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  5032. I965_RCC_CLOCK_GATE_DISABLE |
  5033. I965_RCPB_CLOCK_GATE_DISABLE |
  5034. I965_ISC_CLOCK_GATE_DISABLE |
  5035. I965_FBC_CLOCK_GATE_DISABLE);
  5036. I915_WRITE(RENCLK_GATE_D2, 0);
  5037. } else if (IS_I9XX(dev)) {
  5038. u32 dstate = I915_READ(D_STATE);
  5039. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  5040. DSTATE_DOT_CLOCK_GATING;
  5041. I915_WRITE(D_STATE, dstate);
  5042. } else if (IS_I85X(dev) || IS_I865G(dev)) {
  5043. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  5044. } else if (IS_I830(dev)) {
  5045. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  5046. }
  5047. /*
  5048. * GPU can automatically power down the render unit if given a page
  5049. * to save state.
  5050. */
  5051. if (IS_IRONLAKE_M(dev)) {
  5052. if (dev_priv->renderctx == NULL)
  5053. dev_priv->renderctx = intel_alloc_context_page(dev);
  5054. if (dev_priv->renderctx) {
  5055. struct drm_i915_gem_object *obj_priv;
  5056. obj_priv = to_intel_bo(dev_priv->renderctx);
  5057. if (obj_priv) {
  5058. BEGIN_LP_RING(4);
  5059. OUT_RING(MI_SET_CONTEXT);
  5060. OUT_RING(obj_priv->gtt_offset |
  5061. MI_MM_SPACE_GTT |
  5062. MI_SAVE_EXT_STATE_EN |
  5063. MI_RESTORE_EXT_STATE_EN |
  5064. MI_RESTORE_INHIBIT);
  5065. OUT_RING(MI_NOOP);
  5066. OUT_RING(MI_FLUSH);
  5067. ADVANCE_LP_RING();
  5068. }
  5069. } else
  5070. DRM_DEBUG_KMS("Failed to allocate render context."
  5071. "Disable RC6\n");
  5072. }
  5073. if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
  5074. struct drm_i915_gem_object *obj_priv = NULL;
  5075. if (dev_priv->pwrctx) {
  5076. obj_priv = to_intel_bo(dev_priv->pwrctx);
  5077. } else {
  5078. struct drm_gem_object *pwrctx;
  5079. pwrctx = intel_alloc_context_page(dev);
  5080. if (pwrctx) {
  5081. dev_priv->pwrctx = pwrctx;
  5082. obj_priv = to_intel_bo(pwrctx);
  5083. }
  5084. }
  5085. if (obj_priv) {
  5086. I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
  5087. I915_WRITE(MCHBAR_RENDER_STANDBY,
  5088. I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
  5089. }
  5090. }
  5091. }
  5092. /* Set up chip specific display functions */
  5093. static void intel_init_display(struct drm_device *dev)
  5094. {
  5095. struct drm_i915_private *dev_priv = dev->dev_private;
  5096. /* We always want a DPMS function */
  5097. if (HAS_PCH_SPLIT(dev))
  5098. dev_priv->display.dpms = ironlake_crtc_dpms;
  5099. else
  5100. dev_priv->display.dpms = i9xx_crtc_dpms;
  5101. if (I915_HAS_FBC(dev)) {
  5102. if (IS_IRONLAKE_M(dev)) {
  5103. dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  5104. dev_priv->display.enable_fbc = ironlake_enable_fbc;
  5105. dev_priv->display.disable_fbc = ironlake_disable_fbc;
  5106. } else if (IS_GM45(dev)) {
  5107. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  5108. dev_priv->display.enable_fbc = g4x_enable_fbc;
  5109. dev_priv->display.disable_fbc = g4x_disable_fbc;
  5110. } else if (IS_I965GM(dev)) {
  5111. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  5112. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  5113. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  5114. }
  5115. /* 855GM needs testing */
  5116. }
  5117. /* Returns the core display clock speed */
  5118. if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
  5119. dev_priv->display.get_display_clock_speed =
  5120. i945_get_display_clock_speed;
  5121. else if (IS_I915G(dev))
  5122. dev_priv->display.get_display_clock_speed =
  5123. i915_get_display_clock_speed;
  5124. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  5125. dev_priv->display.get_display_clock_speed =
  5126. i9xx_misc_get_display_clock_speed;
  5127. else if (IS_I915GM(dev))
  5128. dev_priv->display.get_display_clock_speed =
  5129. i915gm_get_display_clock_speed;
  5130. else if (IS_I865G(dev))
  5131. dev_priv->display.get_display_clock_speed =
  5132. i865_get_display_clock_speed;
  5133. else if (IS_I85X(dev))
  5134. dev_priv->display.get_display_clock_speed =
  5135. i855_get_display_clock_speed;
  5136. else /* 852, 830 */
  5137. dev_priv->display.get_display_clock_speed =
  5138. i830_get_display_clock_speed;
  5139. /* For FIFO watermark updates */
  5140. if (HAS_PCH_SPLIT(dev)) {
  5141. if (IS_IRONLAKE(dev)) {
  5142. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  5143. dev_priv->display.update_wm = ironlake_update_wm;
  5144. else {
  5145. DRM_DEBUG_KMS("Failed to get proper latency. "
  5146. "Disable CxSR\n");
  5147. dev_priv->display.update_wm = NULL;
  5148. }
  5149. } else
  5150. dev_priv->display.update_wm = NULL;
  5151. } else if (IS_PINEVIEW(dev)) {
  5152. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  5153. dev_priv->is_ddr3,
  5154. dev_priv->fsb_freq,
  5155. dev_priv->mem_freq)) {
  5156. DRM_INFO("failed to find known CxSR latency "
  5157. "(found ddr%s fsb freq %d, mem freq %d), "
  5158. "disabling CxSR\n",
  5159. (dev_priv->is_ddr3 == 1) ? "3": "2",
  5160. dev_priv->fsb_freq, dev_priv->mem_freq);
  5161. /* Disable CxSR and never update its watermark again */
  5162. pineview_disable_cxsr(dev);
  5163. dev_priv->display.update_wm = NULL;
  5164. } else
  5165. dev_priv->display.update_wm = pineview_update_wm;
  5166. } else if (IS_G4X(dev))
  5167. dev_priv->display.update_wm = g4x_update_wm;
  5168. else if (IS_I965G(dev))
  5169. dev_priv->display.update_wm = i965_update_wm;
  5170. else if (IS_I9XX(dev)) {
  5171. dev_priv->display.update_wm = i9xx_update_wm;
  5172. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  5173. } else if (IS_I85X(dev)) {
  5174. dev_priv->display.update_wm = i9xx_update_wm;
  5175. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  5176. } else {
  5177. dev_priv->display.update_wm = i830_update_wm;
  5178. if (IS_845G(dev))
  5179. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  5180. else
  5181. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  5182. }
  5183. }
  5184. /*
  5185. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  5186. * resume, or other times. This quirk makes sure that's the case for
  5187. * affected systems.
  5188. */
  5189. static void quirk_pipea_force (struct drm_device *dev)
  5190. {
  5191. struct drm_i915_private *dev_priv = dev->dev_private;
  5192. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  5193. DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
  5194. }
  5195. struct intel_quirk {
  5196. int device;
  5197. int subsystem_vendor;
  5198. int subsystem_device;
  5199. void (*hook)(struct drm_device *dev);
  5200. };
  5201. struct intel_quirk intel_quirks[] = {
  5202. /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
  5203. { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
  5204. /* HP Mini needs pipe A force quirk (LP: #322104) */
  5205. { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
  5206. /* Thinkpad R31 needs pipe A force quirk */
  5207. { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
  5208. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  5209. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  5210. /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
  5211. { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
  5212. /* ThinkPad X40 needs pipe A force quirk */
  5213. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  5214. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  5215. /* 855 & before need to leave pipe A & dpll A up */
  5216. { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  5217. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  5218. };
  5219. static void intel_init_quirks(struct drm_device *dev)
  5220. {
  5221. struct pci_dev *d = dev->pdev;
  5222. int i;
  5223. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  5224. struct intel_quirk *q = &intel_quirks[i];
  5225. if (d->device == q->device &&
  5226. (d->subsystem_vendor == q->subsystem_vendor ||
  5227. q->subsystem_vendor == PCI_ANY_ID) &&
  5228. (d->subsystem_device == q->subsystem_device ||
  5229. q->subsystem_device == PCI_ANY_ID))
  5230. q->hook(dev);
  5231. }
  5232. }
  5233. /* Disable the VGA plane that we never use */
  5234. static void i915_disable_vga(struct drm_device *dev)
  5235. {
  5236. struct drm_i915_private *dev_priv = dev->dev_private;
  5237. u8 sr1;
  5238. u32 vga_reg;
  5239. if (HAS_PCH_SPLIT(dev))
  5240. vga_reg = CPU_VGACNTRL;
  5241. else
  5242. vga_reg = VGACNTRL;
  5243. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  5244. outb(1, VGA_SR_INDEX);
  5245. sr1 = inb(VGA_SR_DATA);
  5246. outb(sr1 | 1<<5, VGA_SR_DATA);
  5247. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  5248. udelay(300);
  5249. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  5250. POSTING_READ(vga_reg);
  5251. }
  5252. void intel_modeset_init(struct drm_device *dev)
  5253. {
  5254. struct drm_i915_private *dev_priv = dev->dev_private;
  5255. int i;
  5256. drm_mode_config_init(dev);
  5257. dev->mode_config.min_width = 0;
  5258. dev->mode_config.min_height = 0;
  5259. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  5260. intel_init_quirks(dev);
  5261. intel_init_display(dev);
  5262. if (IS_I965G(dev)) {
  5263. dev->mode_config.max_width = 8192;
  5264. dev->mode_config.max_height = 8192;
  5265. } else if (IS_I9XX(dev)) {
  5266. dev->mode_config.max_width = 4096;
  5267. dev->mode_config.max_height = 4096;
  5268. } else {
  5269. dev->mode_config.max_width = 2048;
  5270. dev->mode_config.max_height = 2048;
  5271. }
  5272. /* set memory base */
  5273. if (IS_I9XX(dev))
  5274. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
  5275. else
  5276. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
  5277. if (IS_MOBILE(dev) || IS_I9XX(dev))
  5278. dev_priv->num_pipe = 2;
  5279. else
  5280. dev_priv->num_pipe = 1;
  5281. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  5282. dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
  5283. for (i = 0; i < dev_priv->num_pipe; i++) {
  5284. intel_crtc_init(dev, i);
  5285. }
  5286. intel_setup_outputs(dev);
  5287. intel_init_clock_gating(dev);
  5288. /* Just disable it once at startup */
  5289. i915_disable_vga(dev);
  5290. if (IS_IRONLAKE_M(dev)) {
  5291. ironlake_enable_drps(dev);
  5292. intel_init_emon(dev);
  5293. }
  5294. INIT_WORK(&dev_priv->idle_work, intel_idle_update);
  5295. setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
  5296. (unsigned long)dev);
  5297. intel_setup_overlay(dev);
  5298. }
  5299. void intel_modeset_cleanup(struct drm_device *dev)
  5300. {
  5301. struct drm_i915_private *dev_priv = dev->dev_private;
  5302. struct drm_crtc *crtc;
  5303. struct intel_crtc *intel_crtc;
  5304. mutex_lock(&dev->struct_mutex);
  5305. drm_kms_helper_poll_fini(dev);
  5306. intel_fbdev_fini(dev);
  5307. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5308. /* Skip inactive CRTCs */
  5309. if (!crtc->fb)
  5310. continue;
  5311. intel_crtc = to_intel_crtc(crtc);
  5312. intel_increase_pllclock(crtc);
  5313. }
  5314. if (dev_priv->display.disable_fbc)
  5315. dev_priv->display.disable_fbc(dev);
  5316. if (dev_priv->renderctx) {
  5317. struct drm_i915_gem_object *obj_priv;
  5318. obj_priv = to_intel_bo(dev_priv->renderctx);
  5319. I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
  5320. I915_READ(CCID);
  5321. i915_gem_object_unpin(dev_priv->renderctx);
  5322. drm_gem_object_unreference(dev_priv->renderctx);
  5323. }
  5324. if (dev_priv->pwrctx) {
  5325. struct drm_i915_gem_object *obj_priv;
  5326. obj_priv = to_intel_bo(dev_priv->pwrctx);
  5327. I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
  5328. I915_READ(PWRCTXA);
  5329. i915_gem_object_unpin(dev_priv->pwrctx);
  5330. drm_gem_object_unreference(dev_priv->pwrctx);
  5331. }
  5332. if (IS_IRONLAKE_M(dev))
  5333. ironlake_disable_drps(dev);
  5334. mutex_unlock(&dev->struct_mutex);
  5335. /* Disable the irq before mode object teardown, for the irq might
  5336. * enqueue unpin/hotplug work. */
  5337. drm_irq_uninstall(dev);
  5338. cancel_work_sync(&dev_priv->hotplug_work);
  5339. /* Shut off idle work before the crtcs get freed. */
  5340. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5341. intel_crtc = to_intel_crtc(crtc);
  5342. del_timer_sync(&intel_crtc->idle_timer);
  5343. }
  5344. del_timer_sync(&dev_priv->idle_timer);
  5345. cancel_work_sync(&dev_priv->idle_work);
  5346. drm_mode_config_cleanup(dev);
  5347. }
  5348. /*
  5349. * Return which encoder is currently attached for connector.
  5350. */
  5351. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  5352. {
  5353. return &intel_attached_encoder(connector)->base;
  5354. }
  5355. void intel_connector_attach_encoder(struct intel_connector *connector,
  5356. struct intel_encoder *encoder)
  5357. {
  5358. connector->encoder = encoder;
  5359. drm_mode_connector_attach_encoder(&connector->base,
  5360. &encoder->base);
  5361. }
  5362. /*
  5363. * set vga decode state - true == enable VGA decode
  5364. */
  5365. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  5366. {
  5367. struct drm_i915_private *dev_priv = dev->dev_private;
  5368. u16 gmch_ctrl;
  5369. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  5370. if (state)
  5371. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  5372. else
  5373. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  5374. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  5375. return 0;
  5376. }