platsmp.c 4.0 KB

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  1. /*
  2. * This file contains Xilinx specific SMP code, used to start up
  3. * the second processor.
  4. *
  5. * Copyright (C) 2011-2013 Xilinx
  6. *
  7. * based on linux/arch/arm/mach-realview/platsmp.c
  8. *
  9. * Copyright (C) 2002 ARM Ltd.
  10. *
  11. * This software is licensed under the terms of the GNU General Public
  12. * License version 2, as published by the Free Software Foundation, and
  13. * may be copied, distributed, and modified under those terms.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. */
  20. #include <linux/export.h>
  21. #include <linux/jiffies.h>
  22. #include <linux/init.h>
  23. #include <linux/io.h>
  24. #include <asm/cacheflush.h>
  25. #include <asm/smp_scu.h>
  26. #include <linux/irqchip/arm-gic.h>
  27. #include "common.h"
  28. /*
  29. * Store number of cores in the system
  30. * Because of scu_get_core_count() must be in __init section and can't
  31. * be called from zynq_cpun_start() because it is in __cpuinit section.
  32. */
  33. static int ncores;
  34. /* Secondary CPU kernel startup is a 2 step process. The primary CPU
  35. * starts the secondary CPU by giving it the address of the kernel and
  36. * then sending it an event to wake it up. The secondary CPU then
  37. * starts the kernel and tells the primary CPU it's up and running.
  38. */
  39. static void __cpuinit zynq_secondary_init(unsigned int cpu)
  40. {
  41. /*
  42. * if any interrupts are already enabled for the primary
  43. * core (e.g. timer irq), then they will not have been enabled
  44. * for us: do so
  45. */
  46. gic_secondary_init(0);
  47. }
  48. int __cpuinit zynq_cpun_start(u32 address, int cpu)
  49. {
  50. u32 trampoline_code_size = &zynq_secondary_trampoline_end -
  51. &zynq_secondary_trampoline;
  52. if (cpu > ncores) {
  53. pr_warn("CPU No. is not available in the system\n");
  54. return -1;
  55. }
  56. /* MS: Expectation that SLCR are directly map and accessible */
  57. /* Not possible to jump to non aligned address */
  58. if (!(address & 3) && (!address || (address >= trampoline_code_size))) {
  59. /* Store pointer to ioremap area which points to address 0x0 */
  60. static u8 __iomem *zero;
  61. u32 trampoline_size = &zynq_secondary_trampoline_jump -
  62. &zynq_secondary_trampoline;
  63. zynq_slcr_cpu_stop(cpu);
  64. if (__pa(PAGE_OFFSET)) {
  65. zero = ioremap(0, trampoline_code_size);
  66. if (!zero) {
  67. pr_warn("BOOTUP jump vectors not accessible\n");
  68. return -1;
  69. }
  70. } else {
  71. zero = (__force u8 __iomem *)PAGE_OFFSET;
  72. }
  73. /*
  74. * This is elegant way how to jump to any address
  75. * 0x0: Load address at 0x8 to r0
  76. * 0x4: Jump by mov instruction
  77. * 0x8: Jumping address
  78. */
  79. memcpy((__force void *)zero, &zynq_secondary_trampoline,
  80. trampoline_size);
  81. writel(address, zero + trampoline_size);
  82. flush_cache_all();
  83. outer_flush_range(0, trampoline_code_size);
  84. smp_wmb();
  85. if (__pa(PAGE_OFFSET))
  86. iounmap(zero);
  87. zynq_slcr_cpu_start(cpu);
  88. return 0;
  89. }
  90. pr_warn("Can't start CPU%d: Wrong starting address %x\n", cpu, address);
  91. return -1;
  92. }
  93. EXPORT_SYMBOL(zynq_cpun_start);
  94. static int __cpuinit zynq_boot_secondary(unsigned int cpu,
  95. struct task_struct *idle)
  96. {
  97. return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
  98. }
  99. /*
  100. * Initialise the CPU possible map early - this describes the CPUs
  101. * which may be present or become present in the system.
  102. */
  103. static void __init zynq_smp_init_cpus(void)
  104. {
  105. int i;
  106. ncores = scu_get_core_count(zynq_scu_base);
  107. for (i = 0; i < ncores && i < CONFIG_NR_CPUS; i++)
  108. set_cpu_possible(i, true);
  109. }
  110. static void __init zynq_smp_prepare_cpus(unsigned int max_cpus)
  111. {
  112. int i;
  113. /*
  114. * Initialise the present map, which describes the set of CPUs
  115. * actually populated at the present time.
  116. */
  117. for (i = 0; i < max_cpus; i++)
  118. set_cpu_present(i, true);
  119. scu_enable(zynq_scu_base);
  120. }
  121. struct smp_operations zynq_smp_ops __initdata = {
  122. .smp_init_cpus = zynq_smp_init_cpus,
  123. .smp_prepare_cpus = zynq_smp_prepare_cpus,
  124. .smp_secondary_init = zynq_secondary_init,
  125. .smp_boot_secondary = zynq_boot_secondary,
  126. #ifdef CONFIG_HOTPLUG_CPU
  127. .cpu_die = zynq_platform_cpu_die,
  128. #endif
  129. };