core.h 23 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifndef CORE_H
  18. #define CORE_H
  19. #include <linux/etherdevice.h>
  20. #include <linux/rtnetlink.h>
  21. #include <linux/firmware.h>
  22. #include <linux/sched.h>
  23. #include <linux/circ_buf.h>
  24. #include <net/cfg80211.h>
  25. #include "htc.h"
  26. #include "wmi.h"
  27. #include "bmi.h"
  28. #include "target.h"
  29. #define MAX_ATH6KL 1
  30. #define ATH6KL_MAX_RX_BUFFERS 16
  31. #define ATH6KL_BUFFER_SIZE 1664
  32. #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4
  33. #define ATH6KL_AMSDU_REFILL_THRESHOLD 3
  34. #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
  35. #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508
  36. #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46
  37. #define USER_SAVEDKEYS_STAT_INIT 0
  38. #define USER_SAVEDKEYS_STAT_RUN 1
  39. #define ATH6KL_TX_TIMEOUT 10
  40. #define ATH6KL_MAX_ENDPOINTS 4
  41. #define MAX_NODE_NUM 15
  42. #define ATH6KL_APSD_ALL_FRAME 0xFFFF
  43. #define ATH6KL_APSD_NUM_OF_AC 0x4
  44. #define ATH6KL_APSD_FRAME_MASK 0xF
  45. /* Extra bytes for htc header alignment */
  46. #define ATH6KL_HTC_ALIGN_BYTES 3
  47. /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
  48. #define MAX_DEF_COOKIE_NUM 180
  49. #define MAX_HI_COOKIE_NUM 18 /* 10% of MAX_COOKIE_NUM */
  50. #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
  51. #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
  52. #define DISCON_TIMER_INTVAL 10000 /* in msec */
  53. /* Channel dwell time in fg scan */
  54. #define ATH6KL_FG_SCAN_INTERVAL 50 /* in ms */
  55. /* includes also the null byte */
  56. #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL"
  57. enum ath6kl_fw_ie_type {
  58. ATH6KL_FW_IE_FW_VERSION = 0,
  59. ATH6KL_FW_IE_TIMESTAMP = 1,
  60. ATH6KL_FW_IE_OTP_IMAGE = 2,
  61. ATH6KL_FW_IE_FW_IMAGE = 3,
  62. ATH6KL_FW_IE_PATCH_IMAGE = 4,
  63. ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
  64. ATH6KL_FW_IE_CAPABILITIES = 6,
  65. ATH6KL_FW_IE_PATCH_ADDR = 7,
  66. ATH6KL_FW_IE_BOARD_ADDR = 8,
  67. ATH6KL_FW_IE_VIF_MAX = 9,
  68. };
  69. enum ath6kl_fw_capability {
  70. ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
  71. ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
  72. /*
  73. * Firmware is capable of supporting P2P mgmt operations on a
  74. * station interface. After group formation, the station
  75. * interface will become a P2P client/GO interface as the case may be
  76. */
  77. ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
  78. /*
  79. * Firmware has support to cleanup inactive stations
  80. * in AP mode.
  81. */
  82. ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT,
  83. /* Firmware has support to override rsn cap of rsn ie */
  84. ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE,
  85. /*
  86. * Multicast support in WOW and host awake mode.
  87. * Allow all multicast in host awake mode.
  88. * Apply multicast filter in WOW mode.
  89. */
  90. ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
  91. /* Firmware supports enhanced bmiss detection */
  92. ATH6KL_FW_CAPABILITY_BMISS_ENHANCE,
  93. /*
  94. * FW supports matching of ssid in schedule scan
  95. */
  96. ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST,
  97. /* Firmware supports filtering BSS results by RSSI */
  98. ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD,
  99. /* FW sets mac_addr[4] ^= 0x80 for newly created interfaces */
  100. ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR,
  101. /* this needs to be last */
  102. ATH6KL_FW_CAPABILITY_MAX,
  103. };
  104. #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
  105. struct ath6kl_fw_ie {
  106. __le32 id;
  107. __le32 len;
  108. u8 data[0];
  109. };
  110. enum ath6kl_hw_flags {
  111. ATH6KL_HW_FLAG_64BIT_RATES = BIT(0),
  112. };
  113. #define ATH6KL_FW_API2_FILE "fw-2.bin"
  114. #define ATH6KL_FW_API3_FILE "fw-3.bin"
  115. /* AR6003 1.0 definitions */
  116. #define AR6003_HW_1_0_VERSION 0x300002ba
  117. /* AR6003 2.0 definitions */
  118. #define AR6003_HW_2_0_VERSION 0x30000384
  119. #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910
  120. #define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0"
  121. #define AR6003_HW_2_0_OTP_FILE "otp.bin.z77"
  122. #define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77"
  123. #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin"
  124. #define AR6003_HW_2_0_PATCH_FILE "data.patch.bin"
  125. #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin"
  126. #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
  127. AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin"
  128. /* AR6003 3.0 definitions */
  129. #define AR6003_HW_2_1_1_VERSION 0x30000582
  130. #define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1"
  131. #define AR6003_HW_2_1_1_OTP_FILE "otp.bin"
  132. #define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin"
  133. #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin"
  134. #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin"
  135. #define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin"
  136. #define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin"
  137. #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin"
  138. #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \
  139. AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin"
  140. /* AR6004 1.0 definitions */
  141. #define AR6004_HW_1_0_VERSION 0x30000623
  142. #define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0"
  143. #define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin"
  144. #define AR6004_HW_1_0_BOARD_DATA_FILE AR6004_HW_1_0_FW_DIR "/bdata.bin"
  145. #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
  146. AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin"
  147. /* AR6004 1.1 definitions */
  148. #define AR6004_HW_1_1_VERSION 0x30000001
  149. #define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1"
  150. #define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin"
  151. #define AR6004_HW_1_1_BOARD_DATA_FILE AR6004_HW_1_1_FW_DIR "/bdata.bin"
  152. #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
  153. AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin"
  154. /* AR6004 1.2 definitions */
  155. #define AR6004_HW_1_2_VERSION 0x300007e8
  156. #define AR6004_HW_1_2_FW_DIR "ath6k/AR6004/hw1.2"
  157. #define AR6004_HW_1_2_FIRMWARE_FILE "fw.ram.bin"
  158. #define AR6004_HW_1_2_BOARD_DATA_FILE AR6004_HW_1_2_FW_DIR "/bdata.bin"
  159. #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \
  160. AR6004_HW_1_2_FW_DIR "/bdata.bin"
  161. /* Per STA data, used in AP mode */
  162. #define STA_PS_AWAKE BIT(0)
  163. #define STA_PS_SLEEP BIT(1)
  164. #define STA_PS_POLLED BIT(2)
  165. #define STA_PS_APSD_TRIGGER BIT(3)
  166. #define STA_PS_APSD_EOSP BIT(4)
  167. /* HTC TX packet tagging definitions */
  168. #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED
  169. #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1)
  170. #define AR6003_CUST_DATA_SIZE 16
  171. #define AGGR_WIN_IDX(x, y) ((x) % (y))
  172. #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y))
  173. #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y))
  174. #define ATH6KL_MAX_SEQ_NO 0xFFF
  175. #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO)
  176. #define NUM_OF_TIDS 8
  177. #define AGGR_SZ_DEFAULT 8
  178. #define AGGR_WIN_SZ_MIN 2
  179. #define AGGR_WIN_SZ_MAX 8
  180. #define TID_WINDOW_SZ(_x) ((_x) << 1)
  181. #define AGGR_NUM_OF_FREE_NETBUFS 16
  182. #define AGGR_RX_TIMEOUT 100 /* in ms */
  183. #define WMI_TIMEOUT (2 * HZ)
  184. #define MBOX_YIELD_LIMIT 99
  185. #define ATH6KL_DEFAULT_LISTEN_INTVAL 100 /* in TUs */
  186. #define ATH6KL_DEFAULT_BMISS_TIME 1500
  187. #define ATH6KL_MAX_WOW_LISTEN_INTL 300 /* in TUs */
  188. #define ATH6KL_MAX_BMISS_TIME 5000
  189. /* configuration lags */
  190. /*
  191. * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in
  192. * ERP IE of beacon to determine the short premable support when
  193. * sending (Re)Assoc req.
  194. * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power
  195. * module state transition failure events which happen during
  196. * scan, to the host.
  197. */
  198. #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0)
  199. #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1)
  200. #define ATH6KL_CONF_ENABLE_11N BIT(2)
  201. #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3)
  202. #define ATH6KL_CONF_UART_DEBUG BIT(4)
  203. #define P2P_WILDCARD_SSID_LEN 7 /* DIRECT- */
  204. enum wlan_low_pwr_state {
  205. WLAN_POWER_STATE_ON,
  206. WLAN_POWER_STATE_CUT_PWR,
  207. WLAN_POWER_STATE_DEEP_SLEEP,
  208. WLAN_POWER_STATE_WOW
  209. };
  210. enum sme_state {
  211. SME_DISCONNECTED,
  212. SME_CONNECTING,
  213. SME_CONNECTED
  214. };
  215. struct skb_hold_q {
  216. struct sk_buff *skb;
  217. bool is_amsdu;
  218. u16 seq_no;
  219. };
  220. struct rxtid {
  221. bool aggr;
  222. bool timer_mon;
  223. u16 win_sz;
  224. u16 seq_next;
  225. u32 hold_q_sz;
  226. struct skb_hold_q *hold_q;
  227. struct sk_buff_head q;
  228. /*
  229. * lock mainly protects seq_next and hold_q. Movement of seq_next
  230. * needs to be protected between aggr_timeout() and
  231. * aggr_process_recv_frm(). hold_q will be holding the pending
  232. * reorder frames and it's access should also be protected.
  233. * Some of the other fields like hold_q_sz, win_sz and aggr are
  234. * initialized/reset when receiving addba/delba req, also while
  235. * deleting aggr state all the pending buffers are flushed before
  236. * resetting these fields, so there should not be any race in accessing
  237. * these fields.
  238. */
  239. spinlock_t lock;
  240. };
  241. struct rxtid_stats {
  242. u32 num_into_aggr;
  243. u32 num_dups;
  244. u32 num_oow;
  245. u32 num_mpdu;
  246. u32 num_amsdu;
  247. u32 num_delivered;
  248. u32 num_timeouts;
  249. u32 num_hole;
  250. u32 num_bar;
  251. };
  252. struct aggr_info_conn {
  253. u8 aggr_sz;
  254. u8 timer_scheduled;
  255. struct timer_list timer;
  256. struct net_device *dev;
  257. struct rxtid rx_tid[NUM_OF_TIDS];
  258. struct rxtid_stats stat[NUM_OF_TIDS];
  259. struct aggr_info *aggr_info;
  260. };
  261. struct aggr_info {
  262. struct aggr_info_conn *aggr_conn;
  263. struct sk_buff_head rx_amsdu_freeq;
  264. };
  265. struct ath6kl_wep_key {
  266. u8 key_index;
  267. u8 key_len;
  268. u8 key[64];
  269. };
  270. #define ATH6KL_KEY_SEQ_LEN 8
  271. struct ath6kl_key {
  272. u8 key[WLAN_MAX_KEY_LEN];
  273. u8 key_len;
  274. u8 seq[ATH6KL_KEY_SEQ_LEN];
  275. u8 seq_len;
  276. u32 cipher;
  277. };
  278. struct ath6kl_node_mapping {
  279. u8 mac_addr[ETH_ALEN];
  280. u8 ep_id;
  281. u8 tx_pend;
  282. };
  283. struct ath6kl_cookie {
  284. struct sk_buff *skb;
  285. u32 map_no;
  286. struct htc_packet htc_pkt;
  287. struct ath6kl_cookie *arc_list_next;
  288. };
  289. struct ath6kl_mgmt_buff {
  290. struct list_head list;
  291. u32 freq;
  292. u32 wait;
  293. u32 id;
  294. bool no_cck;
  295. size_t len;
  296. u8 buf[0];
  297. };
  298. struct ath6kl_sta {
  299. u16 sta_flags;
  300. u8 mac[ETH_ALEN];
  301. u8 aid;
  302. u8 keymgmt;
  303. u8 ucipher;
  304. u8 auth;
  305. u8 wpa_ie[ATH6KL_MAX_IE];
  306. struct sk_buff_head psq;
  307. /* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */
  308. spinlock_t psq_lock;
  309. struct list_head mgmt_psq;
  310. size_t mgmt_psq_len;
  311. u8 apsd_info;
  312. struct sk_buff_head apsdq;
  313. struct aggr_info_conn *aggr_conn;
  314. };
  315. struct ath6kl_version {
  316. u32 target_ver;
  317. u32 wlan_ver;
  318. u32 abi_ver;
  319. };
  320. struct ath6kl_bmi {
  321. u32 cmd_credits;
  322. bool done_sent;
  323. u8 *cmd_buf;
  324. u32 max_data_size;
  325. u32 max_cmd_size;
  326. };
  327. struct target_stats {
  328. u64 tx_pkt;
  329. u64 tx_byte;
  330. u64 tx_ucast_pkt;
  331. u64 tx_ucast_byte;
  332. u64 tx_mcast_pkt;
  333. u64 tx_mcast_byte;
  334. u64 tx_bcast_pkt;
  335. u64 tx_bcast_byte;
  336. u64 tx_rts_success_cnt;
  337. u64 tx_pkt_per_ac[4];
  338. u64 tx_err;
  339. u64 tx_fail_cnt;
  340. u64 tx_retry_cnt;
  341. u64 tx_mult_retry_cnt;
  342. u64 tx_rts_fail_cnt;
  343. u64 rx_pkt;
  344. u64 rx_byte;
  345. u64 rx_ucast_pkt;
  346. u64 rx_ucast_byte;
  347. u64 rx_mcast_pkt;
  348. u64 rx_mcast_byte;
  349. u64 rx_bcast_pkt;
  350. u64 rx_bcast_byte;
  351. u64 rx_frgment_pkt;
  352. u64 rx_err;
  353. u64 rx_crc_err;
  354. u64 rx_key_cache_miss;
  355. u64 rx_decrypt_err;
  356. u64 rx_dupl_frame;
  357. u64 tkip_local_mic_fail;
  358. u64 tkip_cnter_measures_invoked;
  359. u64 tkip_replays;
  360. u64 tkip_fmt_err;
  361. u64 ccmp_fmt_err;
  362. u64 ccmp_replays;
  363. u64 pwr_save_fail_cnt;
  364. u64 cs_bmiss_cnt;
  365. u64 cs_low_rssi_cnt;
  366. u64 cs_connect_cnt;
  367. u64 cs_discon_cnt;
  368. s32 tx_ucast_rate;
  369. s32 rx_ucast_rate;
  370. u32 lq_val;
  371. u32 wow_pkt_dropped;
  372. u16 wow_evt_discarded;
  373. s16 noise_floor_calib;
  374. s16 cs_rssi;
  375. s16 cs_ave_beacon_rssi;
  376. u8 cs_ave_beacon_snr;
  377. u8 cs_last_roam_msec;
  378. u8 cs_snr;
  379. u8 wow_host_pkt_wakeups;
  380. u8 wow_host_evt_wakeups;
  381. u32 arp_received;
  382. u32 arp_matched;
  383. u32 arp_replied;
  384. };
  385. struct ath6kl_mbox_info {
  386. u32 htc_addr;
  387. u32 htc_ext_addr;
  388. u32 htc_ext_sz;
  389. u32 block_size;
  390. u32 gmbox_addr;
  391. u32 gmbox_sz;
  392. };
  393. /*
  394. * 802.11i defines an extended IV for use with non-WEP ciphers.
  395. * When the EXTIV bit is set in the key id byte an additional
  396. * 4 bytes immediately follow the IV for TKIP. For CCMP the
  397. * EXTIV bit is likewise set but the 8 bytes represent the
  398. * CCMP header rather than IV+extended-IV.
  399. */
  400. #define ATH6KL_KEYBUF_SIZE 16
  401. #define ATH6KL_MICBUF_SIZE (8+8) /* space for both tx and rx */
  402. #define ATH6KL_KEY_XMIT 0x01
  403. #define ATH6KL_KEY_RECV 0x02
  404. #define ATH6KL_KEY_DEFAULT 0x80 /* default xmit key */
  405. /* Initial group key for AP mode */
  406. struct ath6kl_req_key {
  407. bool valid;
  408. u8 key_index;
  409. int key_type;
  410. u8 key[WLAN_MAX_KEY_LEN];
  411. u8 key_len;
  412. };
  413. enum ath6kl_hif_type {
  414. ATH6KL_HIF_TYPE_SDIO,
  415. ATH6KL_HIF_TYPE_USB,
  416. };
  417. enum ath6kl_htc_type {
  418. ATH6KL_HTC_TYPE_MBOX,
  419. ATH6KL_HTC_TYPE_PIPE,
  420. };
  421. /* Max number of filters that hw supports */
  422. #define ATH6K_MAX_MC_FILTERS_PER_LIST 7
  423. struct ath6kl_mc_filter {
  424. struct list_head list;
  425. char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
  426. };
  427. struct ath6kl_htcap {
  428. bool ht_enable;
  429. u8 ampdu_factor;
  430. unsigned short cap_info;
  431. };
  432. /*
  433. * Driver's maximum limit, note that some firmwares support only one vif
  434. * and the runtime (current) limit must be checked from ar->vif_max.
  435. */
  436. #define ATH6KL_VIF_MAX 3
  437. /* vif flags info */
  438. enum ath6kl_vif_state {
  439. CONNECTED,
  440. CONNECT_PEND,
  441. WMM_ENABLED,
  442. NETQ_STOPPED,
  443. DTIM_EXPIRED,
  444. NETDEV_REGISTERED,
  445. CLEAR_BSSFILTER_ON_BEACON,
  446. DTIM_PERIOD_AVAIL,
  447. WLAN_ENABLED,
  448. STATS_UPDATE_PEND,
  449. HOST_SLEEP_MODE_CMD_PROCESSED,
  450. NETDEV_MCAST_ALL_ON,
  451. NETDEV_MCAST_ALL_OFF,
  452. };
  453. struct ath6kl_vif {
  454. struct list_head list;
  455. struct wireless_dev wdev;
  456. struct net_device *ndev;
  457. struct ath6kl *ar;
  458. /* Lock to protect vif specific net_stats and flags */
  459. spinlock_t if_lock;
  460. u8 fw_vif_idx;
  461. unsigned long flags;
  462. int ssid_len;
  463. u8 ssid[IEEE80211_MAX_SSID_LEN];
  464. u8 dot11_auth_mode;
  465. u8 auth_mode;
  466. u8 prwise_crypto;
  467. u8 prwise_crypto_len;
  468. u8 grp_crypto;
  469. u8 grp_crypto_len;
  470. u8 def_txkey_index;
  471. u8 next_mode;
  472. u8 nw_type;
  473. u8 bssid[ETH_ALEN];
  474. u8 req_bssid[ETH_ALEN];
  475. u16 ch_hint;
  476. u16 bss_ch;
  477. struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
  478. struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
  479. struct aggr_info *aggr_cntxt;
  480. struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS];
  481. struct timer_list disconnect_timer;
  482. struct timer_list sched_scan_timer;
  483. struct cfg80211_scan_request *scan_req;
  484. enum sme_state sme_state;
  485. int reconnect_flag;
  486. u32 last_roc_id;
  487. u32 last_cancel_roc_id;
  488. u32 send_action_id;
  489. bool probe_req_report;
  490. u16 assoc_bss_beacon_int;
  491. u16 listen_intvl_t;
  492. u16 bmiss_time_t;
  493. u16 bg_scan_period;
  494. u8 assoc_bss_dtim_period;
  495. struct net_device_stats net_stats;
  496. struct target_stats target_stats;
  497. struct wmi_connect_cmd profile;
  498. struct list_head mc_filter;
  499. };
  500. static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev)
  501. {
  502. return container_of(wdev, struct ath6kl_vif, wdev);
  503. }
  504. #define WOW_LIST_ID 0
  505. #define WOW_HOST_REQ_DELAY 500 /* ms */
  506. #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */
  507. /* Flag info */
  508. enum ath6kl_dev_state {
  509. WMI_ENABLED,
  510. WMI_READY,
  511. WMI_CTRL_EP_FULL,
  512. TESTMODE,
  513. DESTROY_IN_PROGRESS,
  514. SKIP_SCAN,
  515. ROAM_TBL_PEND,
  516. FIRST_BOOT,
  517. };
  518. enum ath6kl_state {
  519. ATH6KL_STATE_OFF,
  520. ATH6KL_STATE_ON,
  521. ATH6KL_STATE_SUSPENDING,
  522. ATH6KL_STATE_RESUMING,
  523. ATH6KL_STATE_DEEPSLEEP,
  524. ATH6KL_STATE_CUTPOWER,
  525. ATH6KL_STATE_WOW,
  526. ATH6KL_STATE_SCHED_SCAN,
  527. };
  528. struct ath6kl {
  529. struct device *dev;
  530. struct wiphy *wiphy;
  531. enum ath6kl_state state;
  532. unsigned int testmode;
  533. struct ath6kl_bmi bmi;
  534. const struct ath6kl_hif_ops *hif_ops;
  535. const struct ath6kl_htc_ops *htc_ops;
  536. struct wmi *wmi;
  537. int tx_pending[ENDPOINT_MAX];
  538. int total_tx_data_pend;
  539. struct htc_target *htc_target;
  540. enum ath6kl_hif_type hif_type;
  541. void *hif_priv;
  542. struct list_head vif_list;
  543. /* Lock to avoid race in vif_list entries among add/del/traverse */
  544. spinlock_t list_lock;
  545. u8 num_vif;
  546. unsigned int vif_max;
  547. u8 max_norm_iface;
  548. u8 avail_idx_map;
  549. /*
  550. * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie()
  551. * calls, tx_pending and total_tx_data_pend.
  552. */
  553. spinlock_t lock;
  554. struct semaphore sem;
  555. u8 lrssi_roam_threshold;
  556. struct ath6kl_version version;
  557. u32 target_type;
  558. u8 tx_pwr;
  559. struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
  560. u8 ibss_ps_enable;
  561. bool ibss_if_active;
  562. u8 node_num;
  563. u8 next_ep_id;
  564. struct ath6kl_cookie *cookie_list;
  565. u32 cookie_count;
  566. enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
  567. bool ac_stream_active[WMM_NUM_AC];
  568. u8 ac_stream_pri_map[WMM_NUM_AC];
  569. u8 hiac_stream_active_pri;
  570. u8 ep2ac_map[ENDPOINT_MAX];
  571. enum htc_endpoint_id ctrl_ep;
  572. struct ath6kl_htc_credit_info credit_state_info;
  573. u32 connect_ctrl_flags;
  574. u32 user_key_ctrl;
  575. u8 usr_bss_filter;
  576. struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
  577. u8 sta_list_index;
  578. struct ath6kl_req_key ap_mode_bkey;
  579. struct sk_buff_head mcastpsq;
  580. u32 want_ch_switch;
  581. /*
  582. * FIXME: protects access to mcastpsq but is actually useless as
  583. * all skbe_queue_*() functions provide serialisation themselves
  584. */
  585. spinlock_t mcastpsq_lock;
  586. u8 intra_bss;
  587. struct wmi_ap_mode_stat ap_stats;
  588. u8 ap_country_code[3];
  589. struct list_head amsdu_rx_buffer_queue;
  590. u8 rx_meta_ver;
  591. enum wlan_low_pwr_state wlan_pwr_state;
  592. u8 mac_addr[ETH_ALEN];
  593. #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4
  594. struct {
  595. void *rx_report;
  596. size_t rx_report_len;
  597. } tm;
  598. struct ath6kl_hw {
  599. u32 id;
  600. const char *name;
  601. u32 dataset_patch_addr;
  602. u32 app_load_addr;
  603. u32 app_start_override_addr;
  604. u32 board_ext_data_addr;
  605. u32 reserved_ram_size;
  606. u32 board_addr;
  607. u32 refclk_hz;
  608. u32 uarttx_pin;
  609. u32 testscript_addr;
  610. enum wmi_phy_cap cap;
  611. u32 flags;
  612. struct ath6kl_hw_fw {
  613. const char *dir;
  614. const char *otp;
  615. const char *fw;
  616. const char *tcmd;
  617. const char *patch;
  618. const char *utf;
  619. const char *testscript;
  620. } fw;
  621. const char *fw_board;
  622. const char *fw_default_board;
  623. } hw;
  624. u16 conf_flags;
  625. u16 suspend_mode;
  626. u16 wow_suspend_mode;
  627. wait_queue_head_t event_wq;
  628. struct ath6kl_mbox_info mbox_info;
  629. struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
  630. unsigned long flag;
  631. u8 *fw_board;
  632. size_t fw_board_len;
  633. u8 *fw_otp;
  634. size_t fw_otp_len;
  635. u8 *fw;
  636. size_t fw_len;
  637. u8 *fw_patch;
  638. size_t fw_patch_len;
  639. u8 *fw_testscript;
  640. size_t fw_testscript_len;
  641. unsigned int fw_api;
  642. unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
  643. struct workqueue_struct *ath6kl_wq;
  644. struct dentry *debugfs_phy;
  645. bool p2p;
  646. bool wiphy_registered;
  647. #ifdef CONFIG_ATH6KL_DEBUG
  648. struct {
  649. struct sk_buff_head fwlog_queue;
  650. struct completion fwlog_completion;
  651. bool fwlog_open;
  652. u32 fwlog_mask;
  653. unsigned int dbgfs_diag_reg;
  654. u32 diag_reg_addr_wr;
  655. u32 diag_reg_val_wr;
  656. struct {
  657. unsigned int invalid_rate;
  658. } war_stats;
  659. u8 *roam_tbl;
  660. unsigned int roam_tbl_len;
  661. u8 keepalive;
  662. u8 disc_timeout;
  663. } debug;
  664. #endif /* CONFIG_ATH6KL_DEBUG */
  665. };
  666. static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
  667. {
  668. return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
  669. }
  670. static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
  671. u32 item_offset)
  672. {
  673. u32 addr = 0;
  674. if (ar->target_type == TARGET_TYPE_AR6003)
  675. addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
  676. else if (ar->target_type == TARGET_TYPE_AR6004)
  677. addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
  678. return addr;
  679. }
  680. int ath6kl_configure_target(struct ath6kl *ar);
  681. void ath6kl_detect_error(unsigned long ptr);
  682. void disconnect_timer_handler(unsigned long ptr);
  683. void init_netdev(struct net_device *dev);
  684. void ath6kl_cookie_init(struct ath6kl *ar);
  685. void ath6kl_cookie_cleanup(struct ath6kl *ar);
  686. void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
  687. void ath6kl_tx_complete(struct htc_target *context,
  688. struct list_head *packet_queue);
  689. enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
  690. struct htc_packet *packet);
  691. void ath6kl_stop_txrx(struct ath6kl *ar);
  692. void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
  693. int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
  694. int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
  695. int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
  696. int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
  697. int ath6kl_read_fwlogs(struct ath6kl *ar);
  698. void ath6kl_init_profile_info(struct ath6kl_vif *vif);
  699. void ath6kl_tx_data_cleanup(struct ath6kl *ar);
  700. struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
  701. void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
  702. int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
  703. struct aggr_info *aggr_init(struct ath6kl_vif *vif);
  704. void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
  705. struct aggr_info_conn *aggr_conn);
  706. void ath6kl_rx_refill(struct htc_target *target,
  707. enum htc_endpoint_id endpoint);
  708. void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
  709. struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
  710. enum htc_endpoint_id endpoint,
  711. int len);
  712. void aggr_module_destroy(struct aggr_info *aggr_info);
  713. void aggr_reset_state(struct aggr_info_conn *aggr_conn);
  714. struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr);
  715. struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
  716. void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver,
  717. enum wmi_phy_cap cap);
  718. int ath6kl_control_tx(void *devt, struct sk_buff *skb,
  719. enum htc_endpoint_id eid);
  720. void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
  721. u8 *bssid, u16 listen_int,
  722. u16 beacon_int, enum network_type net_type,
  723. u8 beacon_ie_len, u8 assoc_req_len,
  724. u8 assoc_resp_len, u8 *assoc_info);
  725. void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
  726. void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
  727. u8 keymgmt, u8 ucipher, u8 auth,
  728. u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
  729. void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
  730. u8 *bssid, u8 assoc_resp_len,
  731. u8 *assoc_info, u16 prot_reason_status);
  732. void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
  733. void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
  734. void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
  735. void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
  736. void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
  737. enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
  738. void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
  739. void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
  740. void ath6kl_disconnect(struct ath6kl_vif *vif);
  741. void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
  742. void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
  743. u8 win_sz);
  744. void ath6kl_wakeup_event(void *dev);
  745. void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
  746. bool wait_fot_compltn, bool cold_reset);
  747. void ath6kl_init_control_info(struct ath6kl_vif *vif);
  748. struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
  749. void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
  750. int ath6kl_init_hw_start(struct ath6kl *ar);
  751. int ath6kl_init_hw_stop(struct ath6kl *ar);
  752. int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
  753. int ath6kl_init_hw_params(struct ath6kl *ar);
  754. void ath6kl_check_wow_status(struct ath6kl *ar);
  755. void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb);
  756. void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe);
  757. struct ath6kl *ath6kl_core_create(struct device *dev);
  758. int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type);
  759. void ath6kl_core_cleanup(struct ath6kl *ar);
  760. void ath6kl_core_destroy(struct ath6kl *ar);
  761. #endif /* CORE_H */