netxen_nic_init.c 39 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. struct crb_addr_pair {
  35. u32 addr;
  36. u32 data;
  37. };
  38. #define NETXEN_MAX_CRB_XFORM 60
  39. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  40. #define NETXEN_ADDR_ERROR (0xffffffff)
  41. #define crb_addr_transform(name) \
  42. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  43. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  44. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  45. static void
  46. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  47. struct nx_host_rds_ring *rds_ring);
  48. static void crb_addr_transform_setup(void)
  49. {
  50. crb_addr_transform(XDMA);
  51. crb_addr_transform(TIMR);
  52. crb_addr_transform(SRE);
  53. crb_addr_transform(SQN3);
  54. crb_addr_transform(SQN2);
  55. crb_addr_transform(SQN1);
  56. crb_addr_transform(SQN0);
  57. crb_addr_transform(SQS3);
  58. crb_addr_transform(SQS2);
  59. crb_addr_transform(SQS1);
  60. crb_addr_transform(SQS0);
  61. crb_addr_transform(RPMX7);
  62. crb_addr_transform(RPMX6);
  63. crb_addr_transform(RPMX5);
  64. crb_addr_transform(RPMX4);
  65. crb_addr_transform(RPMX3);
  66. crb_addr_transform(RPMX2);
  67. crb_addr_transform(RPMX1);
  68. crb_addr_transform(RPMX0);
  69. crb_addr_transform(ROMUSB);
  70. crb_addr_transform(SN);
  71. crb_addr_transform(QMN);
  72. crb_addr_transform(QMS);
  73. crb_addr_transform(PGNI);
  74. crb_addr_transform(PGND);
  75. crb_addr_transform(PGN3);
  76. crb_addr_transform(PGN2);
  77. crb_addr_transform(PGN1);
  78. crb_addr_transform(PGN0);
  79. crb_addr_transform(PGSI);
  80. crb_addr_transform(PGSD);
  81. crb_addr_transform(PGS3);
  82. crb_addr_transform(PGS2);
  83. crb_addr_transform(PGS1);
  84. crb_addr_transform(PGS0);
  85. crb_addr_transform(PS);
  86. crb_addr_transform(PH);
  87. crb_addr_transform(NIU);
  88. crb_addr_transform(I2Q);
  89. crb_addr_transform(EG);
  90. crb_addr_transform(MN);
  91. crb_addr_transform(MS);
  92. crb_addr_transform(CAS2);
  93. crb_addr_transform(CAS1);
  94. crb_addr_transform(CAS0);
  95. crb_addr_transform(CAM);
  96. crb_addr_transform(C2C1);
  97. crb_addr_transform(C2C0);
  98. crb_addr_transform(SMB);
  99. crb_addr_transform(OCM0);
  100. crb_addr_transform(I2C0);
  101. }
  102. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  103. {
  104. struct netxen_recv_context *recv_ctx;
  105. struct nx_host_rds_ring *rds_ring;
  106. struct netxen_rx_buffer *rx_buf;
  107. int i, ring;
  108. recv_ctx = &adapter->recv_ctx;
  109. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  110. rds_ring = &recv_ctx->rds_rings[ring];
  111. for (i = 0; i < rds_ring->num_desc; ++i) {
  112. rx_buf = &(rds_ring->rx_buf_arr[i]);
  113. if (rx_buf->state == NETXEN_BUFFER_FREE)
  114. continue;
  115. pci_unmap_single(adapter->pdev,
  116. rx_buf->dma,
  117. rds_ring->dma_size,
  118. PCI_DMA_FROMDEVICE);
  119. if (rx_buf->skb != NULL)
  120. dev_kfree_skb_any(rx_buf->skb);
  121. }
  122. }
  123. }
  124. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  125. {
  126. struct netxen_cmd_buffer *cmd_buf;
  127. struct netxen_skb_frag *buffrag;
  128. int i, j;
  129. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  130. cmd_buf = tx_ring->cmd_buf_arr;
  131. for (i = 0; i < tx_ring->num_desc; i++) {
  132. buffrag = cmd_buf->frag_array;
  133. if (buffrag->dma) {
  134. pci_unmap_single(adapter->pdev, buffrag->dma,
  135. buffrag->length, PCI_DMA_TODEVICE);
  136. buffrag->dma = 0ULL;
  137. }
  138. for (j = 0; j < cmd_buf->frag_count; j++) {
  139. buffrag++;
  140. if (buffrag->dma) {
  141. pci_unmap_page(adapter->pdev, buffrag->dma,
  142. buffrag->length,
  143. PCI_DMA_TODEVICE);
  144. buffrag->dma = 0ULL;
  145. }
  146. }
  147. if (cmd_buf->skb) {
  148. dev_kfree_skb_any(cmd_buf->skb);
  149. cmd_buf->skb = NULL;
  150. }
  151. cmd_buf++;
  152. }
  153. }
  154. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  155. {
  156. struct netxen_recv_context *recv_ctx;
  157. struct nx_host_rds_ring *rds_ring;
  158. struct nx_host_tx_ring *tx_ring;
  159. int ring;
  160. recv_ctx = &adapter->recv_ctx;
  161. if (recv_ctx->rds_rings == NULL)
  162. goto skip_rds;
  163. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  164. rds_ring = &recv_ctx->rds_rings[ring];
  165. vfree(rds_ring->rx_buf_arr);
  166. rds_ring->rx_buf_arr = NULL;
  167. }
  168. kfree(recv_ctx->rds_rings);
  169. skip_rds:
  170. if (adapter->tx_ring == NULL)
  171. return;
  172. tx_ring = adapter->tx_ring;
  173. vfree(tx_ring->cmd_buf_arr);
  174. }
  175. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  176. {
  177. struct netxen_recv_context *recv_ctx;
  178. struct nx_host_rds_ring *rds_ring;
  179. struct nx_host_sds_ring *sds_ring;
  180. struct nx_host_tx_ring *tx_ring;
  181. struct netxen_rx_buffer *rx_buf;
  182. int ring, i, size;
  183. struct netxen_cmd_buffer *cmd_buf_arr;
  184. struct net_device *netdev = adapter->netdev;
  185. struct pci_dev *pdev = adapter->pdev;
  186. size = sizeof(struct nx_host_tx_ring);
  187. tx_ring = kzalloc(size, GFP_KERNEL);
  188. if (tx_ring == NULL) {
  189. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  190. netdev->name);
  191. return -ENOMEM;
  192. }
  193. adapter->tx_ring = tx_ring;
  194. tx_ring->num_desc = adapter->num_txd;
  195. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  196. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  197. if (cmd_buf_arr == NULL) {
  198. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  199. netdev->name);
  200. return -ENOMEM;
  201. }
  202. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  203. tx_ring->cmd_buf_arr = cmd_buf_arr;
  204. recv_ctx = &adapter->recv_ctx;
  205. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  206. rds_ring = kzalloc(size, GFP_KERNEL);
  207. if (rds_ring == NULL) {
  208. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  209. netdev->name);
  210. return -ENOMEM;
  211. }
  212. recv_ctx->rds_rings = rds_ring;
  213. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  214. rds_ring = &recv_ctx->rds_rings[ring];
  215. switch (ring) {
  216. case RCV_RING_NORMAL:
  217. rds_ring->num_desc = adapter->num_rxd;
  218. if (adapter->ahw.cut_through) {
  219. rds_ring->dma_size =
  220. NX_CT_DEFAULT_RX_BUF_LEN;
  221. rds_ring->skb_size =
  222. NX_CT_DEFAULT_RX_BUF_LEN;
  223. } else {
  224. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  225. rds_ring->dma_size =
  226. NX_P3_RX_BUF_MAX_LEN;
  227. else
  228. rds_ring->dma_size =
  229. NX_P2_RX_BUF_MAX_LEN;
  230. rds_ring->skb_size =
  231. rds_ring->dma_size + NET_IP_ALIGN;
  232. }
  233. break;
  234. case RCV_RING_JUMBO:
  235. rds_ring->num_desc = adapter->num_jumbo_rxd;
  236. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  237. rds_ring->dma_size =
  238. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  239. else
  240. rds_ring->dma_size =
  241. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  242. rds_ring->skb_size =
  243. rds_ring->dma_size + NET_IP_ALIGN;
  244. break;
  245. case RCV_RING_LRO:
  246. rds_ring->num_desc = adapter->num_lro_rxd;
  247. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  248. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  249. break;
  250. }
  251. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  252. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  253. if (rds_ring->rx_buf_arr == NULL) {
  254. printk(KERN_ERR "%s: Failed to allocate "
  255. "rx buffer ring %d\n",
  256. netdev->name, ring);
  257. /* free whatever was already allocated */
  258. goto err_out;
  259. }
  260. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  261. INIT_LIST_HEAD(&rds_ring->free_list);
  262. /*
  263. * Now go through all of them, set reference handles
  264. * and put them in the queues.
  265. */
  266. rx_buf = rds_ring->rx_buf_arr;
  267. for (i = 0; i < rds_ring->num_desc; i++) {
  268. list_add_tail(&rx_buf->list,
  269. &rds_ring->free_list);
  270. rx_buf->ref_handle = i;
  271. rx_buf->state = NETXEN_BUFFER_FREE;
  272. rx_buf++;
  273. }
  274. spin_lock_init(&rds_ring->lock);
  275. }
  276. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  277. sds_ring = &recv_ctx->sds_rings[ring];
  278. sds_ring->irq = adapter->msix_entries[ring].vector;
  279. sds_ring->adapter = adapter;
  280. sds_ring->num_desc = adapter->num_rxd;
  281. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  282. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  283. }
  284. return 0;
  285. err_out:
  286. netxen_free_sw_resources(adapter);
  287. return -ENOMEM;
  288. }
  289. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  290. {
  291. adapter->init_port = netxen_niu_xg_init_port;
  292. adapter->stop_port = netxen_niu_disable_xg_port;
  293. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  294. adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
  295. adapter->set_multi = netxen_p2_nic_set_multi;
  296. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  297. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  298. } else {
  299. adapter->set_mtu = nx_fw_cmd_set_mtu;
  300. adapter->set_promisc = netxen_p3_nic_set_promisc;
  301. adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
  302. adapter->set_multi = netxen_p3_nic_set_multi;
  303. }
  304. if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
  305. adapter->phy_read = netxen_niu_gbe_phy_read;
  306. adapter->phy_write = netxen_niu_gbe_phy_write;
  307. }
  308. }
  309. /*
  310. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  311. * address to external PCI CRB address.
  312. */
  313. static u32 netxen_decode_crb_addr(u32 addr)
  314. {
  315. int i;
  316. u32 base_addr, offset, pci_base;
  317. crb_addr_transform_setup();
  318. pci_base = NETXEN_ADDR_ERROR;
  319. base_addr = addr & 0xfff00000;
  320. offset = addr & 0x000fffff;
  321. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  322. if (crb_addr_xform[i] == base_addr) {
  323. pci_base = i << 20;
  324. break;
  325. }
  326. }
  327. if (pci_base == NETXEN_ADDR_ERROR)
  328. return pci_base;
  329. else
  330. return (pci_base + offset);
  331. }
  332. #define NETXEN_MAX_ROM_WAIT_USEC 100
  333. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  334. {
  335. long timeout = 0;
  336. long done = 0;
  337. cond_resched();
  338. while (done == 0) {
  339. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  340. done &= 2;
  341. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  342. dev_err(&adapter->pdev->dev,
  343. "Timeout reached waiting for rom done");
  344. return -EIO;
  345. }
  346. udelay(1);
  347. }
  348. return 0;
  349. }
  350. static int do_rom_fast_read(struct netxen_adapter *adapter,
  351. int addr, int *valp)
  352. {
  353. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  354. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  355. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  356. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  357. if (netxen_wait_rom_done(adapter)) {
  358. printk("Error waiting for rom done\n");
  359. return -EIO;
  360. }
  361. /* reset abyte_cnt and dummy_byte_cnt */
  362. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  363. udelay(10);
  364. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  365. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  366. return 0;
  367. }
  368. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  369. u8 *bytes, size_t size)
  370. {
  371. int addridx;
  372. int ret = 0;
  373. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  374. int v;
  375. ret = do_rom_fast_read(adapter, addridx, &v);
  376. if (ret != 0)
  377. break;
  378. *(__le32 *)bytes = cpu_to_le32(v);
  379. bytes += 4;
  380. }
  381. return ret;
  382. }
  383. int
  384. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  385. u8 *bytes, size_t size)
  386. {
  387. int ret;
  388. ret = netxen_rom_lock(adapter);
  389. if (ret < 0)
  390. return ret;
  391. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  392. netxen_rom_unlock(adapter);
  393. return ret;
  394. }
  395. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  396. {
  397. int ret;
  398. if (netxen_rom_lock(adapter) != 0)
  399. return -EIO;
  400. ret = do_rom_fast_read(adapter, addr, valp);
  401. netxen_rom_unlock(adapter);
  402. return ret;
  403. }
  404. #define NETXEN_BOARDTYPE 0x4008
  405. #define NETXEN_BOARDNUM 0x400c
  406. #define NETXEN_CHIPNUM 0x4010
  407. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  408. {
  409. int addr, val;
  410. int i, n, init_delay = 0;
  411. struct crb_addr_pair *buf;
  412. unsigned offset;
  413. u32 off;
  414. /* resetall */
  415. netxen_rom_lock(adapter);
  416. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  417. netxen_rom_unlock(adapter);
  418. if (verbose) {
  419. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  420. printk("P2 ROM board type: 0x%08x\n", val);
  421. else
  422. printk("Could not read board type\n");
  423. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  424. printk("P2 ROM board num: 0x%08x\n", val);
  425. else
  426. printk("Could not read board number\n");
  427. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  428. printk("P2 ROM chip num: 0x%08x\n", val);
  429. else
  430. printk("Could not read chip number\n");
  431. }
  432. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  433. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  434. (n != 0xcafecafe) ||
  435. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  436. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  437. "n: %08x\n", netxen_nic_driver_name, n);
  438. return -EIO;
  439. }
  440. offset = n & 0xffffU;
  441. n = (n >> 16) & 0xffffU;
  442. } else {
  443. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  444. !(n & 0x80000000)) {
  445. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  446. "n: %08x\n", netxen_nic_driver_name, n);
  447. return -EIO;
  448. }
  449. offset = 1;
  450. n &= ~0x80000000;
  451. }
  452. if (n < 1024) {
  453. if (verbose)
  454. printk(KERN_DEBUG "%s: %d CRB init values found"
  455. " in ROM.\n", netxen_nic_driver_name, n);
  456. } else {
  457. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  458. " initialized.\n", __func__, n);
  459. return -EIO;
  460. }
  461. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  462. if (buf == NULL) {
  463. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  464. netxen_nic_driver_name);
  465. return -ENOMEM;
  466. }
  467. for (i = 0; i < n; i++) {
  468. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  469. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  470. kfree(buf);
  471. return -EIO;
  472. }
  473. buf[i].addr = addr;
  474. buf[i].data = val;
  475. if (verbose)
  476. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  477. netxen_nic_driver_name,
  478. (u32)netxen_decode_crb_addr(addr), val);
  479. }
  480. for (i = 0; i < n; i++) {
  481. off = netxen_decode_crb_addr(buf[i].addr);
  482. if (off == NETXEN_ADDR_ERROR) {
  483. printk(KERN_ERR"CRB init value out of range %x\n",
  484. buf[i].addr);
  485. continue;
  486. }
  487. off += NETXEN_PCI_CRBSPACE;
  488. /* skipping cold reboot MAGIC */
  489. if (off == NETXEN_CAM_RAM(0x1fc))
  490. continue;
  491. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  492. /* do not reset PCI */
  493. if (off == (ROMUSB_GLB + 0xbc))
  494. continue;
  495. if (off == (ROMUSB_GLB + 0xa8))
  496. continue;
  497. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  498. continue;
  499. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  500. continue;
  501. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  502. continue;
  503. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  504. buf[i].data = 0x1020;
  505. /* skip the function enable register */
  506. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  507. continue;
  508. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  509. continue;
  510. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  511. continue;
  512. }
  513. if (off == NETXEN_ADDR_ERROR) {
  514. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  515. netxen_nic_driver_name, buf[i].addr);
  516. continue;
  517. }
  518. init_delay = 1;
  519. /* After writing this register, HW needs time for CRB */
  520. /* to quiet down (else crb_window returns 0xffffffff) */
  521. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  522. init_delay = 1000;
  523. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  524. /* hold xdma in reset also */
  525. buf[i].data = NETXEN_NIC_XDMA_RESET;
  526. buf[i].data = 0x8000ff;
  527. }
  528. }
  529. NXWR32(adapter, off, buf[i].data);
  530. msleep(init_delay);
  531. }
  532. kfree(buf);
  533. /* disable_peg_cache_all */
  534. /* unreset_net_cache */
  535. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  536. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  537. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  538. }
  539. /* p2dn replyCount */
  540. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  541. /* disable_peg_cache 0 */
  542. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  543. /* disable_peg_cache 1 */
  544. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  545. /* peg_clr_all */
  546. /* peg_clr 0 */
  547. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  548. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  549. /* peg_clr 1 */
  550. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  551. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  552. /* peg_clr 2 */
  553. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  554. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  555. /* peg_clr 3 */
  556. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  557. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  558. return 0;
  559. }
  560. int
  561. netxen_need_fw_reset(struct netxen_adapter *adapter)
  562. {
  563. u32 count, old_count;
  564. u32 val, version, major, minor, build;
  565. int i, timeout;
  566. u8 fw_type;
  567. /* NX2031 firmware doesn't support heartbit */
  568. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  569. return 1;
  570. /* last attempt had failed */
  571. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  572. return 1;
  573. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  574. for (i = 0; i < 10; i++) {
  575. timeout = msleep_interruptible(200);
  576. if (timeout) {
  577. NXWR32(adapter, CRB_CMDPEG_STATE,
  578. PHAN_INITIALIZE_FAILED);
  579. return -EINTR;
  580. }
  581. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  582. if (count != old_count)
  583. break;
  584. }
  585. /* firmware is dead */
  586. if (count == old_count)
  587. return 1;
  588. /* check if we have got newer or different file firmware */
  589. if (adapter->fw) {
  590. const struct firmware *fw = adapter->fw;
  591. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  592. version = NETXEN_DECODE_VERSION(val);
  593. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  594. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  595. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  596. if (version > NETXEN_VERSION_CODE(major, minor, build))
  597. return 1;
  598. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  599. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  600. fw_type = (val & 0x4) ?
  601. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  602. if (adapter->fw_type != fw_type)
  603. return 1;
  604. }
  605. }
  606. return 0;
  607. }
  608. static char *fw_name[] = {
  609. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  610. };
  611. int
  612. netxen_load_firmware(struct netxen_adapter *adapter)
  613. {
  614. u64 *ptr64;
  615. u32 i, flashaddr, size;
  616. const struct firmware *fw = adapter->fw;
  617. struct pci_dev *pdev = adapter->pdev;
  618. dev_info(&pdev->dev, "loading firmware from %s\n",
  619. fw_name[adapter->fw_type]);
  620. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  621. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  622. if (fw) {
  623. __le64 data;
  624. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  625. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  626. flashaddr = NETXEN_BOOTLD_START;
  627. for (i = 0; i < size; i++) {
  628. data = cpu_to_le64(ptr64[i]);
  629. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  630. flashaddr += 8;
  631. }
  632. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  633. size = (__force u32)cpu_to_le32(size) / 8;
  634. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  635. flashaddr = NETXEN_IMAGE_START;
  636. for (i = 0; i < size; i++) {
  637. data = cpu_to_le64(ptr64[i]);
  638. if (adapter->pci_mem_write(adapter,
  639. flashaddr, &data, 8))
  640. return -EIO;
  641. flashaddr += 8;
  642. }
  643. } else {
  644. u32 data;
  645. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
  646. flashaddr = NETXEN_BOOTLD_START;
  647. for (i = 0; i < size; i++) {
  648. if (netxen_rom_fast_read(adapter,
  649. flashaddr, (int *)&data) != 0)
  650. return -EIO;
  651. if (adapter->pci_mem_write(adapter,
  652. flashaddr, &data, 4))
  653. return -EIO;
  654. flashaddr += 4;
  655. }
  656. }
  657. msleep(1);
  658. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  659. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  660. else {
  661. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  662. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  663. }
  664. return 0;
  665. }
  666. static int
  667. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  668. {
  669. __le32 val;
  670. u32 ver, min_ver, bios;
  671. struct pci_dev *pdev = adapter->pdev;
  672. const struct firmware *fw = adapter->fw;
  673. if (fw->size < NX_FW_MIN_SIZE)
  674. return -EINVAL;
  675. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  676. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  677. return -EINVAL;
  678. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  679. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  680. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  681. else
  682. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  683. ver = NETXEN_DECODE_VERSION(val);
  684. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  685. dev_err(&pdev->dev,
  686. "%s: firmware version %d.%d.%d unsupported\n",
  687. fwname, _major(ver), _minor(ver), _build(ver));
  688. return -EINVAL;
  689. }
  690. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  691. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  692. if ((__force u32)val != bios) {
  693. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  694. fwname);
  695. return -EINVAL;
  696. }
  697. /* check if flashed firmware is newer */
  698. if (netxen_rom_fast_read(adapter,
  699. NX_FW_VERSION_OFFSET, (int *)&val))
  700. return -EIO;
  701. val = NETXEN_DECODE_VERSION(val);
  702. if (val > ver) {
  703. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  704. fwname);
  705. return -EINVAL;
  706. }
  707. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  708. return 0;
  709. }
  710. static int
  711. netxen_p3_has_mn(struct netxen_adapter *adapter)
  712. {
  713. u32 capability, flashed_ver;
  714. capability = 0;
  715. netxen_rom_fast_read(adapter,
  716. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  717. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  718. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  719. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  720. if (capability & NX_PEG_TUNE_MN_PRESENT)
  721. return 1;
  722. }
  723. return 0;
  724. }
  725. void netxen_request_firmware(struct netxen_adapter *adapter)
  726. {
  727. u8 fw_type;
  728. struct pci_dev *pdev = adapter->pdev;
  729. int rc = 0;
  730. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  731. fw_type = NX_P2_MN_ROMIMAGE;
  732. goto request_fw;
  733. }
  734. fw_type = netxen_p3_has_mn(adapter) ?
  735. NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
  736. request_fw:
  737. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  738. if (rc != 0) {
  739. if (fw_type == NX_P3_MN_ROMIMAGE) {
  740. msleep(1);
  741. fw_type = NX_P3_CT_ROMIMAGE;
  742. goto request_fw;
  743. }
  744. fw_type = NX_FLASH_ROMIMAGE;
  745. adapter->fw = NULL;
  746. goto done;
  747. }
  748. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  749. if (rc != 0) {
  750. release_firmware(adapter->fw);
  751. if (fw_type == NX_P3_MN_ROMIMAGE) {
  752. msleep(1);
  753. fw_type = NX_P3_CT_ROMIMAGE;
  754. goto request_fw;
  755. }
  756. fw_type = NX_FLASH_ROMIMAGE;
  757. adapter->fw = NULL;
  758. goto done;
  759. }
  760. done:
  761. adapter->fw_type = fw_type;
  762. }
  763. void
  764. netxen_release_firmware(struct netxen_adapter *adapter)
  765. {
  766. if (adapter->fw)
  767. release_firmware(adapter->fw);
  768. }
  769. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  770. {
  771. u64 addr;
  772. u32 hi, lo;
  773. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  774. return 0;
  775. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  776. NETXEN_HOST_DUMMY_DMA_SIZE,
  777. &adapter->dummy_dma.phys_addr);
  778. if (adapter->dummy_dma.addr == NULL) {
  779. dev_err(&adapter->pdev->dev,
  780. "ERROR: Could not allocate dummy DMA memory\n");
  781. return -ENOMEM;
  782. }
  783. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  784. hi = (addr >> 32) & 0xffffffff;
  785. lo = addr & 0xffffffff;
  786. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  787. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  788. return 0;
  789. }
  790. /*
  791. * NetXen DMA watchdog control:
  792. *
  793. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  794. * Bit 1 : disable_request => 1 req disable dma watchdog
  795. * Bit 2 : enable_request => 1 req enable dma watchdog
  796. * Bit 3-31 : unused
  797. */
  798. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  799. {
  800. int i = 100;
  801. u32 ctrl;
  802. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  803. return;
  804. if (!adapter->dummy_dma.addr)
  805. return;
  806. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  807. if ((ctrl & 0x1) != 0) {
  808. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  809. while ((ctrl & 0x1) != 0) {
  810. msleep(50);
  811. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  812. if (--i == 0)
  813. break;
  814. };
  815. }
  816. if (i) {
  817. pci_free_consistent(adapter->pdev,
  818. NETXEN_HOST_DUMMY_DMA_SIZE,
  819. adapter->dummy_dma.addr,
  820. adapter->dummy_dma.phys_addr);
  821. adapter->dummy_dma.addr = NULL;
  822. } else
  823. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  824. }
  825. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  826. {
  827. u32 val = 0;
  828. int retries = 60;
  829. if (pegtune_val)
  830. return 0;
  831. do {
  832. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  833. switch (val) {
  834. case PHAN_INITIALIZE_COMPLETE:
  835. case PHAN_INITIALIZE_ACK:
  836. return 0;
  837. case PHAN_INITIALIZE_FAILED:
  838. goto out_err;
  839. default:
  840. break;
  841. }
  842. msleep(500);
  843. } while (--retries);
  844. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  845. out_err:
  846. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  847. return -EIO;
  848. }
  849. static int
  850. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  851. {
  852. u32 val = 0;
  853. int retries = 2000;
  854. do {
  855. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  856. if (val == PHAN_PEG_RCV_INITIALIZED)
  857. return 0;
  858. msleep(10);
  859. } while (--retries);
  860. if (!retries) {
  861. printk(KERN_ERR "Receive Peg initialization not "
  862. "complete, state: 0x%x.\n", val);
  863. return -EIO;
  864. }
  865. return 0;
  866. }
  867. int netxen_init_firmware(struct netxen_adapter *adapter)
  868. {
  869. int err;
  870. err = netxen_receive_peg_ready(adapter);
  871. if (err)
  872. return err;
  873. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  874. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  875. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  876. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  877. return err;
  878. }
  879. static void
  880. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  881. {
  882. u32 cable_OUI;
  883. u16 cable_len;
  884. u16 link_speed;
  885. u8 link_status, module, duplex, autoneg;
  886. struct net_device *netdev = adapter->netdev;
  887. adapter->has_link_events = 1;
  888. cable_OUI = msg->body[1] & 0xffffffff;
  889. cable_len = (msg->body[1] >> 32) & 0xffff;
  890. link_speed = (msg->body[1] >> 48) & 0xffff;
  891. link_status = msg->body[2] & 0xff;
  892. duplex = (msg->body[2] >> 16) & 0xff;
  893. autoneg = (msg->body[2] >> 24) & 0xff;
  894. module = (msg->body[2] >> 8) & 0xff;
  895. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  896. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  897. netdev->name, cable_OUI, cable_len);
  898. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  899. printk(KERN_INFO "%s: unsupported cable length %d\n",
  900. netdev->name, cable_len);
  901. }
  902. netxen_advert_link_change(adapter, link_status);
  903. /* update link parameters */
  904. if (duplex == LINKEVENT_FULL_DUPLEX)
  905. adapter->link_duplex = DUPLEX_FULL;
  906. else
  907. adapter->link_duplex = DUPLEX_HALF;
  908. adapter->module_type = module;
  909. adapter->link_autoneg = autoneg;
  910. adapter->link_speed = link_speed;
  911. }
  912. static void
  913. netxen_handle_fw_message(int desc_cnt, int index,
  914. struct nx_host_sds_ring *sds_ring)
  915. {
  916. nx_fw_msg_t msg;
  917. struct status_desc *desc;
  918. int i = 0, opcode;
  919. while (desc_cnt > 0 && i < 8) {
  920. desc = &sds_ring->desc_head[index];
  921. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  922. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  923. index = get_next_index(index, sds_ring->num_desc);
  924. desc_cnt--;
  925. }
  926. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  927. switch (opcode) {
  928. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  929. netxen_handle_linkevent(sds_ring->adapter, &msg);
  930. break;
  931. default:
  932. break;
  933. }
  934. }
  935. static int
  936. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  937. struct nx_host_rds_ring *rds_ring,
  938. struct netxen_rx_buffer *buffer)
  939. {
  940. struct sk_buff *skb;
  941. dma_addr_t dma;
  942. struct pci_dev *pdev = adapter->pdev;
  943. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  944. if (!buffer->skb)
  945. return 1;
  946. skb = buffer->skb;
  947. if (!adapter->ahw.cut_through)
  948. skb_reserve(skb, 2);
  949. dma = pci_map_single(pdev, skb->data,
  950. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  951. if (pci_dma_mapping_error(pdev, dma)) {
  952. dev_kfree_skb_any(skb);
  953. buffer->skb = NULL;
  954. return 1;
  955. }
  956. buffer->skb = skb;
  957. buffer->dma = dma;
  958. buffer->state = NETXEN_BUFFER_BUSY;
  959. return 0;
  960. }
  961. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  962. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  963. {
  964. struct netxen_rx_buffer *buffer;
  965. struct sk_buff *skb;
  966. buffer = &rds_ring->rx_buf_arr[index];
  967. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  968. PCI_DMA_FROMDEVICE);
  969. skb = buffer->skb;
  970. if (!skb)
  971. goto no_skb;
  972. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  973. adapter->stats.csummed++;
  974. skb->ip_summed = CHECKSUM_UNNECESSARY;
  975. } else
  976. skb->ip_summed = CHECKSUM_NONE;
  977. skb->dev = adapter->netdev;
  978. buffer->skb = NULL;
  979. no_skb:
  980. buffer->state = NETXEN_BUFFER_FREE;
  981. return skb;
  982. }
  983. static struct netxen_rx_buffer *
  984. netxen_process_rcv(struct netxen_adapter *adapter,
  985. struct nx_host_sds_ring *sds_ring,
  986. int ring, u64 sts_data0)
  987. {
  988. struct net_device *netdev = adapter->netdev;
  989. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  990. struct netxen_rx_buffer *buffer;
  991. struct sk_buff *skb;
  992. struct nx_host_rds_ring *rds_ring;
  993. int index, length, cksum, pkt_offset;
  994. if (unlikely(ring >= adapter->max_rds_rings))
  995. return NULL;
  996. rds_ring = &recv_ctx->rds_rings[ring];
  997. index = netxen_get_sts_refhandle(sts_data0);
  998. if (unlikely(index >= rds_ring->num_desc))
  999. return NULL;
  1000. buffer = &rds_ring->rx_buf_arr[index];
  1001. length = netxen_get_sts_totallength(sts_data0);
  1002. cksum = netxen_get_sts_status(sts_data0);
  1003. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1004. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1005. if (!skb)
  1006. return buffer;
  1007. if (length > rds_ring->skb_size)
  1008. skb_put(skb, rds_ring->skb_size);
  1009. else
  1010. skb_put(skb, length);
  1011. if (pkt_offset)
  1012. skb_pull(skb, pkt_offset);
  1013. skb->protocol = eth_type_trans(skb, netdev);
  1014. napi_gro_receive(&sds_ring->napi, skb);
  1015. adapter->stats.rx_pkts++;
  1016. adapter->stats.rxbytes += length;
  1017. return buffer;
  1018. }
  1019. #define TCP_HDR_SIZE 20
  1020. #define TCP_TS_OPTION_SIZE 12
  1021. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1022. static struct netxen_rx_buffer *
  1023. netxen_process_lro(struct netxen_adapter *adapter,
  1024. struct nx_host_sds_ring *sds_ring,
  1025. int ring, u64 sts_data0, u64 sts_data1)
  1026. {
  1027. struct net_device *netdev = adapter->netdev;
  1028. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1029. struct netxen_rx_buffer *buffer;
  1030. struct sk_buff *skb;
  1031. struct nx_host_rds_ring *rds_ring;
  1032. struct iphdr *iph;
  1033. struct tcphdr *th;
  1034. bool push, timestamp;
  1035. int l2_hdr_offset, l4_hdr_offset;
  1036. int index;
  1037. u16 lro_length, length, data_offset;
  1038. u32 seq_number;
  1039. if (unlikely(ring > adapter->max_rds_rings))
  1040. return NULL;
  1041. rds_ring = &recv_ctx->rds_rings[ring];
  1042. index = netxen_get_lro_sts_refhandle(sts_data0);
  1043. if (unlikely(index > rds_ring->num_desc))
  1044. return NULL;
  1045. buffer = &rds_ring->rx_buf_arr[index];
  1046. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1047. lro_length = netxen_get_lro_sts_length(sts_data0);
  1048. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1049. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1050. push = netxen_get_lro_sts_push_flag(sts_data0);
  1051. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1052. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1053. if (!skb)
  1054. return buffer;
  1055. if (timestamp)
  1056. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1057. else
  1058. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1059. skb_put(skb, lro_length + data_offset);
  1060. skb->truesize = (skb->len + sizeof(struct sk_buff) +
  1061. ((unsigned long)skb->data - (unsigned long)skb->head));
  1062. skb_pull(skb, l2_hdr_offset);
  1063. skb->protocol = eth_type_trans(skb, netdev);
  1064. iph = (struct iphdr *)skb->data;
  1065. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1066. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1067. iph->tot_len = htons(length);
  1068. iph->check = 0;
  1069. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1070. th->psh = push;
  1071. th->seq = htonl(seq_number);
  1072. length = skb->len;
  1073. netif_receive_skb(skb);
  1074. adapter->stats.lro_pkts++;
  1075. adapter->stats.rxbytes += length;
  1076. return buffer;
  1077. }
  1078. #define netxen_merge_rx_buffers(list, head) \
  1079. do { list_splice_tail_init(list, head); } while (0);
  1080. int
  1081. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1082. {
  1083. struct netxen_adapter *adapter = sds_ring->adapter;
  1084. struct list_head *cur;
  1085. struct status_desc *desc;
  1086. struct netxen_rx_buffer *rxbuf;
  1087. u32 consumer = sds_ring->consumer;
  1088. int count = 0;
  1089. u64 sts_data0, sts_data1;
  1090. int opcode, ring = 0, desc_cnt;
  1091. while (count < max) {
  1092. desc = &sds_ring->desc_head[consumer];
  1093. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1094. if (!(sts_data0 & STATUS_OWNER_HOST))
  1095. break;
  1096. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1097. opcode = netxen_get_sts_opcode(sts_data0);
  1098. switch (opcode) {
  1099. case NETXEN_NIC_RXPKT_DESC:
  1100. case NETXEN_OLD_RXPKT_DESC:
  1101. case NETXEN_NIC_SYN_OFFLOAD:
  1102. ring = netxen_get_sts_type(sts_data0);
  1103. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1104. ring, sts_data0);
  1105. break;
  1106. case NETXEN_NIC_LRO_DESC:
  1107. ring = netxen_get_lro_sts_type(sts_data0);
  1108. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1109. rxbuf = netxen_process_lro(adapter, sds_ring,
  1110. ring, sts_data0, sts_data1);
  1111. break;
  1112. case NETXEN_NIC_RESPONSE_DESC:
  1113. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1114. default:
  1115. goto skip;
  1116. }
  1117. WARN_ON(desc_cnt > 1);
  1118. if (rxbuf)
  1119. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1120. skip:
  1121. for (; desc_cnt > 0; desc_cnt--) {
  1122. desc = &sds_ring->desc_head[consumer];
  1123. desc->status_desc_data[0] =
  1124. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1125. consumer = get_next_index(consumer, sds_ring->num_desc);
  1126. }
  1127. count++;
  1128. }
  1129. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1130. struct nx_host_rds_ring *rds_ring =
  1131. &adapter->recv_ctx.rds_rings[ring];
  1132. if (!list_empty(&sds_ring->free_list[ring])) {
  1133. list_for_each(cur, &sds_ring->free_list[ring]) {
  1134. rxbuf = list_entry(cur,
  1135. struct netxen_rx_buffer, list);
  1136. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1137. }
  1138. spin_lock(&rds_ring->lock);
  1139. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1140. &rds_ring->free_list);
  1141. spin_unlock(&rds_ring->lock);
  1142. }
  1143. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1144. }
  1145. if (count) {
  1146. sds_ring->consumer = consumer;
  1147. NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
  1148. }
  1149. return count;
  1150. }
  1151. /* Process Command status ring */
  1152. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1153. {
  1154. u32 sw_consumer, hw_consumer;
  1155. int count = 0, i;
  1156. struct netxen_cmd_buffer *buffer;
  1157. struct pci_dev *pdev = adapter->pdev;
  1158. struct net_device *netdev = adapter->netdev;
  1159. struct netxen_skb_frag *frag;
  1160. int done = 0;
  1161. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1162. if (!spin_trylock(&adapter->tx_clean_lock))
  1163. return 1;
  1164. sw_consumer = tx_ring->sw_consumer;
  1165. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1166. while (sw_consumer != hw_consumer) {
  1167. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1168. if (buffer->skb) {
  1169. frag = &buffer->frag_array[0];
  1170. pci_unmap_single(pdev, frag->dma, frag->length,
  1171. PCI_DMA_TODEVICE);
  1172. frag->dma = 0ULL;
  1173. for (i = 1; i < buffer->frag_count; i++) {
  1174. frag++; /* Get the next frag */
  1175. pci_unmap_page(pdev, frag->dma, frag->length,
  1176. PCI_DMA_TODEVICE);
  1177. frag->dma = 0ULL;
  1178. }
  1179. adapter->stats.xmitfinished++;
  1180. dev_kfree_skb_any(buffer->skb);
  1181. buffer->skb = NULL;
  1182. }
  1183. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1184. if (++count >= MAX_STATUS_HANDLE)
  1185. break;
  1186. }
  1187. if (count && netif_running(netdev)) {
  1188. tx_ring->sw_consumer = sw_consumer;
  1189. smp_mb();
  1190. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1191. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1192. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1193. netif_wake_queue(netdev);
  1194. __netif_tx_unlock(tx_ring->txq);
  1195. }
  1196. }
  1197. /*
  1198. * If everything is freed up to consumer then check if the ring is full
  1199. * If the ring is full then check if more needs to be freed and
  1200. * schedule the call back again.
  1201. *
  1202. * This happens when there are 2 CPUs. One could be freeing and the
  1203. * other filling it. If the ring is full when we get out of here and
  1204. * the card has already interrupted the host then the host can miss the
  1205. * interrupt.
  1206. *
  1207. * There is still a possible race condition and the host could miss an
  1208. * interrupt. The card has to take care of this.
  1209. */
  1210. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1211. done = (sw_consumer == hw_consumer);
  1212. spin_unlock(&adapter->tx_clean_lock);
  1213. return (done);
  1214. }
  1215. void
  1216. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1217. struct nx_host_rds_ring *rds_ring)
  1218. {
  1219. struct rcv_desc *pdesc;
  1220. struct netxen_rx_buffer *buffer;
  1221. int producer, count = 0;
  1222. netxen_ctx_msg msg = 0;
  1223. struct list_head *head;
  1224. producer = rds_ring->producer;
  1225. spin_lock(&rds_ring->lock);
  1226. head = &rds_ring->free_list;
  1227. while (!list_empty(head)) {
  1228. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1229. if (!buffer->skb) {
  1230. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1231. break;
  1232. }
  1233. count++;
  1234. list_del(&buffer->list);
  1235. /* make a rcv descriptor */
  1236. pdesc = &rds_ring->desc_head[producer];
  1237. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1238. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1239. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1240. producer = get_next_index(producer, rds_ring->num_desc);
  1241. }
  1242. spin_unlock(&rds_ring->lock);
  1243. if (count) {
  1244. rds_ring->producer = producer;
  1245. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1246. (producer-1) & (rds_ring->num_desc-1));
  1247. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1248. /*
  1249. * Write a doorbell msg to tell phanmon of change in
  1250. * receive ring producer
  1251. * Only for firmware version < 4.0.0
  1252. */
  1253. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1254. netxen_set_msg_privid(msg);
  1255. netxen_set_msg_count(msg,
  1256. ((producer - 1) &
  1257. (rds_ring->num_desc - 1)));
  1258. netxen_set_msg_ctxid(msg, adapter->portnum);
  1259. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1260. writel(msg,
  1261. DB_NORMALIZE(adapter,
  1262. NETXEN_RCV_PRODUCER_OFFSET));
  1263. }
  1264. }
  1265. }
  1266. static void
  1267. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1268. struct nx_host_rds_ring *rds_ring)
  1269. {
  1270. struct rcv_desc *pdesc;
  1271. struct netxen_rx_buffer *buffer;
  1272. int producer, count = 0;
  1273. struct list_head *head;
  1274. producer = rds_ring->producer;
  1275. if (!spin_trylock(&rds_ring->lock))
  1276. return;
  1277. head = &rds_ring->free_list;
  1278. while (!list_empty(head)) {
  1279. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1280. if (!buffer->skb) {
  1281. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1282. break;
  1283. }
  1284. count++;
  1285. list_del(&buffer->list);
  1286. /* make a rcv descriptor */
  1287. pdesc = &rds_ring->desc_head[producer];
  1288. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1289. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1290. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1291. producer = get_next_index(producer, rds_ring->num_desc);
  1292. }
  1293. if (count) {
  1294. rds_ring->producer = producer;
  1295. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1296. (producer - 1) & (rds_ring->num_desc - 1));
  1297. }
  1298. spin_unlock(&rds_ring->lock);
  1299. }
  1300. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1301. {
  1302. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1303. return;
  1304. }