iwl3945-base.c 123 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/wireless.h>
  42. #include <linux/firmware.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/if_arp.h>
  45. #include <net/ieee80211_radiotap.h>
  46. #include <net/mac80211.h>
  47. #include <asm/div64.h>
  48. #define DRV_NAME "iwl3945"
  49. #include "iwl-fh.h"
  50. #include "iwl-3945-fh.h"
  51. #include "iwl-commands.h"
  52. #include "iwl-sta.h"
  53. #include "iwl-3945.h"
  54. #include "iwl-core.h"
  55. #include "iwl-helpers.h"
  56. #include "iwl-dev.h"
  57. #include "iwl-spectrum.h"
  58. /*
  59. * module name, copyright, version, etc.
  60. */
  61. #define DRV_DESCRIPTION \
  62. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  63. #ifdef CONFIG_IWLWIFI_DEBUG
  64. #define VD "d"
  65. #else
  66. #define VD
  67. #endif
  68. /*
  69. * add "s" to indicate spectrum measurement included.
  70. * we add it here to be consistent with previous releases in which
  71. * this was configurable.
  72. */
  73. #define DRV_VERSION IWLWIFI_VERSION VD "s"
  74. #define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation"
  75. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  76. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  77. MODULE_VERSION(DRV_VERSION);
  78. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  79. MODULE_LICENSE("GPL");
  80. /* module parameters */
  81. struct iwl_mod_params iwl3945_mod_params = {
  82. .sw_crypto = 1,
  83. .restart_fw = 1,
  84. /* the rest are 0 by default */
  85. };
  86. /**
  87. * iwl3945_get_antenna_flags - Get antenna flags for RXON command
  88. * @priv: eeprom and antenna fields are used to determine antenna flags
  89. *
  90. * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
  91. * iwl3945_mod_params.antenna specifies the antenna diversity mode:
  92. *
  93. * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
  94. * IWL_ANTENNA_MAIN - Force MAIN antenna
  95. * IWL_ANTENNA_AUX - Force AUX antenna
  96. */
  97. __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
  98. {
  99. struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  100. switch (iwl3945_mod_params.antenna) {
  101. case IWL_ANTENNA_DIVERSITY:
  102. return 0;
  103. case IWL_ANTENNA_MAIN:
  104. if (eeprom->antenna_switch_type)
  105. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  106. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  107. case IWL_ANTENNA_AUX:
  108. if (eeprom->antenna_switch_type)
  109. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  110. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  111. }
  112. /* bad antenna selector value */
  113. IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
  114. iwl3945_mod_params.antenna);
  115. return 0; /* "diversity" is default if error */
  116. }
  117. static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
  118. struct ieee80211_key_conf *keyconf,
  119. u8 sta_id)
  120. {
  121. unsigned long flags;
  122. __le16 key_flags = 0;
  123. int ret;
  124. key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
  125. key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  126. if (sta_id == priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id)
  127. key_flags |= STA_KEY_MULTICAST_MSK;
  128. keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  129. keyconf->hw_key_idx = keyconf->keyidx;
  130. key_flags &= ~STA_KEY_FLG_INVALID;
  131. spin_lock_irqsave(&priv->sta_lock, flags);
  132. priv->stations[sta_id].keyinfo.cipher = keyconf->cipher;
  133. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  134. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  135. keyconf->keylen);
  136. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  137. keyconf->keylen);
  138. if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
  139. == STA_KEY_FLG_NO_ENC)
  140. priv->stations[sta_id].sta.key.key_offset =
  141. iwl_get_free_ucode_key_index(priv);
  142. /* else, we are overriding an existing key => no need to allocated room
  143. * in uCode. */
  144. WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
  145. "no space for a new key");
  146. priv->stations[sta_id].sta.key.key_flags = key_flags;
  147. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  148. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  149. IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
  150. ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  151. spin_unlock_irqrestore(&priv->sta_lock, flags);
  152. return ret;
  153. }
  154. static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
  155. struct ieee80211_key_conf *keyconf,
  156. u8 sta_id)
  157. {
  158. return -EOPNOTSUPP;
  159. }
  160. static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
  161. struct ieee80211_key_conf *keyconf,
  162. u8 sta_id)
  163. {
  164. return -EOPNOTSUPP;
  165. }
  166. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  167. {
  168. unsigned long flags;
  169. struct iwl_addsta_cmd sta_cmd;
  170. spin_lock_irqsave(&priv->sta_lock, flags);
  171. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
  172. memset(&priv->stations[sta_id].sta.key, 0,
  173. sizeof(struct iwl4965_keyinfo));
  174. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  175. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  176. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  177. memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(struct iwl_addsta_cmd));
  178. spin_unlock_irqrestore(&priv->sta_lock, flags);
  179. IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
  180. return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC);
  181. }
  182. static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
  183. struct ieee80211_key_conf *keyconf, u8 sta_id)
  184. {
  185. int ret = 0;
  186. keyconf->hw_key_idx = HW_KEY_DYNAMIC;
  187. switch (keyconf->cipher) {
  188. case WLAN_CIPHER_SUITE_CCMP:
  189. ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
  190. break;
  191. case WLAN_CIPHER_SUITE_TKIP:
  192. ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
  193. break;
  194. case WLAN_CIPHER_SUITE_WEP40:
  195. case WLAN_CIPHER_SUITE_WEP104:
  196. ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
  197. break;
  198. default:
  199. IWL_ERR(priv, "Unknown alg: %s alg=%x\n", __func__,
  200. keyconf->cipher);
  201. ret = -EINVAL;
  202. }
  203. IWL_DEBUG_WEP(priv, "Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
  204. keyconf->cipher, keyconf->keylen, keyconf->keyidx,
  205. sta_id, ret);
  206. return ret;
  207. }
  208. static int iwl3945_remove_static_key(struct iwl_priv *priv)
  209. {
  210. int ret = -EOPNOTSUPP;
  211. return ret;
  212. }
  213. static int iwl3945_set_static_key(struct iwl_priv *priv,
  214. struct ieee80211_key_conf *key)
  215. {
  216. if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  217. key->cipher == WLAN_CIPHER_SUITE_WEP104)
  218. return -EOPNOTSUPP;
  219. IWL_ERR(priv, "Static key invalid: cipher %x\n", key->cipher);
  220. return -EINVAL;
  221. }
  222. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  223. {
  224. struct list_head *element;
  225. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  226. priv->frames_count);
  227. while (!list_empty(&priv->free_frames)) {
  228. element = priv->free_frames.next;
  229. list_del(element);
  230. kfree(list_entry(element, struct iwl3945_frame, list));
  231. priv->frames_count--;
  232. }
  233. if (priv->frames_count) {
  234. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  235. priv->frames_count);
  236. priv->frames_count = 0;
  237. }
  238. }
  239. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  240. {
  241. struct iwl3945_frame *frame;
  242. struct list_head *element;
  243. if (list_empty(&priv->free_frames)) {
  244. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  245. if (!frame) {
  246. IWL_ERR(priv, "Could not allocate frame!\n");
  247. return NULL;
  248. }
  249. priv->frames_count++;
  250. return frame;
  251. }
  252. element = priv->free_frames.next;
  253. list_del(element);
  254. return list_entry(element, struct iwl3945_frame, list);
  255. }
  256. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  257. {
  258. memset(frame, 0, sizeof(*frame));
  259. list_add(&frame->list, &priv->free_frames);
  260. }
  261. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  262. struct ieee80211_hdr *hdr,
  263. int left)
  264. {
  265. if (!iwl_is_associated(priv, IWL_RXON_CTX_BSS) || !priv->ibss_beacon)
  266. return 0;
  267. if (priv->ibss_beacon->len > left)
  268. return 0;
  269. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  270. return priv->ibss_beacon->len;
  271. }
  272. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  273. {
  274. struct iwl3945_frame *frame;
  275. unsigned int frame_size;
  276. int rc;
  277. u8 rate;
  278. frame = iwl3945_get_free_frame(priv);
  279. if (!frame) {
  280. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  281. "command.\n");
  282. return -ENOMEM;
  283. }
  284. rate = iwl_rate_get_lowest_plcp(priv);
  285. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  286. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  287. &frame->u.cmd[0]);
  288. iwl3945_free_frame(priv, frame);
  289. return rc;
  290. }
  291. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  292. {
  293. if (priv->_3945.shared_virt)
  294. dma_free_coherent(&priv->pci_dev->dev,
  295. sizeof(struct iwl3945_shared),
  296. priv->_3945.shared_virt,
  297. priv->_3945.shared_phys);
  298. }
  299. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  300. struct ieee80211_tx_info *info,
  301. struct iwl_device_cmd *cmd,
  302. struct sk_buff *skb_frag,
  303. int sta_id)
  304. {
  305. struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  306. struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
  307. tx_cmd->sec_ctl = 0;
  308. switch (keyinfo->cipher) {
  309. case WLAN_CIPHER_SUITE_CCMP:
  310. tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
  311. memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
  312. IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
  313. break;
  314. case WLAN_CIPHER_SUITE_TKIP:
  315. break;
  316. case WLAN_CIPHER_SUITE_WEP104:
  317. tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
  318. /* fall through */
  319. case WLAN_CIPHER_SUITE_WEP40:
  320. tx_cmd->sec_ctl |= TX_CMD_SEC_WEP |
  321. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  322. memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
  323. IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
  324. "with key %d\n", info->control.hw_key->hw_key_idx);
  325. break;
  326. default:
  327. IWL_ERR(priv, "Unknown encode cipher %x\n", keyinfo->cipher);
  328. break;
  329. }
  330. }
  331. /*
  332. * handle build REPLY_TX command notification.
  333. */
  334. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  335. struct iwl_device_cmd *cmd,
  336. struct ieee80211_tx_info *info,
  337. struct ieee80211_hdr *hdr, u8 std_id)
  338. {
  339. struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  340. __le32 tx_flags = tx_cmd->tx_flags;
  341. __le16 fc = hdr->frame_control;
  342. tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  343. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  344. tx_flags |= TX_CMD_FLG_ACK_MSK;
  345. if (ieee80211_is_mgmt(fc))
  346. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  347. if (ieee80211_is_probe_resp(fc) &&
  348. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  349. tx_flags |= TX_CMD_FLG_TSF_MSK;
  350. } else {
  351. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  352. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  353. }
  354. tx_cmd->sta_id = std_id;
  355. if (ieee80211_has_morefrags(fc))
  356. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  357. if (ieee80211_is_data_qos(fc)) {
  358. u8 *qc = ieee80211_get_qos_ctl(hdr);
  359. tx_cmd->tid_tspec = qc[0] & 0xf;
  360. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  361. } else {
  362. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  363. }
  364. priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags);
  365. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  366. if (ieee80211_is_mgmt(fc)) {
  367. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  368. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
  369. else
  370. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
  371. } else {
  372. tx_cmd->timeout.pm_frame_timeout = 0;
  373. }
  374. tx_cmd->driver_txop = 0;
  375. tx_cmd->tx_flags = tx_flags;
  376. tx_cmd->next_frame_len = 0;
  377. }
  378. /*
  379. * start REPLY_TX command process
  380. */
  381. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  382. {
  383. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  384. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  385. struct iwl3945_tx_cmd *tx_cmd;
  386. struct iwl_tx_queue *txq = NULL;
  387. struct iwl_queue *q = NULL;
  388. struct iwl_device_cmd *out_cmd;
  389. struct iwl_cmd_meta *out_meta;
  390. dma_addr_t phys_addr;
  391. dma_addr_t txcmd_phys;
  392. int txq_id = skb_get_queue_mapping(skb);
  393. u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
  394. u8 id;
  395. u8 unicast;
  396. u8 sta_id;
  397. u8 tid = 0;
  398. __le16 fc;
  399. u8 wait_write_ptr = 0;
  400. unsigned long flags;
  401. spin_lock_irqsave(&priv->lock, flags);
  402. if (iwl_is_rfkill(priv)) {
  403. IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
  404. goto drop_unlock;
  405. }
  406. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  407. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  408. goto drop_unlock;
  409. }
  410. unicast = !is_multicast_ether_addr(hdr->addr1);
  411. id = 0;
  412. fc = hdr->frame_control;
  413. #ifdef CONFIG_IWLWIFI_DEBUG
  414. if (ieee80211_is_auth(fc))
  415. IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
  416. else if (ieee80211_is_assoc_req(fc))
  417. IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
  418. else if (ieee80211_is_reassoc_req(fc))
  419. IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
  420. #endif
  421. spin_unlock_irqrestore(&priv->lock, flags);
  422. hdr_len = ieee80211_hdrlen(fc);
  423. /* Find index into station table for destination station */
  424. sta_id = iwl_sta_id_or_broadcast(
  425. priv, &priv->contexts[IWL_RXON_CTX_BSS],
  426. info->control.sta);
  427. if (sta_id == IWL_INVALID_STATION) {
  428. IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
  429. hdr->addr1);
  430. goto drop;
  431. }
  432. IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
  433. if (ieee80211_is_data_qos(fc)) {
  434. u8 *qc = ieee80211_get_qos_ctl(hdr);
  435. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  436. if (unlikely(tid >= MAX_TID_COUNT))
  437. goto drop;
  438. }
  439. /* Descriptor for chosen Tx queue */
  440. txq = &priv->txq[txq_id];
  441. q = &txq->q;
  442. if ((iwl_queue_space(q) < q->high_mark))
  443. goto drop;
  444. spin_lock_irqsave(&priv->lock, flags);
  445. idx = get_cmd_index(q, q->write_ptr, 0);
  446. /* Set up driver data for this TFD */
  447. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
  448. txq->txb[q->write_ptr].skb = skb;
  449. txq->txb[q->write_ptr].ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  450. /* Init first empty entry in queue's array of Tx/cmd buffers */
  451. out_cmd = txq->cmd[idx];
  452. out_meta = &txq->meta[idx];
  453. tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
  454. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  455. memset(tx_cmd, 0, sizeof(*tx_cmd));
  456. /*
  457. * Set up the Tx-command (not MAC!) header.
  458. * Store the chosen Tx queue and TFD index within the sequence field;
  459. * after Tx, uCode's Tx response will return this value so driver can
  460. * locate the frame within the tx queue and do post-tx processing.
  461. */
  462. out_cmd->hdr.cmd = REPLY_TX;
  463. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  464. INDEX_TO_SEQ(q->write_ptr)));
  465. /* Copy MAC header from skb into command buffer */
  466. memcpy(tx_cmd->hdr, hdr, hdr_len);
  467. if (info->control.hw_key)
  468. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
  469. /* TODO need this for burst mode later on */
  470. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
  471. /* set is_hcca to 0; it probably will never be implemented */
  472. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  473. /* Total # bytes to be transmitted */
  474. len = (u16)skb->len;
  475. tx_cmd->len = cpu_to_le16(len);
  476. iwl_dbg_log_tx_data_frame(priv, len, hdr);
  477. iwl_update_stats(priv, true, fc, len);
  478. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  479. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  480. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  481. txq->need_update = 1;
  482. } else {
  483. wait_write_ptr = 1;
  484. txq->need_update = 0;
  485. }
  486. IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
  487. le16_to_cpu(out_cmd->hdr.sequence));
  488. IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
  489. iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
  490. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
  491. ieee80211_hdrlen(fc));
  492. /*
  493. * Use the first empty entry in this queue's command buffer array
  494. * to contain the Tx command and MAC header concatenated together
  495. * (payload data will be in another buffer).
  496. * Size of this varies, due to varying MAC header length.
  497. * If end is not dword aligned, we'll have 2 extra bytes at the end
  498. * of the MAC header (device reads on dword boundaries).
  499. * We'll tell device about this padding later.
  500. */
  501. len = sizeof(struct iwl3945_tx_cmd) +
  502. sizeof(struct iwl_cmd_header) + hdr_len;
  503. len_org = len;
  504. len = (len + 3) & ~3;
  505. if (len_org != len)
  506. len_org = 1;
  507. else
  508. len_org = 0;
  509. /* Physical address of this Tx command's header (not MAC header!),
  510. * within command buffer array. */
  511. txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
  512. len, PCI_DMA_TODEVICE);
  513. /* we do not map meta data ... so we can safely access address to
  514. * provide to unmap command*/
  515. dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
  516. dma_unmap_len_set(out_meta, len, len);
  517. /* Add buffer containing Tx command and MAC(!) header to TFD's
  518. * first entry */
  519. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  520. txcmd_phys, len, 1, 0);
  521. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  522. * if any (802.11 null frames have no payload). */
  523. len = skb->len - hdr_len;
  524. if (len) {
  525. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  526. len, PCI_DMA_TODEVICE);
  527. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  528. phys_addr, len,
  529. 0, U32_PAD(len));
  530. }
  531. /* Tell device the write index *just past* this latest filled TFD */
  532. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  533. iwl_txq_update_write_ptr(priv, txq);
  534. spin_unlock_irqrestore(&priv->lock, flags);
  535. if ((iwl_queue_space(q) < q->high_mark)
  536. && priv->mac80211_registered) {
  537. if (wait_write_ptr) {
  538. spin_lock_irqsave(&priv->lock, flags);
  539. txq->need_update = 1;
  540. iwl_txq_update_write_ptr(priv, txq);
  541. spin_unlock_irqrestore(&priv->lock, flags);
  542. }
  543. iwl_stop_queue(priv, skb_get_queue_mapping(skb));
  544. }
  545. return 0;
  546. drop_unlock:
  547. spin_unlock_irqrestore(&priv->lock, flags);
  548. drop:
  549. return -1;
  550. }
  551. static int iwl3945_get_measurement(struct iwl_priv *priv,
  552. struct ieee80211_measurement_params *params,
  553. u8 type)
  554. {
  555. struct iwl_spectrum_cmd spectrum;
  556. struct iwl_rx_packet *pkt;
  557. struct iwl_host_cmd cmd = {
  558. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  559. .data = (void *)&spectrum,
  560. .flags = CMD_WANT_SKB,
  561. };
  562. u32 add_time = le64_to_cpu(params->start_time);
  563. int rc;
  564. int spectrum_resp_status;
  565. int duration = le16_to_cpu(params->duration);
  566. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  567. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS))
  568. add_time = iwl_usecs_to_beacons(priv,
  569. le64_to_cpu(params->start_time) - priv->_3945.last_tsf,
  570. le16_to_cpu(ctx->timing.beacon_interval));
  571. memset(&spectrum, 0, sizeof(spectrum));
  572. spectrum.channel_count = cpu_to_le16(1);
  573. spectrum.flags =
  574. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  575. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  576. cmd.len = sizeof(spectrum);
  577. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  578. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS))
  579. spectrum.start_time =
  580. iwl_add_beacon_time(priv,
  581. priv->_3945.last_beacon_time, add_time,
  582. le16_to_cpu(ctx->timing.beacon_interval));
  583. else
  584. spectrum.start_time = 0;
  585. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  586. spectrum.channels[0].channel = params->channel;
  587. spectrum.channels[0].type = type;
  588. if (ctx->active.flags & RXON_FLG_BAND_24G_MSK)
  589. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  590. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  591. rc = iwl_send_cmd_sync(priv, &cmd);
  592. if (rc)
  593. return rc;
  594. pkt = (struct iwl_rx_packet *)cmd.reply_page;
  595. if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
  596. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  597. rc = -EIO;
  598. }
  599. spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
  600. switch (spectrum_resp_status) {
  601. case 0: /* Command will be handled */
  602. if (pkt->u.spectrum.id != 0xff) {
  603. IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
  604. pkt->u.spectrum.id);
  605. priv->measurement_status &= ~MEASUREMENT_READY;
  606. }
  607. priv->measurement_status |= MEASUREMENT_ACTIVE;
  608. rc = 0;
  609. break;
  610. case 1: /* Command will not be handled */
  611. rc = -EAGAIN;
  612. break;
  613. }
  614. iwl_free_pages(priv, cmd.reply_page);
  615. return rc;
  616. }
  617. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  618. struct iwl_rx_mem_buffer *rxb)
  619. {
  620. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  621. struct iwl_alive_resp *palive;
  622. struct delayed_work *pwork;
  623. palive = &pkt->u.alive_frame;
  624. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  625. "0x%01X 0x%01X\n",
  626. palive->is_valid, palive->ver_type,
  627. palive->ver_subtype);
  628. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  629. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  630. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  631. sizeof(struct iwl_alive_resp));
  632. pwork = &priv->init_alive_start;
  633. } else {
  634. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  635. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  636. sizeof(struct iwl_alive_resp));
  637. pwork = &priv->alive_start;
  638. iwl3945_disable_events(priv);
  639. }
  640. /* We delay the ALIVE response by 5ms to
  641. * give the HW RF Kill time to activate... */
  642. if (palive->is_valid == UCODE_VALID_OK)
  643. queue_delayed_work(priv->workqueue, pwork,
  644. msecs_to_jiffies(5));
  645. else
  646. IWL_WARN(priv, "uCode did not respond OK.\n");
  647. }
  648. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  649. struct iwl_rx_mem_buffer *rxb)
  650. {
  651. #ifdef CONFIG_IWLWIFI_DEBUG
  652. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  653. #endif
  654. IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  655. }
  656. static void iwl3945_bg_beacon_update(struct work_struct *work)
  657. {
  658. struct iwl_priv *priv =
  659. container_of(work, struct iwl_priv, beacon_update);
  660. struct sk_buff *beacon;
  661. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  662. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  663. if (!beacon) {
  664. IWL_ERR(priv, "update beacon failed\n");
  665. return;
  666. }
  667. mutex_lock(&priv->mutex);
  668. /* new beacon skb is allocated every time; dispose previous.*/
  669. if (priv->ibss_beacon)
  670. dev_kfree_skb(priv->ibss_beacon);
  671. priv->ibss_beacon = beacon;
  672. mutex_unlock(&priv->mutex);
  673. iwl3945_send_beacon_cmd(priv);
  674. }
  675. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  676. struct iwl_rx_mem_buffer *rxb)
  677. {
  678. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  679. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  680. #ifdef CONFIG_IWLWIFI_DEBUG
  681. u8 rate = beacon->beacon_notify_hdr.rate;
  682. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  683. "tsf %d %d rate %d\n",
  684. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  685. beacon->beacon_notify_hdr.failure_frame,
  686. le32_to_cpu(beacon->ibss_mgr_status),
  687. le32_to_cpu(beacon->high_tsf),
  688. le32_to_cpu(beacon->low_tsf), rate);
  689. #endif
  690. priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
  691. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  692. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  693. queue_work(priv->workqueue, &priv->beacon_update);
  694. }
  695. /* Handle notification from uCode that card's power state is changing
  696. * due to software, hardware, or critical temperature RFKILL */
  697. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  698. struct iwl_rx_mem_buffer *rxb)
  699. {
  700. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  701. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  702. unsigned long status = priv->status;
  703. IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
  704. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  705. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  706. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  707. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  708. if (flags & HW_CARD_DISABLED)
  709. set_bit(STATUS_RF_KILL_HW, &priv->status);
  710. else
  711. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  712. iwl_scan_cancel(priv);
  713. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  714. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  715. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  716. test_bit(STATUS_RF_KILL_HW, &priv->status));
  717. else
  718. wake_up_interruptible(&priv->wait_command_queue);
  719. }
  720. /**
  721. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  722. *
  723. * Setup the RX handlers for each of the reply types sent from the uCode
  724. * to the host.
  725. *
  726. * This function chains into the hardware specific files for them to setup
  727. * any hardware specific handlers as well.
  728. */
  729. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  730. {
  731. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  732. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  733. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  734. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  735. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  736. iwl_rx_spectrum_measure_notif;
  737. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  738. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  739. iwl_rx_pm_debug_statistics_notif;
  740. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  741. /*
  742. * The same handler is used for both the REPLY to a discrete
  743. * statistics request from the host as well as for the periodic
  744. * statistics notifications (after received beacons) from the uCode.
  745. */
  746. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_reply_statistics;
  747. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  748. iwl_setup_rx_scan_handlers(priv);
  749. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  750. /* Set up hardware specific Rx handlers */
  751. iwl3945_hw_rx_handler_setup(priv);
  752. }
  753. /************************** RX-FUNCTIONS ****************************/
  754. /*
  755. * Rx theory of operation
  756. *
  757. * The host allocates 32 DMA target addresses and passes the host address
  758. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  759. * 0 to 31
  760. *
  761. * Rx Queue Indexes
  762. * The host/firmware share two index registers for managing the Rx buffers.
  763. *
  764. * The READ index maps to the first position that the firmware may be writing
  765. * to -- the driver can read up to (but not including) this position and get
  766. * good data.
  767. * The READ index is managed by the firmware once the card is enabled.
  768. *
  769. * The WRITE index maps to the last position the driver has read from -- the
  770. * position preceding WRITE is the last slot the firmware can place a packet.
  771. *
  772. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  773. * WRITE = READ.
  774. *
  775. * During initialization, the host sets up the READ queue position to the first
  776. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  777. *
  778. * When the firmware places a packet in a buffer, it will advance the READ index
  779. * and fire the RX interrupt. The driver can then query the READ index and
  780. * process as many packets as possible, moving the WRITE index forward as it
  781. * resets the Rx queue buffers with new memory.
  782. *
  783. * The management in the driver is as follows:
  784. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  785. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  786. * to replenish the iwl->rxq->rx_free.
  787. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  788. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  789. * 'processed' and 'read' driver indexes as well)
  790. * + A received packet is processed and handed to the kernel network stack,
  791. * detached from the iwl->rxq. The driver 'processed' index is updated.
  792. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  793. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  794. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  795. * were enough free buffers and RX_STALLED is set it is cleared.
  796. *
  797. *
  798. * Driver sequence:
  799. *
  800. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  801. * iwl3945_rx_queue_restock
  802. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  803. * queue, updates firmware pointers, and updates
  804. * the WRITE index. If insufficient rx_free buffers
  805. * are available, schedules iwl3945_rx_replenish
  806. *
  807. * -- enable interrupts --
  808. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  809. * READ INDEX, detaching the SKB from the pool.
  810. * Moves the packet buffer from queue to rx_used.
  811. * Calls iwl3945_rx_queue_restock to refill any empty
  812. * slots.
  813. * ...
  814. *
  815. */
  816. /**
  817. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  818. */
  819. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  820. dma_addr_t dma_addr)
  821. {
  822. return cpu_to_le32((u32)dma_addr);
  823. }
  824. /**
  825. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  826. *
  827. * If there are slots in the RX queue that need to be restocked,
  828. * and we have free pre-allocated buffers, fill the ranks as much
  829. * as we can, pulling from rx_free.
  830. *
  831. * This moves the 'write' index forward to catch up with 'processed', and
  832. * also updates the memory address in the firmware to reference the new
  833. * target buffer.
  834. */
  835. static void iwl3945_rx_queue_restock(struct iwl_priv *priv)
  836. {
  837. struct iwl_rx_queue *rxq = &priv->rxq;
  838. struct list_head *element;
  839. struct iwl_rx_mem_buffer *rxb;
  840. unsigned long flags;
  841. int write;
  842. spin_lock_irqsave(&rxq->lock, flags);
  843. write = rxq->write & ~0x7;
  844. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  845. /* Get next free Rx buffer, remove from free list */
  846. element = rxq->rx_free.next;
  847. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  848. list_del(element);
  849. /* Point to Rx buffer via next RBD in circular buffer */
  850. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
  851. rxq->queue[rxq->write] = rxb;
  852. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  853. rxq->free_count--;
  854. }
  855. spin_unlock_irqrestore(&rxq->lock, flags);
  856. /* If the pre-allocated buffer pool is dropping low, schedule to
  857. * refill it */
  858. if (rxq->free_count <= RX_LOW_WATERMARK)
  859. queue_work(priv->workqueue, &priv->rx_replenish);
  860. /* If we've added more space for the firmware to place data, tell it.
  861. * Increment device's write pointer in multiples of 8. */
  862. if ((rxq->write_actual != (rxq->write & ~0x7))
  863. || (abs(rxq->write - rxq->read) > 7)) {
  864. spin_lock_irqsave(&rxq->lock, flags);
  865. rxq->need_update = 1;
  866. spin_unlock_irqrestore(&rxq->lock, flags);
  867. iwl_rx_queue_update_write_ptr(priv, rxq);
  868. }
  869. }
  870. /**
  871. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  872. *
  873. * When moving to rx_free an SKB is allocated for the slot.
  874. *
  875. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  876. * This is called as a scheduled work item (except for during initialization)
  877. */
  878. static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  879. {
  880. struct iwl_rx_queue *rxq = &priv->rxq;
  881. struct list_head *element;
  882. struct iwl_rx_mem_buffer *rxb;
  883. struct page *page;
  884. unsigned long flags;
  885. gfp_t gfp_mask = priority;
  886. while (1) {
  887. spin_lock_irqsave(&rxq->lock, flags);
  888. if (list_empty(&rxq->rx_used)) {
  889. spin_unlock_irqrestore(&rxq->lock, flags);
  890. return;
  891. }
  892. spin_unlock_irqrestore(&rxq->lock, flags);
  893. if (rxq->free_count > RX_LOW_WATERMARK)
  894. gfp_mask |= __GFP_NOWARN;
  895. if (priv->hw_params.rx_page_order > 0)
  896. gfp_mask |= __GFP_COMP;
  897. /* Alloc a new receive buffer */
  898. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  899. if (!page) {
  900. if (net_ratelimit())
  901. IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
  902. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  903. net_ratelimit())
  904. IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
  905. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  906. rxq->free_count);
  907. /* We don't reschedule replenish work here -- we will
  908. * call the restock method and if it still needs
  909. * more buffers it will schedule replenish */
  910. break;
  911. }
  912. spin_lock_irqsave(&rxq->lock, flags);
  913. if (list_empty(&rxq->rx_used)) {
  914. spin_unlock_irqrestore(&rxq->lock, flags);
  915. __free_pages(page, priv->hw_params.rx_page_order);
  916. return;
  917. }
  918. element = rxq->rx_used.next;
  919. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  920. list_del(element);
  921. spin_unlock_irqrestore(&rxq->lock, flags);
  922. rxb->page = page;
  923. /* Get physical address of RB/SKB */
  924. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  925. PAGE_SIZE << priv->hw_params.rx_page_order,
  926. PCI_DMA_FROMDEVICE);
  927. spin_lock_irqsave(&rxq->lock, flags);
  928. list_add_tail(&rxb->list, &rxq->rx_free);
  929. rxq->free_count++;
  930. priv->alloc_rxb_page++;
  931. spin_unlock_irqrestore(&rxq->lock, flags);
  932. }
  933. }
  934. void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  935. {
  936. unsigned long flags;
  937. int i;
  938. spin_lock_irqsave(&rxq->lock, flags);
  939. INIT_LIST_HEAD(&rxq->rx_free);
  940. INIT_LIST_HEAD(&rxq->rx_used);
  941. /* Fill the rx_used queue with _all_ of the Rx buffers */
  942. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  943. /* In the reset function, these buffers may have been allocated
  944. * to an SKB, so we need to unmap and free potential storage */
  945. if (rxq->pool[i].page != NULL) {
  946. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  947. PAGE_SIZE << priv->hw_params.rx_page_order,
  948. PCI_DMA_FROMDEVICE);
  949. __iwl_free_pages(priv, rxq->pool[i].page);
  950. rxq->pool[i].page = NULL;
  951. }
  952. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  953. }
  954. /* Set us so that we have processed and used all buffers, but have
  955. * not restocked the Rx queue with fresh buffers */
  956. rxq->read = rxq->write = 0;
  957. rxq->write_actual = 0;
  958. rxq->free_count = 0;
  959. spin_unlock_irqrestore(&rxq->lock, flags);
  960. }
  961. void iwl3945_rx_replenish(void *data)
  962. {
  963. struct iwl_priv *priv = data;
  964. unsigned long flags;
  965. iwl3945_rx_allocate(priv, GFP_KERNEL);
  966. spin_lock_irqsave(&priv->lock, flags);
  967. iwl3945_rx_queue_restock(priv);
  968. spin_unlock_irqrestore(&priv->lock, flags);
  969. }
  970. static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
  971. {
  972. iwl3945_rx_allocate(priv, GFP_ATOMIC);
  973. iwl3945_rx_queue_restock(priv);
  974. }
  975. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  976. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  977. * This free routine walks the list of POOL entries and if SKB is set to
  978. * non NULL it is unmapped and freed
  979. */
  980. static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  981. {
  982. int i;
  983. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  984. if (rxq->pool[i].page != NULL) {
  985. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  986. PAGE_SIZE << priv->hw_params.rx_page_order,
  987. PCI_DMA_FROMDEVICE);
  988. __iwl_free_pages(priv, rxq->pool[i].page);
  989. rxq->pool[i].page = NULL;
  990. }
  991. }
  992. dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  993. rxq->bd_dma);
  994. dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
  995. rxq->rb_stts, rxq->rb_stts_dma);
  996. rxq->bd = NULL;
  997. rxq->rb_stts = NULL;
  998. }
  999. /* Convert linear signal-to-noise ratio into dB */
  1000. static u8 ratio2dB[100] = {
  1001. /* 0 1 2 3 4 5 6 7 8 9 */
  1002. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  1003. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  1004. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  1005. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  1006. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  1007. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  1008. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  1009. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  1010. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  1011. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  1012. };
  1013. /* Calculates a relative dB value from a ratio of linear
  1014. * (i.e. not dB) signal levels.
  1015. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  1016. int iwl3945_calc_db_from_ratio(int sig_ratio)
  1017. {
  1018. /* 1000:1 or higher just report as 60 dB */
  1019. if (sig_ratio >= 1000)
  1020. return 60;
  1021. /* 100:1 or higher, divide by 10 and use table,
  1022. * add 20 dB to make up for divide by 10 */
  1023. if (sig_ratio >= 100)
  1024. return 20 + (int)ratio2dB[sig_ratio/10];
  1025. /* We shouldn't see this */
  1026. if (sig_ratio < 1)
  1027. return 0;
  1028. /* Use table for ratios 1:1 - 99:1 */
  1029. return (int)ratio2dB[sig_ratio];
  1030. }
  1031. /**
  1032. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  1033. *
  1034. * Uses the priv->rx_handlers callback function array to invoke
  1035. * the appropriate handlers, including command responses,
  1036. * frame-received notifications, and other notifications.
  1037. */
  1038. static void iwl3945_rx_handle(struct iwl_priv *priv)
  1039. {
  1040. struct iwl_rx_mem_buffer *rxb;
  1041. struct iwl_rx_packet *pkt;
  1042. struct iwl_rx_queue *rxq = &priv->rxq;
  1043. u32 r, i;
  1044. int reclaim;
  1045. unsigned long flags;
  1046. u8 fill_rx = 0;
  1047. u32 count = 8;
  1048. int total_empty = 0;
  1049. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  1050. * buffer that the driver may process (last buffer filled by ucode). */
  1051. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  1052. i = rxq->read;
  1053. /* calculate total frames need to be restock after handling RX */
  1054. total_empty = r - rxq->write_actual;
  1055. if (total_empty < 0)
  1056. total_empty += RX_QUEUE_SIZE;
  1057. if (total_empty > (RX_QUEUE_SIZE / 2))
  1058. fill_rx = 1;
  1059. /* Rx interrupt, but nothing sent from uCode */
  1060. if (i == r)
  1061. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  1062. while (i != r) {
  1063. int len;
  1064. rxb = rxq->queue[i];
  1065. /* If an RXB doesn't have a Rx queue slot associated with it,
  1066. * then a bug has been introduced in the queue refilling
  1067. * routines -- catch it here */
  1068. BUG_ON(rxb == NULL);
  1069. rxq->queue[i] = NULL;
  1070. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  1071. PAGE_SIZE << priv->hw_params.rx_page_order,
  1072. PCI_DMA_FROMDEVICE);
  1073. pkt = rxb_addr(rxb);
  1074. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1075. len += sizeof(u32); /* account for status word */
  1076. trace_iwlwifi_dev_rx(priv, pkt, len);
  1077. /* Reclaim a command buffer only if this packet is a response
  1078. * to a (driver-originated) command.
  1079. * If the packet (e.g. Rx frame) originated from uCode,
  1080. * there is no command buffer to reclaim.
  1081. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  1082. * but apparently a few don't get set; catch them here. */
  1083. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  1084. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  1085. (pkt->hdr.cmd != REPLY_TX);
  1086. /* Based on type of command response or notification,
  1087. * handle those that need handling via function in
  1088. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  1089. if (priv->rx_handlers[pkt->hdr.cmd]) {
  1090. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
  1091. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  1092. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  1093. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  1094. } else {
  1095. /* No handling needed */
  1096. IWL_DEBUG_RX(priv,
  1097. "r %d i %d No handler needed for %s, 0x%02x\n",
  1098. r, i, get_cmd_string(pkt->hdr.cmd),
  1099. pkt->hdr.cmd);
  1100. }
  1101. /*
  1102. * XXX: After here, we should always check rxb->page
  1103. * against NULL before touching it or its virtual
  1104. * memory (pkt). Because some rx_handler might have
  1105. * already taken or freed the pages.
  1106. */
  1107. if (reclaim) {
  1108. /* Invoke any callbacks, transfer the buffer to caller,
  1109. * and fire off the (possibly) blocking iwl_send_cmd()
  1110. * as we reclaim the driver command queue */
  1111. if (rxb->page)
  1112. iwl_tx_cmd_complete(priv, rxb);
  1113. else
  1114. IWL_WARN(priv, "Claim null rxb?\n");
  1115. }
  1116. /* Reuse the page if possible. For notification packets and
  1117. * SKBs that fail to Rx correctly, add them back into the
  1118. * rx_free list for reuse later. */
  1119. spin_lock_irqsave(&rxq->lock, flags);
  1120. if (rxb->page != NULL) {
  1121. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  1122. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  1123. PCI_DMA_FROMDEVICE);
  1124. list_add_tail(&rxb->list, &rxq->rx_free);
  1125. rxq->free_count++;
  1126. } else
  1127. list_add_tail(&rxb->list, &rxq->rx_used);
  1128. spin_unlock_irqrestore(&rxq->lock, flags);
  1129. i = (i + 1) & RX_QUEUE_MASK;
  1130. /* If there are a lot of unused frames,
  1131. * restock the Rx queue so ucode won't assert. */
  1132. if (fill_rx) {
  1133. count++;
  1134. if (count >= 8) {
  1135. rxq->read = i;
  1136. iwl3945_rx_replenish_now(priv);
  1137. count = 0;
  1138. }
  1139. }
  1140. }
  1141. /* Backtrack one entry */
  1142. rxq->read = i;
  1143. if (fill_rx)
  1144. iwl3945_rx_replenish_now(priv);
  1145. else
  1146. iwl3945_rx_queue_restock(priv);
  1147. }
  1148. /* call this function to flush any scheduled tasklet */
  1149. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  1150. {
  1151. /* wait to make sure we flush pending tasklet*/
  1152. synchronize_irq(priv->pci_dev->irq);
  1153. tasklet_kill(&priv->irq_tasklet);
  1154. }
  1155. static const char *desc_lookup(int i)
  1156. {
  1157. switch (i) {
  1158. case 1:
  1159. return "FAIL";
  1160. case 2:
  1161. return "BAD_PARAM";
  1162. case 3:
  1163. return "BAD_CHECKSUM";
  1164. case 4:
  1165. return "NMI_INTERRUPT";
  1166. case 5:
  1167. return "SYSASSERT";
  1168. case 6:
  1169. return "FATAL_ERROR";
  1170. }
  1171. return "UNKNOWN";
  1172. }
  1173. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1174. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1175. void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  1176. {
  1177. u32 i;
  1178. u32 desc, time, count, base, data1;
  1179. u32 blink1, blink2, ilink1, ilink2;
  1180. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1181. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  1182. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1183. return;
  1184. }
  1185. count = iwl_read_targ_mem(priv, base);
  1186. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1187. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1188. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1189. priv->status, count);
  1190. }
  1191. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  1192. "ilink1 nmiPC Line\n");
  1193. for (i = ERROR_START_OFFSET;
  1194. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  1195. i += ERROR_ELEM_SIZE) {
  1196. desc = iwl_read_targ_mem(priv, base + i);
  1197. time =
  1198. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  1199. blink1 =
  1200. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  1201. blink2 =
  1202. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  1203. ilink1 =
  1204. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  1205. ilink2 =
  1206. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  1207. data1 =
  1208. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  1209. IWL_ERR(priv,
  1210. "%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  1211. desc_lookup(desc), desc, time, blink1, blink2,
  1212. ilink1, ilink2, data1);
  1213. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0,
  1214. 0, blink1, blink2, ilink1, ilink2);
  1215. }
  1216. }
  1217. #define EVENT_START_OFFSET (6 * sizeof(u32))
  1218. /**
  1219. * iwl3945_print_event_log - Dump error event log to syslog
  1220. *
  1221. */
  1222. static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1223. u32 num_events, u32 mode,
  1224. int pos, char **buf, size_t bufsz)
  1225. {
  1226. u32 i;
  1227. u32 base; /* SRAM byte address of event log header */
  1228. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1229. u32 ptr; /* SRAM byte address of log data */
  1230. u32 ev, time, data; /* event log data */
  1231. unsigned long reg_flags;
  1232. if (num_events == 0)
  1233. return pos;
  1234. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1235. if (mode == 0)
  1236. event_size = 2 * sizeof(u32);
  1237. else
  1238. event_size = 3 * sizeof(u32);
  1239. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1240. /* Make sure device is powered up for SRAM reads */
  1241. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1242. iwl_grab_nic_access(priv);
  1243. /* Set starting address; reads will auto-increment */
  1244. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1245. rmb();
  1246. /* "time" is actually "data" for mode 0 (no timestamp).
  1247. * place event id # at far right for easier visual parsing. */
  1248. for (i = 0; i < num_events; i++) {
  1249. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1250. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1251. if (mode == 0) {
  1252. /* data, ev */
  1253. if (bufsz) {
  1254. pos += scnprintf(*buf + pos, bufsz - pos,
  1255. "0x%08x:%04u\n",
  1256. time, ev);
  1257. } else {
  1258. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  1259. trace_iwlwifi_dev_ucode_event(priv, 0,
  1260. time, ev);
  1261. }
  1262. } else {
  1263. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1264. if (bufsz) {
  1265. pos += scnprintf(*buf + pos, bufsz - pos,
  1266. "%010u:0x%08x:%04u\n",
  1267. time, data, ev);
  1268. } else {
  1269. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
  1270. time, data, ev);
  1271. trace_iwlwifi_dev_ucode_event(priv, time,
  1272. data, ev);
  1273. }
  1274. }
  1275. }
  1276. /* Allow device to power down */
  1277. iwl_release_nic_access(priv);
  1278. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1279. return pos;
  1280. }
  1281. /**
  1282. * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
  1283. */
  1284. static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1285. u32 num_wraps, u32 next_entry,
  1286. u32 size, u32 mode,
  1287. int pos, char **buf, size_t bufsz)
  1288. {
  1289. /*
  1290. * display the newest DEFAULT_LOG_ENTRIES entries
  1291. * i.e the entries just before the next ont that uCode would fill.
  1292. */
  1293. if (num_wraps) {
  1294. if (next_entry < size) {
  1295. pos = iwl3945_print_event_log(priv,
  1296. capacity - (size - next_entry),
  1297. size - next_entry, mode,
  1298. pos, buf, bufsz);
  1299. pos = iwl3945_print_event_log(priv, 0,
  1300. next_entry, mode,
  1301. pos, buf, bufsz);
  1302. } else
  1303. pos = iwl3945_print_event_log(priv, next_entry - size,
  1304. size, mode,
  1305. pos, buf, bufsz);
  1306. } else {
  1307. if (next_entry < size)
  1308. pos = iwl3945_print_event_log(priv, 0,
  1309. next_entry, mode,
  1310. pos, buf, bufsz);
  1311. else
  1312. pos = iwl3945_print_event_log(priv, next_entry - size,
  1313. size, mode,
  1314. pos, buf, bufsz);
  1315. }
  1316. return pos;
  1317. }
  1318. #define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
  1319. int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1320. char **buf, bool display)
  1321. {
  1322. u32 base; /* SRAM byte address of event log header */
  1323. u32 capacity; /* event log capacity in # entries */
  1324. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1325. u32 num_wraps; /* # times uCode wrapped to top of log */
  1326. u32 next_entry; /* index of next entry to be written by uCode */
  1327. u32 size; /* # entries that we'll print */
  1328. int pos = 0;
  1329. size_t bufsz = 0;
  1330. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1331. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  1332. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1333. return -EINVAL;
  1334. }
  1335. /* event log header */
  1336. capacity = iwl_read_targ_mem(priv, base);
  1337. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1338. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1339. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1340. if (capacity > priv->cfg->max_event_log_size) {
  1341. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1342. capacity, priv->cfg->max_event_log_size);
  1343. capacity = priv->cfg->max_event_log_size;
  1344. }
  1345. if (next_entry > priv->cfg->max_event_log_size) {
  1346. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1347. next_entry, priv->cfg->max_event_log_size);
  1348. next_entry = priv->cfg->max_event_log_size;
  1349. }
  1350. size = num_wraps ? capacity : next_entry;
  1351. /* bail out if nothing in log */
  1352. if (size == 0) {
  1353. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1354. return pos;
  1355. }
  1356. #ifdef CONFIG_IWLWIFI_DEBUG
  1357. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1358. size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
  1359. ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
  1360. #else
  1361. size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
  1362. ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
  1363. #endif
  1364. IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
  1365. size);
  1366. #ifdef CONFIG_IWLWIFI_DEBUG
  1367. if (display) {
  1368. if (full_log)
  1369. bufsz = capacity * 48;
  1370. else
  1371. bufsz = size * 48;
  1372. *buf = kmalloc(bufsz, GFP_KERNEL);
  1373. if (!*buf)
  1374. return -ENOMEM;
  1375. }
  1376. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1377. /* if uCode has wrapped back to top of log,
  1378. * start at the oldest entry,
  1379. * i.e the next one that uCode would fill.
  1380. */
  1381. if (num_wraps)
  1382. pos = iwl3945_print_event_log(priv, next_entry,
  1383. capacity - next_entry, mode,
  1384. pos, buf, bufsz);
  1385. /* (then/else) start at top of log */
  1386. pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
  1387. pos, buf, bufsz);
  1388. } else
  1389. pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
  1390. next_entry, size, mode,
  1391. pos, buf, bufsz);
  1392. #else
  1393. pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
  1394. next_entry, size, mode,
  1395. pos, buf, bufsz);
  1396. #endif
  1397. return pos;
  1398. }
  1399. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  1400. {
  1401. u32 inta, handled = 0;
  1402. u32 inta_fh;
  1403. unsigned long flags;
  1404. #ifdef CONFIG_IWLWIFI_DEBUG
  1405. u32 inta_mask;
  1406. #endif
  1407. spin_lock_irqsave(&priv->lock, flags);
  1408. /* Ack/clear/reset pending uCode interrupts.
  1409. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1410. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  1411. inta = iwl_read32(priv, CSR_INT);
  1412. iwl_write32(priv, CSR_INT, inta);
  1413. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  1414. * Any new interrupts that happen after this, either while we're
  1415. * in this tasklet, or later, will show up in next ISR/tasklet. */
  1416. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1417. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  1418. #ifdef CONFIG_IWLWIFI_DEBUG
  1419. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1420. /* just for debug */
  1421. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1422. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1423. inta, inta_mask, inta_fh);
  1424. }
  1425. #endif
  1426. spin_unlock_irqrestore(&priv->lock, flags);
  1427. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  1428. * atomic, make sure that inta covers all the interrupts that
  1429. * we've discovered, even if FH interrupt came in just after
  1430. * reading CSR_INT. */
  1431. if (inta_fh & CSR39_FH_INT_RX_MASK)
  1432. inta |= CSR_INT_BIT_FH_RX;
  1433. if (inta_fh & CSR39_FH_INT_TX_MASK)
  1434. inta |= CSR_INT_BIT_FH_TX;
  1435. /* Now service all interrupt bits discovered above. */
  1436. if (inta & CSR_INT_BIT_HW_ERR) {
  1437. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1438. /* Tell the device to stop sending interrupts */
  1439. iwl_disable_interrupts(priv);
  1440. priv->isr_stats.hw++;
  1441. iwl_irq_handle_error(priv);
  1442. handled |= CSR_INT_BIT_HW_ERR;
  1443. return;
  1444. }
  1445. #ifdef CONFIG_IWLWIFI_DEBUG
  1446. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1447. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1448. if (inta & CSR_INT_BIT_SCD) {
  1449. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1450. "the frame/frames.\n");
  1451. priv->isr_stats.sch++;
  1452. }
  1453. /* Alive notification via Rx interrupt will do the real work */
  1454. if (inta & CSR_INT_BIT_ALIVE) {
  1455. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1456. priv->isr_stats.alive++;
  1457. }
  1458. }
  1459. #endif
  1460. /* Safely ignore these bits for debug checks below */
  1461. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1462. /* Error detected by uCode */
  1463. if (inta & CSR_INT_BIT_SW_ERR) {
  1464. IWL_ERR(priv, "Microcode SW error detected. "
  1465. "Restarting 0x%X.\n", inta);
  1466. priv->isr_stats.sw++;
  1467. priv->isr_stats.sw_err = inta;
  1468. iwl_irq_handle_error(priv);
  1469. handled |= CSR_INT_BIT_SW_ERR;
  1470. }
  1471. /* uCode wakes up after power-down sleep */
  1472. if (inta & CSR_INT_BIT_WAKEUP) {
  1473. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1474. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1475. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  1476. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  1477. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  1478. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  1479. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  1480. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  1481. priv->isr_stats.wakeup++;
  1482. handled |= CSR_INT_BIT_WAKEUP;
  1483. }
  1484. /* All uCode command responses, including Tx command responses,
  1485. * Rx "responses" (frame-received notification), and other
  1486. * notifications from uCode come through here*/
  1487. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1488. iwl3945_rx_handle(priv);
  1489. priv->isr_stats.rx++;
  1490. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1491. }
  1492. if (inta & CSR_INT_BIT_FH_TX) {
  1493. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1494. priv->isr_stats.tx++;
  1495. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  1496. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  1497. (FH39_SRVC_CHNL), 0x0);
  1498. handled |= CSR_INT_BIT_FH_TX;
  1499. }
  1500. if (inta & ~handled) {
  1501. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1502. priv->isr_stats.unhandled++;
  1503. }
  1504. if (inta & ~priv->inta_mask) {
  1505. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1506. inta & ~priv->inta_mask);
  1507. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1508. }
  1509. /* Re-enable all interrupts */
  1510. /* only Re-enable if disabled by irq */
  1511. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1512. iwl_enable_interrupts(priv);
  1513. #ifdef CONFIG_IWLWIFI_DEBUG
  1514. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1515. inta = iwl_read32(priv, CSR_INT);
  1516. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1517. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1518. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1519. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1520. }
  1521. #endif
  1522. }
  1523. static int iwl3945_get_single_channel_for_scan(struct iwl_priv *priv,
  1524. struct ieee80211_vif *vif,
  1525. enum ieee80211_band band,
  1526. struct iwl3945_scan_channel *scan_ch)
  1527. {
  1528. const struct ieee80211_supported_band *sband;
  1529. u16 passive_dwell = 0;
  1530. u16 active_dwell = 0;
  1531. int added = 0;
  1532. u8 channel = 0;
  1533. sband = iwl_get_hw_mode(priv, band);
  1534. if (!sband) {
  1535. IWL_ERR(priv, "invalid band\n");
  1536. return added;
  1537. }
  1538. active_dwell = iwl_get_active_dwell_time(priv, band, 0);
  1539. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1540. if (passive_dwell <= active_dwell)
  1541. passive_dwell = active_dwell + 1;
  1542. channel = iwl_get_single_channel_number(priv, band);
  1543. if (channel) {
  1544. scan_ch->channel = channel;
  1545. scan_ch->type = 0; /* passive */
  1546. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1547. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1548. /* Set txpower levels to defaults */
  1549. scan_ch->tpc.dsp_atten = 110;
  1550. if (band == IEEE80211_BAND_5GHZ)
  1551. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1552. else
  1553. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1554. added++;
  1555. } else
  1556. IWL_ERR(priv, "no valid channel found\n");
  1557. return added;
  1558. }
  1559. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  1560. enum ieee80211_band band,
  1561. u8 is_active, u8 n_probes,
  1562. struct iwl3945_scan_channel *scan_ch,
  1563. struct ieee80211_vif *vif)
  1564. {
  1565. struct ieee80211_channel *chan;
  1566. const struct ieee80211_supported_band *sband;
  1567. const struct iwl_channel_info *ch_info;
  1568. u16 passive_dwell = 0;
  1569. u16 active_dwell = 0;
  1570. int added, i;
  1571. sband = iwl_get_hw_mode(priv, band);
  1572. if (!sband)
  1573. return 0;
  1574. active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
  1575. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1576. if (passive_dwell <= active_dwell)
  1577. passive_dwell = active_dwell + 1;
  1578. for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
  1579. chan = priv->scan_request->channels[i];
  1580. if (chan->band != band)
  1581. continue;
  1582. scan_ch->channel = chan->hw_value;
  1583. ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
  1584. if (!is_channel_valid(ch_info)) {
  1585. IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
  1586. scan_ch->channel);
  1587. continue;
  1588. }
  1589. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1590. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1591. /* If passive , set up for auto-switch
  1592. * and use long active_dwell time.
  1593. */
  1594. if (!is_active || is_channel_passive(ch_info) ||
  1595. (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  1596. scan_ch->type = 0; /* passive */
  1597. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  1598. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  1599. } else {
  1600. scan_ch->type = 1; /* active */
  1601. }
  1602. /* Set direct probe bits. These may be used both for active
  1603. * scan channels (probes gets sent right away),
  1604. * or for passive channels (probes get se sent only after
  1605. * hearing clear Rx packet).*/
  1606. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  1607. if (n_probes)
  1608. scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
  1609. } else {
  1610. /* uCode v1 does not allow setting direct probe bits on
  1611. * passive channel. */
  1612. if ((scan_ch->type & 1) && n_probes)
  1613. scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
  1614. }
  1615. /* Set txpower levels to defaults */
  1616. scan_ch->tpc.dsp_atten = 110;
  1617. /* scan_pwr_info->tpc.dsp_atten; */
  1618. /*scan_pwr_info->tpc.tx_gain; */
  1619. if (band == IEEE80211_BAND_5GHZ)
  1620. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1621. else {
  1622. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1623. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  1624. * power level:
  1625. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  1626. */
  1627. }
  1628. IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
  1629. scan_ch->channel,
  1630. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  1631. (scan_ch->type & 1) ?
  1632. active_dwell : passive_dwell);
  1633. scan_ch++;
  1634. added++;
  1635. }
  1636. IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
  1637. return added;
  1638. }
  1639. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  1640. struct ieee80211_rate *rates)
  1641. {
  1642. int i;
  1643. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  1644. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  1645. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  1646. rates[i].hw_value_short = i;
  1647. rates[i].flags = 0;
  1648. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  1649. /*
  1650. * If CCK != 1M then set short preamble rate flag.
  1651. */
  1652. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  1653. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  1654. }
  1655. }
  1656. }
  1657. /******************************************************************************
  1658. *
  1659. * uCode download functions
  1660. *
  1661. ******************************************************************************/
  1662. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  1663. {
  1664. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1665. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1666. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1667. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1668. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1669. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1670. }
  1671. /**
  1672. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  1673. * looking at all data.
  1674. */
  1675. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  1676. {
  1677. u32 val;
  1678. u32 save_len = len;
  1679. int rc = 0;
  1680. u32 errcnt;
  1681. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1682. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1683. IWL39_RTC_INST_LOWER_BOUND);
  1684. errcnt = 0;
  1685. for (; len > 0; len -= sizeof(u32), image++) {
  1686. /* read data comes through single port, auto-incr addr */
  1687. /* NOTE: Use the debugless read so we don't flood kernel log
  1688. * if IWL_DL_IO is set */
  1689. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1690. if (val != le32_to_cpu(*image)) {
  1691. IWL_ERR(priv, "uCode INST section is invalid at "
  1692. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1693. save_len - len, val, le32_to_cpu(*image));
  1694. rc = -EIO;
  1695. errcnt++;
  1696. if (errcnt >= 20)
  1697. break;
  1698. }
  1699. }
  1700. if (!errcnt)
  1701. IWL_DEBUG_INFO(priv,
  1702. "ucode image in INSTRUCTION memory is good\n");
  1703. return rc;
  1704. }
  1705. /**
  1706. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1707. * using sample data 100 bytes apart. If these sample points are good,
  1708. * it's a pretty good bet that everything between them is good, too.
  1709. */
  1710. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1711. {
  1712. u32 val;
  1713. int rc = 0;
  1714. u32 errcnt = 0;
  1715. u32 i;
  1716. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1717. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1718. /* read data comes through single port, auto-incr addr */
  1719. /* NOTE: Use the debugless read so we don't flood kernel log
  1720. * if IWL_DL_IO is set */
  1721. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1722. i + IWL39_RTC_INST_LOWER_BOUND);
  1723. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1724. if (val != le32_to_cpu(*image)) {
  1725. #if 0 /* Enable this if you want to see details */
  1726. IWL_ERR(priv, "uCode INST section is invalid at "
  1727. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1728. i, val, *image);
  1729. #endif
  1730. rc = -EIO;
  1731. errcnt++;
  1732. if (errcnt >= 3)
  1733. break;
  1734. }
  1735. }
  1736. return rc;
  1737. }
  1738. /**
  1739. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  1740. * and verify its contents
  1741. */
  1742. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  1743. {
  1744. __le32 *image;
  1745. u32 len;
  1746. int rc = 0;
  1747. /* Try bootstrap */
  1748. image = (__le32 *)priv->ucode_boot.v_addr;
  1749. len = priv->ucode_boot.len;
  1750. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1751. if (rc == 0) {
  1752. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1753. return 0;
  1754. }
  1755. /* Try initialize */
  1756. image = (__le32 *)priv->ucode_init.v_addr;
  1757. len = priv->ucode_init.len;
  1758. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1759. if (rc == 0) {
  1760. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1761. return 0;
  1762. }
  1763. /* Try runtime/protocol */
  1764. image = (__le32 *)priv->ucode_code.v_addr;
  1765. len = priv->ucode_code.len;
  1766. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1767. if (rc == 0) {
  1768. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1769. return 0;
  1770. }
  1771. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1772. /* Since nothing seems to match, show first several data entries in
  1773. * instruction SRAM, so maybe visual inspection will give a clue.
  1774. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1775. image = (__le32 *)priv->ucode_boot.v_addr;
  1776. len = priv->ucode_boot.len;
  1777. rc = iwl3945_verify_inst_full(priv, image, len);
  1778. return rc;
  1779. }
  1780. static void iwl3945_nic_start(struct iwl_priv *priv)
  1781. {
  1782. /* Remove all resets to allow NIC to operate */
  1783. iwl_write32(priv, CSR_RESET, 0);
  1784. }
  1785. #define IWL3945_UCODE_GET(item) \
  1786. static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode)\
  1787. { \
  1788. return le32_to_cpu(ucode->u.v1.item); \
  1789. }
  1790. static u32 iwl3945_ucode_get_header_size(u32 api_ver)
  1791. {
  1792. return 24;
  1793. }
  1794. static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode)
  1795. {
  1796. return (u8 *) ucode->u.v1.data;
  1797. }
  1798. IWL3945_UCODE_GET(inst_size);
  1799. IWL3945_UCODE_GET(data_size);
  1800. IWL3945_UCODE_GET(init_size);
  1801. IWL3945_UCODE_GET(init_data_size);
  1802. IWL3945_UCODE_GET(boot_size);
  1803. /**
  1804. * iwl3945_read_ucode - Read uCode images from disk file.
  1805. *
  1806. * Copy into buffers for card to fetch via bus-mastering
  1807. */
  1808. static int iwl3945_read_ucode(struct iwl_priv *priv)
  1809. {
  1810. const struct iwl_ucode_header *ucode;
  1811. int ret = -EINVAL, index;
  1812. const struct firmware *ucode_raw;
  1813. /* firmware file name contains uCode/driver compatibility version */
  1814. const char *name_pre = priv->cfg->fw_name_pre;
  1815. const unsigned int api_max = priv->cfg->ucode_api_max;
  1816. const unsigned int api_min = priv->cfg->ucode_api_min;
  1817. char buf[25];
  1818. u8 *src;
  1819. size_t len;
  1820. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  1821. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1822. * request_firmware() is synchronous, file is in memory on return. */
  1823. for (index = api_max; index >= api_min; index--) {
  1824. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  1825. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1826. if (ret < 0) {
  1827. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1828. buf, ret);
  1829. if (ret == -ENOENT)
  1830. continue;
  1831. else
  1832. goto error;
  1833. } else {
  1834. if (index < api_max)
  1835. IWL_ERR(priv, "Loaded firmware %s, "
  1836. "which is deprecated. "
  1837. " Please use API v%u instead.\n",
  1838. buf, api_max);
  1839. IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
  1840. "(%zd bytes) from disk\n",
  1841. buf, ucode_raw->size);
  1842. break;
  1843. }
  1844. }
  1845. if (ret < 0)
  1846. goto error;
  1847. /* Make sure that we got at least our header! */
  1848. if (ucode_raw->size < iwl3945_ucode_get_header_size(1)) {
  1849. IWL_ERR(priv, "File size way too small!\n");
  1850. ret = -EINVAL;
  1851. goto err_release;
  1852. }
  1853. /* Data from ucode file: header followed by uCode images */
  1854. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1855. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1856. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1857. inst_size = iwl3945_ucode_get_inst_size(ucode);
  1858. data_size = iwl3945_ucode_get_data_size(ucode);
  1859. init_size = iwl3945_ucode_get_init_size(ucode);
  1860. init_data_size = iwl3945_ucode_get_init_data_size(ucode);
  1861. boot_size = iwl3945_ucode_get_boot_size(ucode);
  1862. src = iwl3945_ucode_get_data(ucode);
  1863. /* api_ver should match the api version forming part of the
  1864. * firmware filename ... but we don't check for that and only rely
  1865. * on the API version read from firmware header from here on forward */
  1866. if (api_ver < api_min || api_ver > api_max) {
  1867. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1868. "Driver supports v%u, firmware is v%u.\n",
  1869. api_max, api_ver);
  1870. priv->ucode_ver = 0;
  1871. ret = -EINVAL;
  1872. goto err_release;
  1873. }
  1874. if (api_ver != api_max)
  1875. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  1876. "got %u. New firmware can be obtained "
  1877. "from http://www.intellinuxwireless.org.\n",
  1878. api_max, api_ver);
  1879. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1880. IWL_UCODE_MAJOR(priv->ucode_ver),
  1881. IWL_UCODE_MINOR(priv->ucode_ver),
  1882. IWL_UCODE_API(priv->ucode_ver),
  1883. IWL_UCODE_SERIAL(priv->ucode_ver));
  1884. snprintf(priv->hw->wiphy->fw_version,
  1885. sizeof(priv->hw->wiphy->fw_version),
  1886. "%u.%u.%u.%u",
  1887. IWL_UCODE_MAJOR(priv->ucode_ver),
  1888. IWL_UCODE_MINOR(priv->ucode_ver),
  1889. IWL_UCODE_API(priv->ucode_ver),
  1890. IWL_UCODE_SERIAL(priv->ucode_ver));
  1891. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1892. priv->ucode_ver);
  1893. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1894. inst_size);
  1895. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1896. data_size);
  1897. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1898. init_size);
  1899. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1900. init_data_size);
  1901. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1902. boot_size);
  1903. /* Verify size of file vs. image size info in file's header */
  1904. if (ucode_raw->size != iwl3945_ucode_get_header_size(api_ver) +
  1905. inst_size + data_size + init_size +
  1906. init_data_size + boot_size) {
  1907. IWL_DEBUG_INFO(priv,
  1908. "uCode file size %zd does not match expected size\n",
  1909. ucode_raw->size);
  1910. ret = -EINVAL;
  1911. goto err_release;
  1912. }
  1913. /* Verify that uCode images will fit in card's SRAM */
  1914. if (inst_size > IWL39_MAX_INST_SIZE) {
  1915. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1916. inst_size);
  1917. ret = -EINVAL;
  1918. goto err_release;
  1919. }
  1920. if (data_size > IWL39_MAX_DATA_SIZE) {
  1921. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1922. data_size);
  1923. ret = -EINVAL;
  1924. goto err_release;
  1925. }
  1926. if (init_size > IWL39_MAX_INST_SIZE) {
  1927. IWL_DEBUG_INFO(priv,
  1928. "uCode init instr len %d too large to fit in\n",
  1929. init_size);
  1930. ret = -EINVAL;
  1931. goto err_release;
  1932. }
  1933. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  1934. IWL_DEBUG_INFO(priv,
  1935. "uCode init data len %d too large to fit in\n",
  1936. init_data_size);
  1937. ret = -EINVAL;
  1938. goto err_release;
  1939. }
  1940. if (boot_size > IWL39_MAX_BSM_SIZE) {
  1941. IWL_DEBUG_INFO(priv,
  1942. "uCode boot instr len %d too large to fit in\n",
  1943. boot_size);
  1944. ret = -EINVAL;
  1945. goto err_release;
  1946. }
  1947. /* Allocate ucode buffers for card's bus-master loading ... */
  1948. /* Runtime instructions and 2 copies of data:
  1949. * 1) unmodified from disk
  1950. * 2) backup cache for save/restore during power-downs */
  1951. priv->ucode_code.len = inst_size;
  1952. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1953. priv->ucode_data.len = data_size;
  1954. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1955. priv->ucode_data_backup.len = data_size;
  1956. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1957. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1958. !priv->ucode_data_backup.v_addr)
  1959. goto err_pci_alloc;
  1960. /* Initialization instructions and data */
  1961. if (init_size && init_data_size) {
  1962. priv->ucode_init.len = init_size;
  1963. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1964. priv->ucode_init_data.len = init_data_size;
  1965. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1966. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1967. goto err_pci_alloc;
  1968. }
  1969. /* Bootstrap (instructions only, no data) */
  1970. if (boot_size) {
  1971. priv->ucode_boot.len = boot_size;
  1972. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1973. if (!priv->ucode_boot.v_addr)
  1974. goto err_pci_alloc;
  1975. }
  1976. /* Copy images into buffers for card's bus-master reads ... */
  1977. /* Runtime instructions (first block of data in file) */
  1978. len = inst_size;
  1979. IWL_DEBUG_INFO(priv,
  1980. "Copying (but not loading) uCode instr len %zd\n", len);
  1981. memcpy(priv->ucode_code.v_addr, src, len);
  1982. src += len;
  1983. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1984. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1985. /* Runtime data (2nd block)
  1986. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  1987. len = data_size;
  1988. IWL_DEBUG_INFO(priv,
  1989. "Copying (but not loading) uCode data len %zd\n", len);
  1990. memcpy(priv->ucode_data.v_addr, src, len);
  1991. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1992. src += len;
  1993. /* Initialization instructions (3rd block) */
  1994. if (init_size) {
  1995. len = init_size;
  1996. IWL_DEBUG_INFO(priv,
  1997. "Copying (but not loading) init instr len %zd\n", len);
  1998. memcpy(priv->ucode_init.v_addr, src, len);
  1999. src += len;
  2000. }
  2001. /* Initialization data (4th block) */
  2002. if (init_data_size) {
  2003. len = init_data_size;
  2004. IWL_DEBUG_INFO(priv,
  2005. "Copying (but not loading) init data len %zd\n", len);
  2006. memcpy(priv->ucode_init_data.v_addr, src, len);
  2007. src += len;
  2008. }
  2009. /* Bootstrap instructions (5th block) */
  2010. len = boot_size;
  2011. IWL_DEBUG_INFO(priv,
  2012. "Copying (but not loading) boot instr len %zd\n", len);
  2013. memcpy(priv->ucode_boot.v_addr, src, len);
  2014. /* We have our copies now, allow OS release its copies */
  2015. release_firmware(ucode_raw);
  2016. return 0;
  2017. err_pci_alloc:
  2018. IWL_ERR(priv, "failed to allocate pci memory\n");
  2019. ret = -ENOMEM;
  2020. iwl3945_dealloc_ucode_pci(priv);
  2021. err_release:
  2022. release_firmware(ucode_raw);
  2023. error:
  2024. return ret;
  2025. }
  2026. /**
  2027. * iwl3945_set_ucode_ptrs - Set uCode address location
  2028. *
  2029. * Tell initialization uCode where to find runtime uCode.
  2030. *
  2031. * BSM registers initially contain pointers to initialization uCode.
  2032. * We need to replace them to load runtime uCode inst and data,
  2033. * and to save runtime data when powering down.
  2034. */
  2035. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  2036. {
  2037. dma_addr_t pinst;
  2038. dma_addr_t pdata;
  2039. /* bits 31:0 for 3945 */
  2040. pinst = priv->ucode_code.p_addr;
  2041. pdata = priv->ucode_data_backup.p_addr;
  2042. /* Tell bootstrap uCode where to find image to load */
  2043. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  2044. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  2045. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  2046. priv->ucode_data.len);
  2047. /* Inst byte count must be last to set up, bit 31 signals uCode
  2048. * that all new ptr/size info is in place */
  2049. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  2050. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  2051. IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
  2052. return 0;
  2053. }
  2054. /**
  2055. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  2056. *
  2057. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  2058. *
  2059. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  2060. */
  2061. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  2062. {
  2063. /* Check alive response for "valid" sign from uCode */
  2064. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  2065. /* We had an error bringing up the hardware, so take it
  2066. * all the way back down so we can try again */
  2067. IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
  2068. goto restart;
  2069. }
  2070. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  2071. * This is a paranoid check, because we would not have gotten the
  2072. * "initialize" alive if code weren't properly loaded. */
  2073. if (iwl3945_verify_ucode(priv)) {
  2074. /* Runtime instruction load was bad;
  2075. * take it all the way back down so we can try again */
  2076. IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
  2077. goto restart;
  2078. }
  2079. /* Send pointers to protocol/runtime uCode image ... init code will
  2080. * load and launch runtime uCode, which will send us another "Alive"
  2081. * notification. */
  2082. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  2083. if (iwl3945_set_ucode_ptrs(priv)) {
  2084. /* Runtime instruction load won't happen;
  2085. * take it all the way back down so we can try again */
  2086. IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
  2087. goto restart;
  2088. }
  2089. return;
  2090. restart:
  2091. queue_work(priv->workqueue, &priv->restart);
  2092. }
  2093. /**
  2094. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  2095. * from protocol/runtime uCode (initialization uCode's
  2096. * Alive gets handled by iwl3945_init_alive_start()).
  2097. */
  2098. static void iwl3945_alive_start(struct iwl_priv *priv)
  2099. {
  2100. int thermal_spin = 0;
  2101. u32 rfkill;
  2102. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2103. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  2104. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  2105. /* We had an error bringing up the hardware, so take it
  2106. * all the way back down so we can try again */
  2107. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  2108. goto restart;
  2109. }
  2110. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  2111. * This is a paranoid check, because we would not have gotten the
  2112. * "runtime" alive if code weren't properly loaded. */
  2113. if (iwl3945_verify_ucode(priv)) {
  2114. /* Runtime instruction load was bad;
  2115. * take it all the way back down so we can try again */
  2116. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  2117. goto restart;
  2118. }
  2119. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  2120. IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
  2121. if (rfkill & 0x1) {
  2122. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2123. /* if RFKILL is not on, then wait for thermal
  2124. * sensor in adapter to kick in */
  2125. while (iwl3945_hw_get_temperature(priv) == 0) {
  2126. thermal_spin++;
  2127. udelay(10);
  2128. }
  2129. if (thermal_spin)
  2130. IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
  2131. thermal_spin * 10);
  2132. } else
  2133. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2134. /* After the ALIVE response, we can send commands to 3945 uCode */
  2135. set_bit(STATUS_ALIVE, &priv->status);
  2136. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2137. /* Enable timer to monitor the driver queues */
  2138. mod_timer(&priv->monitor_recover,
  2139. jiffies +
  2140. msecs_to_jiffies(priv->cfg->monitor_recover_period));
  2141. }
  2142. if (iwl_is_rfkill(priv))
  2143. return;
  2144. ieee80211_wake_queues(priv->hw);
  2145. priv->active_rate = IWL_RATES_MASK;
  2146. iwl_power_update_mode(priv, true);
  2147. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
  2148. struct iwl3945_rxon_cmd *active_rxon =
  2149. (struct iwl3945_rxon_cmd *)(&ctx->active);
  2150. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2151. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2152. } else {
  2153. /* Initialize our rx_config data */
  2154. iwl_connection_init_rx_config(priv, NULL);
  2155. }
  2156. /* Configure Bluetooth device coexistence support */
  2157. priv->cfg->ops->hcmd->send_bt_config(priv);
  2158. /* Configure the adapter for unassociated operation */
  2159. iwlcore_commit_rxon(priv, ctx);
  2160. iwl3945_reg_txpower_periodic(priv);
  2161. iwl_leds_init(priv);
  2162. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2163. set_bit(STATUS_READY, &priv->status);
  2164. wake_up_interruptible(&priv->wait_command_queue);
  2165. return;
  2166. restart:
  2167. queue_work(priv->workqueue, &priv->restart);
  2168. }
  2169. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  2170. static void __iwl3945_down(struct iwl_priv *priv)
  2171. {
  2172. unsigned long flags;
  2173. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  2174. struct ieee80211_conf *conf = NULL;
  2175. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2176. conf = ieee80211_get_hw_conf(priv->hw);
  2177. if (!exit_pending)
  2178. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2179. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  2180. * to prevent rearm timer */
  2181. if (priv->cfg->ops->lib->recover_from_tx_stall)
  2182. del_timer_sync(&priv->monitor_recover);
  2183. /* Station information will now be cleared in device */
  2184. iwl_clear_ucode_stations(priv, NULL);
  2185. iwl_dealloc_bcast_stations(priv);
  2186. iwl_clear_driver_stations(priv);
  2187. /* Unblock any waiting calls */
  2188. wake_up_interruptible_all(&priv->wait_command_queue);
  2189. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2190. * exiting the module */
  2191. if (!exit_pending)
  2192. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2193. /* stop and reset the on-board processor */
  2194. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2195. /* tell the device to stop sending interrupts */
  2196. spin_lock_irqsave(&priv->lock, flags);
  2197. iwl_disable_interrupts(priv);
  2198. spin_unlock_irqrestore(&priv->lock, flags);
  2199. iwl_synchronize_irq(priv);
  2200. if (priv->mac80211_registered)
  2201. ieee80211_stop_queues(priv->hw);
  2202. /* If we have not previously called iwl3945_init() then
  2203. * clear all bits but the RF Kill bits and return */
  2204. if (!iwl_is_init(priv)) {
  2205. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2206. STATUS_RF_KILL_HW |
  2207. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2208. STATUS_GEO_CONFIGURED |
  2209. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2210. STATUS_EXIT_PENDING;
  2211. goto exit;
  2212. }
  2213. /* ...otherwise clear out all the status bits but the RF Kill
  2214. * bit and continue taking the NIC down. */
  2215. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2216. STATUS_RF_KILL_HW |
  2217. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2218. STATUS_GEO_CONFIGURED |
  2219. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2220. STATUS_FW_ERROR |
  2221. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2222. STATUS_EXIT_PENDING;
  2223. iwl3945_hw_txq_ctx_stop(priv);
  2224. iwl3945_hw_rxq_stop(priv);
  2225. /* Power-down device's busmaster DMA clocks */
  2226. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2227. udelay(5);
  2228. /* Stop the device, and put it in low power state */
  2229. priv->cfg->ops->lib->apm_ops.stop(priv);
  2230. exit:
  2231. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2232. if (priv->ibss_beacon)
  2233. dev_kfree_skb(priv->ibss_beacon);
  2234. priv->ibss_beacon = NULL;
  2235. /* clear out any free frames */
  2236. iwl3945_clear_free_frames(priv);
  2237. }
  2238. static void iwl3945_down(struct iwl_priv *priv)
  2239. {
  2240. mutex_lock(&priv->mutex);
  2241. __iwl3945_down(priv);
  2242. mutex_unlock(&priv->mutex);
  2243. iwl3945_cancel_deferred_work(priv);
  2244. }
  2245. #define MAX_HW_RESTARTS 5
  2246. static int __iwl3945_up(struct iwl_priv *priv)
  2247. {
  2248. int rc, i;
  2249. rc = iwl_alloc_bcast_station(priv, &priv->contexts[IWL_RXON_CTX_BSS],
  2250. false);
  2251. if (rc)
  2252. return rc;
  2253. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2254. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2255. return -EIO;
  2256. }
  2257. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2258. IWL_ERR(priv, "ucode not available for device bring up\n");
  2259. return -EIO;
  2260. }
  2261. /* If platform's RF_KILL switch is NOT set to KILL */
  2262. if (iwl_read32(priv, CSR_GP_CNTRL) &
  2263. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2264. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2265. else {
  2266. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2267. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2268. return -ENODEV;
  2269. }
  2270. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2271. rc = iwl3945_hw_nic_init(priv);
  2272. if (rc) {
  2273. IWL_ERR(priv, "Unable to int nic\n");
  2274. return rc;
  2275. }
  2276. /* make sure rfkill handshake bits are cleared */
  2277. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2278. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2279. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2280. /* clear (again), then enable host interrupts */
  2281. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2282. iwl_enable_interrupts(priv);
  2283. /* really make sure rfkill handshake bits are cleared */
  2284. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2285. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2286. /* Copy original ucode data image from disk into backup cache.
  2287. * This will be used to initialize the on-board processor's
  2288. * data SRAM for a clean start when the runtime program first loads. */
  2289. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2290. priv->ucode_data.len);
  2291. /* We return success when we resume from suspend and rf_kill is on. */
  2292. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  2293. return 0;
  2294. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2295. /* load bootstrap state machine,
  2296. * load bootstrap program into processor's memory,
  2297. * prepare to load the "initialize" uCode */
  2298. rc = priv->cfg->ops->lib->load_ucode(priv);
  2299. if (rc) {
  2300. IWL_ERR(priv,
  2301. "Unable to set up bootstrap uCode: %d\n", rc);
  2302. continue;
  2303. }
  2304. /* start card; "initialize" will load runtime ucode */
  2305. iwl3945_nic_start(priv);
  2306. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2307. return 0;
  2308. }
  2309. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2310. __iwl3945_down(priv);
  2311. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2312. /* tried to restart and config the device for as long as our
  2313. * patience could withstand */
  2314. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2315. return -EIO;
  2316. }
  2317. /*****************************************************************************
  2318. *
  2319. * Workqueue callbacks
  2320. *
  2321. *****************************************************************************/
  2322. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  2323. {
  2324. struct iwl_priv *priv =
  2325. container_of(data, struct iwl_priv, init_alive_start.work);
  2326. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2327. return;
  2328. mutex_lock(&priv->mutex);
  2329. iwl3945_init_alive_start(priv);
  2330. mutex_unlock(&priv->mutex);
  2331. }
  2332. static void iwl3945_bg_alive_start(struct work_struct *data)
  2333. {
  2334. struct iwl_priv *priv =
  2335. container_of(data, struct iwl_priv, alive_start.work);
  2336. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2337. return;
  2338. mutex_lock(&priv->mutex);
  2339. iwl3945_alive_start(priv);
  2340. mutex_unlock(&priv->mutex);
  2341. }
  2342. /*
  2343. * 3945 cannot interrupt driver when hardware rf kill switch toggles;
  2344. * driver must poll CSR_GP_CNTRL_REG register for change. This register
  2345. * *is* readable even when device has been SW_RESET into low power mode
  2346. * (e.g. during RF KILL).
  2347. */
  2348. static void iwl3945_rfkill_poll(struct work_struct *data)
  2349. {
  2350. struct iwl_priv *priv =
  2351. container_of(data, struct iwl_priv, _3945.rfkill_poll.work);
  2352. bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
  2353. bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
  2354. & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
  2355. if (new_rfkill != old_rfkill) {
  2356. if (new_rfkill)
  2357. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2358. else
  2359. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2360. wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
  2361. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  2362. new_rfkill ? "disable radio" : "enable radio");
  2363. }
  2364. /* Keep this running, even if radio now enabled. This will be
  2365. * cancelled in mac_start() if system decides to start again */
  2366. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  2367. round_jiffies_relative(2 * HZ));
  2368. }
  2369. void iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2370. {
  2371. struct iwl_host_cmd cmd = {
  2372. .id = REPLY_SCAN_CMD,
  2373. .len = sizeof(struct iwl3945_scan_cmd),
  2374. .flags = CMD_SIZE_HUGE,
  2375. };
  2376. struct iwl3945_scan_cmd *scan;
  2377. struct ieee80211_conf *conf = NULL;
  2378. u8 n_probes = 0;
  2379. enum ieee80211_band band;
  2380. bool is_active = false;
  2381. conf = ieee80211_get_hw_conf(priv->hw);
  2382. cancel_delayed_work(&priv->scan_check);
  2383. if (!iwl_is_ready(priv)) {
  2384. IWL_WARN(priv, "request scan called when driver not ready.\n");
  2385. goto done;
  2386. }
  2387. /* Make sure the scan wasn't canceled before this queued work
  2388. * was given the chance to run... */
  2389. if (!test_bit(STATUS_SCANNING, &priv->status))
  2390. goto done;
  2391. /* This should never be called or scheduled if there is currently
  2392. * a scan active in the hardware. */
  2393. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  2394. IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
  2395. "Ignoring second request.\n");
  2396. goto done;
  2397. }
  2398. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2399. IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
  2400. goto done;
  2401. }
  2402. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2403. IWL_DEBUG_HC(priv,
  2404. "Scan request while abort pending. Queuing.\n");
  2405. goto done;
  2406. }
  2407. if (iwl_is_rfkill(priv)) {
  2408. IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
  2409. goto done;
  2410. }
  2411. if (!test_bit(STATUS_READY, &priv->status)) {
  2412. IWL_DEBUG_HC(priv,
  2413. "Scan request while uninitialized. Queuing.\n");
  2414. goto done;
  2415. }
  2416. if (!priv->scan_cmd) {
  2417. priv->scan_cmd = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  2418. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  2419. if (!priv->scan_cmd) {
  2420. IWL_DEBUG_SCAN(priv, "Fail to allocate scan memory\n");
  2421. goto done;
  2422. }
  2423. }
  2424. scan = priv->scan_cmd;
  2425. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  2426. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  2427. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  2428. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
  2429. u16 interval = 0;
  2430. u32 extra;
  2431. u32 suspend_time = 100;
  2432. u32 scan_suspend_time = 100;
  2433. unsigned long flags;
  2434. IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
  2435. spin_lock_irqsave(&priv->lock, flags);
  2436. if (priv->is_internal_short_scan)
  2437. interval = 0;
  2438. else
  2439. interval = vif->bss_conf.beacon_int;
  2440. spin_unlock_irqrestore(&priv->lock, flags);
  2441. scan->suspend_time = 0;
  2442. scan->max_out_time = cpu_to_le32(200 * 1024);
  2443. if (!interval)
  2444. interval = suspend_time;
  2445. /*
  2446. * suspend time format:
  2447. * 0-19: beacon interval in usec (time before exec.)
  2448. * 20-23: 0
  2449. * 24-31: number of beacons (suspend between channels)
  2450. */
  2451. extra = (suspend_time / interval) << 24;
  2452. scan_suspend_time = 0xFF0FFFFF &
  2453. (extra | ((suspend_time % interval) * 1024));
  2454. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  2455. IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
  2456. scan_suspend_time, interval);
  2457. }
  2458. if (priv->is_internal_short_scan) {
  2459. IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
  2460. } else if (priv->scan_request->n_ssids) {
  2461. int i, p = 0;
  2462. IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
  2463. for (i = 0; i < priv->scan_request->n_ssids; i++) {
  2464. /* always does wildcard anyway */
  2465. if (!priv->scan_request->ssids[i].ssid_len)
  2466. continue;
  2467. scan->direct_scan[p].id = WLAN_EID_SSID;
  2468. scan->direct_scan[p].len =
  2469. priv->scan_request->ssids[i].ssid_len;
  2470. memcpy(scan->direct_scan[p].ssid,
  2471. priv->scan_request->ssids[i].ssid,
  2472. priv->scan_request->ssids[i].ssid_len);
  2473. n_probes++;
  2474. p++;
  2475. }
  2476. is_active = true;
  2477. } else
  2478. IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
  2479. /* We don't build a direct scan probe request; the uCode will do
  2480. * that based on the direct_mask added to each channel entry */
  2481. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  2482. scan->tx_cmd.sta_id = priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
  2483. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2484. /* flags + rate selection */
  2485. switch (priv->scan_band) {
  2486. case IEEE80211_BAND_2GHZ:
  2487. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  2488. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  2489. scan->good_CRC_th = 0;
  2490. band = IEEE80211_BAND_2GHZ;
  2491. break;
  2492. case IEEE80211_BAND_5GHZ:
  2493. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  2494. /*
  2495. * If active scaning is requested but a certain channel
  2496. * is marked passive, we can do active scanning if we
  2497. * detect transmissions.
  2498. */
  2499. scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
  2500. IWL_GOOD_CRC_TH_DISABLED;
  2501. band = IEEE80211_BAND_5GHZ;
  2502. break;
  2503. default:
  2504. IWL_WARN(priv, "Invalid scan band\n");
  2505. goto done;
  2506. }
  2507. if (!priv->is_internal_short_scan) {
  2508. scan->tx_cmd.len = cpu_to_le16(
  2509. iwl_fill_probe_req(priv,
  2510. (struct ieee80211_mgmt *)scan->data,
  2511. vif->addr,
  2512. priv->scan_request->ie,
  2513. priv->scan_request->ie_len,
  2514. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  2515. } else {
  2516. /* use bcast addr, will not be transmitted but must be valid */
  2517. scan->tx_cmd.len = cpu_to_le16(
  2518. iwl_fill_probe_req(priv,
  2519. (struct ieee80211_mgmt *)scan->data,
  2520. iwl_bcast_addr, NULL, 0,
  2521. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  2522. }
  2523. /* select Rx antennas */
  2524. scan->flags |= iwl3945_get_antenna_flags(priv);
  2525. if (priv->is_internal_short_scan) {
  2526. scan->channel_count =
  2527. iwl3945_get_single_channel_for_scan(priv, vif, band,
  2528. (void *)&scan->data[le16_to_cpu(
  2529. scan->tx_cmd.len)]);
  2530. } else {
  2531. scan->channel_count =
  2532. iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
  2533. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)], vif);
  2534. }
  2535. if (scan->channel_count == 0) {
  2536. IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
  2537. goto done;
  2538. }
  2539. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  2540. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  2541. cmd.data = scan;
  2542. scan->len = cpu_to_le16(cmd.len);
  2543. set_bit(STATUS_SCAN_HW, &priv->status);
  2544. if (iwl_send_cmd_sync(priv, &cmd))
  2545. goto done;
  2546. queue_delayed_work(priv->workqueue, &priv->scan_check,
  2547. IWL_SCAN_CHECK_WATCHDOG);
  2548. return;
  2549. done:
  2550. /* can not perform scan make sure we clear scanning
  2551. * bits from status so next scan request can be performed.
  2552. * if we dont clear scanning status bit here all next scan
  2553. * will fail
  2554. */
  2555. clear_bit(STATUS_SCAN_HW, &priv->status);
  2556. clear_bit(STATUS_SCANNING, &priv->status);
  2557. /* inform mac80211 scan aborted */
  2558. queue_work(priv->workqueue, &priv->scan_completed);
  2559. }
  2560. static void iwl3945_bg_restart(struct work_struct *data)
  2561. {
  2562. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2563. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2564. return;
  2565. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2566. mutex_lock(&priv->mutex);
  2567. priv->vif = NULL;
  2568. priv->is_open = 0;
  2569. mutex_unlock(&priv->mutex);
  2570. iwl3945_down(priv);
  2571. ieee80211_restart_hw(priv->hw);
  2572. } else {
  2573. iwl3945_down(priv);
  2574. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2575. return;
  2576. mutex_lock(&priv->mutex);
  2577. __iwl3945_up(priv);
  2578. mutex_unlock(&priv->mutex);
  2579. }
  2580. }
  2581. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  2582. {
  2583. struct iwl_priv *priv =
  2584. container_of(data, struct iwl_priv, rx_replenish);
  2585. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2586. return;
  2587. mutex_lock(&priv->mutex);
  2588. iwl3945_rx_replenish(priv);
  2589. mutex_unlock(&priv->mutex);
  2590. }
  2591. void iwl3945_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2592. {
  2593. int rc = 0;
  2594. struct ieee80211_conf *conf = NULL;
  2595. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2596. if (!vif || !priv->is_open)
  2597. return;
  2598. if (vif->type == NL80211_IFTYPE_AP) {
  2599. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2600. return;
  2601. }
  2602. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2603. vif->bss_conf.aid, ctx->active.bssid_addr);
  2604. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2605. return;
  2606. iwl_scan_cancel_timeout(priv, 200);
  2607. conf = ieee80211_get_hw_conf(priv->hw);
  2608. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2609. iwlcore_commit_rxon(priv, ctx);
  2610. rc = iwl_send_rxon_timing(priv, vif);
  2611. if (rc)
  2612. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2613. "Attempting to continue.\n");
  2614. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2615. ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
  2616. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2617. vif->bss_conf.aid, vif->bss_conf.beacon_int);
  2618. if (vif->bss_conf.use_short_preamble)
  2619. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2620. else
  2621. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2622. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2623. if (vif->bss_conf.use_short_slot)
  2624. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2625. else
  2626. ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2627. }
  2628. iwlcore_commit_rxon(priv, ctx);
  2629. switch (vif->type) {
  2630. case NL80211_IFTYPE_STATION:
  2631. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  2632. break;
  2633. case NL80211_IFTYPE_ADHOC:
  2634. iwl3945_send_beacon_cmd(priv);
  2635. break;
  2636. default:
  2637. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2638. __func__, vif->type);
  2639. break;
  2640. }
  2641. }
  2642. /*****************************************************************************
  2643. *
  2644. * mac80211 entry point functions
  2645. *
  2646. *****************************************************************************/
  2647. #define UCODE_READY_TIMEOUT (2 * HZ)
  2648. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  2649. {
  2650. struct iwl_priv *priv = hw->priv;
  2651. int ret;
  2652. IWL_DEBUG_MAC80211(priv, "enter\n");
  2653. /* we should be verifying the device is ready to be opened */
  2654. mutex_lock(&priv->mutex);
  2655. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2656. * ucode filename and max sizes are card-specific. */
  2657. if (!priv->ucode_code.len) {
  2658. ret = iwl3945_read_ucode(priv);
  2659. if (ret) {
  2660. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2661. mutex_unlock(&priv->mutex);
  2662. goto out_release_irq;
  2663. }
  2664. }
  2665. ret = __iwl3945_up(priv);
  2666. mutex_unlock(&priv->mutex);
  2667. if (ret)
  2668. goto out_release_irq;
  2669. IWL_DEBUG_INFO(priv, "Start UP work.\n");
  2670. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  2671. * mac80211 will not be run successfully. */
  2672. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2673. test_bit(STATUS_READY, &priv->status),
  2674. UCODE_READY_TIMEOUT);
  2675. if (!ret) {
  2676. if (!test_bit(STATUS_READY, &priv->status)) {
  2677. IWL_ERR(priv,
  2678. "Wait for START_ALIVE timeout after %dms.\n",
  2679. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2680. ret = -ETIMEDOUT;
  2681. goto out_release_irq;
  2682. }
  2683. }
  2684. /* ucode is running and will send rfkill notifications,
  2685. * no need to poll the killswitch state anymore */
  2686. cancel_delayed_work(&priv->_3945.rfkill_poll);
  2687. iwl_led_start(priv);
  2688. priv->is_open = 1;
  2689. IWL_DEBUG_MAC80211(priv, "leave\n");
  2690. return 0;
  2691. out_release_irq:
  2692. priv->is_open = 0;
  2693. IWL_DEBUG_MAC80211(priv, "leave - failed\n");
  2694. return ret;
  2695. }
  2696. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  2697. {
  2698. struct iwl_priv *priv = hw->priv;
  2699. IWL_DEBUG_MAC80211(priv, "enter\n");
  2700. if (!priv->is_open) {
  2701. IWL_DEBUG_MAC80211(priv, "leave - skip\n");
  2702. return;
  2703. }
  2704. priv->is_open = 0;
  2705. if (iwl_is_ready_rf(priv)) {
  2706. /* stop mac, cancel any scan request and clear
  2707. * RXON_FILTER_ASSOC_MSK BIT
  2708. */
  2709. mutex_lock(&priv->mutex);
  2710. iwl_scan_cancel_timeout(priv, 100);
  2711. mutex_unlock(&priv->mutex);
  2712. }
  2713. iwl3945_down(priv);
  2714. flush_workqueue(priv->workqueue);
  2715. /* start polling the killswitch state again */
  2716. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  2717. round_jiffies_relative(2 * HZ));
  2718. IWL_DEBUG_MAC80211(priv, "leave\n");
  2719. }
  2720. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2721. {
  2722. struct iwl_priv *priv = hw->priv;
  2723. IWL_DEBUG_MAC80211(priv, "enter\n");
  2724. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2725. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2726. if (iwl3945_tx_skb(priv, skb))
  2727. dev_kfree_skb_any(skb);
  2728. IWL_DEBUG_MAC80211(priv, "leave\n");
  2729. return NETDEV_TX_OK;
  2730. }
  2731. void iwl3945_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2732. {
  2733. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2734. int rc = 0;
  2735. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2736. return;
  2737. /* The following should be done only at AP bring up */
  2738. if (!(iwl_is_associated(priv, IWL_RXON_CTX_BSS))) {
  2739. /* RXON - unassoc (to set timing command) */
  2740. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2741. iwlcore_commit_rxon(priv, ctx);
  2742. /* RXON Timing */
  2743. rc = iwl_send_rxon_timing(priv, vif);
  2744. if (rc)
  2745. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2746. "Attempting to continue.\n");
  2747. ctx->staging.assoc_id = 0;
  2748. if (vif->bss_conf.use_short_preamble)
  2749. ctx->staging.flags |=
  2750. RXON_FLG_SHORT_PREAMBLE_MSK;
  2751. else
  2752. ctx->staging.flags &=
  2753. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2754. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2755. if (vif->bss_conf.use_short_slot)
  2756. ctx->staging.flags |=
  2757. RXON_FLG_SHORT_SLOT_MSK;
  2758. else
  2759. ctx->staging.flags &=
  2760. ~RXON_FLG_SHORT_SLOT_MSK;
  2761. }
  2762. /* restore RXON assoc */
  2763. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2764. iwlcore_commit_rxon(priv, ctx);
  2765. }
  2766. iwl3945_send_beacon_cmd(priv);
  2767. /* FIXME - we need to add code here to detect a totally new
  2768. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2769. * clear sta table, add BCAST sta... */
  2770. }
  2771. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2772. struct ieee80211_vif *vif,
  2773. struct ieee80211_sta *sta,
  2774. struct ieee80211_key_conf *key)
  2775. {
  2776. struct iwl_priv *priv = hw->priv;
  2777. int ret = 0;
  2778. u8 sta_id = IWL_INVALID_STATION;
  2779. u8 static_key;
  2780. IWL_DEBUG_MAC80211(priv, "enter\n");
  2781. if (iwl3945_mod_params.sw_crypto) {
  2782. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2783. return -EOPNOTSUPP;
  2784. }
  2785. static_key = !iwl_is_associated(priv, IWL_RXON_CTX_BSS);
  2786. if (!static_key) {
  2787. sta_id = iwl_sta_id_or_broadcast(
  2788. priv, &priv->contexts[IWL_RXON_CTX_BSS], sta);
  2789. if (sta_id == IWL_INVALID_STATION)
  2790. return -EINVAL;
  2791. }
  2792. mutex_lock(&priv->mutex);
  2793. iwl_scan_cancel_timeout(priv, 100);
  2794. switch (cmd) {
  2795. case SET_KEY:
  2796. if (static_key)
  2797. ret = iwl3945_set_static_key(priv, key);
  2798. else
  2799. ret = iwl3945_set_dynamic_key(priv, key, sta_id);
  2800. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2801. break;
  2802. case DISABLE_KEY:
  2803. if (static_key)
  2804. ret = iwl3945_remove_static_key(priv);
  2805. else
  2806. ret = iwl3945_clear_sta_key_info(priv, sta_id);
  2807. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2808. break;
  2809. default:
  2810. ret = -EINVAL;
  2811. }
  2812. mutex_unlock(&priv->mutex);
  2813. IWL_DEBUG_MAC80211(priv, "leave\n");
  2814. return ret;
  2815. }
  2816. static int iwl3945_mac_sta_add(struct ieee80211_hw *hw,
  2817. struct ieee80211_vif *vif,
  2818. struct ieee80211_sta *sta)
  2819. {
  2820. struct iwl_priv *priv = hw->priv;
  2821. struct iwl3945_sta_priv *sta_priv = (void *)sta->drv_priv;
  2822. int ret;
  2823. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2824. u8 sta_id;
  2825. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2826. sta->addr);
  2827. mutex_lock(&priv->mutex);
  2828. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2829. sta->addr);
  2830. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2831. ret = iwl_add_station_common(priv, &priv->contexts[IWL_RXON_CTX_BSS],
  2832. sta->addr, is_ap, &sta->ht_cap, &sta_id);
  2833. if (ret) {
  2834. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2835. sta->addr, ret);
  2836. /* Should we return success if return code is EEXIST ? */
  2837. mutex_unlock(&priv->mutex);
  2838. return ret;
  2839. }
  2840. sta_priv->common.sta_id = sta_id;
  2841. /* Initialize rate scaling */
  2842. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2843. sta->addr);
  2844. iwl3945_rs_rate_init(priv, sta, sta_id);
  2845. mutex_unlock(&priv->mutex);
  2846. return 0;
  2847. }
  2848. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  2849. unsigned int changed_flags,
  2850. unsigned int *total_flags,
  2851. u64 multicast)
  2852. {
  2853. struct iwl_priv *priv = hw->priv;
  2854. __le32 filter_or = 0, filter_nand = 0;
  2855. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2856. #define CHK(test, flag) do { \
  2857. if (*total_flags & (test)) \
  2858. filter_or |= (flag); \
  2859. else \
  2860. filter_nand |= (flag); \
  2861. } while (0)
  2862. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  2863. changed_flags, *total_flags);
  2864. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2865. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
  2866. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2867. #undef CHK
  2868. mutex_lock(&priv->mutex);
  2869. ctx->staging.filter_flags &= ~filter_nand;
  2870. ctx->staging.filter_flags |= filter_or;
  2871. /*
  2872. * Committing directly here breaks for some reason,
  2873. * but we'll eventually commit the filter flags
  2874. * change anyway.
  2875. */
  2876. mutex_unlock(&priv->mutex);
  2877. /*
  2878. * Receiving all multicast frames is always enabled by the
  2879. * default flags setup in iwl_connection_init_rx_config()
  2880. * since we currently do not support programming multicast
  2881. * filters into the device.
  2882. */
  2883. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2884. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2885. }
  2886. /*****************************************************************************
  2887. *
  2888. * sysfs attributes
  2889. *
  2890. *****************************************************************************/
  2891. #ifdef CONFIG_IWLWIFI_DEBUG
  2892. /*
  2893. * The following adds a new attribute to the sysfs representation
  2894. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  2895. * used for controlling the debug level.
  2896. *
  2897. * See the level definitions in iwl for details.
  2898. *
  2899. * The debug_level being managed using sysfs below is a per device debug
  2900. * level that is used instead of the global debug level if it (the per
  2901. * device debug level) is set.
  2902. */
  2903. static ssize_t show_debug_level(struct device *d,
  2904. struct device_attribute *attr, char *buf)
  2905. {
  2906. struct iwl_priv *priv = dev_get_drvdata(d);
  2907. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2908. }
  2909. static ssize_t store_debug_level(struct device *d,
  2910. struct device_attribute *attr,
  2911. const char *buf, size_t count)
  2912. {
  2913. struct iwl_priv *priv = dev_get_drvdata(d);
  2914. unsigned long val;
  2915. int ret;
  2916. ret = strict_strtoul(buf, 0, &val);
  2917. if (ret)
  2918. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  2919. else {
  2920. priv->debug_level = val;
  2921. if (iwl_alloc_traffic_mem(priv))
  2922. IWL_ERR(priv,
  2923. "Not enough memory to generate traffic log\n");
  2924. }
  2925. return strnlen(buf, count);
  2926. }
  2927. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2928. show_debug_level, store_debug_level);
  2929. #endif /* CONFIG_IWLWIFI_DEBUG */
  2930. static ssize_t show_temperature(struct device *d,
  2931. struct device_attribute *attr, char *buf)
  2932. {
  2933. struct iwl_priv *priv = dev_get_drvdata(d);
  2934. if (!iwl_is_alive(priv))
  2935. return -EAGAIN;
  2936. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  2937. }
  2938. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2939. static ssize_t show_tx_power(struct device *d,
  2940. struct device_attribute *attr, char *buf)
  2941. {
  2942. struct iwl_priv *priv = dev_get_drvdata(d);
  2943. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2944. }
  2945. static ssize_t store_tx_power(struct device *d,
  2946. struct device_attribute *attr,
  2947. const char *buf, size_t count)
  2948. {
  2949. struct iwl_priv *priv = dev_get_drvdata(d);
  2950. char *p = (char *)buf;
  2951. u32 val;
  2952. val = simple_strtoul(p, &p, 10);
  2953. if (p == buf)
  2954. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  2955. else
  2956. iwl3945_hw_reg_set_txpower(priv, val);
  2957. return count;
  2958. }
  2959. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2960. static ssize_t show_flags(struct device *d,
  2961. struct device_attribute *attr, char *buf)
  2962. {
  2963. struct iwl_priv *priv = dev_get_drvdata(d);
  2964. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2965. return sprintf(buf, "0x%04X\n", ctx->active.flags);
  2966. }
  2967. static ssize_t store_flags(struct device *d,
  2968. struct device_attribute *attr,
  2969. const char *buf, size_t count)
  2970. {
  2971. struct iwl_priv *priv = dev_get_drvdata(d);
  2972. u32 flags = simple_strtoul(buf, NULL, 0);
  2973. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2974. mutex_lock(&priv->mutex);
  2975. if (le32_to_cpu(ctx->staging.flags) != flags) {
  2976. /* Cancel any currently running scans... */
  2977. if (iwl_scan_cancel_timeout(priv, 100))
  2978. IWL_WARN(priv, "Could not cancel scan.\n");
  2979. else {
  2980. IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
  2981. flags);
  2982. ctx->staging.flags = cpu_to_le32(flags);
  2983. iwlcore_commit_rxon(priv, ctx);
  2984. }
  2985. }
  2986. mutex_unlock(&priv->mutex);
  2987. return count;
  2988. }
  2989. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2990. static ssize_t show_filter_flags(struct device *d,
  2991. struct device_attribute *attr, char *buf)
  2992. {
  2993. struct iwl_priv *priv = dev_get_drvdata(d);
  2994. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2995. return sprintf(buf, "0x%04X\n",
  2996. le32_to_cpu(ctx->active.filter_flags));
  2997. }
  2998. static ssize_t store_filter_flags(struct device *d,
  2999. struct device_attribute *attr,
  3000. const char *buf, size_t count)
  3001. {
  3002. struct iwl_priv *priv = dev_get_drvdata(d);
  3003. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  3004. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  3005. mutex_lock(&priv->mutex);
  3006. if (le32_to_cpu(ctx->staging.filter_flags) != filter_flags) {
  3007. /* Cancel any currently running scans... */
  3008. if (iwl_scan_cancel_timeout(priv, 100))
  3009. IWL_WARN(priv, "Could not cancel scan.\n");
  3010. else {
  3011. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  3012. "0x%04X\n", filter_flags);
  3013. ctx->staging.filter_flags =
  3014. cpu_to_le32(filter_flags);
  3015. iwlcore_commit_rxon(priv, ctx);
  3016. }
  3017. }
  3018. mutex_unlock(&priv->mutex);
  3019. return count;
  3020. }
  3021. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  3022. store_filter_flags);
  3023. static ssize_t show_measurement(struct device *d,
  3024. struct device_attribute *attr, char *buf)
  3025. {
  3026. struct iwl_priv *priv = dev_get_drvdata(d);
  3027. struct iwl_spectrum_notification measure_report;
  3028. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  3029. u8 *data = (u8 *)&measure_report;
  3030. unsigned long flags;
  3031. spin_lock_irqsave(&priv->lock, flags);
  3032. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  3033. spin_unlock_irqrestore(&priv->lock, flags);
  3034. return 0;
  3035. }
  3036. memcpy(&measure_report, &priv->measure_report, size);
  3037. priv->measurement_status = 0;
  3038. spin_unlock_irqrestore(&priv->lock, flags);
  3039. while (size && (PAGE_SIZE - len)) {
  3040. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  3041. PAGE_SIZE - len, 1);
  3042. len = strlen(buf);
  3043. if (PAGE_SIZE - len)
  3044. buf[len++] = '\n';
  3045. ofs += 16;
  3046. size -= min(size, 16U);
  3047. }
  3048. return len;
  3049. }
  3050. static ssize_t store_measurement(struct device *d,
  3051. struct device_attribute *attr,
  3052. const char *buf, size_t count)
  3053. {
  3054. struct iwl_priv *priv = dev_get_drvdata(d);
  3055. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  3056. struct ieee80211_measurement_params params = {
  3057. .channel = le16_to_cpu(ctx->active.channel),
  3058. .start_time = cpu_to_le64(priv->_3945.last_tsf),
  3059. .duration = cpu_to_le16(1),
  3060. };
  3061. u8 type = IWL_MEASURE_BASIC;
  3062. u8 buffer[32];
  3063. u8 channel;
  3064. if (count) {
  3065. char *p = buffer;
  3066. strncpy(buffer, buf, min(sizeof(buffer), count));
  3067. channel = simple_strtoul(p, NULL, 0);
  3068. if (channel)
  3069. params.channel = channel;
  3070. p = buffer;
  3071. while (*p && *p != ' ')
  3072. p++;
  3073. if (*p)
  3074. type = simple_strtoul(p + 1, NULL, 0);
  3075. }
  3076. IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
  3077. "channel %d (for '%s')\n", type, params.channel, buf);
  3078. iwl3945_get_measurement(priv, &params, type);
  3079. return count;
  3080. }
  3081. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  3082. show_measurement, store_measurement);
  3083. static ssize_t store_retry_rate(struct device *d,
  3084. struct device_attribute *attr,
  3085. const char *buf, size_t count)
  3086. {
  3087. struct iwl_priv *priv = dev_get_drvdata(d);
  3088. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  3089. if (priv->retry_rate <= 0)
  3090. priv->retry_rate = 1;
  3091. return count;
  3092. }
  3093. static ssize_t show_retry_rate(struct device *d,
  3094. struct device_attribute *attr, char *buf)
  3095. {
  3096. struct iwl_priv *priv = dev_get_drvdata(d);
  3097. return sprintf(buf, "%d", priv->retry_rate);
  3098. }
  3099. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  3100. store_retry_rate);
  3101. static ssize_t show_channels(struct device *d,
  3102. struct device_attribute *attr, char *buf)
  3103. {
  3104. /* all this shit doesn't belong into sysfs anyway */
  3105. return 0;
  3106. }
  3107. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  3108. static ssize_t show_antenna(struct device *d,
  3109. struct device_attribute *attr, char *buf)
  3110. {
  3111. struct iwl_priv *priv = dev_get_drvdata(d);
  3112. if (!iwl_is_alive(priv))
  3113. return -EAGAIN;
  3114. return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
  3115. }
  3116. static ssize_t store_antenna(struct device *d,
  3117. struct device_attribute *attr,
  3118. const char *buf, size_t count)
  3119. {
  3120. struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
  3121. int ant;
  3122. if (count == 0)
  3123. return 0;
  3124. if (sscanf(buf, "%1i", &ant) != 1) {
  3125. IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
  3126. return count;
  3127. }
  3128. if ((ant >= 0) && (ant <= 2)) {
  3129. IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
  3130. iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
  3131. } else
  3132. IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
  3133. return count;
  3134. }
  3135. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  3136. static ssize_t show_status(struct device *d,
  3137. struct device_attribute *attr, char *buf)
  3138. {
  3139. struct iwl_priv *priv = dev_get_drvdata(d);
  3140. if (!iwl_is_alive(priv))
  3141. return -EAGAIN;
  3142. return sprintf(buf, "0x%08x\n", (int)priv->status);
  3143. }
  3144. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  3145. static ssize_t dump_error_log(struct device *d,
  3146. struct device_attribute *attr,
  3147. const char *buf, size_t count)
  3148. {
  3149. struct iwl_priv *priv = dev_get_drvdata(d);
  3150. char *p = (char *)buf;
  3151. if (p[0] == '1')
  3152. iwl3945_dump_nic_error_log(priv);
  3153. return strnlen(buf, count);
  3154. }
  3155. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  3156. /*****************************************************************************
  3157. *
  3158. * driver setup and tear down
  3159. *
  3160. *****************************************************************************/
  3161. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  3162. {
  3163. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  3164. init_waitqueue_head(&priv->wait_command_queue);
  3165. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  3166. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  3167. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  3168. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  3169. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  3170. INIT_DELAYED_WORK(&priv->_3945.rfkill_poll, iwl3945_rfkill_poll);
  3171. iwl_setup_scan_deferred_work(priv);
  3172. iwl3945_hw_setup_deferred_work(priv);
  3173. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  3174. init_timer(&priv->monitor_recover);
  3175. priv->monitor_recover.data = (unsigned long)priv;
  3176. priv->monitor_recover.function =
  3177. priv->cfg->ops->lib->recover_from_tx_stall;
  3178. }
  3179. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3180. iwl3945_irq_tasklet, (unsigned long)priv);
  3181. }
  3182. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  3183. {
  3184. iwl3945_hw_cancel_deferred_work(priv);
  3185. cancel_delayed_work_sync(&priv->init_alive_start);
  3186. cancel_delayed_work(&priv->scan_check);
  3187. cancel_delayed_work(&priv->alive_start);
  3188. cancel_work_sync(&priv->start_internal_scan);
  3189. cancel_work_sync(&priv->beacon_update);
  3190. }
  3191. static struct attribute *iwl3945_sysfs_entries[] = {
  3192. &dev_attr_antenna.attr,
  3193. &dev_attr_channels.attr,
  3194. &dev_attr_dump_errors.attr,
  3195. &dev_attr_flags.attr,
  3196. &dev_attr_filter_flags.attr,
  3197. &dev_attr_measurement.attr,
  3198. &dev_attr_retry_rate.attr,
  3199. &dev_attr_status.attr,
  3200. &dev_attr_temperature.attr,
  3201. &dev_attr_tx_power.attr,
  3202. #ifdef CONFIG_IWLWIFI_DEBUG
  3203. &dev_attr_debug_level.attr,
  3204. #endif
  3205. NULL
  3206. };
  3207. static struct attribute_group iwl3945_attribute_group = {
  3208. .name = NULL, /* put in device directory */
  3209. .attrs = iwl3945_sysfs_entries,
  3210. };
  3211. static struct ieee80211_ops iwl3945_hw_ops = {
  3212. .tx = iwl3945_mac_tx,
  3213. .start = iwl3945_mac_start,
  3214. .stop = iwl3945_mac_stop,
  3215. .add_interface = iwl_mac_add_interface,
  3216. .remove_interface = iwl_mac_remove_interface,
  3217. .config = iwl_mac_config,
  3218. .configure_filter = iwl3945_configure_filter,
  3219. .set_key = iwl3945_mac_set_key,
  3220. .conf_tx = iwl_mac_conf_tx,
  3221. .reset_tsf = iwl_mac_reset_tsf,
  3222. .bss_info_changed = iwl_bss_info_changed,
  3223. .hw_scan = iwl_mac_hw_scan,
  3224. .sta_add = iwl3945_mac_sta_add,
  3225. .sta_remove = iwl_mac_sta_remove,
  3226. .tx_last_beacon = iwl_mac_tx_last_beacon,
  3227. };
  3228. static int iwl3945_init_drv(struct iwl_priv *priv)
  3229. {
  3230. int ret;
  3231. struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  3232. priv->retry_rate = 1;
  3233. priv->ibss_beacon = NULL;
  3234. spin_lock_init(&priv->sta_lock);
  3235. spin_lock_init(&priv->hcmd_lock);
  3236. INIT_LIST_HEAD(&priv->free_frames);
  3237. mutex_init(&priv->mutex);
  3238. mutex_init(&priv->sync_cmd_mutex);
  3239. priv->ieee_channels = NULL;
  3240. priv->ieee_rates = NULL;
  3241. priv->band = IEEE80211_BAND_2GHZ;
  3242. priv->iw_mode = NL80211_IFTYPE_STATION;
  3243. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  3244. priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
  3245. if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
  3246. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3247. eeprom->version);
  3248. ret = -EINVAL;
  3249. goto err;
  3250. }
  3251. ret = iwl_init_channel_map(priv);
  3252. if (ret) {
  3253. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  3254. goto err;
  3255. }
  3256. /* Set up txpower settings in driver for all channels */
  3257. if (iwl3945_txpower_set_from_eeprom(priv)) {
  3258. ret = -EIO;
  3259. goto err_free_channel_map;
  3260. }
  3261. ret = iwlcore_init_geos(priv);
  3262. if (ret) {
  3263. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3264. goto err_free_channel_map;
  3265. }
  3266. iwl3945_init_hw_rates(priv, priv->ieee_rates);
  3267. return 0;
  3268. err_free_channel_map:
  3269. iwl_free_channel_map(priv);
  3270. err:
  3271. return ret;
  3272. }
  3273. #define IWL3945_MAX_PROBE_REQUEST 200
  3274. static int iwl3945_setup_mac(struct iwl_priv *priv)
  3275. {
  3276. int ret;
  3277. struct ieee80211_hw *hw = priv->hw;
  3278. hw->rate_control_algorithm = "iwl-3945-rs";
  3279. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  3280. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  3281. /* Tell mac80211 our characteristics */
  3282. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  3283. IEEE80211_HW_SPECTRUM_MGMT;
  3284. if (!priv->cfg->broken_powersave)
  3285. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  3286. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  3287. hw->wiphy->interface_modes =
  3288. BIT(NL80211_IFTYPE_STATION) |
  3289. BIT(NL80211_IFTYPE_ADHOC);
  3290. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  3291. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  3292. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
  3293. /* we create the 802.11 header and a zero-length SSID element */
  3294. hw->wiphy->max_scan_ie_len = IWL3945_MAX_PROBE_REQUEST - 24 - 2;
  3295. /* Default value; 4 EDCA QOS priorities */
  3296. hw->queues = 4;
  3297. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3298. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3299. &priv->bands[IEEE80211_BAND_2GHZ];
  3300. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3301. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3302. &priv->bands[IEEE80211_BAND_5GHZ];
  3303. ret = ieee80211_register_hw(priv->hw);
  3304. if (ret) {
  3305. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  3306. return ret;
  3307. }
  3308. priv->mac80211_registered = 1;
  3309. return 0;
  3310. }
  3311. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3312. {
  3313. int err = 0, i;
  3314. struct iwl_priv *priv;
  3315. struct ieee80211_hw *hw;
  3316. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3317. struct iwl3945_eeprom *eeprom;
  3318. unsigned long flags;
  3319. /***********************
  3320. * 1. Allocating HW data
  3321. * ********************/
  3322. /* mac80211 allocates memory for this device instance, including
  3323. * space for this driver's private structure */
  3324. hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
  3325. if (hw == NULL) {
  3326. pr_err("Can not allocate network device\n");
  3327. err = -ENOMEM;
  3328. goto out;
  3329. }
  3330. priv = hw->priv;
  3331. SET_IEEE80211_DEV(hw, &pdev->dev);
  3332. priv->cmd_queue = IWL39_CMD_QUEUE_NUM;
  3333. /* 3945 has only one valid context */
  3334. priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
  3335. for (i = 0; i < NUM_IWL_RXON_CTX; i++)
  3336. priv->contexts[i].ctxid = i;
  3337. priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
  3338. priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
  3339. priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
  3340. priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
  3341. /*
  3342. * Disabling hardware scan means that mac80211 will perform scans
  3343. * "the hard way", rather than using device's scan.
  3344. */
  3345. if (iwl3945_mod_params.disable_hw_scan) {
  3346. IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
  3347. iwl3945_hw_ops.hw_scan = NULL;
  3348. }
  3349. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3350. priv->cfg = cfg;
  3351. priv->pci_dev = pdev;
  3352. priv->inta_mask = CSR_INI_SET_MASK;
  3353. if (iwl_alloc_traffic_mem(priv))
  3354. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3355. /***************************
  3356. * 2. Initializing PCI bus
  3357. * *************************/
  3358. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  3359. PCIE_LINK_STATE_CLKPM);
  3360. if (pci_enable_device(pdev)) {
  3361. err = -ENODEV;
  3362. goto out_ieee80211_free_hw;
  3363. }
  3364. pci_set_master(pdev);
  3365. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3366. if (!err)
  3367. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3368. if (err) {
  3369. IWL_WARN(priv, "No suitable DMA available.\n");
  3370. goto out_pci_disable_device;
  3371. }
  3372. pci_set_drvdata(pdev, priv);
  3373. err = pci_request_regions(pdev, DRV_NAME);
  3374. if (err)
  3375. goto out_pci_disable_device;
  3376. /***********************
  3377. * 3. Read REV Register
  3378. * ********************/
  3379. priv->hw_base = pci_iomap(pdev, 0, 0);
  3380. if (!priv->hw_base) {
  3381. err = -ENODEV;
  3382. goto out_pci_release_regions;
  3383. }
  3384. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3385. (unsigned long long) pci_resource_len(pdev, 0));
  3386. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3387. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3388. * PCI Tx retries from interfering with C3 CPU state */
  3389. pci_write_config_byte(pdev, 0x41, 0x00);
  3390. /* these spin locks will be used in apm_ops.init and EEPROM access
  3391. * we should init now
  3392. */
  3393. spin_lock_init(&priv->reg_lock);
  3394. spin_lock_init(&priv->lock);
  3395. /*
  3396. * stop and reset the on-board processor just in case it is in a
  3397. * strange state ... like being left stranded by a primary kernel
  3398. * and this is now the kdump kernel trying to start up
  3399. */
  3400. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3401. /***********************
  3402. * 4. Read EEPROM
  3403. * ********************/
  3404. /* Read the EEPROM */
  3405. err = iwl_eeprom_init(priv);
  3406. if (err) {
  3407. IWL_ERR(priv, "Unable to init EEPROM\n");
  3408. goto out_iounmap;
  3409. }
  3410. /* MAC Address location in EEPROM same for 3945/4965 */
  3411. eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  3412. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", eeprom->mac_address);
  3413. SET_IEEE80211_PERM_ADDR(priv->hw, eeprom->mac_address);
  3414. /***********************
  3415. * 5. Setup HW Constants
  3416. * ********************/
  3417. /* Device-specific setup */
  3418. if (iwl3945_hw_set_hw_params(priv)) {
  3419. IWL_ERR(priv, "failed to set hw settings\n");
  3420. goto out_eeprom_free;
  3421. }
  3422. /***********************
  3423. * 6. Setup priv
  3424. * ********************/
  3425. err = iwl3945_init_drv(priv);
  3426. if (err) {
  3427. IWL_ERR(priv, "initializing driver failed\n");
  3428. goto out_unset_hw_params;
  3429. }
  3430. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  3431. priv->cfg->name);
  3432. /***********************
  3433. * 7. Setup Services
  3434. * ********************/
  3435. spin_lock_irqsave(&priv->lock, flags);
  3436. iwl_disable_interrupts(priv);
  3437. spin_unlock_irqrestore(&priv->lock, flags);
  3438. pci_enable_msi(priv->pci_dev);
  3439. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  3440. IRQF_SHARED, DRV_NAME, priv);
  3441. if (err) {
  3442. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3443. goto out_disable_msi;
  3444. }
  3445. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3446. if (err) {
  3447. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  3448. goto out_release_irq;
  3449. }
  3450. iwl_set_rxon_channel(priv,
  3451. &priv->bands[IEEE80211_BAND_2GHZ].channels[5],
  3452. &priv->contexts[IWL_RXON_CTX_BSS]);
  3453. iwl3945_setup_deferred_work(priv);
  3454. iwl3945_setup_rx_handlers(priv);
  3455. iwl_power_initialize(priv);
  3456. /*********************************
  3457. * 8. Setup and Register mac80211
  3458. * *******************************/
  3459. iwl_enable_interrupts(priv);
  3460. err = iwl3945_setup_mac(priv);
  3461. if (err)
  3462. goto out_remove_sysfs;
  3463. err = iwl_dbgfs_register(priv, DRV_NAME);
  3464. if (err)
  3465. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  3466. /* Start monitoring the killswitch */
  3467. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  3468. 2 * HZ);
  3469. return 0;
  3470. out_remove_sysfs:
  3471. destroy_workqueue(priv->workqueue);
  3472. priv->workqueue = NULL;
  3473. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3474. out_release_irq:
  3475. free_irq(priv->pci_dev->irq, priv);
  3476. out_disable_msi:
  3477. pci_disable_msi(priv->pci_dev);
  3478. iwlcore_free_geos(priv);
  3479. iwl_free_channel_map(priv);
  3480. out_unset_hw_params:
  3481. iwl3945_unset_hw_params(priv);
  3482. out_eeprom_free:
  3483. iwl_eeprom_free(priv);
  3484. out_iounmap:
  3485. pci_iounmap(pdev, priv->hw_base);
  3486. out_pci_release_regions:
  3487. pci_release_regions(pdev);
  3488. out_pci_disable_device:
  3489. pci_set_drvdata(pdev, NULL);
  3490. pci_disable_device(pdev);
  3491. out_ieee80211_free_hw:
  3492. iwl_free_traffic_mem(priv);
  3493. ieee80211_free_hw(priv->hw);
  3494. out:
  3495. return err;
  3496. }
  3497. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  3498. {
  3499. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3500. unsigned long flags;
  3501. if (!priv)
  3502. return;
  3503. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3504. iwl_dbgfs_unregister(priv);
  3505. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3506. if (priv->mac80211_registered) {
  3507. ieee80211_unregister_hw(priv->hw);
  3508. priv->mac80211_registered = 0;
  3509. } else {
  3510. iwl3945_down(priv);
  3511. }
  3512. /*
  3513. * Make sure device is reset to low power before unloading driver.
  3514. * This may be redundant with iwl_down(), but there are paths to
  3515. * run iwl_down() without calling apm_ops.stop(), and there are
  3516. * paths to avoid running iwl_down() at all before leaving driver.
  3517. * This (inexpensive) call *makes sure* device is reset.
  3518. */
  3519. priv->cfg->ops->lib->apm_ops.stop(priv);
  3520. /* make sure we flush any pending irq or
  3521. * tasklet for the driver
  3522. */
  3523. spin_lock_irqsave(&priv->lock, flags);
  3524. iwl_disable_interrupts(priv);
  3525. spin_unlock_irqrestore(&priv->lock, flags);
  3526. iwl_synchronize_irq(priv);
  3527. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3528. cancel_delayed_work_sync(&priv->_3945.rfkill_poll);
  3529. iwl3945_dealloc_ucode_pci(priv);
  3530. if (priv->rxq.bd)
  3531. iwl3945_rx_queue_free(priv, &priv->rxq);
  3532. iwl3945_hw_txq_ctx_free(priv);
  3533. iwl3945_unset_hw_params(priv);
  3534. /*netif_stop_queue(dev); */
  3535. flush_workqueue(priv->workqueue);
  3536. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  3537. * priv->workqueue... so we can't take down the workqueue
  3538. * until now... */
  3539. destroy_workqueue(priv->workqueue);
  3540. priv->workqueue = NULL;
  3541. iwl_free_traffic_mem(priv);
  3542. free_irq(pdev->irq, priv);
  3543. pci_disable_msi(pdev);
  3544. pci_iounmap(pdev, priv->hw_base);
  3545. pci_release_regions(pdev);
  3546. pci_disable_device(pdev);
  3547. pci_set_drvdata(pdev, NULL);
  3548. iwl_free_channel_map(priv);
  3549. iwlcore_free_geos(priv);
  3550. kfree(priv->scan_cmd);
  3551. if (priv->ibss_beacon)
  3552. dev_kfree_skb(priv->ibss_beacon);
  3553. ieee80211_free_hw(priv->hw);
  3554. }
  3555. /*****************************************************************************
  3556. *
  3557. * driver and module entry point
  3558. *
  3559. *****************************************************************************/
  3560. static struct pci_driver iwl3945_driver = {
  3561. .name = DRV_NAME,
  3562. .id_table = iwl3945_hw_card_ids,
  3563. .probe = iwl3945_pci_probe,
  3564. .remove = __devexit_p(iwl3945_pci_remove),
  3565. #ifdef CONFIG_PM
  3566. .suspend = iwl_pci_suspend,
  3567. .resume = iwl_pci_resume,
  3568. #endif
  3569. };
  3570. static int __init iwl3945_init(void)
  3571. {
  3572. int ret;
  3573. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3574. pr_info(DRV_COPYRIGHT "\n");
  3575. ret = iwl3945_rate_control_register();
  3576. if (ret) {
  3577. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3578. return ret;
  3579. }
  3580. ret = pci_register_driver(&iwl3945_driver);
  3581. if (ret) {
  3582. pr_err("Unable to initialize PCI module\n");
  3583. goto error_register;
  3584. }
  3585. return ret;
  3586. error_register:
  3587. iwl3945_rate_control_unregister();
  3588. return ret;
  3589. }
  3590. static void __exit iwl3945_exit(void)
  3591. {
  3592. pci_unregister_driver(&iwl3945_driver);
  3593. iwl3945_rate_control_unregister();
  3594. }
  3595. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  3596. module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
  3597. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  3598. module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
  3599. MODULE_PARM_DESC(swcrypto,
  3600. "using software crypto (default 1 [software])\n");
  3601. #ifdef CONFIG_IWLWIFI_DEBUG
  3602. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3603. MODULE_PARM_DESC(debug, "debug output mask");
  3604. #endif
  3605. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
  3606. int, S_IRUGO);
  3607. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3608. module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO);
  3609. MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
  3610. module_exit(iwl3945_exit);
  3611. module_init(iwl3945_init);