ad1848_lib.c 38 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of AD1848/AD1847/CS4248
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #define SNDRV_MAIN_OBJECT_FILE
  22. #include <sound/driver.h>
  23. #include <linux/delay.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/pm.h>
  27. #include <linux/slab.h>
  28. #include <linux/ioport.h>
  29. #include <sound/core.h>
  30. #include <sound/ad1848.h>
  31. #include <sound/control.h>
  32. #include <sound/pcm_params.h>
  33. #include <asm/io.h>
  34. #include <asm/dma.h>
  35. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  36. MODULE_DESCRIPTION("Routines for control of AD1848/AD1847/CS4248");
  37. MODULE_LICENSE("GPL");
  38. #if 0
  39. #define SNDRV_DEBUG_MCE
  40. #endif
  41. /*
  42. * Some variables
  43. */
  44. static unsigned char freq_bits[14] = {
  45. /* 5510 */ 0x00 | AD1848_XTAL2,
  46. /* 6620 */ 0x0E | AD1848_XTAL2,
  47. /* 8000 */ 0x00 | AD1848_XTAL1,
  48. /* 9600 */ 0x0E | AD1848_XTAL1,
  49. /* 11025 */ 0x02 | AD1848_XTAL2,
  50. /* 16000 */ 0x02 | AD1848_XTAL1,
  51. /* 18900 */ 0x04 | AD1848_XTAL2,
  52. /* 22050 */ 0x06 | AD1848_XTAL2,
  53. /* 27042 */ 0x04 | AD1848_XTAL1,
  54. /* 32000 */ 0x06 | AD1848_XTAL1,
  55. /* 33075 */ 0x0C | AD1848_XTAL2,
  56. /* 37800 */ 0x08 | AD1848_XTAL2,
  57. /* 44100 */ 0x0A | AD1848_XTAL2,
  58. /* 48000 */ 0x0C | AD1848_XTAL1
  59. };
  60. static unsigned int rates[14] = {
  61. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  62. 27042, 32000, 33075, 37800, 44100, 48000
  63. };
  64. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  65. .count = 14,
  66. .list = rates,
  67. .mask = 0,
  68. };
  69. static unsigned char snd_ad1848_original_image[16] =
  70. {
  71. 0x00, /* 00 - lic */
  72. 0x00, /* 01 - ric */
  73. 0x9f, /* 02 - la1ic */
  74. 0x9f, /* 03 - ra1ic */
  75. 0x9f, /* 04 - la2ic */
  76. 0x9f, /* 05 - ra2ic */
  77. 0xbf, /* 06 - loc */
  78. 0xbf, /* 07 - roc */
  79. 0x20, /* 08 - dfr */
  80. AD1848_AUTOCALIB, /* 09 - ic */
  81. 0x00, /* 0a - pc */
  82. 0x00, /* 0b - ti */
  83. 0x00, /* 0c - mi */
  84. 0x00, /* 0d - lbc */
  85. 0x00, /* 0e - dru */
  86. 0x00, /* 0f - drl */
  87. };
  88. /*
  89. * Basic I/O functions
  90. */
  91. void snd_ad1848_out(struct snd_ad1848 *chip,
  92. unsigned char reg,
  93. unsigned char value)
  94. {
  95. int timeout;
  96. for (timeout = 250; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  97. udelay(100);
  98. #ifdef CONFIG_SND_DEBUG
  99. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  100. snd_printk(KERN_WARNING "auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  101. #endif
  102. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  103. outb(chip->image[reg] = value, AD1848P(chip, REG));
  104. mb();
  105. #if 0
  106. printk("codec out - reg 0x%x = 0x%x\n", chip->mce_bit | reg, value);
  107. #endif
  108. }
  109. static void snd_ad1848_dout(struct snd_ad1848 *chip,
  110. unsigned char reg, unsigned char value)
  111. {
  112. int timeout;
  113. for (timeout = 250; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  114. udelay(100);
  115. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  116. outb(value, AD1848P(chip, REG));
  117. mb();
  118. }
  119. static unsigned char snd_ad1848_in(struct snd_ad1848 *chip, unsigned char reg)
  120. {
  121. int timeout;
  122. for (timeout = 250; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  123. udelay(100);
  124. #ifdef CONFIG_SND_DEBUG
  125. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  126. snd_printk(KERN_WARNING "auto calibration time out - reg = 0x%x\n", reg);
  127. #endif
  128. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  129. mb();
  130. return inb(AD1848P(chip, REG));
  131. }
  132. #if 0
  133. static void snd_ad1848_debug(struct snd_ad1848 *chip)
  134. {
  135. printk("AD1848 REGS: INDEX = 0x%02x ", inb(AD1848P(chip, REGSEL)));
  136. printk(" STATUS = 0x%02x\n", inb(AD1848P(chip, STATUS)));
  137. printk(" 0x00: left input = 0x%02x ", snd_ad1848_in(chip, 0x00));
  138. printk(" 0x08: playback format = 0x%02x\n", snd_ad1848_in(chip, 0x08));
  139. printk(" 0x01: right input = 0x%02x ", snd_ad1848_in(chip, 0x01));
  140. printk(" 0x09: iface (CFIG 1) = 0x%02x\n", snd_ad1848_in(chip, 0x09));
  141. printk(" 0x02: AUXA left = 0x%02x ", snd_ad1848_in(chip, 0x02));
  142. printk(" 0x0a: pin control = 0x%02x\n", snd_ad1848_in(chip, 0x0a));
  143. printk(" 0x03: AUXA right = 0x%02x ", snd_ad1848_in(chip, 0x03));
  144. printk(" 0x0b: init & status = 0x%02x\n", snd_ad1848_in(chip, 0x0b));
  145. printk(" 0x04: AUXB left = 0x%02x ", snd_ad1848_in(chip, 0x04));
  146. printk(" 0x0c: revision & mode = 0x%02x\n", snd_ad1848_in(chip, 0x0c));
  147. printk(" 0x05: AUXB right = 0x%02x ", snd_ad1848_in(chip, 0x05));
  148. printk(" 0x0d: loopback = 0x%02x\n", snd_ad1848_in(chip, 0x0d));
  149. printk(" 0x06: left output = 0x%02x ", snd_ad1848_in(chip, 0x06));
  150. printk(" 0x0e: data upr count = 0x%02x\n", snd_ad1848_in(chip, 0x0e));
  151. printk(" 0x07: right output = 0x%02x ", snd_ad1848_in(chip, 0x07));
  152. printk(" 0x0f: data lwr count = 0x%02x\n", snd_ad1848_in(chip, 0x0f));
  153. }
  154. #endif
  155. /*
  156. * AD1848 detection / MCE routines
  157. */
  158. static void snd_ad1848_mce_up(struct snd_ad1848 *chip)
  159. {
  160. unsigned long flags;
  161. int timeout;
  162. for (timeout = 250; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  163. udelay(100);
  164. #ifdef CONFIG_SND_DEBUG
  165. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  166. snd_printk(KERN_WARNING "mce_up - auto calibration time out (0)\n");
  167. #endif
  168. spin_lock_irqsave(&chip->reg_lock, flags);
  169. chip->mce_bit |= AD1848_MCE;
  170. timeout = inb(AD1848P(chip, REGSEL));
  171. if (timeout == 0x80)
  172. snd_printk(KERN_WARNING "mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
  173. if (!(timeout & AD1848_MCE))
  174. outb(chip->mce_bit | (timeout & 0x1f), AD1848P(chip, REGSEL));
  175. spin_unlock_irqrestore(&chip->reg_lock, flags);
  176. }
  177. static void snd_ad1848_mce_down(struct snd_ad1848 *chip)
  178. {
  179. unsigned long flags;
  180. int timeout;
  181. signed long time;
  182. spin_lock_irqsave(&chip->reg_lock, flags);
  183. for (timeout = 5; timeout > 0; timeout--)
  184. inb(AD1848P(chip, REGSEL));
  185. /* end of cleanup sequence */
  186. for (timeout = 12000; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  187. udelay(100);
  188. #if 0
  189. printk("(1) timeout = %i\n", timeout);
  190. #endif
  191. #ifdef CONFIG_SND_DEBUG
  192. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  193. snd_printk(KERN_WARNING "mce_down [0x%lx] - auto calibration time out (0)\n", AD1848P(chip, REGSEL));
  194. #endif
  195. chip->mce_bit &= ~AD1848_MCE;
  196. timeout = inb(AD1848P(chip, REGSEL));
  197. outb(chip->mce_bit | (timeout & 0x1f), AD1848P(chip, REGSEL));
  198. if (timeout == 0x80)
  199. snd_printk(KERN_WARNING "mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  200. if ((timeout & AD1848_MCE) == 0) {
  201. spin_unlock_irqrestore(&chip->reg_lock, flags);
  202. return;
  203. }
  204. /* calibration process */
  205. for (timeout = 500; timeout > 0 && (snd_ad1848_in(chip, AD1848_TEST_INIT) & AD1848_CALIB_IN_PROGRESS) == 0; timeout--);
  206. if ((snd_ad1848_in(chip, AD1848_TEST_INIT) & AD1848_CALIB_IN_PROGRESS) == 0) {
  207. snd_printd("mce_down - auto calibration time out (1)\n");
  208. spin_unlock_irqrestore(&chip->reg_lock, flags);
  209. return;
  210. }
  211. #if 0
  212. printk("(2) timeout = %i, jiffies = %li\n", timeout, jiffies);
  213. #endif
  214. time = HZ / 4;
  215. while (snd_ad1848_in(chip, AD1848_TEST_INIT) & AD1848_CALIB_IN_PROGRESS) {
  216. spin_unlock_irqrestore(&chip->reg_lock, flags);
  217. if (time <= 0) {
  218. snd_printk(KERN_ERR "mce_down - auto calibration time out (2)\n");
  219. return;
  220. }
  221. time = schedule_timeout_interruptible(time);
  222. spin_lock_irqsave(&chip->reg_lock, flags);
  223. }
  224. #if 0
  225. printk("(3) jiffies = %li\n", jiffies);
  226. #endif
  227. time = HZ / 10;
  228. while (inb(AD1848P(chip, REGSEL)) & AD1848_INIT) {
  229. spin_unlock_irqrestore(&chip->reg_lock, flags);
  230. if (time <= 0) {
  231. snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
  232. return;
  233. }
  234. time = schedule_timeout_interruptible(time);
  235. spin_lock_irqsave(&chip->reg_lock, flags);
  236. }
  237. spin_unlock_irqrestore(&chip->reg_lock, flags);
  238. #if 0
  239. printk("(4) jiffies = %li\n", jiffies);
  240. snd_printk("mce_down - exit = 0x%x\n", inb(AD1848P(chip, REGSEL)));
  241. #endif
  242. }
  243. static unsigned int snd_ad1848_get_count(unsigned char format,
  244. unsigned int size)
  245. {
  246. switch (format & 0xe0) {
  247. case AD1848_LINEAR_16:
  248. size >>= 1;
  249. break;
  250. }
  251. if (format & AD1848_STEREO)
  252. size >>= 1;
  253. return size;
  254. }
  255. static int snd_ad1848_trigger(struct snd_ad1848 *chip, unsigned char what,
  256. int channel, int cmd)
  257. {
  258. int result = 0;
  259. #if 0
  260. printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, inb(AD1848P(card, STATUS)));
  261. #endif
  262. spin_lock(&chip->reg_lock);
  263. if (cmd == SNDRV_PCM_TRIGGER_START) {
  264. if (chip->image[AD1848_IFACE_CTRL] & what) {
  265. spin_unlock(&chip->reg_lock);
  266. return 0;
  267. }
  268. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL] |= what);
  269. chip->mode |= AD1848_MODE_RUNNING;
  270. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  271. if (!(chip->image[AD1848_IFACE_CTRL] & what)) {
  272. spin_unlock(&chip->reg_lock);
  273. return 0;
  274. }
  275. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL] &= ~what);
  276. chip->mode &= ~AD1848_MODE_RUNNING;
  277. } else {
  278. result = -EINVAL;
  279. }
  280. spin_unlock(&chip->reg_lock);
  281. return result;
  282. }
  283. /*
  284. * CODEC I/O
  285. */
  286. static unsigned char snd_ad1848_get_rate(unsigned int rate)
  287. {
  288. int i;
  289. for (i = 0; i < 14; i++)
  290. if (rate == rates[i])
  291. return freq_bits[i];
  292. snd_BUG();
  293. return freq_bits[13];
  294. }
  295. static int snd_ad1848_ioctl(struct snd_pcm_substream *substream,
  296. unsigned int cmd, void *arg)
  297. {
  298. return snd_pcm_lib_ioctl(substream, cmd, arg);
  299. }
  300. static unsigned char snd_ad1848_get_format(int format, int channels)
  301. {
  302. unsigned char rformat;
  303. rformat = AD1848_LINEAR_8;
  304. switch (format) {
  305. case SNDRV_PCM_FORMAT_A_LAW: rformat = AD1848_ALAW_8; break;
  306. case SNDRV_PCM_FORMAT_MU_LAW: rformat = AD1848_ULAW_8; break;
  307. case SNDRV_PCM_FORMAT_S16_LE: rformat = AD1848_LINEAR_16; break;
  308. }
  309. if (channels > 1)
  310. rformat |= AD1848_STEREO;
  311. #if 0
  312. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  313. #endif
  314. return rformat;
  315. }
  316. static void snd_ad1848_calibrate_mute(struct snd_ad1848 *chip, int mute)
  317. {
  318. unsigned long flags;
  319. mute = mute ? 1 : 0;
  320. spin_lock_irqsave(&chip->reg_lock, flags);
  321. if (chip->calibrate_mute == mute) {
  322. spin_unlock_irqrestore(&chip->reg_lock, flags);
  323. return;
  324. }
  325. if (!mute) {
  326. snd_ad1848_dout(chip, AD1848_LEFT_INPUT, chip->image[AD1848_LEFT_INPUT]);
  327. snd_ad1848_dout(chip, AD1848_RIGHT_INPUT, chip->image[AD1848_RIGHT_INPUT]);
  328. }
  329. snd_ad1848_dout(chip, AD1848_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX1_LEFT_INPUT]);
  330. snd_ad1848_dout(chip, AD1848_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX1_RIGHT_INPUT]);
  331. snd_ad1848_dout(chip, AD1848_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX2_LEFT_INPUT]);
  332. snd_ad1848_dout(chip, AD1848_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX2_RIGHT_INPUT]);
  333. snd_ad1848_dout(chip, AD1848_LEFT_OUTPUT, mute ? 0x80 : chip->image[AD1848_LEFT_OUTPUT]);
  334. snd_ad1848_dout(chip, AD1848_RIGHT_OUTPUT, mute ? 0x80 : chip->image[AD1848_RIGHT_OUTPUT]);
  335. chip->calibrate_mute = mute;
  336. spin_unlock_irqrestore(&chip->reg_lock, flags);
  337. }
  338. static void snd_ad1848_set_data_format(struct snd_ad1848 *chip, struct snd_pcm_hw_params *hw_params)
  339. {
  340. if (hw_params == NULL) {
  341. chip->image[AD1848_DATA_FORMAT] = 0x20;
  342. } else {
  343. chip->image[AD1848_DATA_FORMAT] =
  344. snd_ad1848_get_format(params_format(hw_params), params_channels(hw_params)) |
  345. snd_ad1848_get_rate(params_rate(hw_params));
  346. }
  347. // snd_printk(">>> pmode = 0x%x, dfr = 0x%x\n", pstr->mode, chip->image[AD1848_DATA_FORMAT]);
  348. }
  349. static int snd_ad1848_open(struct snd_ad1848 *chip, unsigned int mode)
  350. {
  351. unsigned long flags;
  352. down(&chip->open_mutex);
  353. if (chip->mode & AD1848_MODE_OPEN) {
  354. up(&chip->open_mutex);
  355. return -EAGAIN;
  356. }
  357. snd_ad1848_mce_down(chip);
  358. #ifdef SNDRV_DEBUG_MCE
  359. snd_printk("open: (1)\n");
  360. #endif
  361. snd_ad1848_mce_up(chip);
  362. spin_lock_irqsave(&chip->reg_lock, flags);
  363. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO |
  364. AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO |
  365. AD1848_CALIB_MODE);
  366. chip->image[AD1848_IFACE_CTRL] |= AD1848_AUTOCALIB;
  367. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL]);
  368. spin_unlock_irqrestore(&chip->reg_lock, flags);
  369. snd_ad1848_mce_down(chip);
  370. #ifdef SNDRV_DEBUG_MCE
  371. snd_printk("open: (2)\n");
  372. #endif
  373. snd_ad1848_set_data_format(chip, NULL);
  374. snd_ad1848_mce_up(chip);
  375. spin_lock_irqsave(&chip->reg_lock, flags);
  376. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  377. spin_unlock_irqrestore(&chip->reg_lock, flags);
  378. snd_ad1848_mce_down(chip);
  379. #ifdef SNDRV_DEBUG_MCE
  380. snd_printk("open: (3)\n");
  381. #endif
  382. /* ok. now enable and ack CODEC IRQ */
  383. spin_lock_irqsave(&chip->reg_lock, flags);
  384. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  385. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  386. chip->image[AD1848_PIN_CTRL] |= AD1848_IRQ_ENABLE;
  387. snd_ad1848_out(chip, AD1848_PIN_CTRL, chip->image[AD1848_PIN_CTRL]);
  388. spin_unlock_irqrestore(&chip->reg_lock, flags);
  389. chip->mode = mode;
  390. up(&chip->open_mutex);
  391. return 0;
  392. }
  393. static void snd_ad1848_close(struct snd_ad1848 *chip)
  394. {
  395. unsigned long flags;
  396. down(&chip->open_mutex);
  397. if (!chip->mode) {
  398. up(&chip->open_mutex);
  399. return;
  400. }
  401. /* disable IRQ */
  402. spin_lock_irqsave(&chip->reg_lock, flags);
  403. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  404. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  405. chip->image[AD1848_PIN_CTRL] &= ~AD1848_IRQ_ENABLE;
  406. snd_ad1848_out(chip, AD1848_PIN_CTRL, chip->image[AD1848_PIN_CTRL]);
  407. spin_unlock_irqrestore(&chip->reg_lock, flags);
  408. /* now disable capture & playback */
  409. snd_ad1848_mce_up(chip);
  410. spin_lock_irqsave(&chip->reg_lock, flags);
  411. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO |
  412. AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO);
  413. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL]);
  414. spin_unlock_irqrestore(&chip->reg_lock, flags);
  415. snd_ad1848_mce_down(chip);
  416. /* clear IRQ again */
  417. spin_lock_irqsave(&chip->reg_lock, flags);
  418. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  419. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  420. spin_unlock_irqrestore(&chip->reg_lock, flags);
  421. chip->mode = 0;
  422. up(&chip->open_mutex);
  423. }
  424. /*
  425. * ok.. exported functions..
  426. */
  427. static int snd_ad1848_playback_trigger(struct snd_pcm_substream *substream,
  428. int cmd)
  429. {
  430. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  431. return snd_ad1848_trigger(chip, AD1848_PLAYBACK_ENABLE, SNDRV_PCM_STREAM_PLAYBACK, cmd);
  432. }
  433. static int snd_ad1848_capture_trigger(struct snd_pcm_substream *substream,
  434. int cmd)
  435. {
  436. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  437. return snd_ad1848_trigger(chip, AD1848_CAPTURE_ENABLE, SNDRV_PCM_STREAM_CAPTURE, cmd);
  438. }
  439. static int snd_ad1848_playback_hw_params(struct snd_pcm_substream *substream,
  440. struct snd_pcm_hw_params *hw_params)
  441. {
  442. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  443. unsigned long flags;
  444. int err;
  445. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  446. return err;
  447. snd_ad1848_calibrate_mute(chip, 1);
  448. snd_ad1848_set_data_format(chip, hw_params);
  449. snd_ad1848_mce_up(chip);
  450. spin_lock_irqsave(&chip->reg_lock, flags);
  451. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  452. spin_unlock_irqrestore(&chip->reg_lock, flags);
  453. snd_ad1848_mce_down(chip);
  454. snd_ad1848_calibrate_mute(chip, 0);
  455. return 0;
  456. }
  457. static int snd_ad1848_playback_hw_free(struct snd_pcm_substream *substream)
  458. {
  459. return snd_pcm_lib_free_pages(substream);
  460. }
  461. static int snd_ad1848_playback_prepare(struct snd_pcm_substream *substream)
  462. {
  463. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  464. struct snd_pcm_runtime *runtime = substream->runtime;
  465. unsigned long flags;
  466. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  467. unsigned int count = snd_pcm_lib_period_bytes(substream);
  468. chip->dma_size = size;
  469. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO);
  470. snd_dma_program(chip->dma, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
  471. count = snd_ad1848_get_count(chip->image[AD1848_DATA_FORMAT], count) - 1;
  472. spin_lock_irqsave(&chip->reg_lock, flags);
  473. snd_ad1848_out(chip, AD1848_DATA_LWR_CNT, (unsigned char) count);
  474. snd_ad1848_out(chip, AD1848_DATA_UPR_CNT, (unsigned char) (count >> 8));
  475. spin_unlock_irqrestore(&chip->reg_lock, flags);
  476. return 0;
  477. }
  478. static int snd_ad1848_capture_hw_params(struct snd_pcm_substream *substream,
  479. struct snd_pcm_hw_params *hw_params)
  480. {
  481. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  482. unsigned long flags;
  483. int err;
  484. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  485. return err;
  486. snd_ad1848_calibrate_mute(chip, 1);
  487. snd_ad1848_set_data_format(chip, hw_params);
  488. snd_ad1848_mce_up(chip);
  489. spin_lock_irqsave(&chip->reg_lock, flags);
  490. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  491. spin_unlock_irqrestore(&chip->reg_lock, flags);
  492. snd_ad1848_mce_down(chip);
  493. snd_ad1848_calibrate_mute(chip, 0);
  494. return 0;
  495. }
  496. static int snd_ad1848_capture_hw_free(struct snd_pcm_substream *substream)
  497. {
  498. return snd_pcm_lib_free_pages(substream);
  499. }
  500. static int snd_ad1848_capture_prepare(struct snd_pcm_substream *substream)
  501. {
  502. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  503. struct snd_pcm_runtime *runtime = substream->runtime;
  504. unsigned long flags;
  505. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  506. unsigned int count = snd_pcm_lib_period_bytes(substream);
  507. chip->dma_size = size;
  508. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO);
  509. snd_dma_program(chip->dma, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
  510. count = snd_ad1848_get_count(chip->image[AD1848_DATA_FORMAT], count) - 1;
  511. spin_lock_irqsave(&chip->reg_lock, flags);
  512. snd_ad1848_out(chip, AD1848_DATA_LWR_CNT, (unsigned char) count);
  513. snd_ad1848_out(chip, AD1848_DATA_UPR_CNT, (unsigned char) (count >> 8));
  514. spin_unlock_irqrestore(&chip->reg_lock, flags);
  515. return 0;
  516. }
  517. static irqreturn_t snd_ad1848_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  518. {
  519. struct snd_ad1848 *chip = dev_id;
  520. if ((chip->mode & AD1848_MODE_PLAY) && chip->playback_substream &&
  521. (chip->mode & AD1848_MODE_RUNNING))
  522. snd_pcm_period_elapsed(chip->playback_substream);
  523. if ((chip->mode & AD1848_MODE_CAPTURE) && chip->capture_substream &&
  524. (chip->mode & AD1848_MODE_RUNNING))
  525. snd_pcm_period_elapsed(chip->capture_substream);
  526. outb(0, AD1848P(chip, STATUS)); /* clear global interrupt bit */
  527. return IRQ_HANDLED;
  528. }
  529. static snd_pcm_uframes_t snd_ad1848_playback_pointer(struct snd_pcm_substream *substream)
  530. {
  531. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  532. size_t ptr;
  533. if (!(chip->image[AD1848_IFACE_CTRL] & AD1848_PLAYBACK_ENABLE))
  534. return 0;
  535. ptr = snd_dma_pointer(chip->dma, chip->dma_size);
  536. return bytes_to_frames(substream->runtime, ptr);
  537. }
  538. static snd_pcm_uframes_t snd_ad1848_capture_pointer(struct snd_pcm_substream *substream)
  539. {
  540. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  541. size_t ptr;
  542. if (!(chip->image[AD1848_IFACE_CTRL] & AD1848_CAPTURE_ENABLE))
  543. return 0;
  544. ptr = snd_dma_pointer(chip->dma, chip->dma_size);
  545. return bytes_to_frames(substream->runtime, ptr);
  546. }
  547. /*
  548. */
  549. static void snd_ad1848_thinkpad_twiddle(struct snd_ad1848 *chip, int on) {
  550. int tmp;
  551. if (!chip->thinkpad_flag) return;
  552. outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
  553. tmp = inb(AD1848_THINKPAD_CTL_PORT2);
  554. if (on)
  555. /* turn it on */
  556. tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
  557. else
  558. /* turn it off */
  559. tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
  560. outb(tmp, AD1848_THINKPAD_CTL_PORT2);
  561. }
  562. #ifdef CONFIG_PM
  563. static int snd_ad1848_suspend(struct snd_card *card, pm_message_t state)
  564. {
  565. struct snd_ad1848 *chip = card->pm_private_data;
  566. snd_pcm_suspend_all(chip->pcm);
  567. /* FIXME: save registers? */
  568. if (chip->thinkpad_flag)
  569. snd_ad1848_thinkpad_twiddle(chip, 0);
  570. return 0;
  571. }
  572. static int snd_ad1848_resume(struct snd_card *card)
  573. {
  574. struct snd_ad1848 *chip = card->pm_private_data;
  575. if (chip->thinkpad_flag)
  576. snd_ad1848_thinkpad_twiddle(chip, 1);
  577. /* FIXME: restore registers? */
  578. return 0;
  579. }
  580. #endif /* CONFIG_PM */
  581. static int snd_ad1848_probe(struct snd_ad1848 * chip)
  582. {
  583. unsigned long flags;
  584. int i, id, rev, ad1847;
  585. unsigned char *ptr;
  586. #if 0
  587. snd_ad1848_debug(chip);
  588. #endif
  589. id = ad1847 = 0;
  590. for (i = 0; i < 1000; i++) {
  591. mb();
  592. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  593. udelay(500);
  594. else {
  595. spin_lock_irqsave(&chip->reg_lock, flags);
  596. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x00);
  597. snd_ad1848_out(chip, AD1848_LEFT_INPUT, 0xaa);
  598. snd_ad1848_out(chip, AD1848_RIGHT_INPUT, 0x45);
  599. rev = snd_ad1848_in(chip, AD1848_RIGHT_INPUT);
  600. if (rev == 0x65) {
  601. spin_unlock_irqrestore(&chip->reg_lock, flags);
  602. id = 1;
  603. ad1847 = 1;
  604. break;
  605. }
  606. if (snd_ad1848_in(chip, AD1848_LEFT_INPUT) == 0xaa && rev == 0x45) {
  607. spin_unlock_irqrestore(&chip->reg_lock, flags);
  608. id = 1;
  609. break;
  610. }
  611. spin_unlock_irqrestore(&chip->reg_lock, flags);
  612. }
  613. }
  614. if (id != 1)
  615. return -ENODEV; /* no valid device found */
  616. if (chip->hardware == AD1848_HW_DETECT) {
  617. if (ad1847) {
  618. chip->hardware = AD1848_HW_AD1847;
  619. } else {
  620. chip->hardware = AD1848_HW_AD1848;
  621. rev = snd_ad1848_in(chip, AD1848_MISC_INFO);
  622. if (rev & 0x80) {
  623. chip->hardware = AD1848_HW_CS4248;
  624. } else if ((rev & 0x0f) == 0x0a) {
  625. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x40);
  626. for (i = 0; i < 16; ++i) {
  627. if (snd_ad1848_in(chip, i) != snd_ad1848_in(chip, i + 16)) {
  628. chip->hardware = AD1848_HW_CMI8330;
  629. break;
  630. }
  631. }
  632. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x00);
  633. }
  634. }
  635. }
  636. spin_lock_irqsave(&chip->reg_lock, flags);
  637. inb(AD1848P(chip, STATUS)); /* clear any pendings IRQ */
  638. outb(0, AD1848P(chip, STATUS));
  639. mb();
  640. spin_unlock_irqrestore(&chip->reg_lock, flags);
  641. chip->image[AD1848_MISC_INFO] = 0x00;
  642. chip->image[AD1848_IFACE_CTRL] =
  643. (chip->image[AD1848_IFACE_CTRL] & ~AD1848_SINGLE_DMA) | AD1848_SINGLE_DMA;
  644. ptr = (unsigned char *) &chip->image;
  645. snd_ad1848_mce_down(chip);
  646. spin_lock_irqsave(&chip->reg_lock, flags);
  647. for (i = 0; i < 16; i++) /* ok.. fill all AD1848 registers */
  648. snd_ad1848_out(chip, i, *ptr++);
  649. spin_unlock_irqrestore(&chip->reg_lock, flags);
  650. snd_ad1848_mce_up(chip);
  651. snd_ad1848_mce_down(chip);
  652. return 0; /* all things are ok.. */
  653. }
  654. /*
  655. */
  656. static struct snd_pcm_hardware snd_ad1848_playback =
  657. {
  658. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  659. SNDRV_PCM_INFO_MMAP_VALID),
  660. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  661. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE),
  662. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  663. .rate_min = 5510,
  664. .rate_max = 48000,
  665. .channels_min = 1,
  666. .channels_max = 2,
  667. .buffer_bytes_max = (128*1024),
  668. .period_bytes_min = 64,
  669. .period_bytes_max = (128*1024),
  670. .periods_min = 1,
  671. .periods_max = 1024,
  672. .fifo_size = 0,
  673. };
  674. static struct snd_pcm_hardware snd_ad1848_capture =
  675. {
  676. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  677. SNDRV_PCM_INFO_MMAP_VALID),
  678. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  679. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE),
  680. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  681. .rate_min = 5510,
  682. .rate_max = 48000,
  683. .channels_min = 1,
  684. .channels_max = 2,
  685. .buffer_bytes_max = (128*1024),
  686. .period_bytes_min = 64,
  687. .period_bytes_max = (128*1024),
  688. .periods_min = 1,
  689. .periods_max = 1024,
  690. .fifo_size = 0,
  691. };
  692. /*
  693. */
  694. static int snd_ad1848_playback_open(struct snd_pcm_substream *substream)
  695. {
  696. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  697. struct snd_pcm_runtime *runtime = substream->runtime;
  698. int err;
  699. if ((err = snd_ad1848_open(chip, AD1848_MODE_PLAY)) < 0)
  700. return err;
  701. chip->playback_substream = substream;
  702. runtime->hw = snd_ad1848_playback;
  703. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.buffer_bytes_max);
  704. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.period_bytes_max);
  705. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  706. return 0;
  707. }
  708. static int snd_ad1848_capture_open(struct snd_pcm_substream *substream)
  709. {
  710. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  711. struct snd_pcm_runtime *runtime = substream->runtime;
  712. int err;
  713. if ((err = snd_ad1848_open(chip, AD1848_MODE_CAPTURE)) < 0)
  714. return err;
  715. chip->capture_substream = substream;
  716. runtime->hw = snd_ad1848_capture;
  717. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.buffer_bytes_max);
  718. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.period_bytes_max);
  719. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  720. return 0;
  721. }
  722. static int snd_ad1848_playback_close(struct snd_pcm_substream *substream)
  723. {
  724. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  725. chip->mode &= ~AD1848_MODE_PLAY;
  726. chip->playback_substream = NULL;
  727. snd_ad1848_close(chip);
  728. return 0;
  729. }
  730. static int snd_ad1848_capture_close(struct snd_pcm_substream *substream)
  731. {
  732. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  733. chip->mode &= ~AD1848_MODE_CAPTURE;
  734. chip->capture_substream = NULL;
  735. snd_ad1848_close(chip);
  736. return 0;
  737. }
  738. static int snd_ad1848_free(struct snd_ad1848 *chip)
  739. {
  740. release_and_free_resource(chip->res_port);
  741. if (chip->irq >= 0)
  742. free_irq(chip->irq, (void *) chip);
  743. if (chip->dma >= 0) {
  744. snd_dma_disable(chip->dma);
  745. free_dma(chip->dma);
  746. }
  747. kfree(chip);
  748. return 0;
  749. }
  750. static int snd_ad1848_dev_free(struct snd_device *device)
  751. {
  752. struct snd_ad1848 *chip = device->device_data;
  753. return snd_ad1848_free(chip);
  754. }
  755. static const char *snd_ad1848_chip_id(struct snd_ad1848 *chip)
  756. {
  757. switch (chip->hardware) {
  758. case AD1848_HW_AD1847: return "AD1847";
  759. case AD1848_HW_AD1848: return "AD1848";
  760. case AD1848_HW_CS4248: return "CS4248";
  761. case AD1848_HW_CMI8330: return "CMI8330/C3D";
  762. default: return "???";
  763. }
  764. }
  765. int snd_ad1848_create(struct snd_card *card,
  766. unsigned long port,
  767. int irq, int dma,
  768. unsigned short hardware,
  769. struct snd_ad1848 ** rchip)
  770. {
  771. static struct snd_device_ops ops = {
  772. .dev_free = snd_ad1848_dev_free,
  773. };
  774. struct snd_ad1848 *chip;
  775. int err;
  776. *rchip = NULL;
  777. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  778. if (chip == NULL)
  779. return -ENOMEM;
  780. spin_lock_init(&chip->reg_lock);
  781. init_MUTEX(&chip->open_mutex);
  782. chip->card = card;
  783. chip->port = port;
  784. chip->irq = -1;
  785. chip->dma = -1;
  786. chip->hardware = hardware;
  787. memcpy(&chip->image, &snd_ad1848_original_image, sizeof(snd_ad1848_original_image));
  788. if ((chip->res_port = request_region(port, 4, "AD1848")) == NULL) {
  789. snd_printk(KERN_ERR "ad1848: can't grab port 0x%lx\n", port);
  790. snd_ad1848_free(chip);
  791. return -EBUSY;
  792. }
  793. if (request_irq(irq, snd_ad1848_interrupt, SA_INTERRUPT, "AD1848", (void *) chip)) {
  794. snd_printk(KERN_ERR "ad1848: can't grab IRQ %d\n", irq);
  795. snd_ad1848_free(chip);
  796. return -EBUSY;
  797. }
  798. chip->irq = irq;
  799. if (request_dma(dma, "AD1848")) {
  800. snd_printk(KERN_ERR "ad1848: can't grab DMA %d\n", dma);
  801. snd_ad1848_free(chip);
  802. return -EBUSY;
  803. }
  804. chip->dma = dma;
  805. if (hardware == AD1848_HW_THINKPAD) {
  806. chip->thinkpad_flag = 1;
  807. chip->hardware = AD1848_HW_DETECT; /* reset */
  808. snd_ad1848_thinkpad_twiddle(chip, 1);
  809. snd_card_set_isa_pm_callback(card, snd_ad1848_suspend, snd_ad1848_resume, chip);
  810. }
  811. if (snd_ad1848_probe(chip) < 0) {
  812. snd_ad1848_free(chip);
  813. return -ENODEV;
  814. }
  815. /* Register device */
  816. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  817. snd_ad1848_free(chip);
  818. return err;
  819. }
  820. *rchip = chip;
  821. return 0;
  822. }
  823. static struct snd_pcm_ops snd_ad1848_playback_ops = {
  824. .open = snd_ad1848_playback_open,
  825. .close = snd_ad1848_playback_close,
  826. .ioctl = snd_ad1848_ioctl,
  827. .hw_params = snd_ad1848_playback_hw_params,
  828. .hw_free = snd_ad1848_playback_hw_free,
  829. .prepare = snd_ad1848_playback_prepare,
  830. .trigger = snd_ad1848_playback_trigger,
  831. .pointer = snd_ad1848_playback_pointer,
  832. };
  833. static struct snd_pcm_ops snd_ad1848_capture_ops = {
  834. .open = snd_ad1848_capture_open,
  835. .close = snd_ad1848_capture_close,
  836. .ioctl = snd_ad1848_ioctl,
  837. .hw_params = snd_ad1848_capture_hw_params,
  838. .hw_free = snd_ad1848_capture_hw_free,
  839. .prepare = snd_ad1848_capture_prepare,
  840. .trigger = snd_ad1848_capture_trigger,
  841. .pointer = snd_ad1848_capture_pointer,
  842. };
  843. int snd_ad1848_pcm(struct snd_ad1848 *chip, int device, struct snd_pcm **rpcm)
  844. {
  845. struct snd_pcm *pcm;
  846. int err;
  847. if ((err = snd_pcm_new(chip->card, "AD1848", device, 1, 1, &pcm)) < 0)
  848. return err;
  849. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ad1848_playback_ops);
  850. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ad1848_capture_ops);
  851. pcm->private_data = chip;
  852. pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  853. strcpy(pcm->name, snd_ad1848_chip_id(chip));
  854. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  855. snd_dma_isa_data(),
  856. 64*1024, chip->dma > 3 ? 128*1024 : 64*1024);
  857. chip->pcm = pcm;
  858. if (rpcm)
  859. *rpcm = pcm;
  860. return 0;
  861. }
  862. const struct snd_pcm_ops *snd_ad1848_get_pcm_ops(int direction)
  863. {
  864. return direction == SNDRV_PCM_STREAM_PLAYBACK ?
  865. &snd_ad1848_playback_ops : &snd_ad1848_capture_ops;
  866. }
  867. /*
  868. * MIXER part
  869. */
  870. static int snd_ad1848_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  871. {
  872. static char *texts[4] = {
  873. "Line", "Aux", "Mic", "Mix"
  874. };
  875. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  876. uinfo->count = 2;
  877. uinfo->value.enumerated.items = 4;
  878. if (uinfo->value.enumerated.item > 3)
  879. uinfo->value.enumerated.item = 3;
  880. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  881. return 0;
  882. }
  883. static int snd_ad1848_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  884. {
  885. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  886. unsigned long flags;
  887. spin_lock_irqsave(&chip->reg_lock, flags);
  888. ucontrol->value.enumerated.item[0] = (chip->image[AD1848_LEFT_INPUT] & AD1848_MIXS_ALL) >> 6;
  889. ucontrol->value.enumerated.item[1] = (chip->image[AD1848_RIGHT_INPUT] & AD1848_MIXS_ALL) >> 6;
  890. spin_unlock_irqrestore(&chip->reg_lock, flags);
  891. return 0;
  892. }
  893. static int snd_ad1848_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  894. {
  895. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  896. unsigned long flags;
  897. unsigned short left, right;
  898. int change;
  899. if (ucontrol->value.enumerated.item[0] > 3 ||
  900. ucontrol->value.enumerated.item[1] > 3)
  901. return -EINVAL;
  902. left = ucontrol->value.enumerated.item[0] << 6;
  903. right = ucontrol->value.enumerated.item[1] << 6;
  904. spin_lock_irqsave(&chip->reg_lock, flags);
  905. left = (chip->image[AD1848_LEFT_INPUT] & ~AD1848_MIXS_ALL) | left;
  906. right = (chip->image[AD1848_RIGHT_INPUT] & ~AD1848_MIXS_ALL) | right;
  907. change = left != chip->image[AD1848_LEFT_INPUT] ||
  908. right != chip->image[AD1848_RIGHT_INPUT];
  909. snd_ad1848_out(chip, AD1848_LEFT_INPUT, left);
  910. snd_ad1848_out(chip, AD1848_RIGHT_INPUT, right);
  911. spin_unlock_irqrestore(&chip->reg_lock, flags);
  912. return change;
  913. }
  914. static int snd_ad1848_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  915. {
  916. int mask = (kcontrol->private_value >> 16) & 0xff;
  917. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  918. uinfo->count = 1;
  919. uinfo->value.integer.min = 0;
  920. uinfo->value.integer.max = mask;
  921. return 0;
  922. }
  923. static int snd_ad1848_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  924. {
  925. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  926. unsigned long flags;
  927. int reg = kcontrol->private_value & 0xff;
  928. int shift = (kcontrol->private_value >> 8) & 0xff;
  929. int mask = (kcontrol->private_value >> 16) & 0xff;
  930. int invert = (kcontrol->private_value >> 24) & 0xff;
  931. spin_lock_irqsave(&chip->reg_lock, flags);
  932. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  933. spin_unlock_irqrestore(&chip->reg_lock, flags);
  934. if (invert)
  935. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  936. return 0;
  937. }
  938. static int snd_ad1848_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  939. {
  940. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  941. unsigned long flags;
  942. int reg = kcontrol->private_value & 0xff;
  943. int shift = (kcontrol->private_value >> 8) & 0xff;
  944. int mask = (kcontrol->private_value >> 16) & 0xff;
  945. int invert = (kcontrol->private_value >> 24) & 0xff;
  946. int change;
  947. unsigned short val;
  948. val = (ucontrol->value.integer.value[0] & mask);
  949. if (invert)
  950. val = mask - val;
  951. val <<= shift;
  952. spin_lock_irqsave(&chip->reg_lock, flags);
  953. val = (chip->image[reg] & ~(mask << shift)) | val;
  954. change = val != chip->image[reg];
  955. snd_ad1848_out(chip, reg, val);
  956. spin_unlock_irqrestore(&chip->reg_lock, flags);
  957. return change;
  958. }
  959. static int snd_ad1848_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  960. {
  961. int mask = (kcontrol->private_value >> 24) & 0xff;
  962. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  963. uinfo->count = 2;
  964. uinfo->value.integer.min = 0;
  965. uinfo->value.integer.max = mask;
  966. return 0;
  967. }
  968. static int snd_ad1848_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  969. {
  970. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  971. unsigned long flags;
  972. int left_reg = kcontrol->private_value & 0xff;
  973. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  974. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  975. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  976. int mask = (kcontrol->private_value >> 24) & 0xff;
  977. int invert = (kcontrol->private_value >> 22) & 1;
  978. spin_lock_irqsave(&chip->reg_lock, flags);
  979. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  980. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  981. spin_unlock_irqrestore(&chip->reg_lock, flags);
  982. if (invert) {
  983. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  984. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  985. }
  986. return 0;
  987. }
  988. static int snd_ad1848_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  989. {
  990. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  991. unsigned long flags;
  992. int left_reg = kcontrol->private_value & 0xff;
  993. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  994. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  995. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  996. int mask = (kcontrol->private_value >> 24) & 0xff;
  997. int invert = (kcontrol->private_value >> 22) & 1;
  998. int change;
  999. unsigned short val1, val2;
  1000. val1 = ucontrol->value.integer.value[0] & mask;
  1001. val2 = ucontrol->value.integer.value[1] & mask;
  1002. if (invert) {
  1003. val1 = mask - val1;
  1004. val2 = mask - val2;
  1005. }
  1006. val1 <<= shift_left;
  1007. val2 <<= shift_right;
  1008. spin_lock_irqsave(&chip->reg_lock, flags);
  1009. if (left_reg != right_reg) {
  1010. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1011. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1012. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1013. snd_ad1848_out(chip, left_reg, val1);
  1014. snd_ad1848_out(chip, right_reg, val2);
  1015. } else {
  1016. val1 = (chip->image[left_reg] & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1017. change = val1 != chip->image[left_reg];
  1018. snd_ad1848_out(chip, left_reg, val1);
  1019. }
  1020. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1021. return change;
  1022. }
  1023. /*
  1024. */
  1025. int snd_ad1848_add_ctl(struct snd_ad1848 *chip, const char *name, int index, int type, unsigned long value)
  1026. {
  1027. static struct snd_kcontrol_new newctls[] = {
  1028. [AD1848_MIX_SINGLE] = {
  1029. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1030. .info = snd_ad1848_info_single,
  1031. .get = snd_ad1848_get_single,
  1032. .put = snd_ad1848_put_single,
  1033. },
  1034. [AD1848_MIX_DOUBLE] = {
  1035. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1036. .info = snd_ad1848_info_double,
  1037. .get = snd_ad1848_get_double,
  1038. .put = snd_ad1848_put_double,
  1039. },
  1040. [AD1848_MIX_CAPTURE] = {
  1041. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1042. .info = snd_ad1848_info_mux,
  1043. .get = snd_ad1848_get_mux,
  1044. .put = snd_ad1848_put_mux,
  1045. },
  1046. };
  1047. struct snd_kcontrol *ctl;
  1048. int err;
  1049. ctl = snd_ctl_new1(&newctls[type], chip);
  1050. if (! ctl)
  1051. return -ENOMEM;
  1052. strlcpy(ctl->id.name, name, sizeof(ctl->id.name));
  1053. ctl->id.index = index;
  1054. ctl->private_value = value;
  1055. if ((err = snd_ctl_add(chip->card, ctl)) < 0) {
  1056. snd_ctl_free_one(ctl);
  1057. return err;
  1058. }
  1059. return 0;
  1060. }
  1061. static struct ad1848_mix_elem snd_ad1848_controls[] = {
  1062. AD1848_DOUBLE("PCM Playback Switch", 0, AD1848_LEFT_OUTPUT, AD1848_RIGHT_OUTPUT, 7, 7, 1, 1),
  1063. AD1848_DOUBLE("PCM Playback Volume", 0, AD1848_LEFT_OUTPUT, AD1848_RIGHT_OUTPUT, 0, 0, 63, 1),
  1064. AD1848_DOUBLE("Aux Playback Switch", 0, AD1848_AUX1_LEFT_INPUT, AD1848_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1065. AD1848_DOUBLE("Aux Playback Volume", 0, AD1848_AUX1_LEFT_INPUT, AD1848_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1066. AD1848_DOUBLE("Aux Playback Switch", 1, AD1848_AUX2_LEFT_INPUT, AD1848_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1067. AD1848_DOUBLE("Aux Playback Volume", 1, AD1848_AUX2_LEFT_INPUT, AD1848_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1068. AD1848_DOUBLE("Capture Volume", 0, AD1848_LEFT_INPUT, AD1848_RIGHT_INPUT, 0, 0, 15, 0),
  1069. {
  1070. .name = "Capture Source",
  1071. .type = AD1848_MIX_CAPTURE,
  1072. },
  1073. AD1848_SINGLE("Loopback Capture Switch", 0, AD1848_LOOPBACK, 0, 1, 0),
  1074. AD1848_SINGLE("Loopback Capture Volume", 0, AD1848_LOOPBACK, 1, 63, 0)
  1075. };
  1076. int snd_ad1848_mixer(struct snd_ad1848 *chip)
  1077. {
  1078. struct snd_card *card;
  1079. struct snd_pcm *pcm;
  1080. unsigned int idx;
  1081. int err;
  1082. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1083. pcm = chip->pcm;
  1084. card = chip->card;
  1085. strcpy(card->mixername, pcm->name);
  1086. for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++)
  1087. if ((err = snd_ad1848_add_ctl_elem(chip, &snd_ad1848_controls[idx])) < 0)
  1088. return err;
  1089. return 0;
  1090. }
  1091. EXPORT_SYMBOL(snd_ad1848_out);
  1092. EXPORT_SYMBOL(snd_ad1848_create);
  1093. EXPORT_SYMBOL(snd_ad1848_pcm);
  1094. EXPORT_SYMBOL(snd_ad1848_get_pcm_ops);
  1095. EXPORT_SYMBOL(snd_ad1848_mixer);
  1096. EXPORT_SYMBOL(snd_ad1848_add_ctl);
  1097. /*
  1098. * INIT part
  1099. */
  1100. static int __init alsa_ad1848_init(void)
  1101. {
  1102. return 0;
  1103. }
  1104. static void __exit alsa_ad1848_exit(void)
  1105. {
  1106. }
  1107. module_init(alsa_ad1848_init)
  1108. module_exit(alsa_ad1848_exit)