gdth.c 178 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: gdth_bufflen
  87. * buffer: gdth_sglist
  88. * dma_handle: unused
  89. * buffers_residual: gdth_sg_count
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #ifdef GDTH_RTC
  117. #include <linux/mc146818rtc.h>
  118. #endif
  119. #include <linux/reboot.h>
  120. #include <asm/dma.h>
  121. #include <asm/system.h>
  122. #include <asm/io.h>
  123. #include <asm/uaccess.h>
  124. #include <linux/spinlock.h>
  125. #include <linux/blkdev.h>
  126. #include <linux/scatterlist.h>
  127. #include "scsi.h"
  128. #include <scsi/scsi_host.h>
  129. #include "gdth.h"
  130. static void gdth_delay(int milliseconds);
  131. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  132. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  133. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int irq,
  134. int gdth_from_wait, int* pIndex);
  135. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  136. Scsi_Cmnd *scp);
  137. static int gdth_async_event(gdth_ha_str *ha);
  138. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  139. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
  140. static void gdth_next(gdth_ha_str *ha);
  141. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
  142. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  143. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  144. ushort idx, gdth_evt_data *evt);
  145. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  146. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  147. gdth_evt_str *estr);
  148. static void gdth_clear_events(void);
  149. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  150. char *buffer, ushort count, int to_buffer);
  151. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  152. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
  153. static void gdth_enable_int(gdth_ha_str *ha);
  154. static unchar gdth_get_status(gdth_ha_str *ha, int irq);
  155. static int gdth_test_busy(gdth_ha_str *ha);
  156. static int gdth_get_cmd_index(gdth_ha_str *ha);
  157. static void gdth_release_event(gdth_ha_str *ha);
  158. static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
  159. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  160. ulong32 p1, ulong64 p2,ulong64 p3);
  161. static int gdth_search_drives(gdth_ha_str *ha);
  162. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
  163. static const char *gdth_ctr_name(gdth_ha_str *ha);
  164. static int gdth_open(struct inode *inode, struct file *filep);
  165. static int gdth_close(struct inode *inode, struct file *filep);
  166. static int gdth_ioctl(struct inode *inode, struct file *filep,
  167. unsigned int cmd, unsigned long arg);
  168. static void gdth_flush(gdth_ha_str *ha);
  169. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  170. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  171. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  172. struct gdth_cmndinfo *cmndinfo);
  173. static void gdth_scsi_done(struct scsi_cmnd *scp);
  174. #ifdef DEBUG_GDTH
  175. static unchar DebugState = DEBUG_GDTH;
  176. #ifdef __SERIAL__
  177. #define MAX_SERBUF 160
  178. static void ser_init(void);
  179. static void ser_puts(char *str);
  180. static void ser_putc(char c);
  181. static int ser_printk(const char *fmt, ...);
  182. static char strbuf[MAX_SERBUF+1];
  183. #ifdef __COM2__
  184. #define COM_BASE 0x2f8
  185. #else
  186. #define COM_BASE 0x3f8
  187. #endif
  188. static void ser_init()
  189. {
  190. unsigned port=COM_BASE;
  191. outb(0x80,port+3);
  192. outb(0,port+1);
  193. /* 19200 Baud, if 9600: outb(12,port) */
  194. outb(6, port);
  195. outb(3,port+3);
  196. outb(0,port+1);
  197. /*
  198. ser_putc('I');
  199. ser_putc(' ');
  200. */
  201. }
  202. static void ser_puts(char *str)
  203. {
  204. char *ptr;
  205. ser_init();
  206. for (ptr=str;*ptr;++ptr)
  207. ser_putc(*ptr);
  208. }
  209. static void ser_putc(char c)
  210. {
  211. unsigned port=COM_BASE;
  212. while ((inb(port+5) & 0x20)==0);
  213. outb(c,port);
  214. if (c==0x0a)
  215. {
  216. while ((inb(port+5) & 0x20)==0);
  217. outb(0x0d,port);
  218. }
  219. }
  220. static int ser_printk(const char *fmt, ...)
  221. {
  222. va_list args;
  223. int i;
  224. va_start(args,fmt);
  225. i = vsprintf(strbuf,fmt,args);
  226. ser_puts(strbuf);
  227. va_end(args);
  228. return i;
  229. }
  230. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  231. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  232. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  233. #else /* !__SERIAL__ */
  234. #define TRACE(a) {if (DebugState==1) {printk a;}}
  235. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  236. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  237. #endif
  238. #else /* !DEBUG */
  239. #define TRACE(a)
  240. #define TRACE2(a)
  241. #define TRACE3(a)
  242. #endif
  243. #ifdef GDTH_STATISTICS
  244. static ulong32 max_rq=0, max_index=0, max_sg=0;
  245. #ifdef INT_COAL
  246. static ulong32 max_int_coal=0;
  247. #endif
  248. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  249. static struct timer_list gdth_timer;
  250. #endif
  251. #define PTR2USHORT(a) (ushort)(ulong)(a)
  252. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  253. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  254. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  255. #ifdef CONFIG_ISA
  256. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  257. #endif
  258. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  259. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  260. #endif
  261. static unchar gdth_polling; /* polling if TRUE */
  262. static int gdth_ctr_count = 0; /* controller count */
  263. static LIST_HEAD(gdth_instances); /* controller list */
  264. static unchar gdth_write_through = FALSE; /* write through */
  265. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  266. static int elastidx;
  267. static int eoldidx;
  268. static int major;
  269. #define DIN 1 /* IN data direction */
  270. #define DOU 2 /* OUT data direction */
  271. #define DNO DIN /* no data transfer */
  272. #define DUN DIN /* unknown data direction */
  273. static unchar gdth_direction_tab[0x100] = {
  274. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  275. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  276. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  277. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  278. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  283. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  284. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  285. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  289. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  290. };
  291. /* LILO and modprobe/insmod parameters */
  292. /* IRQ list for GDT3000/3020 EISA controllers */
  293. static int irq[MAXHA] __initdata =
  294. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  295. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  296. /* disable driver flag */
  297. static int disable __initdata = 0;
  298. /* reserve flag */
  299. static int reserve_mode = 1;
  300. /* reserve list */
  301. static int reserve_list[MAX_RES_ARGS] =
  302. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  303. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  304. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  305. /* scan order for PCI controllers */
  306. static int reverse_scan = 0;
  307. /* virtual channel for the host drives */
  308. static int hdr_channel = 0;
  309. /* max. IDs per channel */
  310. static int max_ids = MAXID;
  311. /* rescan all IDs */
  312. static int rescan = 0;
  313. /* shared access */
  314. static int shared_access = 1;
  315. /* enable support for EISA and ISA controllers */
  316. static int probe_eisa_isa = 0;
  317. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  318. static int force_dma32 = 0;
  319. /* parameters for modprobe/insmod */
  320. module_param_array(irq, int, NULL, 0);
  321. module_param(disable, int, 0);
  322. module_param(reserve_mode, int, 0);
  323. module_param_array(reserve_list, int, NULL, 0);
  324. module_param(reverse_scan, int, 0);
  325. module_param(hdr_channel, int, 0);
  326. module_param(max_ids, int, 0);
  327. module_param(rescan, int, 0);
  328. module_param(shared_access, int, 0);
  329. module_param(probe_eisa_isa, int, 0);
  330. module_param(force_dma32, int, 0);
  331. MODULE_AUTHOR("Achim Leubner");
  332. MODULE_LICENSE("GPL");
  333. /* ioctl interface */
  334. static const struct file_operations gdth_fops = {
  335. .ioctl = gdth_ioctl,
  336. .open = gdth_open,
  337. .release = gdth_close,
  338. };
  339. /*
  340. * gdth scsi_command access wrappers.
  341. * below 6 functions are used throughout the driver to access scsi_command's
  342. * io parameters. The reason we do not use the regular accessors from
  343. * scsi_cmnd.h is because of gdth_execute(). Since it is unrecommended for
  344. * llds to directly set scsi_cmnd's IO members. This driver will use SCp
  345. * members for IO parameters, and will copy scsi_cmnd's members to Scp
  346. * members in queuecommand. For internal commands through gdth_execute()
  347. * SCp's members will be set directly.
  348. */
  349. static inline unsigned gdth_bufflen(struct scsi_cmnd *cmd)
  350. {
  351. return (unsigned)cmd->SCp.this_residual;
  352. }
  353. static inline void gdth_set_bufflen(struct scsi_cmnd *cmd, unsigned bufflen)
  354. {
  355. cmd->SCp.this_residual = bufflen;
  356. }
  357. static inline unsigned gdth_sg_count(struct scsi_cmnd *cmd)
  358. {
  359. return (unsigned)cmd->SCp.buffers_residual;
  360. }
  361. static inline void gdth_set_sg_count(struct scsi_cmnd *cmd, unsigned sg_count)
  362. {
  363. cmd->SCp.buffers_residual = sg_count;
  364. }
  365. static inline struct scatterlist *gdth_sglist(struct scsi_cmnd *cmd)
  366. {
  367. return cmd->SCp.buffer;
  368. }
  369. static inline void gdth_set_sglist(struct scsi_cmnd *cmd,
  370. struct scatterlist *sglist)
  371. {
  372. cmd->SCp.buffer = sglist;
  373. }
  374. #include "gdth_proc.h"
  375. #include "gdth_proc.c"
  376. /* notifier block to get a notify on system shutdown/halt/reboot */
  377. static struct notifier_block gdth_notifier = {
  378. gdth_halt, NULL, 0
  379. };
  380. static int notifier_disabled = 0;
  381. static gdth_ha_str *gdth_find_ha(int hanum)
  382. {
  383. gdth_ha_str *ha;
  384. list_for_each_entry(ha, &gdth_instances, list)
  385. if (hanum == ha->hanum)
  386. return ha;
  387. return NULL;
  388. }
  389. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  390. {
  391. struct gdth_cmndinfo *priv = NULL;
  392. ulong flags;
  393. int i;
  394. spin_lock_irqsave(&ha->smp_lock, flags);
  395. for (i=0; i<GDTH_MAXCMDS; ++i) {
  396. if (ha->cmndinfo[i].index == 0) {
  397. priv = &ha->cmndinfo[i];
  398. priv->index = i+1;
  399. memset(priv, 0, sizeof(*priv));
  400. break;
  401. }
  402. }
  403. spin_unlock_irqrestore(&ha->smp_lock, flags);
  404. return priv;
  405. }
  406. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  407. {
  408. BUG_ON(!priv);
  409. priv->index = 0;
  410. }
  411. static void gdth_delay(int milliseconds)
  412. {
  413. if (milliseconds == 0) {
  414. udelay(1);
  415. } else {
  416. mdelay(milliseconds);
  417. }
  418. }
  419. static void gdth_scsi_done(struct scsi_cmnd *scp)
  420. {
  421. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  422. int internal_command = cmndinfo->internal_command;
  423. TRACE2(("gdth_scsi_done()\n"));
  424. gdth_put_cmndinfo(cmndinfo);
  425. scp->host_scribble = NULL;
  426. if (internal_command)
  427. complete((struct completion *)scp->request);
  428. else
  429. scp->scsi_done(scp);
  430. }
  431. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  432. int timeout, u32 *info)
  433. {
  434. gdth_ha_str *ha = shost_priv(sdev->host);
  435. Scsi_Cmnd *scp;
  436. struct gdth_cmndinfo cmndinfo;
  437. struct scatterlist one_sg;
  438. DECLARE_COMPLETION_ONSTACK(wait);
  439. int rval;
  440. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  441. if (!scp)
  442. return -ENOMEM;
  443. scp->device = sdev;
  444. memset(&cmndinfo, 0, sizeof(cmndinfo));
  445. /* use request field to save the ptr. to completion struct. */
  446. scp->request = (struct request *)&wait;
  447. scp->timeout_per_command = timeout*HZ;
  448. sg_init_one(&one_sg, gdtcmd, sizeof(*gdtcmd));
  449. gdth_set_sglist(scp, &one_sg);
  450. gdth_set_sg_count(scp, 1);
  451. gdth_set_bufflen(scp, sizeof(*gdtcmd));
  452. scp->cmd_len = 12;
  453. memcpy(scp->cmnd, cmnd, 12);
  454. cmndinfo.priority = IOCTL_PRI;
  455. cmndinfo.internal_command = 1;
  456. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  457. __gdth_queuecommand(ha, scp, &cmndinfo);
  458. wait_for_completion(&wait);
  459. rval = cmndinfo.status;
  460. if (info)
  461. *info = cmndinfo.info;
  462. kfree(scp);
  463. return rval;
  464. }
  465. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  466. int timeout, u32 *info)
  467. {
  468. struct scsi_device *sdev = scsi_get_host_dev(shost);
  469. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  470. scsi_free_host_dev(sdev);
  471. return rval;
  472. }
  473. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  474. {
  475. *cyls = size /HEADS/SECS;
  476. if (*cyls <= MAXCYLS) {
  477. *heads = HEADS;
  478. *secs = SECS;
  479. } else { /* too high for 64*32 */
  480. *cyls = size /MEDHEADS/MEDSECS;
  481. if (*cyls <= MAXCYLS) {
  482. *heads = MEDHEADS;
  483. *secs = MEDSECS;
  484. } else { /* too high for 127*63 */
  485. *cyls = size /BIGHEADS/BIGSECS;
  486. *heads = BIGHEADS;
  487. *secs = BIGSECS;
  488. }
  489. }
  490. }
  491. /* controller search and initialization functions */
  492. #ifdef CONFIG_EISA
  493. static int __init gdth_search_eisa(ushort eisa_adr)
  494. {
  495. ulong32 id;
  496. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  497. id = inl(eisa_adr+ID0REG);
  498. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  499. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  500. return 0; /* not EISA configured */
  501. return 1;
  502. }
  503. if (id == GDT3_ID) /* GDT3000 */
  504. return 1;
  505. return 0;
  506. }
  507. #endif /* CONFIG_EISA */
  508. #ifdef CONFIG_ISA
  509. static int __init gdth_search_isa(ulong32 bios_adr)
  510. {
  511. void __iomem *addr;
  512. ulong32 id;
  513. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  514. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  515. id = readl(addr);
  516. iounmap(addr);
  517. if (id == GDT2_ID) /* GDT2000 */
  518. return 1;
  519. }
  520. return 0;
  521. }
  522. #endif /* CONFIG_ISA */
  523. #ifdef CONFIG_PCI
  524. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  525. ushort vendor, ushort dev);
  526. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  527. {
  528. ushort device, cnt;
  529. TRACE(("gdth_search_pci()\n"));
  530. cnt = 0;
  531. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  532. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  533. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  534. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  535. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  536. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  537. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  538. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  539. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  540. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  541. PCI_DEVICE_ID_INTEL_SRC);
  542. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  543. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  544. return cnt;
  545. }
  546. /* Vortex only makes RAID controllers.
  547. * We do not really want to specify all 550 ids here, so wildcard match.
  548. */
  549. static struct pci_device_id gdthtable[] __maybe_unused = {
  550. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  551. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  552. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  553. {0}
  554. };
  555. MODULE_DEVICE_TABLE(pci,gdthtable);
  556. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  557. ushort vendor, ushort device)
  558. {
  559. ulong base0, base1, base2;
  560. struct pci_dev *pdev;
  561. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  562. *cnt, vendor, device));
  563. pdev = NULL;
  564. while ((pdev = pci_find_device(vendor, device, pdev))
  565. != NULL) {
  566. if (pci_enable_device(pdev))
  567. continue;
  568. if (*cnt >= MAXHA)
  569. return;
  570. /* GDT PCI controller found, resources are already in pdev */
  571. pcistr[*cnt].pdev = pdev;
  572. pcistr[*cnt].irq = pdev->irq;
  573. base0 = pci_resource_flags(pdev, 0);
  574. base1 = pci_resource_flags(pdev, 1);
  575. base2 = pci_resource_flags(pdev, 2);
  576. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  577. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  578. if (!(base0 & IORESOURCE_MEM))
  579. continue;
  580. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  581. } else { /* GDT6110, GDT6120, .. */
  582. if (!(base0 & IORESOURCE_MEM) ||
  583. !(base2 & IORESOURCE_MEM) ||
  584. !(base1 & IORESOURCE_IO))
  585. continue;
  586. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  587. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  588. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  589. }
  590. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  591. pcistr[*cnt].pdev->bus->number,
  592. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  593. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  594. (*cnt)++;
  595. }
  596. }
  597. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  598. {
  599. gdth_pci_str temp;
  600. int i, changed;
  601. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  602. if (cnt == 0)
  603. return;
  604. do {
  605. changed = FALSE;
  606. for (i = 0; i < cnt-1; ++i) {
  607. if (!reverse_scan) {
  608. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  609. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  610. PCI_SLOT(pcistr[i].pdev->devfn) >
  611. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  612. temp = pcistr[i];
  613. pcistr[i] = pcistr[i+1];
  614. pcistr[i+1] = temp;
  615. changed = TRUE;
  616. }
  617. } else {
  618. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  619. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  620. PCI_SLOT(pcistr[i].pdev->devfn) <
  621. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  622. temp = pcistr[i];
  623. pcistr[i] = pcistr[i+1];
  624. pcistr[i+1] = temp;
  625. changed = TRUE;
  626. }
  627. }
  628. }
  629. } while (changed);
  630. }
  631. #endif /* CONFIG_PCI */
  632. #ifdef CONFIG_EISA
  633. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  634. {
  635. ulong32 retries,id;
  636. unchar prot_ver,eisacf,i,irq_found;
  637. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  638. /* disable board interrupts, deinitialize services */
  639. outb(0xff,eisa_adr+EDOORREG);
  640. outb(0x00,eisa_adr+EDENABREG);
  641. outb(0x00,eisa_adr+EINTENABREG);
  642. outb(0xff,eisa_adr+LDOORREG);
  643. retries = INIT_RETRIES;
  644. gdth_delay(20);
  645. while (inb(eisa_adr+EDOORREG) != 0xff) {
  646. if (--retries == 0) {
  647. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  648. return 0;
  649. }
  650. gdth_delay(1);
  651. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  652. }
  653. prot_ver = inb(eisa_adr+MAILBOXREG);
  654. outb(0xff,eisa_adr+EDOORREG);
  655. if (prot_ver != PROTOCOL_VERSION) {
  656. printk("GDT-EISA: Illegal protocol version\n");
  657. return 0;
  658. }
  659. ha->bmic = eisa_adr;
  660. ha->brd_phys = (ulong32)eisa_adr >> 12;
  661. outl(0,eisa_adr+MAILBOXREG);
  662. outl(0,eisa_adr+MAILBOXREG+4);
  663. outl(0,eisa_adr+MAILBOXREG+8);
  664. outl(0,eisa_adr+MAILBOXREG+12);
  665. /* detect IRQ */
  666. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  667. ha->oem_id = OEM_ID_ICP;
  668. ha->type = GDT_EISA;
  669. ha->stype = id;
  670. outl(1,eisa_adr+MAILBOXREG+8);
  671. outb(0xfe,eisa_adr+LDOORREG);
  672. retries = INIT_RETRIES;
  673. gdth_delay(20);
  674. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  675. if (--retries == 0) {
  676. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  677. return 0;
  678. }
  679. gdth_delay(1);
  680. }
  681. ha->irq = inb(eisa_adr+MAILBOXREG);
  682. outb(0xff,eisa_adr+EDOORREG);
  683. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  684. /* check the result */
  685. if (ha->irq == 0) {
  686. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  687. for (i = 0, irq_found = FALSE;
  688. i < MAXHA && irq[i] != 0xff; ++i) {
  689. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  690. irq_found = TRUE;
  691. break;
  692. }
  693. }
  694. if (irq_found) {
  695. ha->irq = irq[i];
  696. irq[i] = 0;
  697. printk("GDT-EISA: Can not detect controller IRQ,\n");
  698. printk("Use IRQ setting from command line (IRQ = %d)\n",
  699. ha->irq);
  700. } else {
  701. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  702. printk("the controller BIOS or use command line parameters\n");
  703. return 0;
  704. }
  705. }
  706. } else {
  707. eisacf = inb(eisa_adr+EISAREG) & 7;
  708. if (eisacf > 4) /* level triggered */
  709. eisacf -= 4;
  710. ha->irq = gdth_irq_tab[eisacf];
  711. ha->oem_id = OEM_ID_ICP;
  712. ha->type = GDT_EISA;
  713. ha->stype = id;
  714. }
  715. ha->dma64_support = 0;
  716. return 1;
  717. }
  718. #endif /* CONFIG_EISA */
  719. #ifdef CONFIG_ISA
  720. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  721. {
  722. register gdt2_dpram_str __iomem *dp2_ptr;
  723. int i;
  724. unchar irq_drq,prot_ver;
  725. ulong32 retries;
  726. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  727. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  728. if (ha->brd == NULL) {
  729. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  730. return 0;
  731. }
  732. dp2_ptr = ha->brd;
  733. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  734. /* reset interface area */
  735. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  736. if (readl(&dp2_ptr->u) != 0) {
  737. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  738. iounmap(ha->brd);
  739. return 0;
  740. }
  741. /* disable board interrupts, read DRQ and IRQ */
  742. writeb(0xff, &dp2_ptr->io.irqdel);
  743. writeb(0x00, &dp2_ptr->io.irqen);
  744. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  745. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  746. irq_drq = readb(&dp2_ptr->io.rq);
  747. for (i=0; i<3; ++i) {
  748. if ((irq_drq & 1)==0)
  749. break;
  750. irq_drq >>= 1;
  751. }
  752. ha->drq = gdth_drq_tab[i];
  753. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  754. for (i=1; i<5; ++i) {
  755. if ((irq_drq & 1)==0)
  756. break;
  757. irq_drq >>= 1;
  758. }
  759. ha->irq = gdth_irq_tab[i];
  760. /* deinitialize services */
  761. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  762. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  763. writeb(0, &dp2_ptr->io.event);
  764. retries = INIT_RETRIES;
  765. gdth_delay(20);
  766. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  767. if (--retries == 0) {
  768. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  769. iounmap(ha->brd);
  770. return 0;
  771. }
  772. gdth_delay(1);
  773. }
  774. prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
  775. writeb(0, &dp2_ptr->u.ic.Status);
  776. writeb(0xff, &dp2_ptr->io.irqdel);
  777. if (prot_ver != PROTOCOL_VERSION) {
  778. printk("GDT-ISA: Illegal protocol version\n");
  779. iounmap(ha->brd);
  780. return 0;
  781. }
  782. ha->oem_id = OEM_ID_ICP;
  783. ha->type = GDT_ISA;
  784. ha->ic_all_size = sizeof(dp2_ptr->u);
  785. ha->stype= GDT2_ID;
  786. ha->brd_phys = bios_adr >> 4;
  787. /* special request to controller BIOS */
  788. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  789. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  790. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  791. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  792. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  793. writeb(0, &dp2_ptr->io.event);
  794. retries = INIT_RETRIES;
  795. gdth_delay(20);
  796. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  797. if (--retries == 0) {
  798. printk("GDT-ISA: Initialization error\n");
  799. iounmap(ha->brd);
  800. return 0;
  801. }
  802. gdth_delay(1);
  803. }
  804. writeb(0, &dp2_ptr->u.ic.Status);
  805. writeb(0xff, &dp2_ptr->io.irqdel);
  806. ha->dma64_support = 0;
  807. return 1;
  808. }
  809. #endif /* CONFIG_ISA */
  810. #ifdef CONFIG_PCI
  811. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  812. {
  813. register gdt6_dpram_str __iomem *dp6_ptr;
  814. register gdt6c_dpram_str __iomem *dp6c_ptr;
  815. register gdt6m_dpram_str __iomem *dp6m_ptr;
  816. ulong32 retries;
  817. unchar prot_ver;
  818. ushort command;
  819. int i, found = FALSE;
  820. TRACE(("gdth_init_pci()\n"));
  821. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  822. ha->oem_id = OEM_ID_INTEL;
  823. else
  824. ha->oem_id = OEM_ID_ICP;
  825. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  826. ha->stype = (ulong32)pcistr->pdev->device;
  827. ha->irq = pcistr->irq;
  828. ha->pdev = pcistr->pdev;
  829. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  830. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  831. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  832. if (ha->brd == NULL) {
  833. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  834. return 0;
  835. }
  836. /* check and reset interface area */
  837. dp6_ptr = ha->brd;
  838. writel(DPMEM_MAGIC, &dp6_ptr->u);
  839. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  840. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  841. pcistr->dpmem);
  842. found = FALSE;
  843. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  844. iounmap(ha->brd);
  845. ha->brd = ioremap(i, sizeof(ushort));
  846. if (ha->brd == NULL) {
  847. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  848. return 0;
  849. }
  850. if (readw(ha->brd) != 0xffff) {
  851. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  852. continue;
  853. }
  854. iounmap(ha->brd);
  855. pci_write_config_dword(pcistr->pdev,
  856. PCI_BASE_ADDRESS_0, i);
  857. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  858. if (ha->brd == NULL) {
  859. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  860. return 0;
  861. }
  862. dp6_ptr = ha->brd;
  863. writel(DPMEM_MAGIC, &dp6_ptr->u);
  864. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  865. printk("GDT-PCI: Use free address at 0x%x\n", i);
  866. found = TRUE;
  867. break;
  868. }
  869. }
  870. if (!found) {
  871. printk("GDT-PCI: No free address found!\n");
  872. iounmap(ha->brd);
  873. return 0;
  874. }
  875. }
  876. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  877. if (readl(&dp6_ptr->u) != 0) {
  878. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  879. iounmap(ha->brd);
  880. return 0;
  881. }
  882. /* disable board interrupts, deinit services */
  883. writeb(0xff, &dp6_ptr->io.irqdel);
  884. writeb(0x00, &dp6_ptr->io.irqen);
  885. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  886. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  887. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  888. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  889. writeb(0, &dp6_ptr->io.event);
  890. retries = INIT_RETRIES;
  891. gdth_delay(20);
  892. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  893. if (--retries == 0) {
  894. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  895. iounmap(ha->brd);
  896. return 0;
  897. }
  898. gdth_delay(1);
  899. }
  900. prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
  901. writeb(0, &dp6_ptr->u.ic.S_Status);
  902. writeb(0xff, &dp6_ptr->io.irqdel);
  903. if (prot_ver != PROTOCOL_VERSION) {
  904. printk("GDT-PCI: Illegal protocol version\n");
  905. iounmap(ha->brd);
  906. return 0;
  907. }
  908. ha->type = GDT_PCI;
  909. ha->ic_all_size = sizeof(dp6_ptr->u);
  910. /* special command to controller BIOS */
  911. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  912. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  913. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  914. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  915. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  916. writeb(0, &dp6_ptr->io.event);
  917. retries = INIT_RETRIES;
  918. gdth_delay(20);
  919. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  920. if (--retries == 0) {
  921. printk("GDT-PCI: Initialization error\n");
  922. iounmap(ha->brd);
  923. return 0;
  924. }
  925. gdth_delay(1);
  926. }
  927. writeb(0, &dp6_ptr->u.ic.S_Status);
  928. writeb(0xff, &dp6_ptr->io.irqdel);
  929. ha->dma64_support = 0;
  930. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  931. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  932. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  933. pcistr->dpmem,ha->irq));
  934. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  935. if (ha->brd == NULL) {
  936. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  937. iounmap(ha->brd);
  938. return 0;
  939. }
  940. /* check and reset interface area */
  941. dp6c_ptr = ha->brd;
  942. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  943. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  944. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  945. pcistr->dpmem);
  946. found = FALSE;
  947. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  948. iounmap(ha->brd);
  949. ha->brd = ioremap(i, sizeof(ushort));
  950. if (ha->brd == NULL) {
  951. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  952. return 0;
  953. }
  954. if (readw(ha->brd) != 0xffff) {
  955. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  956. continue;
  957. }
  958. iounmap(ha->brd);
  959. pci_write_config_dword(pcistr->pdev,
  960. PCI_BASE_ADDRESS_2, i);
  961. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  962. if (ha->brd == NULL) {
  963. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  964. return 0;
  965. }
  966. dp6c_ptr = ha->brd;
  967. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  968. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  969. printk("GDT-PCI: Use free address at 0x%x\n", i);
  970. found = TRUE;
  971. break;
  972. }
  973. }
  974. if (!found) {
  975. printk("GDT-PCI: No free address found!\n");
  976. iounmap(ha->brd);
  977. return 0;
  978. }
  979. }
  980. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  981. if (readl(&dp6c_ptr->u) != 0) {
  982. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  983. iounmap(ha->brd);
  984. return 0;
  985. }
  986. /* disable board interrupts, deinit services */
  987. outb(0x00,PTR2USHORT(&ha->plx->control1));
  988. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  989. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  990. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  991. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  992. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  993. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  994. retries = INIT_RETRIES;
  995. gdth_delay(20);
  996. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  997. if (--retries == 0) {
  998. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  999. iounmap(ha->brd);
  1000. return 0;
  1001. }
  1002. gdth_delay(1);
  1003. }
  1004. prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
  1005. writeb(0, &dp6c_ptr->u.ic.Status);
  1006. if (prot_ver != PROTOCOL_VERSION) {
  1007. printk("GDT-PCI: Illegal protocol version\n");
  1008. iounmap(ha->brd);
  1009. return 0;
  1010. }
  1011. ha->type = GDT_PCINEW;
  1012. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1013. /* special command to controller BIOS */
  1014. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1015. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1016. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1017. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1018. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1019. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1020. retries = INIT_RETRIES;
  1021. gdth_delay(20);
  1022. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1023. if (--retries == 0) {
  1024. printk("GDT-PCI: Initialization error\n");
  1025. iounmap(ha->brd);
  1026. return 0;
  1027. }
  1028. gdth_delay(1);
  1029. }
  1030. writeb(0, &dp6c_ptr->u.ic.S_Status);
  1031. ha->dma64_support = 0;
  1032. } else { /* MPR */
  1033. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1034. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1035. if (ha->brd == NULL) {
  1036. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1037. return 0;
  1038. }
  1039. /* manipulate config. space to enable DPMEM, start RP controller */
  1040. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1041. command |= 6;
  1042. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1043. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1044. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1045. i = 0xFEFF0001UL;
  1046. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1047. gdth_delay(1);
  1048. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1049. pci_resource_start(pcistr->pdev, 8));
  1050. dp6m_ptr = ha->brd;
  1051. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1052. * Aditional check needed for Xscale based RAID controllers */
  1053. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1054. gdth_delay(1);
  1055. /* check and reset interface area */
  1056. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1057. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1058. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1059. pcistr->dpmem);
  1060. found = FALSE;
  1061. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1062. iounmap(ha->brd);
  1063. ha->brd = ioremap(i, sizeof(ushort));
  1064. if (ha->brd == NULL) {
  1065. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1066. return 0;
  1067. }
  1068. if (readw(ha->brd) != 0xffff) {
  1069. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1070. continue;
  1071. }
  1072. iounmap(ha->brd);
  1073. pci_write_config_dword(pcistr->pdev,
  1074. PCI_BASE_ADDRESS_0, i);
  1075. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1076. if (ha->brd == NULL) {
  1077. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1078. return 0;
  1079. }
  1080. dp6m_ptr = ha->brd;
  1081. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1082. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1083. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1084. found = TRUE;
  1085. break;
  1086. }
  1087. }
  1088. if (!found) {
  1089. printk("GDT-PCI: No free address found!\n");
  1090. iounmap(ha->brd);
  1091. return 0;
  1092. }
  1093. }
  1094. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1095. /* disable board interrupts, deinit services */
  1096. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1097. &dp6m_ptr->i960r.edoor_en_reg);
  1098. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1099. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1100. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1101. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1102. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1103. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1104. retries = INIT_RETRIES;
  1105. gdth_delay(20);
  1106. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1107. if (--retries == 0) {
  1108. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1109. iounmap(ha->brd);
  1110. return 0;
  1111. }
  1112. gdth_delay(1);
  1113. }
  1114. prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1115. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1116. if (prot_ver != PROTOCOL_VERSION) {
  1117. printk("GDT-PCI: Illegal protocol version\n");
  1118. iounmap(ha->brd);
  1119. return 0;
  1120. }
  1121. ha->type = GDT_PCIMPR;
  1122. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1123. /* special command to controller BIOS */
  1124. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1125. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1126. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1127. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1128. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1129. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1130. retries = INIT_RETRIES;
  1131. gdth_delay(20);
  1132. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1133. if (--retries == 0) {
  1134. printk("GDT-PCI: Initialization error\n");
  1135. iounmap(ha->brd);
  1136. return 0;
  1137. }
  1138. gdth_delay(1);
  1139. }
  1140. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1141. /* read FW version to detect 64-bit DMA support */
  1142. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1143. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1144. retries = INIT_RETRIES;
  1145. gdth_delay(20);
  1146. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1147. if (--retries == 0) {
  1148. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1149. iounmap(ha->brd);
  1150. return 0;
  1151. }
  1152. gdth_delay(1);
  1153. }
  1154. prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1155. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1156. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1157. ha->dma64_support = 0;
  1158. else
  1159. ha->dma64_support = 1;
  1160. }
  1161. return 1;
  1162. }
  1163. #endif /* CONFIG_PCI */
  1164. /* controller protocol functions */
  1165. static void __init gdth_enable_int(gdth_ha_str *ha)
  1166. {
  1167. ulong flags;
  1168. gdt2_dpram_str __iomem *dp2_ptr;
  1169. gdt6_dpram_str __iomem *dp6_ptr;
  1170. gdt6m_dpram_str __iomem *dp6m_ptr;
  1171. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1172. spin_lock_irqsave(&ha->smp_lock, flags);
  1173. if (ha->type == GDT_EISA) {
  1174. outb(0xff, ha->bmic + EDOORREG);
  1175. outb(0xff, ha->bmic + EDENABREG);
  1176. outb(0x01, ha->bmic + EINTENABREG);
  1177. } else if (ha->type == GDT_ISA) {
  1178. dp2_ptr = ha->brd;
  1179. writeb(1, &dp2_ptr->io.irqdel);
  1180. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1181. writeb(1, &dp2_ptr->io.irqen);
  1182. } else if (ha->type == GDT_PCI) {
  1183. dp6_ptr = ha->brd;
  1184. writeb(1, &dp6_ptr->io.irqdel);
  1185. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1186. writeb(1, &dp6_ptr->io.irqen);
  1187. } else if (ha->type == GDT_PCINEW) {
  1188. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1189. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1190. } else if (ha->type == GDT_PCIMPR) {
  1191. dp6m_ptr = ha->brd;
  1192. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1193. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1194. &dp6m_ptr->i960r.edoor_en_reg);
  1195. }
  1196. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1197. }
  1198. /* return IStatus if interrupt was from this card else 0 */
  1199. static unchar gdth_get_status(gdth_ha_str *ha, int irq)
  1200. {
  1201. unchar IStatus = 0;
  1202. TRACE(("gdth_get_status() irq %d ctr_count %d\n", irq, gdth_ctr_count));
  1203. if (ha->irq != (unchar)irq) /* check IRQ */
  1204. return false;
  1205. if (ha->type == GDT_EISA)
  1206. IStatus = inb((ushort)ha->bmic + EDOORREG);
  1207. else if (ha->type == GDT_ISA)
  1208. IStatus =
  1209. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1210. else if (ha->type == GDT_PCI)
  1211. IStatus =
  1212. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1213. else if (ha->type == GDT_PCINEW)
  1214. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1215. else if (ha->type == GDT_PCIMPR)
  1216. IStatus =
  1217. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1218. return IStatus;
  1219. }
  1220. static int gdth_test_busy(gdth_ha_str *ha)
  1221. {
  1222. register int gdtsema0 = 0;
  1223. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1224. if (ha->type == GDT_EISA)
  1225. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1226. else if (ha->type == GDT_ISA)
  1227. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1228. else if (ha->type == GDT_PCI)
  1229. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1230. else if (ha->type == GDT_PCINEW)
  1231. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1232. else if (ha->type == GDT_PCIMPR)
  1233. gdtsema0 =
  1234. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1235. return (gdtsema0 & 1);
  1236. }
  1237. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1238. {
  1239. int i;
  1240. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1241. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1242. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1243. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1244. ha->cmd_tab[i].service = ha->pccb->Service;
  1245. ha->pccb->CommandIndex = (ulong32)i+2;
  1246. return (i+2);
  1247. }
  1248. }
  1249. return 0;
  1250. }
  1251. static void gdth_set_sema0(gdth_ha_str *ha)
  1252. {
  1253. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1254. if (ha->type == GDT_EISA) {
  1255. outb(1, ha->bmic + SEMA0REG);
  1256. } else if (ha->type == GDT_ISA) {
  1257. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1258. } else if (ha->type == GDT_PCI) {
  1259. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1260. } else if (ha->type == GDT_PCINEW) {
  1261. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1262. } else if (ha->type == GDT_PCIMPR) {
  1263. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1264. }
  1265. }
  1266. static void gdth_copy_command(gdth_ha_str *ha)
  1267. {
  1268. register gdth_cmd_str *cmd_ptr;
  1269. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1270. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1271. gdt6_dpram_str __iomem *dp6_ptr;
  1272. gdt2_dpram_str __iomem *dp2_ptr;
  1273. ushort cp_count,dp_offset,cmd_no;
  1274. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1275. cp_count = ha->cmd_len;
  1276. dp_offset= ha->cmd_offs_dpmem;
  1277. cmd_no = ha->cmd_cnt;
  1278. cmd_ptr = ha->pccb;
  1279. ++ha->cmd_cnt;
  1280. if (ha->type == GDT_EISA)
  1281. return; /* no DPMEM, no copy */
  1282. /* set cpcount dword aligned */
  1283. if (cp_count & 3)
  1284. cp_count += (4 - (cp_count & 3));
  1285. ha->cmd_offs_dpmem += cp_count;
  1286. /* set offset and service, copy command to DPMEM */
  1287. if (ha->type == GDT_ISA) {
  1288. dp2_ptr = ha->brd;
  1289. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1290. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1291. writew((ushort)cmd_ptr->Service,
  1292. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1293. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1294. } else if (ha->type == GDT_PCI) {
  1295. dp6_ptr = ha->brd;
  1296. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1297. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1298. writew((ushort)cmd_ptr->Service,
  1299. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1300. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1301. } else if (ha->type == GDT_PCINEW) {
  1302. dp6c_ptr = ha->brd;
  1303. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1304. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1305. writew((ushort)cmd_ptr->Service,
  1306. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1307. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1308. } else if (ha->type == GDT_PCIMPR) {
  1309. dp6m_ptr = ha->brd;
  1310. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1311. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1312. writew((ushort)cmd_ptr->Service,
  1313. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1314. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1315. }
  1316. }
  1317. static void gdth_release_event(gdth_ha_str *ha)
  1318. {
  1319. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1320. #ifdef GDTH_STATISTICS
  1321. {
  1322. ulong32 i,j;
  1323. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1324. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1325. ++i;
  1326. }
  1327. if (max_index < i) {
  1328. max_index = i;
  1329. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1330. }
  1331. }
  1332. #endif
  1333. if (ha->pccb->OpCode == GDT_INIT)
  1334. ha->pccb->Service |= 0x80;
  1335. if (ha->type == GDT_EISA) {
  1336. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1337. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1338. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1339. } else if (ha->type == GDT_ISA) {
  1340. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1341. } else if (ha->type == GDT_PCI) {
  1342. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1343. } else if (ha->type == GDT_PCINEW) {
  1344. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1345. } else if (ha->type == GDT_PCIMPR) {
  1346. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1347. }
  1348. }
  1349. static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
  1350. {
  1351. int answer_found = FALSE;
  1352. int wait_index = 0;
  1353. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1354. if (index == 0)
  1355. return 1; /* no wait required */
  1356. do {
  1357. __gdth_interrupt(ha, (int)ha->irq, true, &wait_index);
  1358. if (wait_index == index) {
  1359. answer_found = TRUE;
  1360. break;
  1361. }
  1362. gdth_delay(1);
  1363. } while (--time);
  1364. while (gdth_test_busy(ha))
  1365. gdth_delay(0);
  1366. return (answer_found);
  1367. }
  1368. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  1369. ulong32 p1, ulong64 p2, ulong64 p3)
  1370. {
  1371. register gdth_cmd_str *cmd_ptr;
  1372. int retries,index;
  1373. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1374. cmd_ptr = ha->pccb;
  1375. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1376. /* make command */
  1377. for (retries = INIT_RETRIES;;) {
  1378. cmd_ptr->Service = service;
  1379. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1380. if (!(index=gdth_get_cmd_index(ha))) {
  1381. TRACE(("GDT: No free command index found\n"));
  1382. return 0;
  1383. }
  1384. gdth_set_sema0(ha);
  1385. cmd_ptr->OpCode = opcode;
  1386. cmd_ptr->BoardNode = LOCALBOARD;
  1387. if (service == CACHESERVICE) {
  1388. if (opcode == GDT_IOCTL) {
  1389. cmd_ptr->u.ioctl.subfunc = p1;
  1390. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1391. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1392. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1393. } else {
  1394. if (ha->cache_feat & GDT_64BIT) {
  1395. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1396. cmd_ptr->u.cache64.BlockNo = p2;
  1397. } else {
  1398. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1399. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1400. }
  1401. }
  1402. } else if (service == SCSIRAWSERVICE) {
  1403. if (ha->raw_feat & GDT_64BIT) {
  1404. cmd_ptr->u.raw64.direction = p1;
  1405. cmd_ptr->u.raw64.bus = (unchar)p2;
  1406. cmd_ptr->u.raw64.target = (unchar)p3;
  1407. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1408. } else {
  1409. cmd_ptr->u.raw.direction = p1;
  1410. cmd_ptr->u.raw.bus = (unchar)p2;
  1411. cmd_ptr->u.raw.target = (unchar)p3;
  1412. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1413. }
  1414. } else if (service == SCREENSERVICE) {
  1415. if (opcode == GDT_REALTIME) {
  1416. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1417. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1418. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1419. }
  1420. }
  1421. ha->cmd_len = sizeof(gdth_cmd_str);
  1422. ha->cmd_offs_dpmem = 0;
  1423. ha->cmd_cnt = 0;
  1424. gdth_copy_command(ha);
  1425. gdth_release_event(ha);
  1426. gdth_delay(20);
  1427. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1428. printk("GDT: Initialization error (timeout service %d)\n",service);
  1429. return 0;
  1430. }
  1431. if (ha->status != S_BSY || --retries == 0)
  1432. break;
  1433. gdth_delay(1);
  1434. }
  1435. return (ha->status != S_OK ? 0:1);
  1436. }
  1437. /* search for devices */
  1438. static int __init gdth_search_drives(gdth_ha_str *ha)
  1439. {
  1440. ushort cdev_cnt, i;
  1441. int ok;
  1442. ulong32 bus_no, drv_cnt, drv_no, j;
  1443. gdth_getch_str *chn;
  1444. gdth_drlist_str *drl;
  1445. gdth_iochan_str *ioc;
  1446. gdth_raw_iochan_str *iocr;
  1447. gdth_arcdl_str *alst;
  1448. gdth_alist_str *alst2;
  1449. gdth_oem_str_ioctl *oemstr;
  1450. #ifdef INT_COAL
  1451. gdth_perf_modes *pmod;
  1452. #endif
  1453. #ifdef GDTH_RTC
  1454. unchar rtc[12];
  1455. ulong flags;
  1456. #endif
  1457. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1458. ok = 0;
  1459. /* initialize controller services, at first: screen service */
  1460. ha->screen_feat = 0;
  1461. if (!force_dma32) {
  1462. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1463. if (ok)
  1464. ha->screen_feat = GDT_64BIT;
  1465. }
  1466. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1467. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1468. if (!ok) {
  1469. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1470. ha->hanum, ha->status);
  1471. return 0;
  1472. }
  1473. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1474. #ifdef GDTH_RTC
  1475. /* read realtime clock info, send to controller */
  1476. /* 1. wait for the falling edge of update flag */
  1477. spin_lock_irqsave(&rtc_lock, flags);
  1478. for (j = 0; j < 1000000; ++j)
  1479. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1480. break;
  1481. for (j = 0; j < 1000000; ++j)
  1482. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1483. break;
  1484. /* 2. read info */
  1485. do {
  1486. for (j = 0; j < 12; ++j)
  1487. rtc[j] = CMOS_READ(j);
  1488. } while (rtc[0] != CMOS_READ(0));
  1489. spin_unlock_irqrestore(&rtc_lock, flags);
  1490. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1491. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1492. /* 3. send to controller firmware */
  1493. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
  1494. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1495. #endif
  1496. /* unfreeze all IOs */
  1497. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1498. /* initialize cache service */
  1499. ha->cache_feat = 0;
  1500. if (!force_dma32) {
  1501. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1502. 0, 0);
  1503. if (ok)
  1504. ha->cache_feat = GDT_64BIT;
  1505. }
  1506. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1507. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1508. if (!ok) {
  1509. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1510. ha->hanum, ha->status);
  1511. return 0;
  1512. }
  1513. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1514. cdev_cnt = (ushort)ha->info;
  1515. ha->fw_vers = ha->service;
  1516. #ifdef INT_COAL
  1517. if (ha->type == GDT_PCIMPR) {
  1518. /* set perf. modes */
  1519. pmod = (gdth_perf_modes *)ha->pscratch;
  1520. pmod->version = 1;
  1521. pmod->st_mode = 1; /* enable one status buffer */
  1522. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1523. pmod->st_buff_indx1 = COALINDEX;
  1524. pmod->st_buff_addr2 = 0;
  1525. pmod->st_buff_u_addr2 = 0;
  1526. pmod->st_buff_indx2 = 0;
  1527. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1528. pmod->cmd_mode = 0; // disable all cmd buffers
  1529. pmod->cmd_buff_addr1 = 0;
  1530. pmod->cmd_buff_u_addr1 = 0;
  1531. pmod->cmd_buff_indx1 = 0;
  1532. pmod->cmd_buff_addr2 = 0;
  1533. pmod->cmd_buff_u_addr2 = 0;
  1534. pmod->cmd_buff_indx2 = 0;
  1535. pmod->cmd_buff_size = 0;
  1536. pmod->reserved1 = 0;
  1537. pmod->reserved2 = 0;
  1538. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1539. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1540. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1541. }
  1542. }
  1543. #endif
  1544. /* detect number of buses - try new IOCTL */
  1545. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1546. iocr->hdr.version = 0xffffffff;
  1547. iocr->hdr.list_entries = MAXBUS;
  1548. iocr->hdr.first_chan = 0;
  1549. iocr->hdr.last_chan = MAXBUS-1;
  1550. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1551. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1552. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1553. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1554. ha->bus_cnt = iocr->hdr.chan_count;
  1555. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1556. if (iocr->list[bus_no].proc_id < MAXID)
  1557. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1558. else
  1559. ha->bus_id[bus_no] = 0xff;
  1560. }
  1561. } else {
  1562. /* old method */
  1563. chn = (gdth_getch_str *)ha->pscratch;
  1564. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1565. chn->channel_no = bus_no;
  1566. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1567. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1568. IO_CHANNEL | INVALID_CHANNEL,
  1569. sizeof(gdth_getch_str))) {
  1570. if (bus_no == 0) {
  1571. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1572. ha->hanum, ha->status);
  1573. return 0;
  1574. }
  1575. break;
  1576. }
  1577. if (chn->siop_id < MAXID)
  1578. ha->bus_id[bus_no] = chn->siop_id;
  1579. else
  1580. ha->bus_id[bus_no] = 0xff;
  1581. }
  1582. ha->bus_cnt = (unchar)bus_no;
  1583. }
  1584. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1585. /* read cache configuration */
  1586. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1587. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1588. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1589. ha->hanum, ha->status);
  1590. return 0;
  1591. }
  1592. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1593. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1594. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1595. ha->cpar.write_back,ha->cpar.block_size));
  1596. /* read board info and features */
  1597. ha->more_proc = FALSE;
  1598. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1599. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1600. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1601. sizeof(gdth_binfo_str));
  1602. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1603. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1604. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1605. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1606. ha->more_proc = TRUE;
  1607. }
  1608. } else {
  1609. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1610. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1611. }
  1612. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1613. /* read more informations */
  1614. if (ha->more_proc) {
  1615. /* physical drives, channel addresses */
  1616. ioc = (gdth_iochan_str *)ha->pscratch;
  1617. ioc->hdr.version = 0xffffffff;
  1618. ioc->hdr.list_entries = MAXBUS;
  1619. ioc->hdr.first_chan = 0;
  1620. ioc->hdr.last_chan = MAXBUS-1;
  1621. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1622. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1623. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1624. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1625. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1626. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1627. }
  1628. } else {
  1629. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1630. ha->raw[bus_no].address = IO_CHANNEL;
  1631. ha->raw[bus_no].local_no = bus_no;
  1632. }
  1633. }
  1634. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1635. chn = (gdth_getch_str *)ha->pscratch;
  1636. chn->channel_no = ha->raw[bus_no].local_no;
  1637. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1638. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1639. ha->raw[bus_no].address | INVALID_CHANNEL,
  1640. sizeof(gdth_getch_str))) {
  1641. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1642. TRACE2(("Channel %d: %d phys. drives\n",
  1643. bus_no,chn->drive_cnt));
  1644. }
  1645. if (ha->raw[bus_no].pdev_cnt > 0) {
  1646. drl = (gdth_drlist_str *)ha->pscratch;
  1647. drl->sc_no = ha->raw[bus_no].local_no;
  1648. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1649. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1650. SCSI_DR_LIST | L_CTRL_PATTERN,
  1651. ha->raw[bus_no].address | INVALID_CHANNEL,
  1652. sizeof(gdth_drlist_str))) {
  1653. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1654. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1655. } else {
  1656. ha->raw[bus_no].pdev_cnt = 0;
  1657. }
  1658. }
  1659. }
  1660. /* logical drives */
  1661. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1662. INVALID_CHANNEL,sizeof(ulong32))) {
  1663. drv_cnt = *(ulong32 *)ha->pscratch;
  1664. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1665. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1666. for (j = 0; j < drv_cnt; ++j) {
  1667. drv_no = ((ulong32 *)ha->pscratch)[j];
  1668. if (drv_no < MAX_LDRIVES) {
  1669. ha->hdr[drv_no].is_logdrv = TRUE;
  1670. TRACE2(("Drive %d is log. drive\n",drv_no));
  1671. }
  1672. }
  1673. }
  1674. alst = (gdth_arcdl_str *)ha->pscratch;
  1675. alst->entries_avail = MAX_LDRIVES;
  1676. alst->first_entry = 0;
  1677. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1678. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1679. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1680. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1681. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1682. for (j = 0; j < alst->entries_init; ++j) {
  1683. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1684. ha->hdr[j].is_master = alst->list[j].is_master;
  1685. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1686. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1687. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1688. }
  1689. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1690. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1691. 0, 35 * sizeof(gdth_alist_str))) {
  1692. for (j = 0; j < 35; ++j) {
  1693. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1694. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1695. ha->hdr[j].is_master = alst2->is_master;
  1696. ha->hdr[j].is_parity = alst2->is_parity;
  1697. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1698. ha->hdr[j].master_no = alst2->cd_handle;
  1699. }
  1700. }
  1701. }
  1702. }
  1703. /* initialize raw service */
  1704. ha->raw_feat = 0;
  1705. if (!force_dma32) {
  1706. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1707. if (ok)
  1708. ha->raw_feat = GDT_64BIT;
  1709. }
  1710. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1711. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1712. if (!ok) {
  1713. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1714. ha->hanum, ha->status);
  1715. return 0;
  1716. }
  1717. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1718. /* set/get features raw service (scatter/gather) */
  1719. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1720. 0, 0)) {
  1721. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1722. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1723. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1724. ha->info));
  1725. ha->raw_feat |= (ushort)ha->info;
  1726. }
  1727. }
  1728. /* set/get features cache service (equal to raw service) */
  1729. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1730. SCATTER_GATHER,0)) {
  1731. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1732. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1733. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1734. ha->info));
  1735. ha->cache_feat |= (ushort)ha->info;
  1736. }
  1737. }
  1738. /* reserve drives for raw service */
  1739. if (reserve_mode != 0) {
  1740. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1741. reserve_mode == 1 ? 1 : 3, 0, 0);
  1742. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1743. ha->status));
  1744. }
  1745. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1746. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1747. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1748. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1749. reserve_list[i], reserve_list[i+1],
  1750. reserve_list[i+2], reserve_list[i+3]));
  1751. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1752. reserve_list[i+1], reserve_list[i+2] |
  1753. (reserve_list[i+3] << 8))) {
  1754. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1755. ha->hanum, ha->status);
  1756. }
  1757. }
  1758. }
  1759. /* Determine OEM string using IOCTL */
  1760. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1761. oemstr->params.ctl_version = 0x01;
  1762. oemstr->params.buffer_size = sizeof(oemstr->text);
  1763. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1764. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1765. sizeof(gdth_oem_str_ioctl))) {
  1766. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1767. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1768. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1769. /* Save the Host Drive inquiry data */
  1770. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1771. sizeof(ha->oem_name));
  1772. } else {
  1773. /* Old method, based on PCI ID */
  1774. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1775. printk("GDT-HA %d: Name: %s\n",
  1776. ha->hanum, ha->binfo.type_string);
  1777. if (ha->oem_id == OEM_ID_INTEL)
  1778. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1779. else
  1780. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1781. }
  1782. /* scanning for host drives */
  1783. for (i = 0; i < cdev_cnt; ++i)
  1784. gdth_analyse_hdrive(ha, i);
  1785. TRACE(("gdth_search_drives() OK\n"));
  1786. return 1;
  1787. }
  1788. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
  1789. {
  1790. ulong32 drv_cyls;
  1791. int drv_hds, drv_secs;
  1792. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1793. if (hdrive >= MAX_HDRIVES)
  1794. return 0;
  1795. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1796. return 0;
  1797. ha->hdr[hdrive].present = TRUE;
  1798. ha->hdr[hdrive].size = ha->info;
  1799. /* evaluate mapping (sectors per head, heads per cylinder) */
  1800. ha->hdr[hdrive].size &= ~SECS32;
  1801. if (ha->info2 == 0) {
  1802. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1803. } else {
  1804. drv_hds = ha->info2 & 0xff;
  1805. drv_secs = (ha->info2 >> 8) & 0xff;
  1806. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1807. }
  1808. ha->hdr[hdrive].heads = (unchar)drv_hds;
  1809. ha->hdr[hdrive].secs = (unchar)drv_secs;
  1810. /* round size */
  1811. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1812. if (ha->cache_feat & GDT_64BIT) {
  1813. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1814. && ha->info2 != 0) {
  1815. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  1816. }
  1817. }
  1818. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1819. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1820. /* get informations about device */
  1821. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1822. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1823. hdrive,ha->info));
  1824. ha->hdr[hdrive].devtype = (ushort)ha->info;
  1825. }
  1826. /* cluster info */
  1827. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1828. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1829. hdrive,ha->info));
  1830. if (!shared_access)
  1831. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  1832. }
  1833. /* R/W attributes */
  1834. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1835. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1836. hdrive,ha->info));
  1837. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  1838. }
  1839. return 1;
  1840. }
  1841. /* command queueing/sending functions */
  1842. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
  1843. {
  1844. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1845. register Scsi_Cmnd *pscp;
  1846. register Scsi_Cmnd *nscp;
  1847. ulong flags;
  1848. unchar b, t;
  1849. TRACE(("gdth_putq() priority %d\n",priority));
  1850. spin_lock_irqsave(&ha->smp_lock, flags);
  1851. if (!cmndinfo->internal_command) {
  1852. cmndinfo->priority = priority;
  1853. b = scp->device->channel;
  1854. t = scp->device->id;
  1855. if (priority >= DEFAULT_PRI) {
  1856. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1857. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  1858. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  1859. cmndinfo->timeout = gdth_update_timeout(scp, 0);
  1860. }
  1861. }
  1862. }
  1863. if (ha->req_first==NULL) {
  1864. ha->req_first = scp; /* queue was empty */
  1865. scp->SCp.ptr = NULL;
  1866. } else { /* queue not empty */
  1867. pscp = ha->req_first;
  1868. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1869. /* priority: 0-highest,..,0xff-lowest */
  1870. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1871. pscp = nscp;
  1872. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1873. }
  1874. pscp->SCp.ptr = (char *)scp;
  1875. scp->SCp.ptr = (char *)nscp;
  1876. }
  1877. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1878. #ifdef GDTH_STATISTICS
  1879. flags = 0;
  1880. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1881. ++flags;
  1882. if (max_rq < flags) {
  1883. max_rq = flags;
  1884. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  1885. }
  1886. #endif
  1887. }
  1888. static void gdth_next(gdth_ha_str *ha)
  1889. {
  1890. register Scsi_Cmnd *pscp;
  1891. register Scsi_Cmnd *nscp;
  1892. unchar b, t, l, firsttime;
  1893. unchar this_cmd, next_cmd;
  1894. ulong flags = 0;
  1895. int cmd_index;
  1896. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1897. if (!gdth_polling)
  1898. spin_lock_irqsave(&ha->smp_lock, flags);
  1899. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1900. this_cmd = firsttime = TRUE;
  1901. next_cmd = gdth_polling ? FALSE:TRUE;
  1902. cmd_index = 0;
  1903. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1904. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1905. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1906. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1907. if (!nscp_cmndinfo->internal_command) {
  1908. b = nscp->device->channel;
  1909. t = nscp->device->id;
  1910. l = nscp->device->lun;
  1911. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1912. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1913. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1914. continue;
  1915. }
  1916. } else
  1917. b = t = l = 0;
  1918. if (firsttime) {
  1919. if (gdth_test_busy(ha)) { /* controller busy ? */
  1920. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1921. if (!gdth_polling) {
  1922. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1923. return;
  1924. }
  1925. while (gdth_test_busy(ha))
  1926. gdth_delay(1);
  1927. }
  1928. firsttime = FALSE;
  1929. }
  1930. if (!nscp_cmndinfo->internal_command) {
  1931. if (nscp_cmndinfo->phase == -1) {
  1932. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1933. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1934. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1935. b, t, l));
  1936. /* TEST_UNIT_READY -> set scan mode */
  1937. if ((ha->scan_mode & 0x0f) == 0) {
  1938. if (b == 0 && t == 0 && l == 0) {
  1939. ha->scan_mode |= 1;
  1940. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1941. }
  1942. } else if ((ha->scan_mode & 0x0f) == 1) {
  1943. if (b == 0 && ((t == 0 && l == 1) ||
  1944. (t == 1 && l == 0))) {
  1945. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1946. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1947. | SCSIRAWSERVICE;
  1948. ha->scan_mode = 0x12;
  1949. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1950. ha->scan_mode));
  1951. } else {
  1952. ha->scan_mode &= 0x10;
  1953. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1954. }
  1955. } else if (ha->scan_mode == 0x12) {
  1956. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1957. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1958. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1959. ha->scan_mode &= 0x10;
  1960. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1961. ha->scan_mode));
  1962. }
  1963. }
  1964. }
  1965. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1966. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1967. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1968. /* always GDT_CLUST_INFO! */
  1969. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1970. }
  1971. }
  1972. }
  1973. if (nscp_cmndinfo->OpCode != -1) {
  1974. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1975. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1976. this_cmd = FALSE;
  1977. next_cmd = FALSE;
  1978. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1979. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1980. this_cmd = FALSE;
  1981. next_cmd = FALSE;
  1982. } else {
  1983. memset((char*)nscp->sense_buffer,0,16);
  1984. nscp->sense_buffer[0] = 0x70;
  1985. nscp->sense_buffer[2] = NOT_READY;
  1986. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1987. if (!nscp_cmndinfo->wait_for_completion)
  1988. nscp_cmndinfo->wait_for_completion++;
  1989. else
  1990. gdth_scsi_done(nscp);
  1991. }
  1992. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1993. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1994. this_cmd = FALSE;
  1995. next_cmd = FALSE;
  1996. } else if (b != ha->virt_bus) {
  1997. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1998. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1999. this_cmd = FALSE;
  2000. else
  2001. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  2002. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2003. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2004. nscp->cmnd[0], b, t, l));
  2005. nscp->result = DID_BAD_TARGET << 16;
  2006. if (!nscp_cmndinfo->wait_for_completion)
  2007. nscp_cmndinfo->wait_for_completion++;
  2008. else
  2009. gdth_scsi_done(nscp);
  2010. } else {
  2011. switch (nscp->cmnd[0]) {
  2012. case TEST_UNIT_READY:
  2013. case INQUIRY:
  2014. case REQUEST_SENSE:
  2015. case READ_CAPACITY:
  2016. case VERIFY:
  2017. case START_STOP:
  2018. case MODE_SENSE:
  2019. case SERVICE_ACTION_IN:
  2020. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2021. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2022. nscp->cmnd[4],nscp->cmnd[5]));
  2023. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2024. /* return UNIT_ATTENTION */
  2025. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2026. nscp->cmnd[0], t));
  2027. ha->hdr[t].media_changed = FALSE;
  2028. memset((char*)nscp->sense_buffer,0,16);
  2029. nscp->sense_buffer[0] = 0x70;
  2030. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2031. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2032. if (!nscp_cmndinfo->wait_for_completion)
  2033. nscp_cmndinfo->wait_for_completion++;
  2034. else
  2035. gdth_scsi_done(nscp);
  2036. } else if (gdth_internal_cache_cmd(ha, nscp))
  2037. gdth_scsi_done(nscp);
  2038. break;
  2039. case ALLOW_MEDIUM_REMOVAL:
  2040. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2041. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2042. nscp->cmnd[4],nscp->cmnd[5]));
  2043. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2044. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2045. nscp->result = DID_OK << 16;
  2046. nscp->sense_buffer[0] = 0;
  2047. if (!nscp_cmndinfo->wait_for_completion)
  2048. nscp_cmndinfo->wait_for_completion++;
  2049. else
  2050. gdth_scsi_done(nscp);
  2051. } else {
  2052. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2053. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2054. nscp->cmnd[4],nscp->cmnd[3]));
  2055. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2056. this_cmd = FALSE;
  2057. }
  2058. break;
  2059. case RESERVE:
  2060. case RELEASE:
  2061. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2062. "RESERVE" : "RELEASE"));
  2063. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2064. this_cmd = FALSE;
  2065. break;
  2066. case READ_6:
  2067. case WRITE_6:
  2068. case READ_10:
  2069. case WRITE_10:
  2070. case READ_16:
  2071. case WRITE_16:
  2072. if (ha->hdr[t].media_changed) {
  2073. /* return UNIT_ATTENTION */
  2074. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2075. nscp->cmnd[0], t));
  2076. ha->hdr[t].media_changed = FALSE;
  2077. memset((char*)nscp->sense_buffer,0,16);
  2078. nscp->sense_buffer[0] = 0x70;
  2079. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2080. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2081. if (!nscp_cmndinfo->wait_for_completion)
  2082. nscp_cmndinfo->wait_for_completion++;
  2083. else
  2084. gdth_scsi_done(nscp);
  2085. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2086. this_cmd = FALSE;
  2087. break;
  2088. default:
  2089. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2090. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2091. nscp->cmnd[4],nscp->cmnd[5]));
  2092. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2093. ha->hanum, nscp->cmnd[0]);
  2094. nscp->result = DID_ABORT << 16;
  2095. if (!nscp_cmndinfo->wait_for_completion)
  2096. nscp_cmndinfo->wait_for_completion++;
  2097. else
  2098. gdth_scsi_done(nscp);
  2099. break;
  2100. }
  2101. }
  2102. if (!this_cmd)
  2103. break;
  2104. if (nscp == ha->req_first)
  2105. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2106. else
  2107. pscp->SCp.ptr = nscp->SCp.ptr;
  2108. if (!next_cmd)
  2109. break;
  2110. }
  2111. if (ha->cmd_cnt > 0) {
  2112. gdth_release_event(ha);
  2113. }
  2114. if (!gdth_polling)
  2115. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2116. if (gdth_polling && ha->cmd_cnt > 0) {
  2117. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2118. printk("GDT-HA %d: Command %d timed out !\n",
  2119. ha->hanum, cmd_index);
  2120. }
  2121. }
  2122. /*
  2123. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2124. * buffers, kmap_atomic() as needed.
  2125. */
  2126. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2127. char *buffer, ushort count, int to_buffer)
  2128. {
  2129. ushort cpcount,i, max_sg = gdth_sg_count(scp);
  2130. ushort cpsum,cpnow;
  2131. struct scatterlist *sl;
  2132. char *address;
  2133. cpcount = min_t(ushort, count, gdth_bufflen(scp));
  2134. if (cpcount) {
  2135. cpsum=0;
  2136. scsi_for_each_sg(scp, sl, max_sg, i) {
  2137. unsigned long flags;
  2138. cpnow = (ushort)sl->length;
  2139. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2140. cpnow, cpsum, cpcount, gdth_bufflen(scp)));
  2141. if (cpsum+cpnow > cpcount)
  2142. cpnow = cpcount - cpsum;
  2143. cpsum += cpnow;
  2144. if (!sl->page) {
  2145. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2146. ha->hanum);
  2147. return;
  2148. }
  2149. local_irq_save(flags);
  2150. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2151. if (to_buffer)
  2152. memcpy(buffer, address, cpnow);
  2153. else
  2154. memcpy(address, buffer, cpnow);
  2155. flush_dcache_page(sl->page);
  2156. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2157. local_irq_restore(flags);
  2158. if (cpsum == cpcount)
  2159. break;
  2160. buffer += cpnow;
  2161. }
  2162. } else if (count) {
  2163. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2164. ha->hanum);
  2165. WARN_ON(1);
  2166. }
  2167. }
  2168. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2169. {
  2170. unchar t;
  2171. gdth_inq_data inq;
  2172. gdth_rdcap_data rdc;
  2173. gdth_sense_data sd;
  2174. gdth_modep_data mpd;
  2175. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2176. t = scp->device->id;
  2177. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2178. scp->cmnd[0],t));
  2179. scp->result = DID_OK << 16;
  2180. scp->sense_buffer[0] = 0;
  2181. switch (scp->cmnd[0]) {
  2182. case TEST_UNIT_READY:
  2183. case VERIFY:
  2184. case START_STOP:
  2185. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2186. break;
  2187. case INQUIRY:
  2188. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2189. t,ha->hdr[t].devtype));
  2190. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2191. /* you can here set all disks to removable, if you want to do
  2192. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2193. inq.modif_rmb = 0x00;
  2194. if ((ha->hdr[t].devtype & 1) ||
  2195. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2196. inq.modif_rmb = 0x80;
  2197. inq.version = 2;
  2198. inq.resp_aenc = 2;
  2199. inq.add_length= 32;
  2200. strcpy(inq.vendor,ha->oem_name);
  2201. sprintf(inq.product,"Host Drive #%02d",t);
  2202. strcpy(inq.revision," ");
  2203. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data), 0);
  2204. break;
  2205. case REQUEST_SENSE:
  2206. TRACE2(("Request sense hdrive %d\n",t));
  2207. sd.errorcode = 0x70;
  2208. sd.segno = 0x00;
  2209. sd.key = NO_SENSE;
  2210. sd.info = 0;
  2211. sd.add_length= 0;
  2212. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data), 0);
  2213. break;
  2214. case MODE_SENSE:
  2215. TRACE2(("Mode sense hdrive %d\n",t));
  2216. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2217. mpd.hd.data_length = sizeof(gdth_modep_data);
  2218. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2219. mpd.hd.bd_length = sizeof(mpd.bd);
  2220. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2221. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2222. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2223. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data), 0);
  2224. break;
  2225. case READ_CAPACITY:
  2226. TRACE2(("Read capacity hdrive %d\n",t));
  2227. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2228. rdc.last_block_no = 0xffffffff;
  2229. else
  2230. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2231. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2232. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data), 0);
  2233. break;
  2234. case SERVICE_ACTION_IN:
  2235. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2236. (ha->cache_feat & GDT_64BIT)) {
  2237. gdth_rdcap16_data rdc16;
  2238. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2239. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2240. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2241. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2242. sizeof(gdth_rdcap16_data), 0);
  2243. } else {
  2244. scp->result = DID_ABORT << 16;
  2245. }
  2246. break;
  2247. default:
  2248. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2249. break;
  2250. }
  2251. if (!cmndinfo->wait_for_completion)
  2252. cmndinfo->wait_for_completion++;
  2253. else
  2254. return 1;
  2255. return 0;
  2256. }
  2257. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
  2258. {
  2259. register gdth_cmd_str *cmdp;
  2260. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2261. ulong32 cnt, blockcnt;
  2262. ulong64 no, blockno;
  2263. int i, cmd_index, read_write, sgcnt, mode64;
  2264. cmdp = ha->pccb;
  2265. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2266. scp->cmnd[0],scp->cmd_len,hdrive));
  2267. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2268. return 0;
  2269. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2270. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2271. not required, should not occur due to error return on
  2272. READ_CAPACITY_16 */
  2273. cmdp->Service = CACHESERVICE;
  2274. cmdp->RequestBuffer = scp;
  2275. /* search free command index */
  2276. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2277. TRACE(("GDT: No free command index found\n"));
  2278. return 0;
  2279. }
  2280. /* if it's the first command, set command semaphore */
  2281. if (ha->cmd_cnt == 0)
  2282. gdth_set_sema0(ha);
  2283. /* fill command */
  2284. read_write = 0;
  2285. if (cmndinfo->OpCode != -1)
  2286. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2287. else if (scp->cmnd[0] == RESERVE)
  2288. cmdp->OpCode = GDT_RESERVE_DRV;
  2289. else if (scp->cmnd[0] == RELEASE)
  2290. cmdp->OpCode = GDT_RELEASE_DRV;
  2291. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2292. if (scp->cmnd[4] & 1) /* prevent ? */
  2293. cmdp->OpCode = GDT_MOUNT;
  2294. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2295. cmdp->OpCode = GDT_UNMOUNT;
  2296. else
  2297. cmdp->OpCode = GDT_FLUSH;
  2298. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2299. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2300. ) {
  2301. read_write = 1;
  2302. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2303. (ha->cache_feat & GDT_WR_THROUGH)))
  2304. cmdp->OpCode = GDT_WRITE_THR;
  2305. else
  2306. cmdp->OpCode = GDT_WRITE;
  2307. } else {
  2308. read_write = 2;
  2309. cmdp->OpCode = GDT_READ;
  2310. }
  2311. cmdp->BoardNode = LOCALBOARD;
  2312. if (mode64) {
  2313. cmdp->u.cache64.DeviceNo = hdrive;
  2314. cmdp->u.cache64.BlockNo = 1;
  2315. cmdp->u.cache64.sg_canz = 0;
  2316. } else {
  2317. cmdp->u.cache.DeviceNo = hdrive;
  2318. cmdp->u.cache.BlockNo = 1;
  2319. cmdp->u.cache.sg_canz = 0;
  2320. }
  2321. if (read_write) {
  2322. if (scp->cmd_len == 16) {
  2323. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2324. blockno = be64_to_cpu(no);
  2325. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2326. blockcnt = be32_to_cpu(cnt);
  2327. } else if (scp->cmd_len == 10) {
  2328. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2329. blockno = be32_to_cpu(no);
  2330. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2331. blockcnt = be16_to_cpu(cnt);
  2332. } else {
  2333. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2334. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2335. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2336. }
  2337. if (mode64) {
  2338. cmdp->u.cache64.BlockNo = blockno;
  2339. cmdp->u.cache64.BlockCnt = blockcnt;
  2340. } else {
  2341. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2342. cmdp->u.cache.BlockCnt = blockcnt;
  2343. }
  2344. if (gdth_bufflen(scp)) {
  2345. cmndinfo->dma_dir = (read_write == 1 ?
  2346. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2347. sgcnt = pci_map_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  2348. cmndinfo->dma_dir);
  2349. if (mode64) {
  2350. struct scatterlist *sl;
  2351. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2352. cmdp->u.cache64.sg_canz = sgcnt;
  2353. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2354. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2355. #ifdef GDTH_DMA_STATISTICS
  2356. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2357. ha->dma64_cnt++;
  2358. else
  2359. ha->dma32_cnt++;
  2360. #endif
  2361. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2362. }
  2363. } else {
  2364. struct scatterlist *sl;
  2365. cmdp->u.cache.DestAddr= 0xffffffff;
  2366. cmdp->u.cache.sg_canz = sgcnt;
  2367. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2368. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2369. #ifdef GDTH_DMA_STATISTICS
  2370. ha->dma32_cnt++;
  2371. #endif
  2372. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2373. }
  2374. }
  2375. #ifdef GDTH_STATISTICS
  2376. if (max_sg < (ulong32)sgcnt) {
  2377. max_sg = (ulong32)sgcnt;
  2378. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2379. }
  2380. #endif
  2381. }
  2382. }
  2383. /* evaluate command size, check space */
  2384. if (mode64) {
  2385. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2386. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2387. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2388. cmdp->u.cache64.sg_lst[0].sg_len));
  2389. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2390. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2391. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2392. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2393. } else {
  2394. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2395. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2396. cmdp->u.cache.sg_lst[0].sg_ptr,
  2397. cmdp->u.cache.sg_lst[0].sg_len));
  2398. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2399. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2400. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2401. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2402. }
  2403. if (ha->cmd_len & 3)
  2404. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2405. if (ha->cmd_cnt > 0) {
  2406. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2407. ha->ic_all_size) {
  2408. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2409. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2410. return 0;
  2411. }
  2412. }
  2413. /* copy command */
  2414. gdth_copy_command(ha);
  2415. return cmd_index;
  2416. }
  2417. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
  2418. {
  2419. register gdth_cmd_str *cmdp;
  2420. ushort i;
  2421. dma_addr_t sense_paddr;
  2422. int cmd_index, sgcnt, mode64;
  2423. unchar t,l;
  2424. struct page *page;
  2425. ulong offset;
  2426. struct gdth_cmndinfo *cmndinfo;
  2427. t = scp->device->id;
  2428. l = scp->device->lun;
  2429. cmdp = ha->pccb;
  2430. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2431. scp->cmnd[0],b,t,l));
  2432. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2433. return 0;
  2434. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2435. cmdp->Service = SCSIRAWSERVICE;
  2436. cmdp->RequestBuffer = scp;
  2437. /* search free command index */
  2438. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2439. TRACE(("GDT: No free command index found\n"));
  2440. return 0;
  2441. }
  2442. /* if it's the first command, set command semaphore */
  2443. if (ha->cmd_cnt == 0)
  2444. gdth_set_sema0(ha);
  2445. cmndinfo = gdth_cmnd_priv(scp);
  2446. /* fill command */
  2447. if (cmndinfo->OpCode != -1) {
  2448. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2449. cmdp->BoardNode = LOCALBOARD;
  2450. if (mode64) {
  2451. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2452. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2453. cmdp->OpCode, cmdp->u.raw64.direction));
  2454. /* evaluate command size */
  2455. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2456. } else {
  2457. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2458. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2459. cmdp->OpCode, cmdp->u.raw.direction));
  2460. /* evaluate command size */
  2461. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2462. }
  2463. } else {
  2464. page = virt_to_page(scp->sense_buffer);
  2465. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2466. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2467. 16,PCI_DMA_FROMDEVICE);
  2468. cmndinfo->sense_paddr = sense_paddr;
  2469. cmdp->OpCode = GDT_WRITE; /* always */
  2470. cmdp->BoardNode = LOCALBOARD;
  2471. if (mode64) {
  2472. cmdp->u.raw64.reserved = 0;
  2473. cmdp->u.raw64.mdisc_time = 0;
  2474. cmdp->u.raw64.mcon_time = 0;
  2475. cmdp->u.raw64.clen = scp->cmd_len;
  2476. cmdp->u.raw64.target = t;
  2477. cmdp->u.raw64.lun = l;
  2478. cmdp->u.raw64.bus = b;
  2479. cmdp->u.raw64.priority = 0;
  2480. cmdp->u.raw64.sdlen = gdth_bufflen(scp);
  2481. cmdp->u.raw64.sense_len = 16;
  2482. cmdp->u.raw64.sense_data = sense_paddr;
  2483. cmdp->u.raw64.direction =
  2484. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2485. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2486. cmdp->u.raw64.sg_ranz = 0;
  2487. } else {
  2488. cmdp->u.raw.reserved = 0;
  2489. cmdp->u.raw.mdisc_time = 0;
  2490. cmdp->u.raw.mcon_time = 0;
  2491. cmdp->u.raw.clen = scp->cmd_len;
  2492. cmdp->u.raw.target = t;
  2493. cmdp->u.raw.lun = l;
  2494. cmdp->u.raw.bus = b;
  2495. cmdp->u.raw.priority = 0;
  2496. cmdp->u.raw.link_p = 0;
  2497. cmdp->u.raw.sdlen = gdth_bufflen(scp);
  2498. cmdp->u.raw.sense_len = 16;
  2499. cmdp->u.raw.sense_data = sense_paddr;
  2500. cmdp->u.raw.direction =
  2501. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2502. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2503. cmdp->u.raw.sg_ranz = 0;
  2504. }
  2505. if (gdth_bufflen(scp)) {
  2506. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2507. sgcnt = pci_map_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  2508. cmndinfo->dma_dir);
  2509. if (mode64) {
  2510. struct scatterlist *sl;
  2511. cmdp->u.raw64.sdata = (ulong64)-1;
  2512. cmdp->u.raw64.sg_ranz = sgcnt;
  2513. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2514. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2515. #ifdef GDTH_DMA_STATISTICS
  2516. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2517. ha->dma64_cnt++;
  2518. else
  2519. ha->dma32_cnt++;
  2520. #endif
  2521. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2522. }
  2523. } else {
  2524. struct scatterlist *sl;
  2525. cmdp->u.raw.sdata = 0xffffffff;
  2526. cmdp->u.raw.sg_ranz = sgcnt;
  2527. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2528. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2529. #ifdef GDTH_DMA_STATISTICS
  2530. ha->dma32_cnt++;
  2531. #endif
  2532. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2533. }
  2534. }
  2535. #ifdef GDTH_STATISTICS
  2536. if (max_sg < sgcnt) {
  2537. max_sg = sgcnt;
  2538. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2539. }
  2540. #endif
  2541. }
  2542. if (mode64) {
  2543. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2544. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2545. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2546. cmdp->u.raw64.sg_lst[0].sg_len));
  2547. /* evaluate command size */
  2548. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2549. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2550. } else {
  2551. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2552. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2553. cmdp->u.raw.sg_lst[0].sg_ptr,
  2554. cmdp->u.raw.sg_lst[0].sg_len));
  2555. /* evaluate command size */
  2556. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2557. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2558. }
  2559. }
  2560. /* check space */
  2561. if (ha->cmd_len & 3)
  2562. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2563. if (ha->cmd_cnt > 0) {
  2564. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2565. ha->ic_all_size) {
  2566. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2567. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2568. return 0;
  2569. }
  2570. }
  2571. /* copy command */
  2572. gdth_copy_command(ha);
  2573. return cmd_index;
  2574. }
  2575. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2576. {
  2577. register gdth_cmd_str *cmdp;
  2578. int cmd_index;
  2579. cmdp= ha->pccb;
  2580. TRACE2(("gdth_special_cmd(): "));
  2581. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2582. return 0;
  2583. gdth_copy_internal_data(ha, scp, (char *)cmdp, sizeof(gdth_cmd_str), 1);
  2584. cmdp->RequestBuffer = scp;
  2585. /* search free command index */
  2586. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2587. TRACE(("GDT: No free command index found\n"));
  2588. return 0;
  2589. }
  2590. /* if it's the first command, set command semaphore */
  2591. if (ha->cmd_cnt == 0)
  2592. gdth_set_sema0(ha);
  2593. /* evaluate command size, check space */
  2594. if (cmdp->OpCode == GDT_IOCTL) {
  2595. TRACE2(("IOCTL\n"));
  2596. ha->cmd_len =
  2597. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2598. } else if (cmdp->Service == CACHESERVICE) {
  2599. TRACE2(("cache command %d\n",cmdp->OpCode));
  2600. if (ha->cache_feat & GDT_64BIT)
  2601. ha->cmd_len =
  2602. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2603. else
  2604. ha->cmd_len =
  2605. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2606. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2607. TRACE2(("raw command %d\n",cmdp->OpCode));
  2608. if (ha->raw_feat & GDT_64BIT)
  2609. ha->cmd_len =
  2610. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2611. else
  2612. ha->cmd_len =
  2613. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2614. }
  2615. if (ha->cmd_len & 3)
  2616. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2617. if (ha->cmd_cnt > 0) {
  2618. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2619. ha->ic_all_size) {
  2620. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2621. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2622. return 0;
  2623. }
  2624. }
  2625. /* copy command */
  2626. gdth_copy_command(ha);
  2627. return cmd_index;
  2628. }
  2629. /* Controller event handling functions */
  2630. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2631. ushort idx, gdth_evt_data *evt)
  2632. {
  2633. gdth_evt_str *e;
  2634. struct timeval tv;
  2635. /* no GDTH_LOCK_HA() ! */
  2636. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2637. if (source == 0) /* no source -> no event */
  2638. return NULL;
  2639. if (ebuffer[elastidx].event_source == source &&
  2640. ebuffer[elastidx].event_idx == idx &&
  2641. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2642. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2643. (char *)&evt->eu, evt->size)) ||
  2644. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2645. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2646. (char *)&evt->event_string)))) {
  2647. e = &ebuffer[elastidx];
  2648. do_gettimeofday(&tv);
  2649. e->last_stamp = tv.tv_sec;
  2650. ++e->same_count;
  2651. } else {
  2652. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2653. ++elastidx;
  2654. if (elastidx == MAX_EVENTS)
  2655. elastidx = 0;
  2656. if (elastidx == eoldidx) { /* reached mark ? */
  2657. ++eoldidx;
  2658. if (eoldidx == MAX_EVENTS)
  2659. eoldidx = 0;
  2660. }
  2661. }
  2662. e = &ebuffer[elastidx];
  2663. e->event_source = source;
  2664. e->event_idx = idx;
  2665. do_gettimeofday(&tv);
  2666. e->first_stamp = e->last_stamp = tv.tv_sec;
  2667. e->same_count = 1;
  2668. e->event_data = *evt;
  2669. e->application = 0;
  2670. }
  2671. return e;
  2672. }
  2673. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2674. {
  2675. gdth_evt_str *e;
  2676. int eindex;
  2677. ulong flags;
  2678. TRACE2(("gdth_read_event() handle %d\n", handle));
  2679. spin_lock_irqsave(&ha->smp_lock, flags);
  2680. if (handle == -1)
  2681. eindex = eoldidx;
  2682. else
  2683. eindex = handle;
  2684. estr->event_source = 0;
  2685. if (eindex >= MAX_EVENTS) {
  2686. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2687. return eindex;
  2688. }
  2689. e = &ebuffer[eindex];
  2690. if (e->event_source != 0) {
  2691. if (eindex != elastidx) {
  2692. if (++eindex == MAX_EVENTS)
  2693. eindex = 0;
  2694. } else {
  2695. eindex = -1;
  2696. }
  2697. memcpy(estr, e, sizeof(gdth_evt_str));
  2698. }
  2699. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2700. return eindex;
  2701. }
  2702. static void gdth_readapp_event(gdth_ha_str *ha,
  2703. unchar application, gdth_evt_str *estr)
  2704. {
  2705. gdth_evt_str *e;
  2706. int eindex;
  2707. ulong flags;
  2708. unchar found = FALSE;
  2709. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2710. spin_lock_irqsave(&ha->smp_lock, flags);
  2711. eindex = eoldidx;
  2712. for (;;) {
  2713. e = &ebuffer[eindex];
  2714. if (e->event_source == 0)
  2715. break;
  2716. if ((e->application & application) == 0) {
  2717. e->application |= application;
  2718. found = TRUE;
  2719. break;
  2720. }
  2721. if (eindex == elastidx)
  2722. break;
  2723. if (++eindex == MAX_EVENTS)
  2724. eindex = 0;
  2725. }
  2726. if (found)
  2727. memcpy(estr, e, sizeof(gdth_evt_str));
  2728. else
  2729. estr->event_source = 0;
  2730. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2731. }
  2732. static void gdth_clear_events(void)
  2733. {
  2734. TRACE(("gdth_clear_events()"));
  2735. eoldidx = elastidx = 0;
  2736. ebuffer[0].event_source = 0;
  2737. }
  2738. /* SCSI interface functions */
  2739. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int irq,
  2740. int gdth_from_wait, int* pIndex)
  2741. {
  2742. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2743. gdt6_dpram_str __iomem *dp6_ptr;
  2744. gdt2_dpram_str __iomem *dp2_ptr;
  2745. Scsi_Cmnd *scp;
  2746. int rval, i;
  2747. unchar IStatus;
  2748. ushort Service;
  2749. ulong flags = 0;
  2750. #ifdef INT_COAL
  2751. int coalesced = FALSE;
  2752. int next = FALSE;
  2753. gdth_coal_status *pcs = NULL;
  2754. int act_int_coal = 0;
  2755. #endif
  2756. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  2757. /* if polling and not from gdth_wait() -> return */
  2758. if (gdth_polling) {
  2759. if (!gdth_from_wait) {
  2760. return IRQ_HANDLED;
  2761. }
  2762. }
  2763. if (!gdth_polling)
  2764. spin_lock_irqsave(&ha->smp_lock, flags);
  2765. /* search controller */
  2766. if (0 == (IStatus = gdth_get_status(ha, irq))) {
  2767. /* spurious interrupt */
  2768. if (!gdth_polling)
  2769. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2770. return IRQ_HANDLED;
  2771. }
  2772. #ifdef GDTH_STATISTICS
  2773. ++act_ints;
  2774. #endif
  2775. #ifdef INT_COAL
  2776. /* See if the fw is returning coalesced status */
  2777. if (IStatus == COALINDEX) {
  2778. /* Coalesced status. Setup the initial status
  2779. buffer pointer and flags */
  2780. pcs = ha->coal_stat;
  2781. coalesced = TRUE;
  2782. next = TRUE;
  2783. }
  2784. do {
  2785. if (coalesced) {
  2786. /* For coalesced requests all status
  2787. information is found in the status buffer */
  2788. IStatus = (unchar)(pcs->status & 0xff);
  2789. }
  2790. #endif
  2791. if (ha->type == GDT_EISA) {
  2792. if (IStatus & 0x80) { /* error flag */
  2793. IStatus &= ~0x80;
  2794. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2795. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2796. } else /* no error */
  2797. ha->status = S_OK;
  2798. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2799. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2800. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2801. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2802. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2803. } else if (ha->type == GDT_ISA) {
  2804. dp2_ptr = ha->brd;
  2805. if (IStatus & 0x80) { /* error flag */
  2806. IStatus &= ~0x80;
  2807. ha->status = readw(&dp2_ptr->u.ic.Status);
  2808. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2809. } else /* no error */
  2810. ha->status = S_OK;
  2811. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2812. ha->service = readw(&dp2_ptr->u.ic.Service);
  2813. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2814. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2815. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2816. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2817. } else if (ha->type == GDT_PCI) {
  2818. dp6_ptr = ha->brd;
  2819. if (IStatus & 0x80) { /* error flag */
  2820. IStatus &= ~0x80;
  2821. ha->status = readw(&dp6_ptr->u.ic.Status);
  2822. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2823. } else /* no error */
  2824. ha->status = S_OK;
  2825. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2826. ha->service = readw(&dp6_ptr->u.ic.Service);
  2827. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2828. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2829. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2830. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2831. } else if (ha->type == GDT_PCINEW) {
  2832. if (IStatus & 0x80) { /* error flag */
  2833. IStatus &= ~0x80;
  2834. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2835. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2836. } else
  2837. ha->status = S_OK;
  2838. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2839. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2840. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2841. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2842. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2843. } else if (ha->type == GDT_PCIMPR) {
  2844. dp6m_ptr = ha->brd;
  2845. if (IStatus & 0x80) { /* error flag */
  2846. IStatus &= ~0x80;
  2847. #ifdef INT_COAL
  2848. if (coalesced)
  2849. ha->status = pcs->ext_status & 0xffff;
  2850. else
  2851. #endif
  2852. ha->status = readw(&dp6m_ptr->i960r.status);
  2853. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2854. } else /* no error */
  2855. ha->status = S_OK;
  2856. #ifdef INT_COAL
  2857. /* get information */
  2858. if (coalesced) {
  2859. ha->info = pcs->info0;
  2860. ha->info2 = pcs->info1;
  2861. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2862. } else
  2863. #endif
  2864. {
  2865. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2866. ha->service = readw(&dp6m_ptr->i960r.service);
  2867. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2868. }
  2869. /* event string */
  2870. if (IStatus == ASYNCINDEX) {
  2871. if (ha->service != SCREENSERVICE &&
  2872. (ha->fw_vers & 0xff) >= 0x1a) {
  2873. ha->dvr.severity = readb
  2874. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2875. for (i = 0; i < 256; ++i) {
  2876. ha->dvr.event_string[i] = readb
  2877. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2878. if (ha->dvr.event_string[i] == 0)
  2879. break;
  2880. }
  2881. }
  2882. }
  2883. #ifdef INT_COAL
  2884. /* Make sure that non coalesced interrupts get cleared
  2885. before being handled by gdth_async_event/gdth_sync_event */
  2886. if (!coalesced)
  2887. #endif
  2888. {
  2889. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2890. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2891. }
  2892. } else {
  2893. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2894. if (!gdth_polling)
  2895. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2896. return IRQ_HANDLED;
  2897. }
  2898. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2899. IStatus,ha->status,ha->info));
  2900. if (gdth_from_wait) {
  2901. *pIndex = (int)IStatus;
  2902. }
  2903. if (IStatus == ASYNCINDEX) {
  2904. TRACE2(("gdth_interrupt() async. event\n"));
  2905. gdth_async_event(ha);
  2906. if (!gdth_polling)
  2907. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2908. gdth_next(ha);
  2909. return IRQ_HANDLED;
  2910. }
  2911. if (IStatus == SPEZINDEX) {
  2912. TRACE2(("Service unknown or not initialized !\n"));
  2913. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2914. ha->dvr.eu.driver.ionode = ha->hanum;
  2915. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2916. if (!gdth_polling)
  2917. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2918. return IRQ_HANDLED;
  2919. }
  2920. scp = ha->cmd_tab[IStatus-2].cmnd;
  2921. Service = ha->cmd_tab[IStatus-2].service;
  2922. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2923. if (scp == UNUSED_CMND) {
  2924. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2925. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2926. ha->dvr.eu.driver.ionode = ha->hanum;
  2927. ha->dvr.eu.driver.index = IStatus;
  2928. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2929. if (!gdth_polling)
  2930. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2931. return IRQ_HANDLED;
  2932. }
  2933. if (scp == INTERNAL_CMND) {
  2934. TRACE(("gdth_interrupt() answer to internal command\n"));
  2935. if (!gdth_polling)
  2936. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2937. return IRQ_HANDLED;
  2938. }
  2939. TRACE(("gdth_interrupt() sync. status\n"));
  2940. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2941. if (!gdth_polling)
  2942. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2943. if (rval == 2) {
  2944. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2945. } else if (rval == 1) {
  2946. gdth_scsi_done(scp);
  2947. }
  2948. #ifdef INT_COAL
  2949. if (coalesced) {
  2950. /* go to the next status in the status buffer */
  2951. ++pcs;
  2952. #ifdef GDTH_STATISTICS
  2953. ++act_int_coal;
  2954. if (act_int_coal > max_int_coal) {
  2955. max_int_coal = act_int_coal;
  2956. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  2957. }
  2958. #endif
  2959. /* see if there is another status */
  2960. if (pcs->status == 0)
  2961. /* Stop the coalesce loop */
  2962. next = FALSE;
  2963. }
  2964. } while (next);
  2965. /* coalescing only for new GDT_PCIMPR controllers available */
  2966. if (ha->type == GDT_PCIMPR && coalesced) {
  2967. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2968. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2969. }
  2970. #endif
  2971. gdth_next(ha);
  2972. return IRQ_HANDLED;
  2973. }
  2974. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2975. {
  2976. gdth_ha_str *ha = (gdth_ha_str *)dev_id;
  2977. return __gdth_interrupt(ha, irq, false, NULL);
  2978. }
  2979. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  2980. Scsi_Cmnd *scp)
  2981. {
  2982. gdth_msg_str *msg;
  2983. gdth_cmd_str *cmdp;
  2984. unchar b, t;
  2985. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2986. cmdp = ha->pccb;
  2987. TRACE(("gdth_sync_event() serv %d status %d\n",
  2988. service,ha->status));
  2989. if (service == SCREENSERVICE) {
  2990. msg = ha->pmsg;
  2991. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2992. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2993. if (msg->msg_len > MSGLEN+1)
  2994. msg->msg_len = MSGLEN+1;
  2995. if (msg->msg_len)
  2996. if (!(msg->msg_answer && msg->msg_ext)) {
  2997. msg->msg_text[msg->msg_len] = '\0';
  2998. printk("%s",msg->msg_text);
  2999. }
  3000. if (msg->msg_ext && !msg->msg_answer) {
  3001. while (gdth_test_busy(ha))
  3002. gdth_delay(0);
  3003. cmdp->Service = SCREENSERVICE;
  3004. cmdp->RequestBuffer = SCREEN_CMND;
  3005. gdth_get_cmd_index(ha);
  3006. gdth_set_sema0(ha);
  3007. cmdp->OpCode = GDT_READ;
  3008. cmdp->BoardNode = LOCALBOARD;
  3009. cmdp->u.screen.reserved = 0;
  3010. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3011. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3012. ha->cmd_offs_dpmem = 0;
  3013. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3014. + sizeof(ulong64);
  3015. ha->cmd_cnt = 0;
  3016. gdth_copy_command(ha);
  3017. gdth_release_event(ha);
  3018. return 0;
  3019. }
  3020. if (msg->msg_answer && msg->msg_alen) {
  3021. /* default answers (getchar() not possible) */
  3022. if (msg->msg_alen == 1) {
  3023. msg->msg_alen = 0;
  3024. msg->msg_len = 1;
  3025. msg->msg_text[0] = 0;
  3026. } else {
  3027. msg->msg_alen -= 2;
  3028. msg->msg_len = 2;
  3029. msg->msg_text[0] = 1;
  3030. msg->msg_text[1] = 0;
  3031. }
  3032. msg->msg_ext = 0;
  3033. msg->msg_answer = 0;
  3034. while (gdth_test_busy(ha))
  3035. gdth_delay(0);
  3036. cmdp->Service = SCREENSERVICE;
  3037. cmdp->RequestBuffer = SCREEN_CMND;
  3038. gdth_get_cmd_index(ha);
  3039. gdth_set_sema0(ha);
  3040. cmdp->OpCode = GDT_WRITE;
  3041. cmdp->BoardNode = LOCALBOARD;
  3042. cmdp->u.screen.reserved = 0;
  3043. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3044. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3045. ha->cmd_offs_dpmem = 0;
  3046. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3047. + sizeof(ulong64);
  3048. ha->cmd_cnt = 0;
  3049. gdth_copy_command(ha);
  3050. gdth_release_event(ha);
  3051. return 0;
  3052. }
  3053. printk("\n");
  3054. } else {
  3055. b = scp->device->channel;
  3056. t = scp->device->id;
  3057. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  3058. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3059. }
  3060. /* cache or raw service */
  3061. if (ha->status == S_BSY) {
  3062. TRACE2(("Controller busy -> retry !\n"));
  3063. if (cmndinfo->OpCode == GDT_MOUNT)
  3064. cmndinfo->OpCode = GDT_CLUST_INFO;
  3065. /* retry */
  3066. return 2;
  3067. }
  3068. if (gdth_bufflen(scp))
  3069. pci_unmap_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  3070. cmndinfo->dma_dir);
  3071. if (cmndinfo->sense_paddr)
  3072. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  3073. PCI_DMA_FROMDEVICE);
  3074. if (ha->status == S_OK) {
  3075. cmndinfo->status = S_OK;
  3076. cmndinfo->info = ha->info;
  3077. if (cmndinfo->OpCode != -1) {
  3078. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3079. cmndinfo->OpCode));
  3080. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3081. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  3082. ha->hdr[t].cluster_type = (unchar)ha->info;
  3083. if (!(ha->hdr[t].cluster_type &
  3084. CLUSTER_MOUNTED)) {
  3085. /* NOT MOUNTED -> MOUNT */
  3086. cmndinfo->OpCode = GDT_MOUNT;
  3087. if (ha->hdr[t].cluster_type &
  3088. CLUSTER_RESERVED) {
  3089. /* cluster drive RESERVED (on the other node) */
  3090. cmndinfo->phase = -2; /* reservation conflict */
  3091. }
  3092. } else {
  3093. cmndinfo->OpCode = -1;
  3094. }
  3095. } else {
  3096. if (cmndinfo->OpCode == GDT_MOUNT) {
  3097. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3098. ha->hdr[t].media_changed = TRUE;
  3099. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3100. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3101. ha->hdr[t].media_changed = TRUE;
  3102. }
  3103. cmndinfo->OpCode = -1;
  3104. }
  3105. /* retry */
  3106. cmndinfo->priority = HIGH_PRI;
  3107. return 2;
  3108. } else {
  3109. /* RESERVE/RELEASE ? */
  3110. if (scp->cmnd[0] == RESERVE) {
  3111. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3112. } else if (scp->cmnd[0] == RELEASE) {
  3113. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3114. }
  3115. scp->result = DID_OK << 16;
  3116. scp->sense_buffer[0] = 0;
  3117. }
  3118. } else {
  3119. cmndinfo->status = ha->status;
  3120. cmndinfo->info = ha->info;
  3121. if (cmndinfo->OpCode != -1) {
  3122. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3123. cmndinfo->OpCode, ha->status));
  3124. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3125. cmndinfo->OpCode == GDT_SCAN_END) {
  3126. cmndinfo->OpCode = -1;
  3127. /* retry */
  3128. cmndinfo->priority = HIGH_PRI;
  3129. return 2;
  3130. }
  3131. memset((char*)scp->sense_buffer,0,16);
  3132. scp->sense_buffer[0] = 0x70;
  3133. scp->sense_buffer[2] = NOT_READY;
  3134. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3135. } else if (service == CACHESERVICE) {
  3136. if (ha->status == S_CACHE_UNKNOWN &&
  3137. (ha->hdr[t].cluster_type &
  3138. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3139. /* bus reset -> force GDT_CLUST_INFO */
  3140. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3141. }
  3142. memset((char*)scp->sense_buffer,0,16);
  3143. if (ha->status == (ushort)S_CACHE_RESERV) {
  3144. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3145. } else {
  3146. scp->sense_buffer[0] = 0x70;
  3147. scp->sense_buffer[2] = NOT_READY;
  3148. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3149. }
  3150. if (!cmndinfo->internal_command) {
  3151. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3152. ha->dvr.eu.sync.ionode = ha->hanum;
  3153. ha->dvr.eu.sync.service = service;
  3154. ha->dvr.eu.sync.status = ha->status;
  3155. ha->dvr.eu.sync.info = ha->info;
  3156. ha->dvr.eu.sync.hostdrive = t;
  3157. if (ha->status >= 0x8000)
  3158. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3159. else
  3160. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3161. }
  3162. } else {
  3163. /* sense buffer filled from controller firmware (DMA) */
  3164. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3165. scp->result = DID_BAD_TARGET << 16;
  3166. } else {
  3167. scp->result = (DID_OK << 16) | ha->info;
  3168. }
  3169. }
  3170. }
  3171. if (!cmndinfo->wait_for_completion)
  3172. cmndinfo->wait_for_completion++;
  3173. else
  3174. return 1;
  3175. }
  3176. return 0;
  3177. }
  3178. static char *async_cache_tab[] = {
  3179. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3180. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3181. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3182. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3183. /* 2*/ "\005\000\002\006\004"
  3184. "GDT HA %u, Host Drive %lu not ready",
  3185. /* 3*/ "\005\000\002\006\004"
  3186. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3187. /* 4*/ "\005\000\002\006\004"
  3188. "GDT HA %u, mirror update on Host Drive %lu failed",
  3189. /* 5*/ "\005\000\002\006\004"
  3190. "GDT HA %u, Mirror Drive %lu failed",
  3191. /* 6*/ "\005\000\002\006\004"
  3192. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3193. /* 7*/ "\005\000\002\006\004"
  3194. "GDT HA %u, Host Drive %lu write protected",
  3195. /* 8*/ "\005\000\002\006\004"
  3196. "GDT HA %u, media changed in Host Drive %lu",
  3197. /* 9*/ "\005\000\002\006\004"
  3198. "GDT HA %u, Host Drive %lu is offline",
  3199. /*10*/ "\005\000\002\006\004"
  3200. "GDT HA %u, media change of Mirror Drive %lu",
  3201. /*11*/ "\005\000\002\006\004"
  3202. "GDT HA %u, Mirror Drive %lu is write protected",
  3203. /*12*/ "\005\000\002\006\004"
  3204. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3205. /*13*/ "\007\000\002\006\002\010\002"
  3206. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3207. /*14*/ "\005\000\002\006\002"
  3208. "GDT HA %u, Array Drive %u: FAIL state entered",
  3209. /*15*/ "\005\000\002\006\002"
  3210. "GDT HA %u, Array Drive %u: error",
  3211. /*16*/ "\007\000\002\006\002\010\002"
  3212. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3213. /*17*/ "\005\000\002\006\002"
  3214. "GDT HA %u, Array Drive %u: parity build failed",
  3215. /*18*/ "\005\000\002\006\002"
  3216. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3217. /*19*/ "\005\000\002\010\002"
  3218. "GDT HA %u, Test of Hot Fix %u failed",
  3219. /*20*/ "\005\000\002\006\002"
  3220. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3221. /*21*/ "\005\000\002\006\002"
  3222. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3223. /*22*/ "\007\000\002\006\002\010\002"
  3224. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3225. /*23*/ "\005\000\002\006\002"
  3226. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3227. /*24*/ "\005\000\002\010\002"
  3228. "GDT HA %u, mirror update on Cache Drive %u completed",
  3229. /*25*/ "\005\000\002\010\002"
  3230. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3231. /*26*/ "\005\000\002\006\002"
  3232. "GDT HA %u, Array Drive %u: drive rebuild started",
  3233. /*27*/ "\005\000\002\012\001"
  3234. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3235. /*28*/ "\005\000\002\012\001"
  3236. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3237. /*29*/ "\007\000\002\012\001\013\001"
  3238. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3239. /*30*/ "\007\000\002\012\001\013\001"
  3240. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3241. /*31*/ "\007\000\002\012\001\013\001"
  3242. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3243. /*32*/ "\007\000\002\012\001\013\001"
  3244. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3245. /*33*/ "\007\000\002\012\001\013\001"
  3246. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3247. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3248. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3249. /*35*/ "\007\000\002\012\001\013\001"
  3250. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3251. /*36*/ "\007\000\002\012\001\013\001"
  3252. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3253. /*37*/ "\007\000\002\012\001\006\004"
  3254. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3255. /*38*/ "\007\000\002\012\001\013\001"
  3256. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3257. /*39*/ "\007\000\002\012\001\013\001"
  3258. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3259. /*40*/ "\007\000\002\012\001\013\001"
  3260. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3261. /*41*/ "\007\000\002\012\001\013\001"
  3262. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3263. /*42*/ "\005\000\002\006\002"
  3264. "GDT HA %u, Array Drive %u: drive build started",
  3265. /*43*/ "\003\000\002"
  3266. "GDT HA %u, DRAM parity error detected",
  3267. /*44*/ "\005\000\002\006\002"
  3268. "GDT HA %u, Mirror Drive %u: update started",
  3269. /*45*/ "\007\000\002\006\002\010\002"
  3270. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3271. /*46*/ "\005\000\002\006\002"
  3272. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3273. /*47*/ "\005\000\002\006\002"
  3274. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3275. /*48*/ "\005\000\002\006\002"
  3276. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3277. /*49*/ "\005\000\002\006\002"
  3278. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3279. /*50*/ "\007\000\002\012\001\013\001"
  3280. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3281. /*51*/ "\005\000\002\006\002"
  3282. "GDT HA %u, Array Drive %u: expand started",
  3283. /*52*/ "\005\000\002\006\002"
  3284. "GDT HA %u, Array Drive %u: expand finished successfully",
  3285. /*53*/ "\005\000\002\006\002"
  3286. "GDT HA %u, Array Drive %u: expand failed",
  3287. /*54*/ "\003\000\002"
  3288. "GDT HA %u, CPU temperature critical",
  3289. /*55*/ "\003\000\002"
  3290. "GDT HA %u, CPU temperature OK",
  3291. /*56*/ "\005\000\002\006\004"
  3292. "GDT HA %u, Host drive %lu created",
  3293. /*57*/ "\005\000\002\006\002"
  3294. "GDT HA %u, Array Drive %u: expand restarted",
  3295. /*58*/ "\005\000\002\006\002"
  3296. "GDT HA %u, Array Drive %u: expand stopped",
  3297. /*59*/ "\005\000\002\010\002"
  3298. "GDT HA %u, Mirror Drive %u: drive build quited",
  3299. /*60*/ "\005\000\002\006\002"
  3300. "GDT HA %u, Array Drive %u: parity build quited",
  3301. /*61*/ "\005\000\002\006\002"
  3302. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3303. /*62*/ "\005\000\002\006\002"
  3304. "GDT HA %u, Array Drive %u: parity verify started",
  3305. /*63*/ "\005\000\002\006\002"
  3306. "GDT HA %u, Array Drive %u: parity verify done",
  3307. /*64*/ "\005\000\002\006\002"
  3308. "GDT HA %u, Array Drive %u: parity verify failed",
  3309. /*65*/ "\005\000\002\006\002"
  3310. "GDT HA %u, Array Drive %u: parity error detected",
  3311. /*66*/ "\005\000\002\006\002"
  3312. "GDT HA %u, Array Drive %u: parity verify quited",
  3313. /*67*/ "\005\000\002\006\002"
  3314. "GDT HA %u, Host Drive %u reserved",
  3315. /*68*/ "\005\000\002\006\002"
  3316. "GDT HA %u, Host Drive %u mounted and released",
  3317. /*69*/ "\005\000\002\006\002"
  3318. "GDT HA %u, Host Drive %u released",
  3319. /*70*/ "\003\000\002"
  3320. "GDT HA %u, DRAM error detected and corrected with ECC",
  3321. /*71*/ "\003\000\002"
  3322. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3323. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3324. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3325. /*73*/ "\005\000\002\006\002"
  3326. "GDT HA %u, Host drive %u resetted locally",
  3327. /*74*/ "\005\000\002\006\002"
  3328. "GDT HA %u, Host drive %u resetted remotely",
  3329. /*75*/ "\003\000\002"
  3330. "GDT HA %u, async. status 75 unknown",
  3331. };
  3332. static int gdth_async_event(gdth_ha_str *ha)
  3333. {
  3334. gdth_cmd_str *cmdp;
  3335. int cmd_index;
  3336. cmdp= ha->pccb;
  3337. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3338. ha->hanum, ha->service));
  3339. if (ha->service == SCREENSERVICE) {
  3340. if (ha->status == MSG_REQUEST) {
  3341. while (gdth_test_busy(ha))
  3342. gdth_delay(0);
  3343. cmdp->Service = SCREENSERVICE;
  3344. cmdp->RequestBuffer = SCREEN_CMND;
  3345. cmd_index = gdth_get_cmd_index(ha);
  3346. gdth_set_sema0(ha);
  3347. cmdp->OpCode = GDT_READ;
  3348. cmdp->BoardNode = LOCALBOARD;
  3349. cmdp->u.screen.reserved = 0;
  3350. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3351. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3352. ha->cmd_offs_dpmem = 0;
  3353. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3354. + sizeof(ulong64);
  3355. ha->cmd_cnt = 0;
  3356. gdth_copy_command(ha);
  3357. if (ha->type == GDT_EISA)
  3358. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3359. else if (ha->type == GDT_ISA)
  3360. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3361. else
  3362. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3363. (ushort)((ha->brd_phys>>3)&0x1f));
  3364. gdth_release_event(ha);
  3365. }
  3366. } else {
  3367. if (ha->type == GDT_PCIMPR &&
  3368. (ha->fw_vers & 0xff) >= 0x1a) {
  3369. ha->dvr.size = 0;
  3370. ha->dvr.eu.async.ionode = ha->hanum;
  3371. ha->dvr.eu.async.status = ha->status;
  3372. /* severity and event_string already set! */
  3373. } else {
  3374. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3375. ha->dvr.eu.async.ionode = ha->hanum;
  3376. ha->dvr.eu.async.service = ha->service;
  3377. ha->dvr.eu.async.status = ha->status;
  3378. ha->dvr.eu.async.info = ha->info;
  3379. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3380. }
  3381. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3382. gdth_log_event( &ha->dvr, NULL );
  3383. /* new host drive from expand? */
  3384. if (ha->service == CACHESERVICE && ha->status == 56) {
  3385. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3386. (ushort)ha->info));
  3387. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3388. }
  3389. }
  3390. return 1;
  3391. }
  3392. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3393. {
  3394. gdth_stackframe stack;
  3395. char *f = NULL;
  3396. int i,j;
  3397. TRACE2(("gdth_log_event()\n"));
  3398. if (dvr->size == 0) {
  3399. if (buffer == NULL) {
  3400. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3401. } else {
  3402. sprintf(buffer,"Adapter %d: %s\n",
  3403. dvr->eu.async.ionode,dvr->event_string);
  3404. }
  3405. } else if (dvr->eu.async.service == CACHESERVICE &&
  3406. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3407. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3408. dvr->eu.async.status));
  3409. f = async_cache_tab[dvr->eu.async.status];
  3410. /* i: parameter to push, j: stack element to fill */
  3411. for (j=0,i=1; i < f[0]; i+=2) {
  3412. switch (f[i+1]) {
  3413. case 4:
  3414. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3415. break;
  3416. case 2:
  3417. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3418. break;
  3419. case 1:
  3420. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3421. break;
  3422. default:
  3423. break;
  3424. }
  3425. }
  3426. if (buffer == NULL) {
  3427. printk(&f[(int)f[0]],stack);
  3428. printk("\n");
  3429. } else {
  3430. sprintf(buffer,&f[(int)f[0]],stack);
  3431. }
  3432. } else {
  3433. if (buffer == NULL) {
  3434. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3435. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3436. } else {
  3437. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3438. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3439. }
  3440. }
  3441. }
  3442. #ifdef GDTH_STATISTICS
  3443. static void gdth_timeout(ulong data)
  3444. {
  3445. ulong32 i;
  3446. Scsi_Cmnd *nscp;
  3447. gdth_ha_str *ha;
  3448. ulong flags;
  3449. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3450. spin_lock_irqsave(&ha->smp_lock, flags);
  3451. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3452. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3453. ++act_stats;
  3454. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3455. ++act_rq;
  3456. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3457. act_ints, act_ios, act_stats, act_rq));
  3458. act_ints = act_ios = 0;
  3459. gdth_timer.expires = jiffies + 30 * HZ;
  3460. add_timer(&gdth_timer);
  3461. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3462. }
  3463. #endif
  3464. static void __init internal_setup(char *str,int *ints)
  3465. {
  3466. int i, argc;
  3467. char *cur_str, *argv;
  3468. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3469. str ? str:"NULL", ints ? ints[0]:0));
  3470. /* read irq[] from ints[] */
  3471. if (ints) {
  3472. argc = ints[0];
  3473. if (argc > 0) {
  3474. if (argc > MAXHA)
  3475. argc = MAXHA;
  3476. for (i = 0; i < argc; ++i)
  3477. irq[i] = ints[i+1];
  3478. }
  3479. }
  3480. /* analyse string */
  3481. argv = str;
  3482. while (argv && (cur_str = strchr(argv, ':'))) {
  3483. int val = 0, c = *++cur_str;
  3484. if (c == 'n' || c == 'N')
  3485. val = 0;
  3486. else if (c == 'y' || c == 'Y')
  3487. val = 1;
  3488. else
  3489. val = (int)simple_strtoul(cur_str, NULL, 0);
  3490. if (!strncmp(argv, "disable:", 8))
  3491. disable = val;
  3492. else if (!strncmp(argv, "reserve_mode:", 13))
  3493. reserve_mode = val;
  3494. else if (!strncmp(argv, "reverse_scan:", 13))
  3495. reverse_scan = val;
  3496. else if (!strncmp(argv, "hdr_channel:", 12))
  3497. hdr_channel = val;
  3498. else if (!strncmp(argv, "max_ids:", 8))
  3499. max_ids = val;
  3500. else if (!strncmp(argv, "rescan:", 7))
  3501. rescan = val;
  3502. else if (!strncmp(argv, "shared_access:", 14))
  3503. shared_access = val;
  3504. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3505. probe_eisa_isa = val;
  3506. else if (!strncmp(argv, "reserve_list:", 13)) {
  3507. reserve_list[0] = val;
  3508. for (i = 1; i < MAX_RES_ARGS; i++) {
  3509. cur_str = strchr(cur_str, ',');
  3510. if (!cur_str)
  3511. break;
  3512. if (!isdigit((int)*++cur_str)) {
  3513. --cur_str;
  3514. break;
  3515. }
  3516. reserve_list[i] =
  3517. (int)simple_strtoul(cur_str, NULL, 0);
  3518. }
  3519. if (!cur_str)
  3520. break;
  3521. argv = ++cur_str;
  3522. continue;
  3523. }
  3524. if ((argv = strchr(argv, ',')))
  3525. ++argv;
  3526. }
  3527. }
  3528. int __init option_setup(char *str)
  3529. {
  3530. int ints[MAXHA];
  3531. char *cur = str;
  3532. int i = 1;
  3533. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3534. while (cur && isdigit(*cur) && i <= MAXHA) {
  3535. ints[i++] = simple_strtoul(cur, NULL, 0);
  3536. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3537. }
  3538. ints[0] = i - 1;
  3539. internal_setup(cur, ints);
  3540. return 1;
  3541. }
  3542. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3543. {
  3544. TRACE2(("gdth_ctr_name()\n"));
  3545. if (ha->type == GDT_EISA) {
  3546. switch (ha->stype) {
  3547. case GDT3_ID:
  3548. return("GDT3000/3020");
  3549. case GDT3A_ID:
  3550. return("GDT3000A/3020A/3050A");
  3551. case GDT3B_ID:
  3552. return("GDT3000B/3010A");
  3553. }
  3554. } else if (ha->type == GDT_ISA) {
  3555. return("GDT2000/2020");
  3556. } else if (ha->type == GDT_PCI) {
  3557. switch (ha->pdev->device) {
  3558. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3559. return("GDT6000/6020/6050");
  3560. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3561. return("GDT6000B/6010");
  3562. }
  3563. }
  3564. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3565. return("");
  3566. }
  3567. static const char *gdth_info(struct Scsi_Host *shp)
  3568. {
  3569. gdth_ha_str *ha = shost_priv(shp);
  3570. TRACE2(("gdth_info()\n"));
  3571. return ((const char *)ha->binfo.type_string);
  3572. }
  3573. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3574. {
  3575. gdth_ha_str *ha = shost_priv(scp->device->host);
  3576. int i;
  3577. ulong flags;
  3578. Scsi_Cmnd *cmnd;
  3579. unchar b;
  3580. TRACE2(("gdth_eh_bus_reset()\n"));
  3581. b = scp->device->channel;
  3582. /* clear command tab */
  3583. spin_lock_irqsave(&ha->smp_lock, flags);
  3584. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3585. cmnd = ha->cmd_tab[i].cmnd;
  3586. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3587. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3588. }
  3589. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3590. if (b == ha->virt_bus) {
  3591. /* host drives */
  3592. for (i = 0; i < MAX_HDRIVES; ++i) {
  3593. if (ha->hdr[i].present) {
  3594. spin_lock_irqsave(&ha->smp_lock, flags);
  3595. gdth_polling = TRUE;
  3596. while (gdth_test_busy(ha))
  3597. gdth_delay(0);
  3598. if (gdth_internal_cmd(ha, CACHESERVICE,
  3599. GDT_CLUST_RESET, i, 0, 0))
  3600. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3601. gdth_polling = FALSE;
  3602. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3603. }
  3604. }
  3605. } else {
  3606. /* raw devices */
  3607. spin_lock_irqsave(&ha->smp_lock, flags);
  3608. for (i = 0; i < MAXID; ++i)
  3609. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3610. gdth_polling = TRUE;
  3611. while (gdth_test_busy(ha))
  3612. gdth_delay(0);
  3613. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3614. BUS_L2P(ha,b), 0, 0);
  3615. gdth_polling = FALSE;
  3616. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3617. }
  3618. return SUCCESS;
  3619. }
  3620. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3621. {
  3622. unchar b, t;
  3623. gdth_ha_str *ha = shost_priv(sdev->host);
  3624. struct scsi_device *sd;
  3625. unsigned capacity;
  3626. sd = sdev;
  3627. capacity = cap;
  3628. b = sd->channel;
  3629. t = sd->id;
  3630. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3631. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3632. /* raw device or host drive without mapping information */
  3633. TRACE2(("Evaluate mapping\n"));
  3634. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3635. } else {
  3636. ip[0] = ha->hdr[t].heads;
  3637. ip[1] = ha->hdr[t].secs;
  3638. ip[2] = capacity / ip[0] / ip[1];
  3639. }
  3640. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3641. ip[0],ip[1],ip[2]));
  3642. return 0;
  3643. }
  3644. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3645. void (*done)(struct scsi_cmnd *))
  3646. {
  3647. gdth_ha_str *ha = shost_priv(scp->device->host);
  3648. struct gdth_cmndinfo *cmndinfo;
  3649. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3650. cmndinfo = gdth_get_cmndinfo(ha);
  3651. BUG_ON(!cmndinfo);
  3652. scp->scsi_done = done;
  3653. gdth_update_timeout(scp, scp->timeout_per_command * 6);
  3654. cmndinfo->priority = DEFAULT_PRI;
  3655. gdth_set_bufflen(scp, scsi_bufflen(scp));
  3656. gdth_set_sg_count(scp, scsi_sg_count(scp));
  3657. gdth_set_sglist(scp, scsi_sglist(scp));
  3658. return __gdth_queuecommand(ha, scp, cmndinfo);
  3659. }
  3660. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3661. struct gdth_cmndinfo *cmndinfo)
  3662. {
  3663. scp->host_scribble = (unsigned char *)cmndinfo;
  3664. cmndinfo->wait_for_completion = 1;
  3665. cmndinfo->phase = -1;
  3666. cmndinfo->OpCode = -1;
  3667. #ifdef GDTH_STATISTICS
  3668. ++act_ios;
  3669. #endif
  3670. gdth_putq(ha, scp, cmndinfo->priority);
  3671. gdth_next(ha);
  3672. return 0;
  3673. }
  3674. static int gdth_open(struct inode *inode, struct file *filep)
  3675. {
  3676. gdth_ha_str *ha;
  3677. list_for_each_entry(ha, &gdth_instances, list) {
  3678. if (!ha->sdev)
  3679. ha->sdev = scsi_get_host_dev(ha->shost);
  3680. }
  3681. TRACE(("gdth_open()\n"));
  3682. return 0;
  3683. }
  3684. static int gdth_close(struct inode *inode, struct file *filep)
  3685. {
  3686. TRACE(("gdth_close()\n"));
  3687. return 0;
  3688. }
  3689. static int ioc_event(void __user *arg)
  3690. {
  3691. gdth_ioctl_event evt;
  3692. gdth_ha_str *ha;
  3693. ulong flags;
  3694. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3695. return -EFAULT;
  3696. ha = gdth_find_ha(evt.ionode);
  3697. if (!ha)
  3698. return -EFAULT;
  3699. if (evt.erase == 0xff) {
  3700. if (evt.event.event_source == ES_TEST)
  3701. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3702. else if (evt.event.event_source == ES_DRIVER)
  3703. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3704. else if (evt.event.event_source == ES_SYNC)
  3705. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3706. else
  3707. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3708. spin_lock_irqsave(&ha->smp_lock, flags);
  3709. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3710. &evt.event.event_data);
  3711. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3712. } else if (evt.erase == 0xfe) {
  3713. gdth_clear_events();
  3714. } else if (evt.erase == 0) {
  3715. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3716. } else {
  3717. gdth_readapp_event(ha, evt.erase, &evt.event);
  3718. }
  3719. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3720. return -EFAULT;
  3721. return 0;
  3722. }
  3723. static int ioc_lockdrv(void __user *arg)
  3724. {
  3725. gdth_ioctl_lockdrv ldrv;
  3726. unchar i, j;
  3727. ulong flags;
  3728. gdth_ha_str *ha;
  3729. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3730. return -EFAULT;
  3731. ha = gdth_find_ha(ldrv.ionode);
  3732. if (!ha)
  3733. return -EFAULT;
  3734. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3735. j = ldrv.drives[i];
  3736. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3737. continue;
  3738. if (ldrv.lock) {
  3739. spin_lock_irqsave(&ha->smp_lock, flags);
  3740. ha->hdr[j].lock = 1;
  3741. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3742. gdth_wait_completion(ha, ha->bus_cnt, j);
  3743. gdth_stop_timeout(ha, ha->bus_cnt, j);
  3744. } else {
  3745. spin_lock_irqsave(&ha->smp_lock, flags);
  3746. ha->hdr[j].lock = 0;
  3747. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3748. gdth_start_timeout(ha, ha->bus_cnt, j);
  3749. gdth_next(ha);
  3750. }
  3751. }
  3752. return 0;
  3753. }
  3754. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3755. {
  3756. gdth_ioctl_reset res;
  3757. gdth_cmd_str cmd;
  3758. gdth_ha_str *ha;
  3759. int rval;
  3760. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3761. res.number >= MAX_HDRIVES)
  3762. return -EFAULT;
  3763. ha = gdth_find_ha(res.ionode);
  3764. if (!ha)
  3765. return -EFAULT;
  3766. if (!ha->hdr[res.number].present)
  3767. return 0;
  3768. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3769. cmd.Service = CACHESERVICE;
  3770. cmd.OpCode = GDT_CLUST_RESET;
  3771. if (ha->cache_feat & GDT_64BIT)
  3772. cmd.u.cache64.DeviceNo = res.number;
  3773. else
  3774. cmd.u.cache.DeviceNo = res.number;
  3775. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3776. if (rval < 0)
  3777. return rval;
  3778. res.status = rval;
  3779. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3780. return -EFAULT;
  3781. return 0;
  3782. }
  3783. static int ioc_general(void __user *arg, char *cmnd)
  3784. {
  3785. gdth_ioctl_general gen;
  3786. char *buf = NULL;
  3787. ulong64 paddr;
  3788. gdth_ha_str *ha;
  3789. int rval;
  3790. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3791. return -EFAULT;
  3792. ha = gdth_find_ha(gen.ionode);
  3793. if (!ha)
  3794. return -EFAULT;
  3795. if (gen.data_len + gen.sense_len != 0) {
  3796. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3797. FALSE, &paddr)))
  3798. return -EFAULT;
  3799. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3800. gen.data_len + gen.sense_len)) {
  3801. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3802. return -EFAULT;
  3803. }
  3804. if (gen.command.OpCode == GDT_IOCTL) {
  3805. gen.command.u.ioctl.p_param = paddr;
  3806. } else if (gen.command.Service == CACHESERVICE) {
  3807. if (ha->cache_feat & GDT_64BIT) {
  3808. /* copy elements from 32-bit IOCTL structure */
  3809. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3810. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3811. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3812. /* addresses */
  3813. if (ha->cache_feat & SCATTER_GATHER) {
  3814. gen.command.u.cache64.DestAddr = (ulong64)-1;
  3815. gen.command.u.cache64.sg_canz = 1;
  3816. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3817. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3818. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3819. } else {
  3820. gen.command.u.cache64.DestAddr = paddr;
  3821. gen.command.u.cache64.sg_canz = 0;
  3822. }
  3823. } else {
  3824. if (ha->cache_feat & SCATTER_GATHER) {
  3825. gen.command.u.cache.DestAddr = 0xffffffff;
  3826. gen.command.u.cache.sg_canz = 1;
  3827. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  3828. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3829. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3830. } else {
  3831. gen.command.u.cache.DestAddr = paddr;
  3832. gen.command.u.cache.sg_canz = 0;
  3833. }
  3834. }
  3835. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3836. if (ha->raw_feat & GDT_64BIT) {
  3837. /* copy elements from 32-bit IOCTL structure */
  3838. char cmd[16];
  3839. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3840. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3841. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3842. gen.command.u.raw64.target = gen.command.u.raw.target;
  3843. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3844. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3845. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3846. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3847. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3848. /* addresses */
  3849. if (ha->raw_feat & SCATTER_GATHER) {
  3850. gen.command.u.raw64.sdata = (ulong64)-1;
  3851. gen.command.u.raw64.sg_ranz = 1;
  3852. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3853. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3854. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3855. } else {
  3856. gen.command.u.raw64.sdata = paddr;
  3857. gen.command.u.raw64.sg_ranz = 0;
  3858. }
  3859. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3860. } else {
  3861. if (ha->raw_feat & SCATTER_GATHER) {
  3862. gen.command.u.raw.sdata = 0xffffffff;
  3863. gen.command.u.raw.sg_ranz = 1;
  3864. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  3865. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3866. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3867. } else {
  3868. gen.command.u.raw.sdata = paddr;
  3869. gen.command.u.raw.sg_ranz = 0;
  3870. }
  3871. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  3872. }
  3873. } else {
  3874. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3875. return -EFAULT;
  3876. }
  3877. }
  3878. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3879. if (rval < 0)
  3880. return rval;
  3881. gen.status = rval;
  3882. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3883. gen.data_len + gen.sense_len)) {
  3884. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3885. return -EFAULT;
  3886. }
  3887. if (copy_to_user(arg, &gen,
  3888. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3889. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3890. return -EFAULT;
  3891. }
  3892. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3893. return 0;
  3894. }
  3895. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3896. {
  3897. gdth_ioctl_rescan *rsc;
  3898. gdth_cmd_str *cmd;
  3899. gdth_ha_str *ha;
  3900. unchar i;
  3901. int rc = -ENOMEM;
  3902. u32 cluster_type = 0;
  3903. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3904. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3905. if (!rsc || !cmd)
  3906. goto free_fail;
  3907. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3908. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3909. rc = -EFAULT;
  3910. goto free_fail;
  3911. }
  3912. memset(cmd, 0, sizeof(gdth_cmd_str));
  3913. for (i = 0; i < MAX_HDRIVES; ++i) {
  3914. if (!ha->hdr[i].present) {
  3915. rsc->hdr_list[i].bus = 0xff;
  3916. continue;
  3917. }
  3918. rsc->hdr_list[i].bus = ha->virt_bus;
  3919. rsc->hdr_list[i].target = i;
  3920. rsc->hdr_list[i].lun = 0;
  3921. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3922. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3923. cmd->Service = CACHESERVICE;
  3924. cmd->OpCode = GDT_CLUST_INFO;
  3925. if (ha->cache_feat & GDT_64BIT)
  3926. cmd->u.cache64.DeviceNo = i;
  3927. else
  3928. cmd->u.cache.DeviceNo = i;
  3929. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3930. rsc->hdr_list[i].cluster_type = cluster_type;
  3931. }
  3932. }
  3933. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3934. rc = -EFAULT;
  3935. else
  3936. rc = 0;
  3937. free_fail:
  3938. kfree(rsc);
  3939. kfree(cmd);
  3940. return rc;
  3941. }
  3942. static int ioc_rescan(void __user *arg, char *cmnd)
  3943. {
  3944. gdth_ioctl_rescan *rsc;
  3945. gdth_cmd_str *cmd;
  3946. ushort i, status, hdr_cnt;
  3947. ulong32 info;
  3948. int cyls, hds, secs;
  3949. int rc = -ENOMEM;
  3950. ulong flags;
  3951. gdth_ha_str *ha;
  3952. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3953. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3954. if (!cmd || !rsc)
  3955. goto free_fail;
  3956. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3957. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3958. rc = -EFAULT;
  3959. goto free_fail;
  3960. }
  3961. memset(cmd, 0, sizeof(gdth_cmd_str));
  3962. if (rsc->flag == 0) {
  3963. /* old method: re-init. cache service */
  3964. cmd->Service = CACHESERVICE;
  3965. if (ha->cache_feat & GDT_64BIT) {
  3966. cmd->OpCode = GDT_X_INIT_HOST;
  3967. cmd->u.cache64.DeviceNo = LINUX_OS;
  3968. } else {
  3969. cmd->OpCode = GDT_INIT;
  3970. cmd->u.cache.DeviceNo = LINUX_OS;
  3971. }
  3972. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3973. i = 0;
  3974. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  3975. } else {
  3976. i = rsc->hdr_no;
  3977. hdr_cnt = i + 1;
  3978. }
  3979. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3980. cmd->Service = CACHESERVICE;
  3981. cmd->OpCode = GDT_INFO;
  3982. if (ha->cache_feat & GDT_64BIT)
  3983. cmd->u.cache64.DeviceNo = i;
  3984. else
  3985. cmd->u.cache.DeviceNo = i;
  3986. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3987. spin_lock_irqsave(&ha->smp_lock, flags);
  3988. rsc->hdr_list[i].bus = ha->virt_bus;
  3989. rsc->hdr_list[i].target = i;
  3990. rsc->hdr_list[i].lun = 0;
  3991. if (status != S_OK) {
  3992. ha->hdr[i].present = FALSE;
  3993. } else {
  3994. ha->hdr[i].present = TRUE;
  3995. ha->hdr[i].size = info;
  3996. /* evaluate mapping */
  3997. ha->hdr[i].size &= ~SECS32;
  3998. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3999. ha->hdr[i].heads = hds;
  4000. ha->hdr[i].secs = secs;
  4001. /* round size */
  4002. ha->hdr[i].size = cyls * hds * secs;
  4003. }
  4004. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4005. if (status != S_OK)
  4006. continue;
  4007. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4008. /* but we need ha->info2, not yet stored in scp->SCp */
  4009. /* devtype, cluster info, R/W attribs */
  4010. cmd->Service = CACHESERVICE;
  4011. cmd->OpCode = GDT_DEVTYPE;
  4012. if (ha->cache_feat & GDT_64BIT)
  4013. cmd->u.cache64.DeviceNo = i;
  4014. else
  4015. cmd->u.cache.DeviceNo = i;
  4016. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4017. spin_lock_irqsave(&ha->smp_lock, flags);
  4018. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4019. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4020. cmd->Service = CACHESERVICE;
  4021. cmd->OpCode = GDT_CLUST_INFO;
  4022. if (ha->cache_feat & GDT_64BIT)
  4023. cmd->u.cache64.DeviceNo = i;
  4024. else
  4025. cmd->u.cache.DeviceNo = i;
  4026. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4027. spin_lock_irqsave(&ha->smp_lock, flags);
  4028. ha->hdr[i].cluster_type =
  4029. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4030. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4031. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4032. cmd->Service = CACHESERVICE;
  4033. cmd->OpCode = GDT_RW_ATTRIBS;
  4034. if (ha->cache_feat & GDT_64BIT)
  4035. cmd->u.cache64.DeviceNo = i;
  4036. else
  4037. cmd->u.cache.DeviceNo = i;
  4038. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4039. spin_lock_irqsave(&ha->smp_lock, flags);
  4040. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4041. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4042. }
  4043. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4044. rc = -EFAULT;
  4045. else
  4046. rc = 0;
  4047. free_fail:
  4048. kfree(rsc);
  4049. kfree(cmd);
  4050. return rc;
  4051. }
  4052. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4053. unsigned int cmd, unsigned long arg)
  4054. {
  4055. gdth_ha_str *ha;
  4056. Scsi_Cmnd *scp;
  4057. ulong flags;
  4058. char cmnd[MAX_COMMAND_SIZE];
  4059. void __user *argp = (void __user *)arg;
  4060. memset(cmnd, 0xff, 12);
  4061. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4062. switch (cmd) {
  4063. case GDTIOCTL_CTRCNT:
  4064. {
  4065. int cnt = gdth_ctr_count;
  4066. if (put_user(cnt, (int __user *)argp))
  4067. return -EFAULT;
  4068. break;
  4069. }
  4070. case GDTIOCTL_DRVERS:
  4071. {
  4072. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4073. if (put_user(ver, (int __user *)argp))
  4074. return -EFAULT;
  4075. break;
  4076. }
  4077. case GDTIOCTL_OSVERS:
  4078. {
  4079. gdth_ioctl_osvers osv;
  4080. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4081. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4082. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4083. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4084. return -EFAULT;
  4085. break;
  4086. }
  4087. case GDTIOCTL_CTRTYPE:
  4088. {
  4089. gdth_ioctl_ctrtype ctrt;
  4090. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4091. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4092. return -EFAULT;
  4093. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4094. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4095. } else {
  4096. if (ha->type != GDT_PCIMPR) {
  4097. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4098. } else {
  4099. ctrt.type =
  4100. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4101. if (ha->stype >= 0x300)
  4102. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4103. else
  4104. ctrt.ext_type = 0x6000 | ha->stype;
  4105. }
  4106. ctrt.device_id = ha->pdev->device;
  4107. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4108. }
  4109. ctrt.info = ha->brd_phys;
  4110. ctrt.oem_id = ha->oem_id;
  4111. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4112. return -EFAULT;
  4113. break;
  4114. }
  4115. case GDTIOCTL_GENERAL:
  4116. return ioc_general(argp, cmnd);
  4117. case GDTIOCTL_EVENT:
  4118. return ioc_event(argp);
  4119. case GDTIOCTL_LOCKDRV:
  4120. return ioc_lockdrv(argp);
  4121. case GDTIOCTL_LOCKCHN:
  4122. {
  4123. gdth_ioctl_lockchn lchn;
  4124. unchar i, j;
  4125. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4126. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4127. return -EFAULT;
  4128. i = lchn.channel;
  4129. if (i < ha->bus_cnt) {
  4130. if (lchn.lock) {
  4131. spin_lock_irqsave(&ha->smp_lock, flags);
  4132. ha->raw[i].lock = 1;
  4133. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4134. for (j = 0; j < ha->tid_cnt; ++j) {
  4135. gdth_wait_completion(ha, i, j);
  4136. gdth_stop_timeout(ha, i, j);
  4137. }
  4138. } else {
  4139. spin_lock_irqsave(&ha->smp_lock, flags);
  4140. ha->raw[i].lock = 0;
  4141. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4142. for (j = 0; j < ha->tid_cnt; ++j) {
  4143. gdth_start_timeout(ha, i, j);
  4144. gdth_next(ha);
  4145. }
  4146. }
  4147. }
  4148. break;
  4149. }
  4150. case GDTIOCTL_RESCAN:
  4151. return ioc_rescan(argp, cmnd);
  4152. case GDTIOCTL_HDRLIST:
  4153. return ioc_hdrlist(argp, cmnd);
  4154. case GDTIOCTL_RESET_BUS:
  4155. {
  4156. gdth_ioctl_reset res;
  4157. int rval;
  4158. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4159. (NULL == (ha = gdth_find_ha(res.ionode))))
  4160. return -EFAULT;
  4161. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4162. if (!scp)
  4163. return -ENOMEM;
  4164. scp->device = ha->sdev;
  4165. scp->cmd_len = 12;
  4166. scp->device->channel = res.number;
  4167. rval = gdth_eh_bus_reset(scp);
  4168. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4169. kfree(scp);
  4170. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4171. return -EFAULT;
  4172. break;
  4173. }
  4174. case GDTIOCTL_RESET_DRV:
  4175. return ioc_resetdrv(argp, cmnd);
  4176. default:
  4177. break;
  4178. }
  4179. return 0;
  4180. }
  4181. /* flush routine */
  4182. static void gdth_flush(gdth_ha_str *ha)
  4183. {
  4184. int i;
  4185. gdth_cmd_str gdtcmd;
  4186. char cmnd[MAX_COMMAND_SIZE];
  4187. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4188. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4189. for (i = 0; i < MAX_HDRIVES; ++i) {
  4190. if (ha->hdr[i].present) {
  4191. gdtcmd.BoardNode = LOCALBOARD;
  4192. gdtcmd.Service = CACHESERVICE;
  4193. gdtcmd.OpCode = GDT_FLUSH;
  4194. if (ha->cache_feat & GDT_64BIT) {
  4195. gdtcmd.u.cache64.DeviceNo = i;
  4196. gdtcmd.u.cache64.BlockNo = 1;
  4197. gdtcmd.u.cache64.sg_canz = 0;
  4198. } else {
  4199. gdtcmd.u.cache.DeviceNo = i;
  4200. gdtcmd.u.cache.BlockNo = 1;
  4201. gdtcmd.u.cache.sg_canz = 0;
  4202. }
  4203. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4204. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4205. }
  4206. }
  4207. }
  4208. /* shutdown routine */
  4209. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4210. {
  4211. gdth_ha_str *ha;
  4212. #ifndef __alpha__
  4213. gdth_cmd_str gdtcmd;
  4214. char cmnd[MAX_COMMAND_SIZE];
  4215. #endif
  4216. if (notifier_disabled)
  4217. return NOTIFY_OK;
  4218. TRACE2(("gdth_halt() event %d\n",(int)event));
  4219. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4220. return NOTIFY_DONE;
  4221. notifier_disabled = 1;
  4222. printk("GDT-HA: Flushing all host drives .. ");
  4223. list_for_each_entry(ha, &gdth_instances, list) {
  4224. gdth_flush(ha);
  4225. #ifndef __alpha__
  4226. /* controller reset */
  4227. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4228. gdtcmd.BoardNode = LOCALBOARD;
  4229. gdtcmd.Service = CACHESERVICE;
  4230. gdtcmd.OpCode = GDT_RESET;
  4231. TRACE2(("gdth_halt(): reset controller %d\n", ha->hanum));
  4232. gdth_execute(ha->shost, &gdtcmd, cmnd, 10, NULL);
  4233. #endif
  4234. }
  4235. printk("Done.\n");
  4236. #ifdef GDTH_STATISTICS
  4237. del_timer(&gdth_timer);
  4238. #endif
  4239. return NOTIFY_OK;
  4240. }
  4241. /* configure lun */
  4242. static int gdth_slave_configure(struct scsi_device *sdev)
  4243. {
  4244. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4245. sdev->skip_ms_page_3f = 1;
  4246. sdev->skip_ms_page_8 = 1;
  4247. return 0;
  4248. }
  4249. static struct scsi_host_template gdth_template = {
  4250. .name = "GDT SCSI Disk Array Controller",
  4251. .info = gdth_info,
  4252. .queuecommand = gdth_queuecommand,
  4253. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4254. .slave_configure = gdth_slave_configure,
  4255. .bios_param = gdth_bios_param,
  4256. .proc_info = gdth_proc_info,
  4257. .proc_name = "gdth",
  4258. .can_queue = GDTH_MAXCMDS,
  4259. .this_id = -1,
  4260. .sg_tablesize = GDTH_MAXSG,
  4261. .cmd_per_lun = GDTH_MAXC_P_L,
  4262. .unchecked_isa_dma = 1,
  4263. .use_clustering = ENABLE_CLUSTERING,
  4264. };
  4265. #ifdef CONFIG_ISA
  4266. static int gdth_isa_probe_one(ulong32 isa_bios)
  4267. {
  4268. struct Scsi_Host *shp;
  4269. gdth_ha_str *ha;
  4270. dma_addr_t scratch_dma_handle = 0;
  4271. int error, i;
  4272. if (!gdth_search_isa(isa_bios))
  4273. return -ENXIO;
  4274. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4275. if (!shp)
  4276. return -ENOMEM;
  4277. ha = shost_priv(shp);
  4278. error = -ENODEV;
  4279. if (!gdth_init_isa(isa_bios,ha))
  4280. goto out_host_put;
  4281. /* controller found and initialized */
  4282. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4283. isa_bios, ha->irq, ha->drq);
  4284. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4285. if (error) {
  4286. printk("GDT-ISA: Unable to allocate IRQ\n");
  4287. goto out_host_put;
  4288. }
  4289. error = request_dma(ha->drq, "gdth");
  4290. if (error) {
  4291. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4292. goto out_free_irq;
  4293. }
  4294. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4295. enable_dma(ha->drq);
  4296. shp->unchecked_isa_dma = 1;
  4297. shp->irq = ha->irq;
  4298. shp->dma_channel = ha->drq;
  4299. ha->hanum = gdth_ctr_count++;
  4300. ha->shost = shp;
  4301. ha->pccb = &ha->cmdext;
  4302. ha->ccb_phys = 0L;
  4303. ha->pdev = NULL;
  4304. error = -ENOMEM;
  4305. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4306. &scratch_dma_handle);
  4307. if (!ha->pscratch)
  4308. goto out_dec_counters;
  4309. ha->scratch_phys = scratch_dma_handle;
  4310. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4311. &scratch_dma_handle);
  4312. if (!ha->pmsg)
  4313. goto out_free_pscratch;
  4314. ha->msg_phys = scratch_dma_handle;
  4315. #ifdef INT_COAL
  4316. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4317. sizeof(gdth_coal_status) * MAXOFFSETS,
  4318. &scratch_dma_handle);
  4319. if (!ha->coal_stat)
  4320. goto out_free_pmsg;
  4321. ha->coal_stat_phys = scratch_dma_handle;
  4322. #endif
  4323. ha->scratch_busy = FALSE;
  4324. ha->req_first = NULL;
  4325. ha->tid_cnt = MAX_HDRIVES;
  4326. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4327. ha->tid_cnt = max_ids;
  4328. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4329. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4330. ha->scan_mode = rescan ? 0x10 : 0;
  4331. error = -ENODEV;
  4332. if (!gdth_search_drives(ha)) {
  4333. printk("GDT-ISA: Error during device scan\n");
  4334. goto out_free_coal_stat;
  4335. }
  4336. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4337. hdr_channel = ha->bus_cnt;
  4338. ha->virt_bus = hdr_channel;
  4339. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4340. shp->max_cmd_len = 16;
  4341. shp->max_id = ha->tid_cnt;
  4342. shp->max_lun = MAXLUN;
  4343. shp->max_channel = ha->bus_cnt;
  4344. spin_lock_init(&ha->smp_lock);
  4345. gdth_enable_int(ha);
  4346. error = scsi_add_host(shp, NULL);
  4347. if (error)
  4348. goto out_free_coal_stat;
  4349. list_add_tail(&ha->list, &gdth_instances);
  4350. return 0;
  4351. out_free_coal_stat:
  4352. #ifdef INT_COAL
  4353. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4354. ha->coal_stat, ha->coal_stat_phys);
  4355. out_free_pmsg:
  4356. #endif
  4357. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4358. ha->pmsg, ha->msg_phys);
  4359. out_free_pscratch:
  4360. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4361. ha->pscratch, ha->scratch_phys);
  4362. out_dec_counters:
  4363. gdth_ctr_count--;
  4364. out_free_irq:
  4365. free_irq(ha->irq, ha);
  4366. out_host_put:
  4367. scsi_host_put(shp);
  4368. return error;
  4369. }
  4370. #endif /* CONFIG_ISA */
  4371. #ifdef CONFIG_EISA
  4372. static int gdth_eisa_probe_one(ushort eisa_slot)
  4373. {
  4374. struct Scsi_Host *shp;
  4375. gdth_ha_str *ha;
  4376. dma_addr_t scratch_dma_handle = 0;
  4377. int error, i;
  4378. if (!gdth_search_eisa(eisa_slot))
  4379. return -ENXIO;
  4380. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4381. if (!shp)
  4382. return -ENOMEM;
  4383. ha = shost_priv(shp);
  4384. error = -ENODEV;
  4385. if (!gdth_init_eisa(eisa_slot,ha))
  4386. goto out_host_put;
  4387. /* controller found and initialized */
  4388. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4389. eisa_slot >> 12, ha->irq);
  4390. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4391. if (error) {
  4392. printk("GDT-EISA: Unable to allocate IRQ\n");
  4393. goto out_host_put;
  4394. }
  4395. shp->unchecked_isa_dma = 0;
  4396. shp->irq = ha->irq;
  4397. shp->dma_channel = 0xff;
  4398. ha->hanum = gdth_ctr_count++;
  4399. ha->shost = shp;
  4400. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4401. ha->pccb = &ha->cmdext;
  4402. ha->ccb_phys = 0L;
  4403. error = -ENOMEM;
  4404. ha->pdev = NULL;
  4405. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4406. &scratch_dma_handle);
  4407. if (!ha->pscratch)
  4408. goto out_free_irq;
  4409. ha->scratch_phys = scratch_dma_handle;
  4410. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4411. &scratch_dma_handle);
  4412. if (!ha->pmsg)
  4413. goto out_free_pscratch;
  4414. ha->msg_phys = scratch_dma_handle;
  4415. #ifdef INT_COAL
  4416. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4417. sizeof(gdth_coal_status) * MAXOFFSETS,
  4418. &scratch_dma_handle);
  4419. if (!ha->coal_stat)
  4420. goto out_free_pmsg;
  4421. ha->coal_stat_phys = scratch_dma_handle;
  4422. #endif
  4423. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4424. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4425. if (!ha->ccb_phys)
  4426. goto out_free_coal_stat;
  4427. ha->scratch_busy = FALSE;
  4428. ha->req_first = NULL;
  4429. ha->tid_cnt = MAX_HDRIVES;
  4430. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4431. ha->tid_cnt = max_ids;
  4432. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4433. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4434. ha->scan_mode = rescan ? 0x10 : 0;
  4435. if (!gdth_search_drives(ha)) {
  4436. printk("GDT-EISA: Error during device scan\n");
  4437. error = -ENODEV;
  4438. goto out_free_ccb_phys;
  4439. }
  4440. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4441. hdr_channel = ha->bus_cnt;
  4442. ha->virt_bus = hdr_channel;
  4443. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4444. shp->max_cmd_len = 16;
  4445. shp->max_id = ha->tid_cnt;
  4446. shp->max_lun = MAXLUN;
  4447. shp->max_channel = ha->bus_cnt;
  4448. spin_lock_init(&ha->smp_lock);
  4449. gdth_enable_int(ha);
  4450. error = scsi_add_host(shp, NULL);
  4451. if (error)
  4452. goto out_free_coal_stat;
  4453. list_add_tail(&ha->list, &gdth_instances);
  4454. return 0;
  4455. out_free_ccb_phys:
  4456. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4457. PCI_DMA_BIDIRECTIONAL);
  4458. out_free_coal_stat:
  4459. #ifdef INT_COAL
  4460. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4461. ha->coal_stat, ha->coal_stat_phys);
  4462. out_free_pmsg:
  4463. #endif
  4464. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4465. ha->pmsg, ha->msg_phys);
  4466. out_free_pscratch:
  4467. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4468. ha->pscratch, ha->scratch_phys);
  4469. out_free_irq:
  4470. free_irq(ha->irq, ha);
  4471. gdth_ctr_count--;
  4472. out_host_put:
  4473. scsi_host_put(shp);
  4474. return error;
  4475. }
  4476. #endif /* CONFIG_EISA */
  4477. #ifdef CONFIG_PCI
  4478. static int gdth_pci_probe_one(gdth_pci_str *pcistr, int ctr)
  4479. {
  4480. struct Scsi_Host *shp;
  4481. gdth_ha_str *ha;
  4482. dma_addr_t scratch_dma_handle = 0;
  4483. int error, i;
  4484. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4485. if (!shp)
  4486. return -ENOMEM;
  4487. ha = shost_priv(shp);
  4488. error = -ENODEV;
  4489. if (!gdth_init_pci(&pcistr[ctr],ha))
  4490. goto out_host_put;
  4491. /* controller found and initialized */
  4492. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4493. pcistr[ctr].pdev->bus->number,
  4494. PCI_SLOT(pcistr[ctr].pdev->devfn),
  4495. ha->irq);
  4496. error = request_irq(ha->irq, gdth_interrupt,
  4497. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4498. if (error) {
  4499. printk("GDT-PCI: Unable to allocate IRQ\n");
  4500. goto out_host_put;
  4501. }
  4502. shp->unchecked_isa_dma = 0;
  4503. shp->irq = ha->irq;
  4504. shp->dma_channel = 0xff;
  4505. ha->hanum = gdth_ctr_count++;
  4506. ha->shost = shp;
  4507. ha->pccb = &ha->cmdext;
  4508. ha->ccb_phys = 0L;
  4509. error = -ENOMEM;
  4510. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4511. &scratch_dma_handle);
  4512. if (!ha->pscratch)
  4513. goto out_free_irq;
  4514. ha->scratch_phys = scratch_dma_handle;
  4515. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4516. &scratch_dma_handle);
  4517. if (!ha->pmsg)
  4518. goto out_free_pscratch;
  4519. ha->msg_phys = scratch_dma_handle;
  4520. #ifdef INT_COAL
  4521. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4522. sizeof(gdth_coal_status) * MAXOFFSETS,
  4523. &scratch_dma_handle);
  4524. if (!ha->coal_stat)
  4525. goto out_free_pmsg;
  4526. ha->coal_stat_phys = scratch_dma_handle;
  4527. #endif
  4528. ha->scratch_busy = FALSE;
  4529. ha->req_first = NULL;
  4530. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4531. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4532. ha->tid_cnt = max_ids;
  4533. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4534. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4535. ha->scan_mode = rescan ? 0x10 : 0;
  4536. error = -ENODEV;
  4537. if (!gdth_search_drives(ha)) {
  4538. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4539. goto out_free_coal_stat;
  4540. }
  4541. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4542. hdr_channel = ha->bus_cnt;
  4543. ha->virt_bus = hdr_channel;
  4544. /* 64-bit DMA only supported from FW >= x.43 */
  4545. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4546. !ha->dma64_support) {
  4547. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4548. printk(KERN_WARNING "GDT-PCI %d: "
  4549. "Unable to set 32-bit DMA\n", ha->hanum);
  4550. goto out_free_coal_stat;
  4551. }
  4552. } else {
  4553. shp->max_cmd_len = 16;
  4554. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4555. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4556. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4557. printk(KERN_WARNING "GDT-PCI %d: "
  4558. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4559. goto out_free_coal_stat;
  4560. }
  4561. }
  4562. shp->max_id = ha->tid_cnt;
  4563. shp->max_lun = MAXLUN;
  4564. shp->max_channel = ha->bus_cnt;
  4565. spin_lock_init(&ha->smp_lock);
  4566. gdth_enable_int(ha);
  4567. error = scsi_add_host(shp, &pcistr[ctr].pdev->dev);
  4568. if (error)
  4569. goto out_free_coal_stat;
  4570. list_add_tail(&ha->list, &gdth_instances);
  4571. return 0;
  4572. out_free_coal_stat:
  4573. #ifdef INT_COAL
  4574. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4575. ha->coal_stat, ha->coal_stat_phys);
  4576. out_free_pmsg:
  4577. #endif
  4578. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4579. ha->pmsg, ha->msg_phys);
  4580. out_free_pscratch:
  4581. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4582. ha->pscratch, ha->scratch_phys);
  4583. out_free_irq:
  4584. free_irq(ha->irq, ha);
  4585. gdth_ctr_count--;
  4586. out_host_put:
  4587. scsi_host_put(shp);
  4588. return error;
  4589. }
  4590. #endif /* CONFIG_PCI */
  4591. static void gdth_remove_one(gdth_ha_str *ha)
  4592. {
  4593. struct Scsi_Host *shp = ha->shost;
  4594. TRACE2(("gdth_remove_one()\n"));
  4595. scsi_remove_host(shp);
  4596. if (ha->sdev) {
  4597. scsi_free_host_dev(ha->sdev);
  4598. ha->sdev = NULL;
  4599. }
  4600. gdth_flush(ha);
  4601. if (shp->irq)
  4602. free_irq(shp->irq,ha);
  4603. #ifdef CONFIG_ISA
  4604. if (shp->dma_channel != 0xff)
  4605. free_dma(shp->dma_channel);
  4606. #endif
  4607. #ifdef INT_COAL
  4608. if (ha->coal_stat)
  4609. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4610. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4611. #endif
  4612. if (ha->pscratch)
  4613. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4614. ha->pscratch, ha->scratch_phys);
  4615. if (ha->pmsg)
  4616. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4617. ha->pmsg, ha->msg_phys);
  4618. if (ha->ccb_phys)
  4619. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4620. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4621. scsi_host_put(shp);
  4622. }
  4623. static int __init gdth_init(void)
  4624. {
  4625. if (disable) {
  4626. printk("GDT-HA: Controller driver disabled from"
  4627. " command line !\n");
  4628. return 0;
  4629. }
  4630. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4631. GDTH_VERSION_STR);
  4632. /* initializations */
  4633. gdth_polling = TRUE;
  4634. gdth_clear_events();
  4635. /* As default we do not probe for EISA or ISA controllers */
  4636. if (probe_eisa_isa) {
  4637. /* scanning for controllers, at first: ISA controller */
  4638. #ifdef CONFIG_ISA
  4639. ulong32 isa_bios;
  4640. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4641. isa_bios += 0x8000UL)
  4642. gdth_isa_probe_one(isa_bios);
  4643. #endif
  4644. #ifdef CONFIG_EISA
  4645. {
  4646. ushort eisa_slot;
  4647. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4648. eisa_slot += 0x1000)
  4649. gdth_eisa_probe_one(eisa_slot);
  4650. }
  4651. #endif
  4652. }
  4653. #ifdef CONFIG_PCI
  4654. /* scanning for PCI controllers */
  4655. {
  4656. gdth_pci_str pcistr[MAXHA];
  4657. int cnt,ctr;
  4658. cnt = gdth_search_pci(pcistr);
  4659. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n", cnt);
  4660. gdth_sort_pci(pcistr,cnt);
  4661. for (ctr = 0; ctr < cnt; ++ctr)
  4662. gdth_pci_probe_one(pcistr, ctr);
  4663. }
  4664. #endif /* CONFIG_PCI */
  4665. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4666. #ifdef GDTH_STATISTICS
  4667. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4668. init_timer(&gdth_timer);
  4669. gdth_timer.expires = jiffies + HZ;
  4670. gdth_timer.data = 0L;
  4671. gdth_timer.function = gdth_timeout;
  4672. add_timer(&gdth_timer);
  4673. #endif
  4674. major = register_chrdev(0,"gdth", &gdth_fops);
  4675. notifier_disabled = 0;
  4676. register_reboot_notifier(&gdth_notifier);
  4677. gdth_polling = FALSE;
  4678. return 0;
  4679. }
  4680. static void __exit gdth_exit(void)
  4681. {
  4682. gdth_ha_str *ha;
  4683. list_for_each_entry(ha, &gdth_instances, list)
  4684. gdth_remove_one(ha);
  4685. #ifdef GDTH_STATISTICS
  4686. del_timer(&gdth_timer);
  4687. #endif
  4688. unregister_chrdev(major,"gdth");
  4689. unregister_reboot_notifier(&gdth_notifier);
  4690. }
  4691. module_init(gdth_init);
  4692. module_exit(gdth_exit);
  4693. #ifndef MODULE
  4694. __setup("gdth=", option_setup);
  4695. #endif