r600_cs.c 25 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include "drmP.h"
  29. #include "radeon.h"
  30. #include "r600d.h"
  31. static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
  32. struct radeon_cs_reloc **cs_reloc);
  33. static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
  34. struct radeon_cs_reloc **cs_reloc);
  35. typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
  36. static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
  37. struct r600_cs_track {
  38. u32 cb_color0_base_last;
  39. };
  40. /**
  41. * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
  42. * @parser: parser structure holding parsing context.
  43. * @pkt: where to store packet informations
  44. *
  45. * Assume that chunk_ib_index is properly set. Will return -EINVAL
  46. * if packet is bigger than remaining ib size. or if packets is unknown.
  47. **/
  48. int r600_cs_packet_parse(struct radeon_cs_parser *p,
  49. struct radeon_cs_packet *pkt,
  50. unsigned idx)
  51. {
  52. struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
  53. uint32_t header;
  54. if (idx >= ib_chunk->length_dw) {
  55. DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
  56. idx, ib_chunk->length_dw);
  57. return -EINVAL;
  58. }
  59. header = radeon_get_ib_value(p, idx);
  60. pkt->idx = idx;
  61. pkt->type = CP_PACKET_GET_TYPE(header);
  62. pkt->count = CP_PACKET_GET_COUNT(header);
  63. pkt->one_reg_wr = 0;
  64. switch (pkt->type) {
  65. case PACKET_TYPE0:
  66. pkt->reg = CP_PACKET0_GET_REG(header);
  67. break;
  68. case PACKET_TYPE3:
  69. pkt->opcode = CP_PACKET3_GET_OPCODE(header);
  70. break;
  71. case PACKET_TYPE2:
  72. pkt->count = -1;
  73. break;
  74. default:
  75. DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
  76. return -EINVAL;
  77. }
  78. if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
  79. DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
  80. pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
  81. return -EINVAL;
  82. }
  83. return 0;
  84. }
  85. /**
  86. * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
  87. * @parser: parser structure holding parsing context.
  88. * @data: pointer to relocation data
  89. * @offset_start: starting offset
  90. * @offset_mask: offset mask (to align start offset on)
  91. * @reloc: reloc informations
  92. *
  93. * Check next packet is relocation packet3, do bo validation and compute
  94. * GPU offset using the provided start.
  95. **/
  96. static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
  97. struct radeon_cs_reloc **cs_reloc)
  98. {
  99. struct radeon_cs_chunk *relocs_chunk;
  100. struct radeon_cs_packet p3reloc;
  101. unsigned idx;
  102. int r;
  103. if (p->chunk_relocs_idx == -1) {
  104. DRM_ERROR("No relocation chunk !\n");
  105. return -EINVAL;
  106. }
  107. *cs_reloc = NULL;
  108. relocs_chunk = &p->chunks[p->chunk_relocs_idx];
  109. r = r600_cs_packet_parse(p, &p3reloc, p->idx);
  110. if (r) {
  111. return r;
  112. }
  113. p->idx += p3reloc.count + 2;
  114. if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
  115. DRM_ERROR("No packet3 for relocation for packet at %d.\n",
  116. p3reloc.idx);
  117. return -EINVAL;
  118. }
  119. idx = radeon_get_ib_value(p, p3reloc.idx + 1);
  120. if (idx >= relocs_chunk->length_dw) {
  121. DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
  122. idx, relocs_chunk->length_dw);
  123. return -EINVAL;
  124. }
  125. /* FIXME: we assume reloc size is 4 dwords */
  126. *cs_reloc = p->relocs_ptr[(idx / 4)];
  127. return 0;
  128. }
  129. /**
  130. * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
  131. * @parser: parser structure holding parsing context.
  132. * @data: pointer to relocation data
  133. * @offset_start: starting offset
  134. * @offset_mask: offset mask (to align start offset on)
  135. * @reloc: reloc informations
  136. *
  137. * Check next packet is relocation packet3, do bo validation and compute
  138. * GPU offset using the provided start.
  139. **/
  140. static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
  141. struct radeon_cs_reloc **cs_reloc)
  142. {
  143. struct radeon_cs_chunk *relocs_chunk;
  144. struct radeon_cs_packet p3reloc;
  145. unsigned idx;
  146. int r;
  147. if (p->chunk_relocs_idx == -1) {
  148. DRM_ERROR("No relocation chunk !\n");
  149. return -EINVAL;
  150. }
  151. *cs_reloc = NULL;
  152. relocs_chunk = &p->chunks[p->chunk_relocs_idx];
  153. r = r600_cs_packet_parse(p, &p3reloc, p->idx);
  154. if (r) {
  155. return r;
  156. }
  157. p->idx += p3reloc.count + 2;
  158. if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
  159. DRM_ERROR("No packet3 for relocation for packet at %d.\n",
  160. p3reloc.idx);
  161. return -EINVAL;
  162. }
  163. idx = radeon_get_ib_value(p, p3reloc.idx + 1);
  164. if (idx >= relocs_chunk->length_dw) {
  165. DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
  166. idx, relocs_chunk->length_dw);
  167. return -EINVAL;
  168. }
  169. *cs_reloc = p->relocs;
  170. (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
  171. (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
  172. return 0;
  173. }
  174. /**
  175. * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
  176. * @parser: parser structure holding parsing context.
  177. *
  178. * Check next packet is relocation packet3, do bo validation and compute
  179. * GPU offset using the provided start.
  180. **/
  181. static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
  182. {
  183. struct radeon_cs_packet p3reloc;
  184. int r;
  185. r = r600_cs_packet_parse(p, &p3reloc, p->idx);
  186. if (r) {
  187. return 0;
  188. }
  189. if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
  190. return 0;
  191. }
  192. return 1;
  193. }
  194. /**
  195. * r600_cs_packet_next_vline() - parse userspace VLINE packet
  196. * @parser: parser structure holding parsing context.
  197. *
  198. * Userspace sends a special sequence for VLINE waits.
  199. * PACKET0 - VLINE_START_END + value
  200. * PACKET3 - WAIT_REG_MEM poll vline status reg
  201. * RELOC (P3) - crtc_id in reloc.
  202. *
  203. * This function parses this and relocates the VLINE START END
  204. * and WAIT_REG_MEM packets to the correct crtc.
  205. * It also detects a switched off crtc and nulls out the
  206. * wait in that case.
  207. */
  208. static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
  209. {
  210. struct drm_mode_object *obj;
  211. struct drm_crtc *crtc;
  212. struct radeon_crtc *radeon_crtc;
  213. struct radeon_cs_packet p3reloc, wait_reg_mem;
  214. int crtc_id;
  215. int r;
  216. uint32_t header, h_idx, reg, wait_reg_mem_info;
  217. volatile uint32_t *ib;
  218. ib = p->ib->ptr;
  219. /* parse the WAIT_REG_MEM */
  220. r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
  221. if (r)
  222. return r;
  223. /* check its a WAIT_REG_MEM */
  224. if (wait_reg_mem.type != PACKET_TYPE3 ||
  225. wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
  226. DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
  227. r = -EINVAL;
  228. return r;
  229. }
  230. wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
  231. /* bit 4 is reg (0) or mem (1) */
  232. if (wait_reg_mem_info & 0x10) {
  233. DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
  234. r = -EINVAL;
  235. return r;
  236. }
  237. /* waiting for value to be equal */
  238. if ((wait_reg_mem_info & 0x7) != 0x3) {
  239. DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
  240. r = -EINVAL;
  241. return r;
  242. }
  243. if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
  244. DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
  245. r = -EINVAL;
  246. return r;
  247. }
  248. if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
  249. DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
  250. r = -EINVAL;
  251. return r;
  252. }
  253. /* jump over the NOP */
  254. r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
  255. if (r)
  256. return r;
  257. h_idx = p->idx - 2;
  258. p->idx += wait_reg_mem.count + 2;
  259. p->idx += p3reloc.count + 2;
  260. header = radeon_get_ib_value(p, h_idx);
  261. crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
  262. reg = CP_PACKET0_GET_REG(header);
  263. mutex_lock(&p->rdev->ddev->mode_config.mutex);
  264. obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
  265. if (!obj) {
  266. DRM_ERROR("cannot find crtc %d\n", crtc_id);
  267. r = -EINVAL;
  268. goto out;
  269. }
  270. crtc = obj_to_crtc(obj);
  271. radeon_crtc = to_radeon_crtc(crtc);
  272. crtc_id = radeon_crtc->crtc_id;
  273. if (!crtc->enabled) {
  274. /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
  275. ib[h_idx + 2] = PACKET2(0);
  276. ib[h_idx + 3] = PACKET2(0);
  277. ib[h_idx + 4] = PACKET2(0);
  278. ib[h_idx + 5] = PACKET2(0);
  279. ib[h_idx + 6] = PACKET2(0);
  280. ib[h_idx + 7] = PACKET2(0);
  281. ib[h_idx + 8] = PACKET2(0);
  282. } else if (crtc_id == 1) {
  283. switch (reg) {
  284. case AVIVO_D1MODE_VLINE_START_END:
  285. header &= ~R600_CP_PACKET0_REG_MASK;
  286. header |= AVIVO_D2MODE_VLINE_START_END >> 2;
  287. break;
  288. default:
  289. DRM_ERROR("unknown crtc reloc\n");
  290. r = -EINVAL;
  291. goto out;
  292. }
  293. ib[h_idx] = header;
  294. ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
  295. }
  296. out:
  297. mutex_unlock(&p->rdev->ddev->mode_config.mutex);
  298. return r;
  299. }
  300. static int r600_packet0_check(struct radeon_cs_parser *p,
  301. struct radeon_cs_packet *pkt,
  302. unsigned idx, unsigned reg)
  303. {
  304. int r;
  305. switch (reg) {
  306. case AVIVO_D1MODE_VLINE_START_END:
  307. r = r600_cs_packet_parse_vline(p);
  308. if (r) {
  309. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  310. idx, reg);
  311. return r;
  312. }
  313. break;
  314. default:
  315. printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
  316. reg, idx);
  317. return -EINVAL;
  318. }
  319. return 0;
  320. }
  321. static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
  322. struct radeon_cs_packet *pkt)
  323. {
  324. unsigned reg, i;
  325. unsigned idx;
  326. int r;
  327. idx = pkt->idx + 1;
  328. reg = pkt->reg;
  329. for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
  330. r = r600_packet0_check(p, pkt, idx, reg);
  331. if (r) {
  332. return r;
  333. }
  334. }
  335. return 0;
  336. }
  337. static int r600_packet3_check(struct radeon_cs_parser *p,
  338. struct radeon_cs_packet *pkt)
  339. {
  340. struct radeon_cs_reloc *reloc;
  341. struct r600_cs_track *track;
  342. volatile u32 *ib;
  343. unsigned idx;
  344. unsigned i;
  345. unsigned start_reg, end_reg, reg;
  346. int r;
  347. u32 idx_value;
  348. track = (struct r600_cs_track *)p->track;
  349. ib = p->ib->ptr;
  350. idx = pkt->idx + 1;
  351. idx_value = radeon_get_ib_value(p, idx);
  352. switch (pkt->opcode) {
  353. case PACKET3_START_3D_CMDBUF:
  354. if (p->family >= CHIP_RV770 || pkt->count) {
  355. DRM_ERROR("bad START_3D\n");
  356. return -EINVAL;
  357. }
  358. break;
  359. case PACKET3_CONTEXT_CONTROL:
  360. if (pkt->count != 1) {
  361. DRM_ERROR("bad CONTEXT_CONTROL\n");
  362. return -EINVAL;
  363. }
  364. break;
  365. case PACKET3_INDEX_TYPE:
  366. case PACKET3_NUM_INSTANCES:
  367. if (pkt->count) {
  368. DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
  369. return -EINVAL;
  370. }
  371. break;
  372. case PACKET3_DRAW_INDEX:
  373. if (pkt->count != 3) {
  374. DRM_ERROR("bad DRAW_INDEX\n");
  375. return -EINVAL;
  376. }
  377. r = r600_cs_packet_next_reloc(p, &reloc);
  378. if (r) {
  379. DRM_ERROR("bad DRAW_INDEX\n");
  380. return -EINVAL;
  381. }
  382. ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  383. ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  384. break;
  385. case PACKET3_DRAW_INDEX_AUTO:
  386. if (pkt->count != 1) {
  387. DRM_ERROR("bad DRAW_INDEX_AUTO\n");
  388. return -EINVAL;
  389. }
  390. break;
  391. case PACKET3_DRAW_INDEX_IMMD_BE:
  392. case PACKET3_DRAW_INDEX_IMMD:
  393. if (pkt->count < 2) {
  394. DRM_ERROR("bad DRAW_INDEX_IMMD\n");
  395. return -EINVAL;
  396. }
  397. break;
  398. case PACKET3_WAIT_REG_MEM:
  399. if (pkt->count != 5) {
  400. DRM_ERROR("bad WAIT_REG_MEM\n");
  401. return -EINVAL;
  402. }
  403. /* bit 4 is reg (0) or mem (1) */
  404. if (idx_value & 0x10) {
  405. r = r600_cs_packet_next_reloc(p, &reloc);
  406. if (r) {
  407. DRM_ERROR("bad WAIT_REG_MEM\n");
  408. return -EINVAL;
  409. }
  410. ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  411. ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  412. }
  413. break;
  414. case PACKET3_SURFACE_SYNC:
  415. if (pkt->count != 3) {
  416. DRM_ERROR("bad SURFACE_SYNC\n");
  417. return -EINVAL;
  418. }
  419. /* 0xffffffff/0x0 is flush all cache flag */
  420. if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
  421. radeon_get_ib_value(p, idx + 2) != 0) {
  422. r = r600_cs_packet_next_reloc(p, &reloc);
  423. if (r) {
  424. DRM_ERROR("bad SURFACE_SYNC\n");
  425. return -EINVAL;
  426. }
  427. ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  428. }
  429. break;
  430. case PACKET3_EVENT_WRITE:
  431. if (pkt->count != 2 && pkt->count != 0) {
  432. DRM_ERROR("bad EVENT_WRITE\n");
  433. return -EINVAL;
  434. }
  435. if (pkt->count) {
  436. r = r600_cs_packet_next_reloc(p, &reloc);
  437. if (r) {
  438. DRM_ERROR("bad EVENT_WRITE\n");
  439. return -EINVAL;
  440. }
  441. ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  442. ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  443. }
  444. break;
  445. case PACKET3_EVENT_WRITE_EOP:
  446. if (pkt->count != 4) {
  447. DRM_ERROR("bad EVENT_WRITE_EOP\n");
  448. return -EINVAL;
  449. }
  450. r = r600_cs_packet_next_reloc(p, &reloc);
  451. if (r) {
  452. DRM_ERROR("bad EVENT_WRITE\n");
  453. return -EINVAL;
  454. }
  455. ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  456. ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  457. break;
  458. case PACKET3_SET_CONFIG_REG:
  459. start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
  460. end_reg = 4 * pkt->count + start_reg - 4;
  461. if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
  462. (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
  463. (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
  464. DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
  465. return -EINVAL;
  466. }
  467. for (i = 0; i < pkt->count; i++) {
  468. reg = start_reg + (4 * i);
  469. switch (reg) {
  470. case SQ_ESGS_RING_BASE:
  471. case SQ_GSVS_RING_BASE:
  472. case SQ_ESTMP_RING_BASE:
  473. case SQ_GSTMP_RING_BASE:
  474. case SQ_VSTMP_RING_BASE:
  475. case SQ_PSTMP_RING_BASE:
  476. case SQ_FBUF_RING_BASE:
  477. case SQ_REDUC_RING_BASE:
  478. case SX_MEMORY_EXPORT_BASE:
  479. r = r600_cs_packet_next_reloc(p, &reloc);
  480. if (r) {
  481. DRM_ERROR("bad SET_CONFIG_REG "
  482. "0x%04X\n", reg);
  483. return -EINVAL;
  484. }
  485. ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  486. break;
  487. case CP_COHER_BASE:
  488. /* use PACKET3_SURFACE_SYNC */
  489. return -EINVAL;
  490. default:
  491. break;
  492. }
  493. }
  494. break;
  495. case PACKET3_SET_CONTEXT_REG:
  496. start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
  497. end_reg = 4 * pkt->count + start_reg - 4;
  498. if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
  499. (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
  500. (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
  501. DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
  502. return -EINVAL;
  503. }
  504. for (i = 0; i < pkt->count; i++) {
  505. reg = start_reg + (4 * i);
  506. switch (reg) {
  507. /* This register were added late, there is userspace
  508. * which does provide relocation for those but set
  509. * 0 offset. In order to avoid breaking old userspace
  510. * we detect this and set address to point to last
  511. * CB_COLOR0_BASE, note that if userspace doesn't set
  512. * CB_COLOR0_BASE before this register we will report
  513. * error. Old userspace always set CB_COLOR0_BASE
  514. * before any of this.
  515. */
  516. case R_0280E0_CB_COLOR0_FRAG:
  517. case R_0280E4_CB_COLOR1_FRAG:
  518. case R_0280E8_CB_COLOR2_FRAG:
  519. case R_0280EC_CB_COLOR3_FRAG:
  520. case R_0280F0_CB_COLOR4_FRAG:
  521. case R_0280F4_CB_COLOR5_FRAG:
  522. case R_0280F8_CB_COLOR6_FRAG:
  523. case R_0280FC_CB_COLOR7_FRAG:
  524. case R_0280C0_CB_COLOR0_TILE:
  525. case R_0280C4_CB_COLOR1_TILE:
  526. case R_0280C8_CB_COLOR2_TILE:
  527. case R_0280CC_CB_COLOR3_TILE:
  528. case R_0280D0_CB_COLOR4_TILE:
  529. case R_0280D4_CB_COLOR5_TILE:
  530. case R_0280D8_CB_COLOR6_TILE:
  531. case R_0280DC_CB_COLOR7_TILE:
  532. if (!r600_cs_packet_next_is_pkt3_nop(p)) {
  533. if (!track->cb_color0_base_last) {
  534. dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
  535. return -EINVAL;
  536. }
  537. ib[idx+1+i] = track->cb_color0_base_last;
  538. printk_once(KERN_WARNING "You have old & broken userspace "
  539. "please consider updating mesa & xf86-video-ati\n");
  540. } else {
  541. r = r600_cs_packet_next_reloc(p, &reloc);
  542. if (r) {
  543. dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
  544. return -EINVAL;
  545. }
  546. ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  547. }
  548. break;
  549. case DB_DEPTH_BASE:
  550. case DB_HTILE_DATA_BASE:
  551. case CB_COLOR0_BASE:
  552. r = r600_cs_packet_next_reloc(p, &reloc);
  553. if (r) {
  554. DRM_ERROR("bad SET_CONTEXT_REG "
  555. "0x%04X\n", reg);
  556. return -EINVAL;
  557. }
  558. ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  559. track->cb_color0_base_last = ib[idx+1+i];
  560. break;
  561. case CB_COLOR1_BASE:
  562. case CB_COLOR2_BASE:
  563. case CB_COLOR3_BASE:
  564. case CB_COLOR4_BASE:
  565. case CB_COLOR5_BASE:
  566. case CB_COLOR6_BASE:
  567. case CB_COLOR7_BASE:
  568. case SQ_PGM_START_FS:
  569. case SQ_PGM_START_ES:
  570. case SQ_PGM_START_VS:
  571. case SQ_PGM_START_GS:
  572. case SQ_PGM_START_PS:
  573. r = r600_cs_packet_next_reloc(p, &reloc);
  574. if (r) {
  575. DRM_ERROR("bad SET_CONTEXT_REG "
  576. "0x%04X\n", reg);
  577. return -EINVAL;
  578. }
  579. ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  580. break;
  581. case VGT_DMA_BASE:
  582. case VGT_DMA_BASE_HI:
  583. /* These should be handled by DRAW_INDEX packet 3 */
  584. case VGT_STRMOUT_BASE_OFFSET_0:
  585. case VGT_STRMOUT_BASE_OFFSET_1:
  586. case VGT_STRMOUT_BASE_OFFSET_2:
  587. case VGT_STRMOUT_BASE_OFFSET_3:
  588. case VGT_STRMOUT_BASE_OFFSET_HI_0:
  589. case VGT_STRMOUT_BASE_OFFSET_HI_1:
  590. case VGT_STRMOUT_BASE_OFFSET_HI_2:
  591. case VGT_STRMOUT_BASE_OFFSET_HI_3:
  592. case VGT_STRMOUT_BUFFER_BASE_0:
  593. case VGT_STRMOUT_BUFFER_BASE_1:
  594. case VGT_STRMOUT_BUFFER_BASE_2:
  595. case VGT_STRMOUT_BUFFER_BASE_3:
  596. case VGT_STRMOUT_BUFFER_OFFSET_0:
  597. case VGT_STRMOUT_BUFFER_OFFSET_1:
  598. case VGT_STRMOUT_BUFFER_OFFSET_2:
  599. case VGT_STRMOUT_BUFFER_OFFSET_3:
  600. /* These should be handled by STRMOUT_BUFFER packet 3 */
  601. DRM_ERROR("bad context reg: 0x%08x\n", reg);
  602. return -EINVAL;
  603. default:
  604. break;
  605. }
  606. }
  607. break;
  608. case PACKET3_SET_RESOURCE:
  609. if (pkt->count % 7) {
  610. DRM_ERROR("bad SET_RESOURCE\n");
  611. return -EINVAL;
  612. }
  613. start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
  614. end_reg = 4 * pkt->count + start_reg - 4;
  615. if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
  616. (start_reg >= PACKET3_SET_RESOURCE_END) ||
  617. (end_reg >= PACKET3_SET_RESOURCE_END)) {
  618. DRM_ERROR("bad SET_RESOURCE\n");
  619. return -EINVAL;
  620. }
  621. for (i = 0; i < (pkt->count / 7); i++) {
  622. switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
  623. case SQ_TEX_VTX_VALID_TEXTURE:
  624. /* tex base */
  625. r = r600_cs_packet_next_reloc(p, &reloc);
  626. if (r) {
  627. DRM_ERROR("bad SET_RESOURCE\n");
  628. return -EINVAL;
  629. }
  630. ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  631. /* tex mip base */
  632. r = r600_cs_packet_next_reloc(p, &reloc);
  633. if (r) {
  634. DRM_ERROR("bad SET_RESOURCE\n");
  635. return -EINVAL;
  636. }
  637. ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  638. break;
  639. case SQ_TEX_VTX_VALID_BUFFER:
  640. /* vtx base */
  641. r = r600_cs_packet_next_reloc(p, &reloc);
  642. if (r) {
  643. DRM_ERROR("bad SET_RESOURCE\n");
  644. return -EINVAL;
  645. }
  646. ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
  647. ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  648. break;
  649. case SQ_TEX_VTX_INVALID_TEXTURE:
  650. case SQ_TEX_VTX_INVALID_BUFFER:
  651. default:
  652. DRM_ERROR("bad SET_RESOURCE\n");
  653. return -EINVAL;
  654. }
  655. }
  656. break;
  657. case PACKET3_SET_ALU_CONST:
  658. start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
  659. end_reg = 4 * pkt->count + start_reg - 4;
  660. if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
  661. (start_reg >= PACKET3_SET_ALU_CONST_END) ||
  662. (end_reg >= PACKET3_SET_ALU_CONST_END)) {
  663. DRM_ERROR("bad SET_ALU_CONST\n");
  664. return -EINVAL;
  665. }
  666. break;
  667. case PACKET3_SET_BOOL_CONST:
  668. start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
  669. end_reg = 4 * pkt->count + start_reg - 4;
  670. if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
  671. (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
  672. (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
  673. DRM_ERROR("bad SET_BOOL_CONST\n");
  674. return -EINVAL;
  675. }
  676. break;
  677. case PACKET3_SET_LOOP_CONST:
  678. start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
  679. end_reg = 4 * pkt->count + start_reg - 4;
  680. if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
  681. (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
  682. (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
  683. DRM_ERROR("bad SET_LOOP_CONST\n");
  684. return -EINVAL;
  685. }
  686. break;
  687. case PACKET3_SET_CTL_CONST:
  688. start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
  689. end_reg = 4 * pkt->count + start_reg - 4;
  690. if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
  691. (start_reg >= PACKET3_SET_CTL_CONST_END) ||
  692. (end_reg >= PACKET3_SET_CTL_CONST_END)) {
  693. DRM_ERROR("bad SET_CTL_CONST\n");
  694. return -EINVAL;
  695. }
  696. break;
  697. case PACKET3_SET_SAMPLER:
  698. if (pkt->count % 3) {
  699. DRM_ERROR("bad SET_SAMPLER\n");
  700. return -EINVAL;
  701. }
  702. start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
  703. end_reg = 4 * pkt->count + start_reg - 4;
  704. if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
  705. (start_reg >= PACKET3_SET_SAMPLER_END) ||
  706. (end_reg >= PACKET3_SET_SAMPLER_END)) {
  707. DRM_ERROR("bad SET_SAMPLER\n");
  708. return -EINVAL;
  709. }
  710. break;
  711. case PACKET3_SURFACE_BASE_UPDATE:
  712. if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
  713. DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
  714. return -EINVAL;
  715. }
  716. if (pkt->count) {
  717. DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
  718. return -EINVAL;
  719. }
  720. break;
  721. case PACKET3_NOP:
  722. break;
  723. default:
  724. DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
  725. return -EINVAL;
  726. }
  727. return 0;
  728. }
  729. int r600_cs_parse(struct radeon_cs_parser *p)
  730. {
  731. struct radeon_cs_packet pkt;
  732. struct r600_cs_track *track;
  733. int r;
  734. track = kzalloc(sizeof(*track), GFP_KERNEL);
  735. p->track = track;
  736. do {
  737. r = r600_cs_packet_parse(p, &pkt, p->idx);
  738. if (r) {
  739. return r;
  740. }
  741. p->idx += pkt.count + 2;
  742. switch (pkt.type) {
  743. case PACKET_TYPE0:
  744. r = r600_cs_parse_packet0(p, &pkt);
  745. break;
  746. case PACKET_TYPE2:
  747. break;
  748. case PACKET_TYPE3:
  749. r = r600_packet3_check(p, &pkt);
  750. break;
  751. default:
  752. DRM_ERROR("Unknown packet type %d !\n", pkt.type);
  753. return -EINVAL;
  754. }
  755. if (r) {
  756. return r;
  757. }
  758. } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
  759. #if 0
  760. for (r = 0; r < p->ib->length_dw; r++) {
  761. printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
  762. mdelay(1);
  763. }
  764. #endif
  765. return 0;
  766. }
  767. static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
  768. {
  769. if (p->chunk_relocs_idx == -1) {
  770. return 0;
  771. }
  772. p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
  773. if (p->relocs == NULL) {
  774. return -ENOMEM;
  775. }
  776. return 0;
  777. }
  778. /**
  779. * cs_parser_fini() - clean parser states
  780. * @parser: parser structure holding parsing context.
  781. * @error: error number
  782. *
  783. * If error is set than unvalidate buffer, otherwise just free memory
  784. * used by parsing context.
  785. **/
  786. static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
  787. {
  788. unsigned i;
  789. kfree(parser->relocs);
  790. for (i = 0; i < parser->nchunks; i++) {
  791. kfree(parser->chunks[i].kdata);
  792. kfree(parser->chunks[i].kpage[0]);
  793. kfree(parser->chunks[i].kpage[1]);
  794. }
  795. kfree(parser->chunks);
  796. kfree(parser->chunks_array);
  797. }
  798. int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
  799. unsigned family, u32 *ib, int *l)
  800. {
  801. struct radeon_cs_parser parser;
  802. struct radeon_cs_chunk *ib_chunk;
  803. struct radeon_ib fake_ib;
  804. int r;
  805. /* initialize parser */
  806. memset(&parser, 0, sizeof(struct radeon_cs_parser));
  807. parser.filp = filp;
  808. parser.dev = &dev->pdev->dev;
  809. parser.rdev = NULL;
  810. parser.family = family;
  811. parser.ib = &fake_ib;
  812. fake_ib.ptr = ib;
  813. r = radeon_cs_parser_init(&parser, data);
  814. if (r) {
  815. DRM_ERROR("Failed to initialize parser !\n");
  816. r600_cs_parser_fini(&parser, r);
  817. return r;
  818. }
  819. r = r600_cs_parser_relocs_legacy(&parser);
  820. if (r) {
  821. DRM_ERROR("Failed to parse relocation !\n");
  822. r600_cs_parser_fini(&parser, r);
  823. return r;
  824. }
  825. /* Copy the packet into the IB, the parser will read from the
  826. * input memory (cached) and write to the IB (which can be
  827. * uncached). */
  828. ib_chunk = &parser.chunks[parser.chunk_ib_idx];
  829. parser.ib->length_dw = ib_chunk->length_dw;
  830. *l = parser.ib->length_dw;
  831. r = r600_cs_parse(&parser);
  832. if (r) {
  833. DRM_ERROR("Invalid command stream !\n");
  834. r600_cs_parser_fini(&parser, r);
  835. return r;
  836. }
  837. r = radeon_cs_finish_pages(&parser);
  838. if (r) {
  839. DRM_ERROR("Invalid command stream !\n");
  840. r600_cs_parser_fini(&parser, r);
  841. return r;
  842. }
  843. r600_cs_parser_fini(&parser, r);
  844. return r;
  845. }
  846. void r600_cs_legacy_init(void)
  847. {
  848. r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
  849. }