twl4030.c 73 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl.h>
  29. #include <linux/slab.h>
  30. #include <sound/core.h>
  31. #include <sound/pcm.h>
  32. #include <sound/pcm_params.h>
  33. #include <sound/soc.h>
  34. #include <sound/soc-dapm.h>
  35. #include <sound/initval.h>
  36. #include <sound/tlv.h>
  37. #include "twl4030.h"
  38. /*
  39. * twl4030 register cache & default register settings
  40. */
  41. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  42. 0x00, /* this register not used */
  43. 0x00, /* REG_CODEC_MODE (0x1) */
  44. 0x00, /* REG_OPTION (0x2) */
  45. 0x00, /* REG_UNKNOWN (0x3) */
  46. 0x00, /* REG_MICBIAS_CTL (0x4) */
  47. 0x00, /* REG_ANAMICL (0x5) */
  48. 0x00, /* REG_ANAMICR (0x6) */
  49. 0x00, /* REG_AVADC_CTL (0x7) */
  50. 0x00, /* REG_ADCMICSEL (0x8) */
  51. 0x00, /* REG_DIGMIXING (0x9) */
  52. 0x0f, /* REG_ATXL1PGA (0xA) */
  53. 0x0f, /* REG_ATXR1PGA (0xB) */
  54. 0x0f, /* REG_AVTXL2PGA (0xC) */
  55. 0x0f, /* REG_AVTXR2PGA (0xD) */
  56. 0x00, /* REG_AUDIO_IF (0xE) */
  57. 0x00, /* REG_VOICE_IF (0xF) */
  58. 0x3f, /* REG_ARXR1PGA (0x10) */
  59. 0x3f, /* REG_ARXL1PGA (0x11) */
  60. 0x3f, /* REG_ARXR2PGA (0x12) */
  61. 0x3f, /* REG_ARXL2PGA (0x13) */
  62. 0x25, /* REG_VRXPGA (0x14) */
  63. 0x00, /* REG_VSTPGA (0x15) */
  64. 0x00, /* REG_VRX2ARXPGA (0x16) */
  65. 0x00, /* REG_AVDAC_CTL (0x17) */
  66. 0x00, /* REG_ARX2VTXPGA (0x18) */
  67. 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
  68. 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
  69. 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
  70. 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
  71. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  72. 0x00, /* REG_BT_IF (0x1E) */
  73. 0x55, /* REG_BTPGA (0x1F) */
  74. 0x00, /* REG_BTSTPGA (0x20) */
  75. 0x00, /* REG_EAR_CTL (0x21) */
  76. 0x00, /* REG_HS_SEL (0x22) */
  77. 0x00, /* REG_HS_GAIN_SET (0x23) */
  78. 0x00, /* REG_HS_POPN_SET (0x24) */
  79. 0x00, /* REG_PREDL_CTL (0x25) */
  80. 0x00, /* REG_PREDR_CTL (0x26) */
  81. 0x00, /* REG_PRECKL_CTL (0x27) */
  82. 0x00, /* REG_PRECKR_CTL (0x28) */
  83. 0x00, /* REG_HFL_CTL (0x29) */
  84. 0x00, /* REG_HFR_CTL (0x2A) */
  85. 0x05, /* REG_ALC_CTL (0x2B) */
  86. 0x00, /* REG_ALC_SET1 (0x2C) */
  87. 0x00, /* REG_ALC_SET2 (0x2D) */
  88. 0x00, /* REG_BOOST_CTL (0x2E) */
  89. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  90. 0x13, /* REG_DTMF_FREQSEL (0x30) */
  91. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  92. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  93. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  94. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  95. 0x79, /* REG_DTMF_TONOFF (0x35) */
  96. 0x11, /* REG_DTMF_WANONOFF (0x36) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  99. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  100. 0x06, /* REG_APLL_CTL (0x3A) */
  101. 0x00, /* REG_DTMF_CTL (0x3B) */
  102. 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
  103. 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
  104. 0x00, /* REG_MISC_SET_1 (0x3E) */
  105. 0x00, /* REG_PCMBTMUX (0x3F) */
  106. 0x00, /* not used (0x40) */
  107. 0x00, /* not used (0x41) */
  108. 0x00, /* not used (0x42) */
  109. 0x00, /* REG_RX_PATH_SEL (0x43) */
  110. 0x32, /* REG_VDL_APGA_CTL (0x44) */
  111. 0x00, /* REG_VIBRA_CTL (0x45) */
  112. 0x00, /* REG_VIBRA_SET (0x46) */
  113. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  114. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  115. 0x00, /* REG_MISC_SET_2 (0x49) */
  116. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  117. };
  118. /* codec private data */
  119. struct twl4030_priv {
  120. struct snd_soc_codec codec;
  121. unsigned int codec_powered;
  122. /* reference counts of AIF/APLL users */
  123. unsigned int apll_enabled;
  124. struct snd_pcm_substream *master_substream;
  125. struct snd_pcm_substream *slave_substream;
  126. unsigned int configured;
  127. unsigned int rate;
  128. unsigned int sample_bits;
  129. unsigned int channels;
  130. unsigned int sysclk;
  131. /* Output (with associated amp) states */
  132. u8 hsl_enabled, hsr_enabled;
  133. u8 earpiece_enabled;
  134. u8 predrivel_enabled, predriver_enabled;
  135. u8 carkitl_enabled, carkitr_enabled;
  136. };
  137. /*
  138. * read twl4030 register cache
  139. */
  140. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  141. unsigned int reg)
  142. {
  143. u8 *cache = codec->reg_cache;
  144. if (reg >= TWL4030_CACHEREGNUM)
  145. return -EIO;
  146. return cache[reg];
  147. }
  148. /*
  149. * write twl4030 register cache
  150. */
  151. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  152. u8 reg, u8 value)
  153. {
  154. u8 *cache = codec->reg_cache;
  155. if (reg >= TWL4030_CACHEREGNUM)
  156. return;
  157. cache[reg] = value;
  158. }
  159. /*
  160. * write to the twl4030 register space
  161. */
  162. static int twl4030_write(struct snd_soc_codec *codec,
  163. unsigned int reg, unsigned int value)
  164. {
  165. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  166. int write_to_reg = 0;
  167. twl4030_write_reg_cache(codec, reg, value);
  168. if (likely(reg < TWL4030_REG_SW_SHADOW)) {
  169. /* Decide if the given register can be written */
  170. switch (reg) {
  171. case TWL4030_REG_EAR_CTL:
  172. if (twl4030->earpiece_enabled)
  173. write_to_reg = 1;
  174. break;
  175. case TWL4030_REG_PREDL_CTL:
  176. if (twl4030->predrivel_enabled)
  177. write_to_reg = 1;
  178. break;
  179. case TWL4030_REG_PREDR_CTL:
  180. if (twl4030->predriver_enabled)
  181. write_to_reg = 1;
  182. break;
  183. case TWL4030_REG_PRECKL_CTL:
  184. if (twl4030->carkitl_enabled)
  185. write_to_reg = 1;
  186. break;
  187. case TWL4030_REG_PRECKR_CTL:
  188. if (twl4030->carkitr_enabled)
  189. write_to_reg = 1;
  190. break;
  191. case TWL4030_REG_HS_GAIN_SET:
  192. if (twl4030->hsl_enabled || twl4030->hsr_enabled)
  193. write_to_reg = 1;
  194. break;
  195. default:
  196. /* All other register can be written */
  197. write_to_reg = 1;
  198. break;
  199. }
  200. if (write_to_reg)
  201. return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  202. value, reg);
  203. }
  204. return 0;
  205. }
  206. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  207. {
  208. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  209. int mode;
  210. if (enable == twl4030->codec_powered)
  211. return;
  212. if (enable)
  213. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  214. else
  215. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  216. if (mode >= 0) {
  217. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  218. twl4030->codec_powered = enable;
  219. }
  220. /* REVISIT: this delay is present in TI sample drivers */
  221. /* but there seems to be no TRM requirement for it */
  222. udelay(10);
  223. }
  224. static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
  225. {
  226. int i, difference = 0;
  227. u8 val;
  228. dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
  229. for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
  230. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
  231. if (val != twl4030_reg[i]) {
  232. difference++;
  233. dev_dbg(codec->dev,
  234. "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
  235. i, val, twl4030_reg[i]);
  236. }
  237. }
  238. dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
  239. difference, difference ? "Not OK" : "OK");
  240. }
  241. static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
  242. {
  243. int i;
  244. /* set all audio section registers to reasonable defaults */
  245. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  246. if (i != TWL4030_REG_APLL_CTL)
  247. twl4030_write(codec, i, twl4030_reg[i]);
  248. }
  249. static void twl4030_init_chip(struct platform_device *pdev)
  250. {
  251. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  252. struct twl4030_setup_data *setup = socdev->codec_data;
  253. struct snd_soc_codec *codec = socdev->card->codec;
  254. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  255. u8 reg, byte;
  256. int i = 0;
  257. /* Check defaults, if instructed before anything else */
  258. if (setup && setup->check_defaults)
  259. twl4030_check_defaults(codec);
  260. /* Reset registers, if no setup data or if instructed to do so */
  261. if (!setup || (setup && setup->reset_registers))
  262. twl4030_reset_registers(codec);
  263. /* Refresh APLL_CTL register from HW */
  264. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  265. TWL4030_REG_APLL_CTL);
  266. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
  267. /* anti-pop when changing analog gain */
  268. reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  269. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  270. reg | TWL4030_SMOOTH_ANAVOL_EN);
  271. twl4030_write(codec, TWL4030_REG_OPTION,
  272. TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
  273. TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
  274. /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
  275. twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
  276. /* Machine dependent setup */
  277. if (!setup)
  278. return;
  279. /* Configuration for headset ramp delay from setup data */
  280. if (setup->sysclk != twl4030->sysclk)
  281. dev_warn(codec->dev,
  282. "Mismatch in APLL mclk: %u (configured: %u)\n",
  283. setup->sysclk, twl4030->sysclk);
  284. reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  285. reg &= ~TWL4030_RAMP_DELAY;
  286. reg |= (setup->ramp_delay_value << 2);
  287. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
  288. /* initiate offset cancellation */
  289. twl4030_codec_enable(codec, 1);
  290. reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  291. reg &= ~TWL4030_OFFSET_CNCL_SEL;
  292. reg |= setup->offset_cncl_path;
  293. twl4030_write(codec, TWL4030_REG_ANAMICL,
  294. reg | TWL4030_CNCL_OFFSET_START);
  295. /* wait for offset cancellation to complete */
  296. do {
  297. /* this takes a little while, so don't slam i2c */
  298. udelay(2000);
  299. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  300. TWL4030_REG_ANAMICL);
  301. } while ((i++ < 100) &&
  302. ((byte & TWL4030_CNCL_OFFSET_START) ==
  303. TWL4030_CNCL_OFFSET_START));
  304. /* Make sure that the reg_cache has the same value as the HW */
  305. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  306. twl4030_codec_enable(codec, 0);
  307. }
  308. static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
  309. {
  310. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  311. int status = -1;
  312. if (enable) {
  313. twl4030->apll_enabled++;
  314. if (twl4030->apll_enabled == 1)
  315. status = twl4030_codec_enable_resource(
  316. TWL4030_CODEC_RES_APLL);
  317. } else {
  318. twl4030->apll_enabled--;
  319. if (!twl4030->apll_enabled)
  320. status = twl4030_codec_disable_resource(
  321. TWL4030_CODEC_RES_APLL);
  322. }
  323. if (status >= 0)
  324. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  325. }
  326. /* Earpiece */
  327. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  328. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  329. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  330. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  331. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  332. };
  333. /* PreDrive Left */
  334. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  335. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  336. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  337. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  338. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  339. };
  340. /* PreDrive Right */
  341. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  342. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  343. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  344. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  345. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  346. };
  347. /* Headset Left */
  348. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  349. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  350. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  351. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  352. };
  353. /* Headset Right */
  354. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  355. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  356. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  357. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  358. };
  359. /* Carkit Left */
  360. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  361. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  362. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  363. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  364. };
  365. /* Carkit Right */
  366. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  367. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  368. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  369. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  370. };
  371. /* Handsfree Left */
  372. static const char *twl4030_handsfreel_texts[] =
  373. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  374. static const struct soc_enum twl4030_handsfreel_enum =
  375. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  376. ARRAY_SIZE(twl4030_handsfreel_texts),
  377. twl4030_handsfreel_texts);
  378. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  379. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  380. /* Handsfree Left virtual mute */
  381. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  382. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  383. /* Handsfree Right */
  384. static const char *twl4030_handsfreer_texts[] =
  385. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  386. static const struct soc_enum twl4030_handsfreer_enum =
  387. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  388. ARRAY_SIZE(twl4030_handsfreer_texts),
  389. twl4030_handsfreer_texts);
  390. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  391. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  392. /* Handsfree Right virtual mute */
  393. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  394. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  395. /* Vibra */
  396. /* Vibra audio path selection */
  397. static const char *twl4030_vibra_texts[] =
  398. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  399. static const struct soc_enum twl4030_vibra_enum =
  400. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  401. ARRAY_SIZE(twl4030_vibra_texts),
  402. twl4030_vibra_texts);
  403. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  404. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  405. /* Vibra path selection: local vibrator (PWM) or audio driven */
  406. static const char *twl4030_vibrapath_texts[] =
  407. {"Local vibrator", "Audio"};
  408. static const struct soc_enum twl4030_vibrapath_enum =
  409. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  410. ARRAY_SIZE(twl4030_vibrapath_texts),
  411. twl4030_vibrapath_texts);
  412. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  413. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  414. /* Left analog microphone selection */
  415. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  416. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  417. TWL4030_REG_ANAMICL, 0, 1, 0),
  418. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  419. TWL4030_REG_ANAMICL, 1, 1, 0),
  420. SOC_DAPM_SINGLE("AUXL Capture Switch",
  421. TWL4030_REG_ANAMICL, 2, 1, 0),
  422. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  423. TWL4030_REG_ANAMICL, 3, 1, 0),
  424. };
  425. /* Right analog microphone selection */
  426. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  427. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  428. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  429. };
  430. /* TX1 L/R Analog/Digital microphone selection */
  431. static const char *twl4030_micpathtx1_texts[] =
  432. {"Analog", "Digimic0"};
  433. static const struct soc_enum twl4030_micpathtx1_enum =
  434. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  435. ARRAY_SIZE(twl4030_micpathtx1_texts),
  436. twl4030_micpathtx1_texts);
  437. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  438. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  439. /* TX2 L/R Analog/Digital microphone selection */
  440. static const char *twl4030_micpathtx2_texts[] =
  441. {"Analog", "Digimic1"};
  442. static const struct soc_enum twl4030_micpathtx2_enum =
  443. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  444. ARRAY_SIZE(twl4030_micpathtx2_texts),
  445. twl4030_micpathtx2_texts);
  446. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  447. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  448. /* Analog bypass for AudioR1 */
  449. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  450. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  451. /* Analog bypass for AudioL1 */
  452. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  453. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  454. /* Analog bypass for AudioR2 */
  455. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  456. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  457. /* Analog bypass for AudioL2 */
  458. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  459. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  460. /* Analog bypass for Voice */
  461. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  462. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  463. /* Digital bypass gain, 0 mutes the bypass */
  464. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  465. TLV_DB_RANGE_HEAD(2),
  466. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  467. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  468. };
  469. /* Digital bypass left (TX1L -> RX2L) */
  470. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  471. SOC_DAPM_SINGLE_TLV("Volume",
  472. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  473. twl4030_dapm_dbypass_tlv);
  474. /* Digital bypass right (TX1R -> RX2R) */
  475. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  476. SOC_DAPM_SINGLE_TLV("Volume",
  477. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  478. twl4030_dapm_dbypass_tlv);
  479. /*
  480. * Voice Sidetone GAIN volume control:
  481. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  482. */
  483. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  484. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  485. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  486. SOC_DAPM_SINGLE_TLV("Volume",
  487. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  488. twl4030_dapm_dbypassv_tlv);
  489. static int micpath_event(struct snd_soc_dapm_widget *w,
  490. struct snd_kcontrol *kcontrol, int event)
  491. {
  492. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  493. unsigned char adcmicsel, micbias_ctl;
  494. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  495. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  496. /* Prepare the bits for the given TX path:
  497. * shift_l == 0: TX1 microphone path
  498. * shift_l == 2: TX2 microphone path */
  499. if (e->shift_l) {
  500. /* TX2 microphone path */
  501. if (adcmicsel & TWL4030_TX2IN_SEL)
  502. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  503. else
  504. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  505. } else {
  506. /* TX1 microphone path */
  507. if (adcmicsel & TWL4030_TX1IN_SEL)
  508. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  509. else
  510. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  511. }
  512. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  513. return 0;
  514. }
  515. /*
  516. * Output PGA builder:
  517. * Handle the muting and unmuting of the given output (turning off the
  518. * amplifier associated with the output pin)
  519. * On mute bypass the reg_cache and write 0 to the register
  520. * On unmute: restore the register content from the reg_cache
  521. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  522. */
  523. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  524. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  525. struct snd_kcontrol *kcontrol, int event) \
  526. { \
  527. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
  528. \
  529. switch (event) { \
  530. case SND_SOC_DAPM_POST_PMU: \
  531. twl4030->pin_name##_enabled = 1; \
  532. twl4030_write(w->codec, reg, \
  533. twl4030_read_reg_cache(w->codec, reg)); \
  534. break; \
  535. case SND_SOC_DAPM_POST_PMD: \
  536. twl4030->pin_name##_enabled = 0; \
  537. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  538. 0, reg); \
  539. break; \
  540. } \
  541. return 0; \
  542. }
  543. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  544. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  545. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  546. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  547. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  548. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  549. {
  550. unsigned char hs_ctl;
  551. hs_ctl = twl4030_read_reg_cache(codec, reg);
  552. if (ramp) {
  553. /* HF ramp-up */
  554. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  555. twl4030_write(codec, reg, hs_ctl);
  556. udelay(10);
  557. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  558. twl4030_write(codec, reg, hs_ctl);
  559. udelay(40);
  560. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  561. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  562. twl4030_write(codec, reg, hs_ctl);
  563. } else {
  564. /* HF ramp-down */
  565. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  566. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  567. twl4030_write(codec, reg, hs_ctl);
  568. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  569. twl4030_write(codec, reg, hs_ctl);
  570. udelay(40);
  571. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  572. twl4030_write(codec, reg, hs_ctl);
  573. }
  574. }
  575. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  576. struct snd_kcontrol *kcontrol, int event)
  577. {
  578. switch (event) {
  579. case SND_SOC_DAPM_POST_PMU:
  580. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  581. break;
  582. case SND_SOC_DAPM_POST_PMD:
  583. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  584. break;
  585. }
  586. return 0;
  587. }
  588. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  589. struct snd_kcontrol *kcontrol, int event)
  590. {
  591. switch (event) {
  592. case SND_SOC_DAPM_POST_PMU:
  593. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  594. break;
  595. case SND_SOC_DAPM_POST_PMD:
  596. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  597. break;
  598. }
  599. return 0;
  600. }
  601. static int vibramux_event(struct snd_soc_dapm_widget *w,
  602. struct snd_kcontrol *kcontrol, int event)
  603. {
  604. twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
  605. return 0;
  606. }
  607. static int apll_event(struct snd_soc_dapm_widget *w,
  608. struct snd_kcontrol *kcontrol, int event)
  609. {
  610. switch (event) {
  611. case SND_SOC_DAPM_PRE_PMU:
  612. twl4030_apll_enable(w->codec, 1);
  613. break;
  614. case SND_SOC_DAPM_POST_PMD:
  615. twl4030_apll_enable(w->codec, 0);
  616. break;
  617. }
  618. return 0;
  619. }
  620. static int aif_event(struct snd_soc_dapm_widget *w,
  621. struct snd_kcontrol *kcontrol, int event)
  622. {
  623. u8 audio_if;
  624. audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
  625. switch (event) {
  626. case SND_SOC_DAPM_PRE_PMU:
  627. /* Enable AIF */
  628. /* enable the PLL before we use it to clock the DAI */
  629. twl4030_apll_enable(w->codec, 1);
  630. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  631. audio_if | TWL4030_AIF_EN);
  632. break;
  633. case SND_SOC_DAPM_POST_PMD:
  634. /* disable the DAI before we stop it's source PLL */
  635. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  636. audio_if & ~TWL4030_AIF_EN);
  637. twl4030_apll_enable(w->codec, 0);
  638. break;
  639. }
  640. return 0;
  641. }
  642. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  643. {
  644. struct snd_soc_device *socdev = codec->socdev;
  645. struct twl4030_setup_data *setup = socdev->codec_data;
  646. unsigned char hs_gain, hs_pop;
  647. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  648. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  649. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  650. 8388608, 16777216, 33554432, 67108864};
  651. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  652. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  653. /* Enable external mute control, this dramatically reduces
  654. * the pop-noise */
  655. if (setup && setup->hs_extmute) {
  656. if (setup->set_hs_extmute) {
  657. setup->set_hs_extmute(1);
  658. } else {
  659. hs_pop |= TWL4030_EXTMUTE;
  660. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  661. }
  662. }
  663. if (ramp) {
  664. /* Headset ramp-up according to the TRM */
  665. hs_pop |= TWL4030_VMID_EN;
  666. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  667. /* Actually write to the register */
  668. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  669. hs_gain,
  670. TWL4030_REG_HS_GAIN_SET);
  671. hs_pop |= TWL4030_RAMP_EN;
  672. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  673. /* Wait ramp delay time + 1, so the VMID can settle */
  674. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  675. twl4030->sysclk) + 1);
  676. } else {
  677. /* Headset ramp-down _not_ according to
  678. * the TRM, but in a way that it is working */
  679. hs_pop &= ~TWL4030_RAMP_EN;
  680. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  681. /* Wait ramp delay time + 1, so the VMID can settle */
  682. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  683. twl4030->sysclk) + 1);
  684. /* Bypass the reg_cache to mute the headset */
  685. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  686. hs_gain & (~0x0f),
  687. TWL4030_REG_HS_GAIN_SET);
  688. hs_pop &= ~TWL4030_VMID_EN;
  689. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  690. }
  691. /* Disable external mute */
  692. if (setup && setup->hs_extmute) {
  693. if (setup->set_hs_extmute) {
  694. setup->set_hs_extmute(0);
  695. } else {
  696. hs_pop &= ~TWL4030_EXTMUTE;
  697. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  698. }
  699. }
  700. }
  701. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  702. struct snd_kcontrol *kcontrol, int event)
  703. {
  704. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  705. switch (event) {
  706. case SND_SOC_DAPM_POST_PMU:
  707. /* Do the ramp-up only once */
  708. if (!twl4030->hsr_enabled)
  709. headset_ramp(w->codec, 1);
  710. twl4030->hsl_enabled = 1;
  711. break;
  712. case SND_SOC_DAPM_POST_PMD:
  713. /* Do the ramp-down only if both headsetL/R is disabled */
  714. if (!twl4030->hsr_enabled)
  715. headset_ramp(w->codec, 0);
  716. twl4030->hsl_enabled = 0;
  717. break;
  718. }
  719. return 0;
  720. }
  721. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  722. struct snd_kcontrol *kcontrol, int event)
  723. {
  724. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  725. switch (event) {
  726. case SND_SOC_DAPM_POST_PMU:
  727. /* Do the ramp-up only once */
  728. if (!twl4030->hsl_enabled)
  729. headset_ramp(w->codec, 1);
  730. twl4030->hsr_enabled = 1;
  731. break;
  732. case SND_SOC_DAPM_POST_PMD:
  733. /* Do the ramp-down only if both headsetL/R is disabled */
  734. if (!twl4030->hsl_enabled)
  735. headset_ramp(w->codec, 0);
  736. twl4030->hsr_enabled = 0;
  737. break;
  738. }
  739. return 0;
  740. }
  741. /*
  742. * Some of the gain controls in TWL (mostly those which are associated with
  743. * the outputs) are implemented in an interesting way:
  744. * 0x0 : Power down (mute)
  745. * 0x1 : 6dB
  746. * 0x2 : 0 dB
  747. * 0x3 : -6 dB
  748. * Inverting not going to help with these.
  749. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  750. */
  751. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  752. xinvert, tlv_array) \
  753. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  754. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  755. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  756. .tlv.p = (tlv_array), \
  757. .info = snd_soc_info_volsw, \
  758. .get = snd_soc_get_volsw_twl4030, \
  759. .put = snd_soc_put_volsw_twl4030, \
  760. .private_value = (unsigned long)&(struct soc_mixer_control) \
  761. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  762. .max = xmax, .invert = xinvert} }
  763. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  764. xinvert, tlv_array) \
  765. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  766. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  767. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  768. .tlv.p = (tlv_array), \
  769. .info = snd_soc_info_volsw_2r, \
  770. .get = snd_soc_get_volsw_r2_twl4030,\
  771. .put = snd_soc_put_volsw_r2_twl4030, \
  772. .private_value = (unsigned long)&(struct soc_mixer_control) \
  773. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  774. .rshift = xshift, .max = xmax, .invert = xinvert} }
  775. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  776. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  777. xinvert, tlv_array)
  778. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  779. struct snd_ctl_elem_value *ucontrol)
  780. {
  781. struct soc_mixer_control *mc =
  782. (struct soc_mixer_control *)kcontrol->private_value;
  783. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  784. unsigned int reg = mc->reg;
  785. unsigned int shift = mc->shift;
  786. unsigned int rshift = mc->rshift;
  787. int max = mc->max;
  788. int mask = (1 << fls(max)) - 1;
  789. ucontrol->value.integer.value[0] =
  790. (snd_soc_read(codec, reg) >> shift) & mask;
  791. if (ucontrol->value.integer.value[0])
  792. ucontrol->value.integer.value[0] =
  793. max + 1 - ucontrol->value.integer.value[0];
  794. if (shift != rshift) {
  795. ucontrol->value.integer.value[1] =
  796. (snd_soc_read(codec, reg) >> rshift) & mask;
  797. if (ucontrol->value.integer.value[1])
  798. ucontrol->value.integer.value[1] =
  799. max + 1 - ucontrol->value.integer.value[1];
  800. }
  801. return 0;
  802. }
  803. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  804. struct snd_ctl_elem_value *ucontrol)
  805. {
  806. struct soc_mixer_control *mc =
  807. (struct soc_mixer_control *)kcontrol->private_value;
  808. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  809. unsigned int reg = mc->reg;
  810. unsigned int shift = mc->shift;
  811. unsigned int rshift = mc->rshift;
  812. int max = mc->max;
  813. int mask = (1 << fls(max)) - 1;
  814. unsigned short val, val2, val_mask;
  815. val = (ucontrol->value.integer.value[0] & mask);
  816. val_mask = mask << shift;
  817. if (val)
  818. val = max + 1 - val;
  819. val = val << shift;
  820. if (shift != rshift) {
  821. val2 = (ucontrol->value.integer.value[1] & mask);
  822. val_mask |= mask << rshift;
  823. if (val2)
  824. val2 = max + 1 - val2;
  825. val |= val2 << rshift;
  826. }
  827. return snd_soc_update_bits(codec, reg, val_mask, val);
  828. }
  829. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  830. struct snd_ctl_elem_value *ucontrol)
  831. {
  832. struct soc_mixer_control *mc =
  833. (struct soc_mixer_control *)kcontrol->private_value;
  834. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  835. unsigned int reg = mc->reg;
  836. unsigned int reg2 = mc->rreg;
  837. unsigned int shift = mc->shift;
  838. int max = mc->max;
  839. int mask = (1<<fls(max))-1;
  840. ucontrol->value.integer.value[0] =
  841. (snd_soc_read(codec, reg) >> shift) & mask;
  842. ucontrol->value.integer.value[1] =
  843. (snd_soc_read(codec, reg2) >> shift) & mask;
  844. if (ucontrol->value.integer.value[0])
  845. ucontrol->value.integer.value[0] =
  846. max + 1 - ucontrol->value.integer.value[0];
  847. if (ucontrol->value.integer.value[1])
  848. ucontrol->value.integer.value[1] =
  849. max + 1 - ucontrol->value.integer.value[1];
  850. return 0;
  851. }
  852. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  853. struct snd_ctl_elem_value *ucontrol)
  854. {
  855. struct soc_mixer_control *mc =
  856. (struct soc_mixer_control *)kcontrol->private_value;
  857. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  858. unsigned int reg = mc->reg;
  859. unsigned int reg2 = mc->rreg;
  860. unsigned int shift = mc->shift;
  861. int max = mc->max;
  862. int mask = (1 << fls(max)) - 1;
  863. int err;
  864. unsigned short val, val2, val_mask;
  865. val_mask = mask << shift;
  866. val = (ucontrol->value.integer.value[0] & mask);
  867. val2 = (ucontrol->value.integer.value[1] & mask);
  868. if (val)
  869. val = max + 1 - val;
  870. if (val2)
  871. val2 = max + 1 - val2;
  872. val = val << shift;
  873. val2 = val2 << shift;
  874. err = snd_soc_update_bits(codec, reg, val_mask, val);
  875. if (err < 0)
  876. return err;
  877. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  878. return err;
  879. }
  880. /* Codec operation modes */
  881. static const char *twl4030_op_modes_texts[] = {
  882. "Option 2 (voice/audio)", "Option 1 (audio)"
  883. };
  884. static const struct soc_enum twl4030_op_modes_enum =
  885. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  886. ARRAY_SIZE(twl4030_op_modes_texts),
  887. twl4030_op_modes_texts);
  888. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  889. struct snd_ctl_elem_value *ucontrol)
  890. {
  891. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  892. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  893. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  894. unsigned short val;
  895. unsigned short mask, bitmask;
  896. if (twl4030->configured) {
  897. printk(KERN_ERR "twl4030 operation mode cannot be "
  898. "changed on-the-fly\n");
  899. return -EBUSY;
  900. }
  901. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  902. ;
  903. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  904. return -EINVAL;
  905. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  906. mask = (bitmask - 1) << e->shift_l;
  907. if (e->shift_l != e->shift_r) {
  908. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  909. return -EINVAL;
  910. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  911. mask |= (bitmask - 1) << e->shift_r;
  912. }
  913. return snd_soc_update_bits(codec, e->reg, mask, val);
  914. }
  915. /*
  916. * FGAIN volume control:
  917. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  918. */
  919. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  920. /*
  921. * CGAIN volume control:
  922. * 0 dB to 12 dB in 6 dB steps
  923. * value 2 and 3 means 12 dB
  924. */
  925. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  926. /*
  927. * Voice Downlink GAIN volume control:
  928. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  929. */
  930. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  931. /*
  932. * Analog playback gain
  933. * -24 dB to 12 dB in 2 dB steps
  934. */
  935. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  936. /*
  937. * Gain controls tied to outputs
  938. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  939. */
  940. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  941. /*
  942. * Gain control for earpiece amplifier
  943. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  944. */
  945. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  946. /*
  947. * Capture gain after the ADCs
  948. * from 0 dB to 31 dB in 1 dB steps
  949. */
  950. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  951. /*
  952. * Gain control for input amplifiers
  953. * 0 dB to 30 dB in 6 dB steps
  954. */
  955. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  956. /* AVADC clock priority */
  957. static const char *twl4030_avadc_clk_priority_texts[] = {
  958. "Voice high priority", "HiFi high priority"
  959. };
  960. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  961. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  962. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  963. twl4030_avadc_clk_priority_texts);
  964. static const char *twl4030_rampdelay_texts[] = {
  965. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  966. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  967. "3495/2581/1748 ms"
  968. };
  969. static const struct soc_enum twl4030_rampdelay_enum =
  970. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  971. ARRAY_SIZE(twl4030_rampdelay_texts),
  972. twl4030_rampdelay_texts);
  973. /* Vibra H-bridge direction mode */
  974. static const char *twl4030_vibradirmode_texts[] = {
  975. "Vibra H-bridge direction", "Audio data MSB",
  976. };
  977. static const struct soc_enum twl4030_vibradirmode_enum =
  978. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  979. ARRAY_SIZE(twl4030_vibradirmode_texts),
  980. twl4030_vibradirmode_texts);
  981. /* Vibra H-bridge direction */
  982. static const char *twl4030_vibradir_texts[] = {
  983. "Positive polarity", "Negative polarity",
  984. };
  985. static const struct soc_enum twl4030_vibradir_enum =
  986. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  987. ARRAY_SIZE(twl4030_vibradir_texts),
  988. twl4030_vibradir_texts);
  989. /* Digimic Left and right swapping */
  990. static const char *twl4030_digimicswap_texts[] = {
  991. "Not swapped", "Swapped",
  992. };
  993. static const struct soc_enum twl4030_digimicswap_enum =
  994. SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
  995. ARRAY_SIZE(twl4030_digimicswap_texts),
  996. twl4030_digimicswap_texts);
  997. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  998. /* Codec operation mode control */
  999. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  1000. snd_soc_get_enum_double,
  1001. snd_soc_put_twl4030_opmode_enum_double),
  1002. /* Common playback gain controls */
  1003. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  1004. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  1005. 0, 0x3f, 0, digital_fine_tlv),
  1006. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  1007. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  1008. 0, 0x3f, 0, digital_fine_tlv),
  1009. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  1010. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  1011. 6, 0x2, 0, digital_coarse_tlv),
  1012. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  1013. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  1014. 6, 0x2, 0, digital_coarse_tlv),
  1015. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  1016. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1017. 3, 0x12, 1, analog_tlv),
  1018. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  1019. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1020. 3, 0x12, 1, analog_tlv),
  1021. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  1022. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1023. 1, 1, 0),
  1024. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  1025. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1026. 1, 1, 0),
  1027. /* Common voice downlink gain controls */
  1028. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  1029. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  1030. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  1031. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  1032. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  1033. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  1034. /* Separate output gain controls */
  1035. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  1036. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  1037. 4, 3, 0, output_tvl),
  1038. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  1039. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  1040. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  1041. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  1042. 4, 3, 0, output_tvl),
  1043. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  1044. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  1045. /* Common capture gain controls */
  1046. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  1047. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  1048. 0, 0x1f, 0, digital_capture_tlv),
  1049. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  1050. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  1051. 0, 0x1f, 0, digital_capture_tlv),
  1052. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  1053. 0, 3, 5, 0, input_gain_tlv),
  1054. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  1055. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  1056. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  1057. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  1058. SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
  1059. };
  1060. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  1061. /* Left channel inputs */
  1062. SND_SOC_DAPM_INPUT("MAINMIC"),
  1063. SND_SOC_DAPM_INPUT("HSMIC"),
  1064. SND_SOC_DAPM_INPUT("AUXL"),
  1065. SND_SOC_DAPM_INPUT("CARKITMIC"),
  1066. /* Right channel inputs */
  1067. SND_SOC_DAPM_INPUT("SUBMIC"),
  1068. SND_SOC_DAPM_INPUT("AUXR"),
  1069. /* Digital microphones (Stereo) */
  1070. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  1071. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  1072. /* Outputs */
  1073. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1074. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1075. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1076. SND_SOC_DAPM_OUTPUT("HSOL"),
  1077. SND_SOC_DAPM_OUTPUT("HSOR"),
  1078. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1079. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1080. SND_SOC_DAPM_OUTPUT("HFL"),
  1081. SND_SOC_DAPM_OUTPUT("HFR"),
  1082. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1083. /* AIF and APLL clocks for running DAIs (including loopback) */
  1084. SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
  1085. SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
  1086. SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
  1087. /* DACs */
  1088. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1089. SND_SOC_NOPM, 0, 0),
  1090. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1091. SND_SOC_NOPM, 0, 0),
  1092. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1093. SND_SOC_NOPM, 0, 0),
  1094. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1095. SND_SOC_NOPM, 0, 0),
  1096. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1097. SND_SOC_NOPM, 0, 0),
  1098. /* Analog bypasses */
  1099. SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1100. &twl4030_dapm_abypassr1_control),
  1101. SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1102. &twl4030_dapm_abypassl1_control),
  1103. SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1104. &twl4030_dapm_abypassr2_control),
  1105. SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1106. &twl4030_dapm_abypassl2_control),
  1107. SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1108. &twl4030_dapm_abypassv_control),
  1109. /* Master analog loopback switch */
  1110. SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
  1111. NULL, 0),
  1112. /* Digital bypasses */
  1113. SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1114. &twl4030_dapm_dbypassl_control),
  1115. SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1116. &twl4030_dapm_dbypassr_control),
  1117. SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1118. &twl4030_dapm_dbypassv_control),
  1119. /* Digital mixers, power control for the physical DACs */
  1120. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1121. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1122. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1123. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1124. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1125. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1126. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1127. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1128. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1129. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1130. /* Analog mixers, power control for the physical PGAs */
  1131. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1132. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1133. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1134. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1135. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1136. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1137. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1138. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1139. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1140. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1141. SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
  1142. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1143. SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
  1144. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1145. /* Output MIXER controls */
  1146. /* Earpiece */
  1147. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1148. &twl4030_dapm_earpiece_controls[0],
  1149. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1150. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1151. 0, 0, NULL, 0, earpiecepga_event,
  1152. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1153. /* PreDrivL/R */
  1154. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1155. &twl4030_dapm_predrivel_controls[0],
  1156. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1157. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1158. 0, 0, NULL, 0, predrivelpga_event,
  1159. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1160. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1161. &twl4030_dapm_predriver_controls[0],
  1162. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1163. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1164. 0, 0, NULL, 0, predriverpga_event,
  1165. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1166. /* HeadsetL/R */
  1167. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1168. &twl4030_dapm_hsol_controls[0],
  1169. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1170. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1171. 0, 0, NULL, 0, headsetlpga_event,
  1172. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1173. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1174. &twl4030_dapm_hsor_controls[0],
  1175. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1176. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1177. 0, 0, NULL, 0, headsetrpga_event,
  1178. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1179. /* CarkitL/R */
  1180. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1181. &twl4030_dapm_carkitl_controls[0],
  1182. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1183. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1184. 0, 0, NULL, 0, carkitlpga_event,
  1185. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1186. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1187. &twl4030_dapm_carkitr_controls[0],
  1188. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1189. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1190. 0, 0, NULL, 0, carkitrpga_event,
  1191. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1192. /* Output MUX controls */
  1193. /* HandsfreeL/R */
  1194. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1195. &twl4030_dapm_handsfreel_control),
  1196. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1197. &twl4030_dapm_handsfreelmute_control),
  1198. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1199. 0, 0, NULL, 0, handsfreelpga_event,
  1200. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1201. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1202. &twl4030_dapm_handsfreer_control),
  1203. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1204. &twl4030_dapm_handsfreermute_control),
  1205. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1206. 0, 0, NULL, 0, handsfreerpga_event,
  1207. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1208. /* Vibra */
  1209. SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1210. &twl4030_dapm_vibra_control, vibramux_event,
  1211. SND_SOC_DAPM_PRE_PMU),
  1212. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1213. &twl4030_dapm_vibrapath_control),
  1214. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1215. capture */
  1216. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1217. SND_SOC_NOPM, 0, 0),
  1218. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1219. SND_SOC_NOPM, 0, 0),
  1220. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1221. SND_SOC_NOPM, 0, 0),
  1222. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1223. SND_SOC_NOPM, 0, 0),
  1224. /* Analog/Digital mic path selection.
  1225. TX1 Left/Right: either analog Left/Right or Digimic0
  1226. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1227. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1228. &twl4030_dapm_micpathtx1_control, micpath_event,
  1229. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1230. SND_SOC_DAPM_POST_REG),
  1231. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1232. &twl4030_dapm_micpathtx2_control, micpath_event,
  1233. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1234. SND_SOC_DAPM_POST_REG),
  1235. /* Analog input mixers for the capture amplifiers */
  1236. SND_SOC_DAPM_MIXER("Analog Left",
  1237. TWL4030_REG_ANAMICL, 4, 0,
  1238. &twl4030_dapm_analoglmic_controls[0],
  1239. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1240. SND_SOC_DAPM_MIXER("Analog Right",
  1241. TWL4030_REG_ANAMICR, 4, 0,
  1242. &twl4030_dapm_analogrmic_controls[0],
  1243. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1244. SND_SOC_DAPM_PGA("ADC Physical Left",
  1245. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1246. SND_SOC_DAPM_PGA("ADC Physical Right",
  1247. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1248. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1249. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1250. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1251. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1252. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1253. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1254. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1255. };
  1256. static const struct snd_soc_dapm_route intercon[] = {
  1257. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1258. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1259. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1260. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1261. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1262. /* Supply for the digital part (APLL) */
  1263. {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
  1264. {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
  1265. {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
  1266. {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
  1267. {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
  1268. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1269. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1270. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1271. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1272. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1273. /* Internal playback routings */
  1274. /* Earpiece */
  1275. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1276. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1277. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1278. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1279. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1280. /* PreDrivL */
  1281. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1282. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1283. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1284. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1285. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1286. /* PreDrivR */
  1287. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1288. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1289. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1290. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1291. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1292. /* HeadsetL */
  1293. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1294. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1295. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1296. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1297. /* HeadsetR */
  1298. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1299. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1300. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1301. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1302. /* CarkitL */
  1303. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1304. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1305. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1306. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1307. /* CarkitR */
  1308. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1309. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1310. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1311. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1312. /* HandsfreeL */
  1313. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1314. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1315. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1316. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1317. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1318. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1319. /* HandsfreeR */
  1320. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1321. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1322. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1323. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1324. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1325. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1326. /* Vibra */
  1327. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1328. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1329. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1330. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1331. /* outputs */
  1332. /* Must be always connected (for AIF and APLL) */
  1333. {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"},
  1334. {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"},
  1335. {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"},
  1336. {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"},
  1337. /* Must be always connected (for APLL) */
  1338. {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
  1339. /* Physical outputs */
  1340. {"EARPIECE", NULL, "Earpiece PGA"},
  1341. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1342. {"PREDRIVER", NULL, "PredriveR PGA"},
  1343. {"HSOL", NULL, "HeadsetL PGA"},
  1344. {"HSOR", NULL, "HeadsetR PGA"},
  1345. {"CARKITL", NULL, "CarkitL PGA"},
  1346. {"CARKITR", NULL, "CarkitR PGA"},
  1347. {"HFL", NULL, "HandsfreeL PGA"},
  1348. {"HFR", NULL, "HandsfreeR PGA"},
  1349. {"Vibra Route", "Audio", "Vibra Mux"},
  1350. {"VIBRA", NULL, "Vibra Route"},
  1351. /* Capture path */
  1352. /* Must be always connected (for AIF and APLL) */
  1353. {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
  1354. {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
  1355. {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
  1356. {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
  1357. /* Physical inputs */
  1358. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1359. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1360. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1361. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1362. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1363. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1364. {"ADC Physical Left", NULL, "Analog Left"},
  1365. {"ADC Physical Right", NULL, "Analog Right"},
  1366. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1367. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1368. /* TX1 Left capture path */
  1369. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1370. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1371. /* TX1 Right capture path */
  1372. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1373. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1374. /* TX2 Left capture path */
  1375. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1376. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1377. /* TX2 Right capture path */
  1378. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1379. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1380. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1381. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1382. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1383. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1384. {"ADC Virtual Left1", NULL, "AIF Enable"},
  1385. {"ADC Virtual Right1", NULL, "AIF Enable"},
  1386. {"ADC Virtual Left2", NULL, "AIF Enable"},
  1387. {"ADC Virtual Right2", NULL, "AIF Enable"},
  1388. /* Analog bypass routes */
  1389. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1390. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1391. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1392. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1393. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1394. /* Supply for the Analog loopbacks */
  1395. {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
  1396. {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
  1397. {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
  1398. {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
  1399. {"Voice Analog Loopback", NULL, "FM Loop Enable"},
  1400. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1401. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1402. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1403. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1404. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1405. /* Digital bypass routes */
  1406. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1407. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1408. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1409. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1410. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1411. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1412. };
  1413. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1414. {
  1415. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1416. ARRAY_SIZE(twl4030_dapm_widgets));
  1417. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1418. return 0;
  1419. }
  1420. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1421. enum snd_soc_bias_level level)
  1422. {
  1423. switch (level) {
  1424. case SND_SOC_BIAS_ON:
  1425. break;
  1426. case SND_SOC_BIAS_PREPARE:
  1427. break;
  1428. case SND_SOC_BIAS_STANDBY:
  1429. if (codec->bias_level == SND_SOC_BIAS_OFF)
  1430. twl4030_codec_enable(codec, 1);
  1431. break;
  1432. case SND_SOC_BIAS_OFF:
  1433. twl4030_codec_enable(codec, 0);
  1434. break;
  1435. }
  1436. codec->bias_level = level;
  1437. return 0;
  1438. }
  1439. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1440. struct snd_pcm_substream *mst_substream)
  1441. {
  1442. struct snd_pcm_substream *slv_substream;
  1443. /* Pick the stream, which need to be constrained */
  1444. if (mst_substream == twl4030->master_substream)
  1445. slv_substream = twl4030->slave_substream;
  1446. else if (mst_substream == twl4030->slave_substream)
  1447. slv_substream = twl4030->master_substream;
  1448. else /* This should not happen.. */
  1449. return;
  1450. /* Set the constraints according to the already configured stream */
  1451. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1452. SNDRV_PCM_HW_PARAM_RATE,
  1453. twl4030->rate,
  1454. twl4030->rate);
  1455. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1456. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1457. twl4030->sample_bits,
  1458. twl4030->sample_bits);
  1459. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1460. SNDRV_PCM_HW_PARAM_CHANNELS,
  1461. twl4030->channels,
  1462. twl4030->channels);
  1463. }
  1464. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1465. * capture has to be enabled/disabled. */
  1466. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1467. int enable)
  1468. {
  1469. u8 reg, mask;
  1470. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1471. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1472. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1473. else
  1474. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1475. if (enable)
  1476. reg |= mask;
  1477. else
  1478. reg &= ~mask;
  1479. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1480. }
  1481. static int twl4030_startup(struct snd_pcm_substream *substream,
  1482. struct snd_soc_dai *dai)
  1483. {
  1484. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1485. struct snd_soc_device *socdev = rtd->socdev;
  1486. struct snd_soc_codec *codec = socdev->card->codec;
  1487. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1488. if (twl4030->master_substream) {
  1489. twl4030->slave_substream = substream;
  1490. /* The DAI has one configuration for playback and capture, so
  1491. * if the DAI has been already configured then constrain this
  1492. * substream to match it. */
  1493. if (twl4030->configured)
  1494. twl4030_constraints(twl4030, twl4030->master_substream);
  1495. } else {
  1496. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1497. TWL4030_OPTION_1)) {
  1498. /* In option2 4 channel is not supported, set the
  1499. * constraint for the first stream for channels, the
  1500. * second stream will 'inherit' this cosntraint */
  1501. snd_pcm_hw_constraint_minmax(substream->runtime,
  1502. SNDRV_PCM_HW_PARAM_CHANNELS,
  1503. 2, 2);
  1504. }
  1505. twl4030->master_substream = substream;
  1506. }
  1507. return 0;
  1508. }
  1509. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1510. struct snd_soc_dai *dai)
  1511. {
  1512. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1513. struct snd_soc_device *socdev = rtd->socdev;
  1514. struct snd_soc_codec *codec = socdev->card->codec;
  1515. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1516. if (twl4030->master_substream == substream)
  1517. twl4030->master_substream = twl4030->slave_substream;
  1518. twl4030->slave_substream = NULL;
  1519. /* If all streams are closed, or the remaining stream has not yet
  1520. * been configured than set the DAI as not configured. */
  1521. if (!twl4030->master_substream)
  1522. twl4030->configured = 0;
  1523. else if (!twl4030->master_substream->runtime->channels)
  1524. twl4030->configured = 0;
  1525. /* If the closing substream had 4 channel, do the necessary cleanup */
  1526. if (substream->runtime->channels == 4)
  1527. twl4030_tdm_enable(codec, substream->stream, 0);
  1528. }
  1529. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1530. struct snd_pcm_hw_params *params,
  1531. struct snd_soc_dai *dai)
  1532. {
  1533. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1534. struct snd_soc_device *socdev = rtd->socdev;
  1535. struct snd_soc_codec *codec = socdev->card->codec;
  1536. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1537. u8 mode, old_mode, format, old_format;
  1538. /* If the substream has 4 channel, do the necessary setup */
  1539. if (params_channels(params) == 4) {
  1540. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1541. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1542. /* Safety check: are we in the correct operating mode and
  1543. * the interface is in TDM mode? */
  1544. if ((mode & TWL4030_OPTION_1) &&
  1545. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1546. twl4030_tdm_enable(codec, substream->stream, 1);
  1547. else
  1548. return -EINVAL;
  1549. }
  1550. if (twl4030->configured)
  1551. /* Ignoring hw_params for already configured DAI */
  1552. return 0;
  1553. /* bit rate */
  1554. old_mode = twl4030_read_reg_cache(codec,
  1555. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1556. mode = old_mode & ~TWL4030_APLL_RATE;
  1557. switch (params_rate(params)) {
  1558. case 8000:
  1559. mode |= TWL4030_APLL_RATE_8000;
  1560. break;
  1561. case 11025:
  1562. mode |= TWL4030_APLL_RATE_11025;
  1563. break;
  1564. case 12000:
  1565. mode |= TWL4030_APLL_RATE_12000;
  1566. break;
  1567. case 16000:
  1568. mode |= TWL4030_APLL_RATE_16000;
  1569. break;
  1570. case 22050:
  1571. mode |= TWL4030_APLL_RATE_22050;
  1572. break;
  1573. case 24000:
  1574. mode |= TWL4030_APLL_RATE_24000;
  1575. break;
  1576. case 32000:
  1577. mode |= TWL4030_APLL_RATE_32000;
  1578. break;
  1579. case 44100:
  1580. mode |= TWL4030_APLL_RATE_44100;
  1581. break;
  1582. case 48000:
  1583. mode |= TWL4030_APLL_RATE_48000;
  1584. break;
  1585. case 96000:
  1586. mode |= TWL4030_APLL_RATE_96000;
  1587. break;
  1588. default:
  1589. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1590. params_rate(params));
  1591. return -EINVAL;
  1592. }
  1593. /* sample size */
  1594. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1595. format = old_format;
  1596. format &= ~TWL4030_DATA_WIDTH;
  1597. switch (params_format(params)) {
  1598. case SNDRV_PCM_FORMAT_S16_LE:
  1599. format |= TWL4030_DATA_WIDTH_16S_16W;
  1600. break;
  1601. case SNDRV_PCM_FORMAT_S24_LE:
  1602. format |= TWL4030_DATA_WIDTH_32S_24W;
  1603. break;
  1604. default:
  1605. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1606. params_format(params));
  1607. return -EINVAL;
  1608. }
  1609. if (format != old_format || mode != old_mode) {
  1610. if (twl4030->codec_powered) {
  1611. /*
  1612. * If the codec is powered, than we need to toggle the
  1613. * codec power.
  1614. */
  1615. twl4030_codec_enable(codec, 0);
  1616. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1617. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1618. twl4030_codec_enable(codec, 1);
  1619. } else {
  1620. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1621. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1622. }
  1623. }
  1624. /* Store the important parameters for the DAI configuration and set
  1625. * the DAI as configured */
  1626. twl4030->configured = 1;
  1627. twl4030->rate = params_rate(params);
  1628. twl4030->sample_bits = hw_param_interval(params,
  1629. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1630. twl4030->channels = params_channels(params);
  1631. /* If both playback and capture streams are open, and one of them
  1632. * is setting the hw parameters right now (since we are here), set
  1633. * constraints to the other stream to match the current one. */
  1634. if (twl4030->slave_substream)
  1635. twl4030_constraints(twl4030, substream);
  1636. return 0;
  1637. }
  1638. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1639. int clk_id, unsigned int freq, int dir)
  1640. {
  1641. struct snd_soc_codec *codec = codec_dai->codec;
  1642. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1643. switch (freq) {
  1644. case 19200000:
  1645. case 26000000:
  1646. case 38400000:
  1647. break;
  1648. default:
  1649. dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
  1650. return -EINVAL;
  1651. }
  1652. if ((freq / 1000) != twl4030->sysclk) {
  1653. dev_err(codec->dev,
  1654. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1655. freq, twl4030->sysclk * 1000);
  1656. return -EINVAL;
  1657. }
  1658. return 0;
  1659. }
  1660. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1661. unsigned int fmt)
  1662. {
  1663. struct snd_soc_codec *codec = codec_dai->codec;
  1664. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1665. u8 old_format, format;
  1666. /* get format */
  1667. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1668. format = old_format;
  1669. /* set master/slave audio interface */
  1670. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1671. case SND_SOC_DAIFMT_CBM_CFM:
  1672. format &= ~(TWL4030_AIF_SLAVE_EN);
  1673. format &= ~(TWL4030_CLK256FS_EN);
  1674. break;
  1675. case SND_SOC_DAIFMT_CBS_CFS:
  1676. format |= TWL4030_AIF_SLAVE_EN;
  1677. format |= TWL4030_CLK256FS_EN;
  1678. break;
  1679. default:
  1680. return -EINVAL;
  1681. }
  1682. /* interface format */
  1683. format &= ~TWL4030_AIF_FORMAT;
  1684. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1685. case SND_SOC_DAIFMT_I2S:
  1686. format |= TWL4030_AIF_FORMAT_CODEC;
  1687. break;
  1688. case SND_SOC_DAIFMT_DSP_A:
  1689. format |= TWL4030_AIF_FORMAT_TDM;
  1690. break;
  1691. default:
  1692. return -EINVAL;
  1693. }
  1694. if (format != old_format) {
  1695. if (twl4030->codec_powered) {
  1696. /*
  1697. * If the codec is powered, than we need to toggle the
  1698. * codec power.
  1699. */
  1700. twl4030_codec_enable(codec, 0);
  1701. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1702. twl4030_codec_enable(codec, 1);
  1703. } else {
  1704. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1705. }
  1706. }
  1707. return 0;
  1708. }
  1709. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1710. {
  1711. struct snd_soc_codec *codec = dai->codec;
  1712. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1713. if (tristate)
  1714. reg |= TWL4030_AIF_TRI_EN;
  1715. else
  1716. reg &= ~TWL4030_AIF_TRI_EN;
  1717. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1718. }
  1719. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1720. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1721. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1722. int enable)
  1723. {
  1724. u8 reg, mask;
  1725. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1726. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1727. mask = TWL4030_ARXL1_VRX_EN;
  1728. else
  1729. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1730. if (enable)
  1731. reg |= mask;
  1732. else
  1733. reg &= ~mask;
  1734. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1735. }
  1736. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1737. struct snd_soc_dai *dai)
  1738. {
  1739. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1740. struct snd_soc_device *socdev = rtd->socdev;
  1741. struct snd_soc_codec *codec = socdev->card->codec;
  1742. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1743. u8 mode;
  1744. /* If the system master clock is not 26MHz, the voice PCM interface is
  1745. * not avilable.
  1746. */
  1747. if (twl4030->sysclk != 26000) {
  1748. dev_err(codec->dev, "The board is configured for %u Hz, while"
  1749. "the Voice interface needs 26MHz APLL mclk\n",
  1750. twl4030->sysclk * 1000);
  1751. return -EINVAL;
  1752. }
  1753. /* If the codec mode is not option2, the voice PCM interface is not
  1754. * avilable.
  1755. */
  1756. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1757. & TWL4030_OPT_MODE;
  1758. if (mode != TWL4030_OPTION_2) {
  1759. printk(KERN_ERR "TWL4030 voice startup: "
  1760. "the codec mode is not option2\n");
  1761. return -EINVAL;
  1762. }
  1763. return 0;
  1764. }
  1765. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1766. struct snd_soc_dai *dai)
  1767. {
  1768. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1769. struct snd_soc_device *socdev = rtd->socdev;
  1770. struct snd_soc_codec *codec = socdev->card->codec;
  1771. /* Enable voice digital filters */
  1772. twl4030_voice_enable(codec, substream->stream, 0);
  1773. }
  1774. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1775. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1776. {
  1777. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1778. struct snd_soc_device *socdev = rtd->socdev;
  1779. struct snd_soc_codec *codec = socdev->card->codec;
  1780. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1781. u8 old_mode, mode;
  1782. /* Enable voice digital filters */
  1783. twl4030_voice_enable(codec, substream->stream, 1);
  1784. /* bit rate */
  1785. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1786. & ~(TWL4030_CODECPDZ);
  1787. mode = old_mode;
  1788. switch (params_rate(params)) {
  1789. case 8000:
  1790. mode &= ~(TWL4030_SEL_16K);
  1791. break;
  1792. case 16000:
  1793. mode |= TWL4030_SEL_16K;
  1794. break;
  1795. default:
  1796. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1797. params_rate(params));
  1798. return -EINVAL;
  1799. }
  1800. if (mode != old_mode) {
  1801. if (twl4030->codec_powered) {
  1802. /*
  1803. * If the codec is powered, than we need to toggle the
  1804. * codec power.
  1805. */
  1806. twl4030_codec_enable(codec, 0);
  1807. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1808. twl4030_codec_enable(codec, 1);
  1809. } else {
  1810. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1811. }
  1812. }
  1813. return 0;
  1814. }
  1815. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1816. int clk_id, unsigned int freq, int dir)
  1817. {
  1818. struct snd_soc_codec *codec = codec_dai->codec;
  1819. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1820. if (freq != 26000000) {
  1821. dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
  1822. "interface needs 26MHz APLL mclk\n", freq);
  1823. return -EINVAL;
  1824. }
  1825. if ((freq / 1000) != twl4030->sysclk) {
  1826. dev_err(codec->dev,
  1827. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1828. freq, twl4030->sysclk * 1000);
  1829. return -EINVAL;
  1830. }
  1831. return 0;
  1832. }
  1833. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1834. unsigned int fmt)
  1835. {
  1836. struct snd_soc_codec *codec = codec_dai->codec;
  1837. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1838. u8 old_format, format;
  1839. /* get format */
  1840. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1841. format = old_format;
  1842. /* set master/slave audio interface */
  1843. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1844. case SND_SOC_DAIFMT_CBM_CFM:
  1845. format &= ~(TWL4030_VIF_SLAVE_EN);
  1846. break;
  1847. case SND_SOC_DAIFMT_CBS_CFS:
  1848. format |= TWL4030_VIF_SLAVE_EN;
  1849. break;
  1850. default:
  1851. return -EINVAL;
  1852. }
  1853. /* clock inversion */
  1854. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1855. case SND_SOC_DAIFMT_IB_NF:
  1856. format &= ~(TWL4030_VIF_FORMAT);
  1857. break;
  1858. case SND_SOC_DAIFMT_NB_IF:
  1859. format |= TWL4030_VIF_FORMAT;
  1860. break;
  1861. default:
  1862. return -EINVAL;
  1863. }
  1864. if (format != old_format) {
  1865. if (twl4030->codec_powered) {
  1866. /*
  1867. * If the codec is powered, than we need to toggle the
  1868. * codec power.
  1869. */
  1870. twl4030_codec_enable(codec, 0);
  1871. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1872. twl4030_codec_enable(codec, 1);
  1873. } else {
  1874. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1875. }
  1876. }
  1877. return 0;
  1878. }
  1879. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1880. {
  1881. struct snd_soc_codec *codec = dai->codec;
  1882. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1883. if (tristate)
  1884. reg |= TWL4030_VIF_TRI_EN;
  1885. else
  1886. reg &= ~TWL4030_VIF_TRI_EN;
  1887. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1888. }
  1889. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1890. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1891. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1892. .startup = twl4030_startup,
  1893. .shutdown = twl4030_shutdown,
  1894. .hw_params = twl4030_hw_params,
  1895. .set_sysclk = twl4030_set_dai_sysclk,
  1896. .set_fmt = twl4030_set_dai_fmt,
  1897. .set_tristate = twl4030_set_tristate,
  1898. };
  1899. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1900. .startup = twl4030_voice_startup,
  1901. .shutdown = twl4030_voice_shutdown,
  1902. .hw_params = twl4030_voice_hw_params,
  1903. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1904. .set_fmt = twl4030_voice_set_dai_fmt,
  1905. .set_tristate = twl4030_voice_set_tristate,
  1906. };
  1907. struct snd_soc_dai twl4030_dai[] = {
  1908. {
  1909. .name = "twl4030",
  1910. .playback = {
  1911. .stream_name = "HiFi Playback",
  1912. .channels_min = 2,
  1913. .channels_max = 4,
  1914. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1915. .formats = TWL4030_FORMATS,},
  1916. .capture = {
  1917. .stream_name = "Capture",
  1918. .channels_min = 2,
  1919. .channels_max = 4,
  1920. .rates = TWL4030_RATES,
  1921. .formats = TWL4030_FORMATS,},
  1922. .ops = &twl4030_dai_ops,
  1923. },
  1924. {
  1925. .name = "twl4030 Voice",
  1926. .playback = {
  1927. .stream_name = "Voice Playback",
  1928. .channels_min = 1,
  1929. .channels_max = 1,
  1930. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1931. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1932. .capture = {
  1933. .stream_name = "Capture",
  1934. .channels_min = 1,
  1935. .channels_max = 2,
  1936. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1937. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1938. .ops = &twl4030_dai_voice_ops,
  1939. },
  1940. };
  1941. EXPORT_SYMBOL_GPL(twl4030_dai);
  1942. static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1943. {
  1944. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1945. struct snd_soc_codec *codec = socdev->card->codec;
  1946. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1947. return 0;
  1948. }
  1949. static int twl4030_soc_resume(struct platform_device *pdev)
  1950. {
  1951. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1952. struct snd_soc_codec *codec = socdev->card->codec;
  1953. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1954. return 0;
  1955. }
  1956. static struct snd_soc_codec *twl4030_codec;
  1957. static int twl4030_soc_probe(struct platform_device *pdev)
  1958. {
  1959. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1960. struct snd_soc_codec *codec;
  1961. int ret;
  1962. BUG_ON(!twl4030_codec);
  1963. codec = twl4030_codec;
  1964. socdev->card->codec = codec;
  1965. twl4030_init_chip(pdev);
  1966. /* register pcms */
  1967. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1968. if (ret < 0) {
  1969. dev_err(&pdev->dev, "failed to create pcms\n");
  1970. return ret;
  1971. }
  1972. snd_soc_add_controls(codec, twl4030_snd_controls,
  1973. ARRAY_SIZE(twl4030_snd_controls));
  1974. twl4030_add_widgets(codec);
  1975. return 0;
  1976. }
  1977. static int twl4030_soc_remove(struct platform_device *pdev)
  1978. {
  1979. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1980. struct snd_soc_codec *codec = socdev->card->codec;
  1981. /* Reset registers to their chip default before leaving */
  1982. twl4030_reset_registers(codec);
  1983. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1984. snd_soc_free_pcms(socdev);
  1985. snd_soc_dapm_free(socdev);
  1986. return 0;
  1987. }
  1988. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  1989. {
  1990. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  1991. struct snd_soc_codec *codec;
  1992. struct twl4030_priv *twl4030;
  1993. int ret;
  1994. if (!pdata) {
  1995. dev_err(&pdev->dev, "platform_data is missing\n");
  1996. return -EINVAL;
  1997. }
  1998. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1999. if (twl4030 == NULL) {
  2000. dev_err(&pdev->dev, "Can not allocate memroy\n");
  2001. return -ENOMEM;
  2002. }
  2003. codec = &twl4030->codec;
  2004. snd_soc_codec_set_drvdata(codec, twl4030);
  2005. codec->dev = &pdev->dev;
  2006. twl4030_dai[0].dev = &pdev->dev;
  2007. twl4030_dai[1].dev = &pdev->dev;
  2008. mutex_init(&codec->mutex);
  2009. INIT_LIST_HEAD(&codec->dapm_widgets);
  2010. INIT_LIST_HEAD(&codec->dapm_paths);
  2011. codec->name = "twl4030";
  2012. codec->owner = THIS_MODULE;
  2013. codec->read = twl4030_read_reg_cache;
  2014. codec->write = twl4030_write;
  2015. codec->set_bias_level = twl4030_set_bias_level;
  2016. codec->idle_bias_off = 1;
  2017. codec->dai = twl4030_dai;
  2018. codec->num_dai = ARRAY_SIZE(twl4030_dai);
  2019. codec->reg_cache_size = sizeof(twl4030_reg);
  2020. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  2021. GFP_KERNEL);
  2022. if (codec->reg_cache == NULL) {
  2023. ret = -ENOMEM;
  2024. goto error_cache;
  2025. }
  2026. platform_set_drvdata(pdev, twl4030);
  2027. twl4030_codec = codec;
  2028. /* Set the defaults, and power up the codec */
  2029. twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
  2030. codec->bias_level = SND_SOC_BIAS_OFF;
  2031. ret = snd_soc_register_codec(codec);
  2032. if (ret != 0) {
  2033. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  2034. goto error_codec;
  2035. }
  2036. ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2037. if (ret != 0) {
  2038. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  2039. snd_soc_unregister_codec(codec);
  2040. goto error_codec;
  2041. }
  2042. return 0;
  2043. error_codec:
  2044. twl4030_codec_enable(codec, 0);
  2045. kfree(codec->reg_cache);
  2046. error_cache:
  2047. kfree(twl4030);
  2048. return ret;
  2049. }
  2050. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  2051. {
  2052. struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
  2053. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2054. snd_soc_unregister_codec(&twl4030->codec);
  2055. kfree(twl4030->codec.reg_cache);
  2056. kfree(twl4030);
  2057. twl4030_codec = NULL;
  2058. return 0;
  2059. }
  2060. MODULE_ALIAS("platform:twl4030_codec_audio");
  2061. static struct platform_driver twl4030_codec_driver = {
  2062. .probe = twl4030_codec_probe,
  2063. .remove = __devexit_p(twl4030_codec_remove),
  2064. .driver = {
  2065. .name = "twl4030_codec_audio",
  2066. .owner = THIS_MODULE,
  2067. },
  2068. };
  2069. static int __init twl4030_modinit(void)
  2070. {
  2071. return platform_driver_register(&twl4030_codec_driver);
  2072. }
  2073. module_init(twl4030_modinit);
  2074. static void __exit twl4030_exit(void)
  2075. {
  2076. platform_driver_unregister(&twl4030_codec_driver);
  2077. }
  2078. module_exit(twl4030_exit);
  2079. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  2080. .probe = twl4030_soc_probe,
  2081. .remove = twl4030_soc_remove,
  2082. .suspend = twl4030_soc_suspend,
  2083. .resume = twl4030_soc_resume,
  2084. };
  2085. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  2086. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  2087. MODULE_AUTHOR("Steve Sakoman");
  2088. MODULE_LICENSE("GPL");