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powerpc
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sysdev
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ppc4xx_pci.h

ppc4xx_pci.h 3.2 KB
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  1. /*
    2. 

  2.  * PCI / PCI-X / PCI-Express support for 4xx parts
    3. 

  3.  *
    4. 

  4.  * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
    5. 

  5.  *
    6. 

  6.  * Bits and pieces extracted from arch/ppc support by
    7. 

  7.  *
    8. 

  8.  * Matt Porter <mporter@kernel.crashing.org>
    9. 

  9.  *
    10. 

  10.  * Copyright 2002-2005 MontaVista Software Inc.
    11. 

  11.  */
    12. 

  12. #ifndef __PPC4XX_PCI_H__
    13. 

  13. #define __PPC4XX_PCI_H__
    14. 

  14. 

  15. /*
    16. 

  16.  * 4xx PCI-X bridge register definitions
    17. 

  17.  */
    18. 

  18. #define PCIX0_VENDID		0x000
    19. 

  19. #define PCIX0_DEVID		0x002
    20. 

  20. #define PCIX0_COMMAND		0x004
    21. 

  21. #define PCIX0_STATUS		0x006
    22. 

  22. #define PCIX0_REVID		0x008
    23. 

  23. #define PCIX0_CLS		0x009
    24. 

  24. #define PCIX0_CACHELS		0x00c
    25. 

  25. #define PCIX0_LATTIM		0x00d
    26. 

  26. #define PCIX0_HDTYPE		0x00e
    27. 

  27. #define PCIX0_BIST		0x00f
    28. 

  28. #define PCIX0_BAR0L		0x010
    29. 

  29. #define PCIX0_BAR0H		0x014
    30. 

  30. #define PCIX0_BAR1		0x018
    31. 

  31. #define PCIX0_BAR2L		0x01c
    32. 

  32. #define PCIX0_BAR2H		0x020
    33. 

  33. #define PCIX0_BAR3		0x024
    34. 

  34. #define PCIX0_CISPTR		0x028
    35. 

  35. #define PCIX0_SBSYSVID		0x02c
    36. 

  36. #define PCIX0_SBSYSID		0x02e
    37. 

  37. #define PCIX0_EROMBA		0x030
    38. 

  38. #define PCIX0_CAP		0x034
    39. 

  39. #define PCIX0_RES0		0x035
    40. 

  40. #define PCIX0_RES1		0x036
    41. 

  41. #define PCIX0_RES2		0x038
    42. 

  42. #define PCIX0_INTLN		0x03c
    43. 

  43. #define PCIX0_INTPN		0x03d
    44. 

  44. #define PCIX0_MINGNT		0x03e
    45. 

  45. #define PCIX0_MAXLTNCY		0x03f
    46. 

  46. #define PCIX0_BRDGOPT1		0x040
    47. 

  47. #define PCIX0_BRDGOPT2		0x044
    48. 

  48. #define PCIX0_ERREN		0x050
    49. 

  49. #define PCIX0_ERRSTS		0x054
    50. 

  50. #define PCIX0_PLBBESR		0x058
    51. 

  51. #define PCIX0_PLBBEARL		0x05c
    52. 

  52. #define PCIX0_PLBBEARH		0x060
    53. 

  53. #define PCIX0_POM0LAL		0x068
    54. 

  54. #define PCIX0_POM0LAH		0x06c
    55. 

  55. #define PCIX0_POM0SA		0x070
    56. 

  56. #define PCIX0_POM0PCIAL		0x074
    57. 

  57. #define PCIX0_POM0PCIAH		0x078
    58. 

  58. #define PCIX0_POM1LAL		0x07c
    59. 

  59. #define PCIX0_POM1LAH		0x080
    60. 

  60. #define PCIX0_POM1SA		0x084
    61. 

  61. #define PCIX0_POM1PCIAL		0x088
    62. 

  62. #define PCIX0_POM1PCIAH		0x08c
    63. 

  63. #define PCIX0_POM2SA		0x090
    64. 

  64. #define PCIX0_PIM0SAL		0x098
    65. 

  65. #define PCIX0_PIM0SA		PCIX0_PIM0SAL
    66. 

  66. #define PCIX0_PIM0LAL		0x09c
    67. 

  67. #define PCIX0_PIM0LAH		0x0a0
    68. 

  68. #define PCIX0_PIM1SA		0x0a4
    69. 

  69. #define PCIX0_PIM1LAL		0x0a8
    70. 

  70. #define PCIX0_PIM1LAH		0x0ac
    71. 

  71. #define PCIX0_PIM2SAL		0x0b0
    72. 

  72. #define PCIX0_PIM2SA		PCIX0_PIM2SAL
    73. 

  73. #define PCIX0_PIM2LAL		0x0b4
    74. 

  74. #define PCIX0_PIM2LAH		0x0b8
    75. 

  75. #define PCIX0_OMCAPID		0x0c0
    76. 

  76. #define PCIX0_OMNIPTR		0x0c1
    77. 

  77. #define PCIX0_OMMC		0x0c2
    78. 

  78. #define PCIX0_OMMA		0x0c4
    79. 

  79. #define PCIX0_OMMUA		0x0c8
    80. 

  80. #define PCIX0_OMMDATA		0x0cc
    81. 

  81. #define PCIX0_OMMEOI		0x0ce
    82. 

  82. #define PCIX0_PMCAPID		0x0d0
    83. 

  83. #define PCIX0_PMNIPTR		0x0d1
    84. 

  84. #define PCIX0_PMC		0x0d2
    85. 

  85. #define PCIX0_PMCSR		0x0d4
    86. 

  86. #define PCIX0_PMCSRBSE		0x0d6
    87. 

  87. #define PCIX0_PMDATA		0x0d7
    88. 

  88. #define PCIX0_PMSCRR		0x0d8
    89. 

  89. #define PCIX0_CAPID		0x0dc
    90. 

  90. #define PCIX0_NIPTR		0x0dd
    91. 

  91. #define PCIX0_CMD		0x0de
    92. 

  92. #define PCIX0_STS		0x0e0
    93. 

  93. #define PCIX0_IDR		0x0e4
    94. 

  94. #define PCIX0_CID		0x0e8
    95. 

  95. #define PCIX0_RID		0x0ec
    96. 

  96. #define PCIX0_PIM0SAH		0x0f8
    97. 

  97. #define PCIX0_PIM2SAH		0x0fc
    98. 

  98. #define PCIX0_MSGIL		0x100
    99. 

  99. #define PCIX0_MSGIH		0x104
    100. 

  100. #define PCIX0_MSGOL		0x108
    101. 

  101. #define PCIX0_MSGOH		0x10c
    102. 

  102. #define PCIX0_IM		0x1f8
    103. 

  103. 

  104. /*
    105. 

  105.  * 4xx PCI bridge register definitions
    106. 

  106.  */
    107. 

  107. #define PCIL0_PMM0LA		0x00
    108. 

  108. #define PCIL0_PMM0MA		0x04
    109. 

  109. #define PCIL0_PMM0PCILA		0x08
    110. 

  110. #define PCIL0_PMM0PCIHA		0x0c
    111. 

  111. #define PCIL0_PMM1LA		0x10
    112. 

  112. #define PCIL0_PMM1MA		0x14
    113. 

  113. #define PCIL0_PMM1PCILA		0x18
    114. 

  114. #define PCIL0_PMM1PCIHA		0x1c
    115. 

  115. #define PCIL0_PMM2LA		0x20
    116. 

  116. #define PCIL0_PMM2MA		0x24
    117. 

  117. #define PCIL0_PMM2PCILA		0x28
    118. 

  118. #define PCIL0_PMM2PCIHA		0x2c
    119. 

  119. #define PCIL0_PTM1MS		0x30
    120. 

  120. #define PCIL0_PTM1LA		0x34
    121. 

  121. #define PCIL0_PTM2MS		0x38
    122. 

  122. #define PCIL0_PTM2LA		0x3c
    123. 

  123. 

  124. 

  125. #endif /* __PPC4XX_PCI_H__ */
    126.