em28xx-core.c 18 KB

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  1. /*
  2. em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  3. Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  4. Markus Rechberger <mrechberger@gmail.com>
  5. Mauro Carvalho Chehab <mchehab@infradead.org>
  6. Sascha Sommer <saschasommer@freenet.de>
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/module.h>
  22. #include <linux/usb.h>
  23. #include <linux/vmalloc.h>
  24. #include "em28xx.h"
  25. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  26. static unsigned int core_debug;
  27. module_param(core_debug,int,0644);
  28. MODULE_PARM_DESC(core_debug,"enable debug messages [core]");
  29. #define em28xx_coredbg(fmt, arg...) do {\
  30. if (core_debug) \
  31. printk(KERN_INFO "%s %s :"fmt, \
  32. dev->name, __func__ , ##arg); } while (0)
  33. static unsigned int reg_debug;
  34. module_param(reg_debug,int,0644);
  35. MODULE_PARM_DESC(reg_debug,"enable debug messages [URB reg]");
  36. #define em28xx_regdbg(fmt, arg...) do {\
  37. if (reg_debug) \
  38. printk(KERN_INFO "%s %s :"fmt, \
  39. dev->name, __func__ , ##arg); } while (0)
  40. static int alt = EM28XX_PINOUT;
  41. module_param(alt, int, 0644);
  42. MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
  43. /* FIXME */
  44. #define em28xx_isocdbg(fmt, arg...) do {\
  45. if (core_debug) \
  46. printk(KERN_INFO "%s %s :"fmt, \
  47. dev->name, __func__ , ##arg); } while (0)
  48. /*
  49. * em28xx_read_reg_req()
  50. * reads data from the usb device specifying bRequest
  51. */
  52. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  53. char *buf, int len)
  54. {
  55. int ret, byte;
  56. if (dev->state & DEV_DISCONNECTED)
  57. return(-ENODEV);
  58. em28xx_regdbg("req=%02x, reg=%02x ", req, reg);
  59. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req,
  60. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  61. 0x0000, reg, buf, len, HZ);
  62. if (reg_debug) {
  63. printk(ret < 0 ? " failed!\n" : "%02x values: ", ret);
  64. for (byte = 0; byte < len; byte++)
  65. printk(" %02x", (unsigned char)buf[byte]);
  66. printk("\n");
  67. }
  68. return ret;
  69. }
  70. /*
  71. * em28xx_read_reg_req()
  72. * reads data from the usb device specifying bRequest
  73. */
  74. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  75. {
  76. u8 val;
  77. int ret;
  78. if (dev->state & DEV_DISCONNECTED)
  79. return(-ENODEV);
  80. em28xx_regdbg("req=%02x, reg=%02x:", req, reg);
  81. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req,
  82. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  83. 0x0000, reg, &val, 1, HZ);
  84. if (reg_debug)
  85. printk(ret < 0 ? " failed!\n" :
  86. "%02x\n", (unsigned char) val);
  87. if (ret < 0)
  88. return ret;
  89. return val;
  90. }
  91. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  92. {
  93. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  94. }
  95. /*
  96. * em28xx_write_regs_req()
  97. * sends data to the usb device, specifying bRequest
  98. */
  99. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  100. int len)
  101. {
  102. int ret;
  103. /*usb_control_msg seems to expect a kmalloced buffer */
  104. unsigned char *bufs;
  105. if (dev->state & DEV_DISCONNECTED)
  106. return -ENODEV;
  107. if (len < 1)
  108. return -EINVAL;
  109. bufs = kmalloc(len, GFP_KERNEL);
  110. em28xx_regdbg("req=%02x reg=%02x:", req, reg);
  111. if (reg_debug) {
  112. int i;
  113. for (i = 0; i < len; ++i)
  114. printk(" %02x", (unsigned char)buf[i]);
  115. printk("\n");
  116. }
  117. if (!bufs)
  118. return -ENOMEM;
  119. memcpy(bufs, buf, len);
  120. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), req,
  121. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  122. 0x0000, reg, bufs, len, HZ);
  123. if (dev->wait_after_write)
  124. msleep(dev->wait_after_write);
  125. kfree(bufs);
  126. return ret;
  127. }
  128. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  129. {
  130. int rc;
  131. rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  132. /* Stores GPO/GPIO values at the cache, if changed
  133. Only write values should be stored, since input on a GPIO
  134. register will return the input bits.
  135. Not sure what happens on reading GPO register.
  136. */
  137. if (rc >= 0) {
  138. if (reg == EM2880_R04_GPO)
  139. dev->reg_gpo = buf[0];
  140. else if (reg == EM28XX_R08_GPIO)
  141. dev->reg_gpio = buf[0];
  142. }
  143. return rc;
  144. }
  145. /*
  146. * em28xx_write_reg_bits()
  147. * sets only some bits (specified by bitmask) of a register, by first reading
  148. * the actual value
  149. */
  150. static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  151. u8 bitmask)
  152. {
  153. int oldval;
  154. u8 newval;
  155. /* Uses cache for gpo/gpio registers */
  156. if (reg == EM2880_R04_GPO)
  157. oldval = dev->reg_gpo;
  158. else if (reg == EM28XX_R08_GPIO)
  159. oldval = dev->reg_gpio;
  160. else
  161. oldval = em28xx_read_reg(dev, reg);
  162. if (oldval < 0)
  163. return oldval;
  164. newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
  165. return em28xx_write_regs(dev, reg, &newval, 1);
  166. }
  167. /*
  168. * em28xx_write_ac97()
  169. * write a 16 bit value to the specified AC97 address (LSB first!)
  170. */
  171. static int em28xx_write_ac97(struct em28xx *dev, u8 reg, u8 *val)
  172. {
  173. int ret, i;
  174. u8 addr = reg & 0x7f;
  175. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, val, 2);
  176. if (ret < 0)
  177. return ret;
  178. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  179. if (ret < 0)
  180. return ret;
  181. /* Wait up to 50 ms for AC97 command to complete */
  182. for (i = 0; i < 10; i++) {
  183. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  184. if (ret < 0)
  185. return ret;
  186. if (!(ret & 0x01))
  187. return 0;
  188. msleep(5);
  189. }
  190. em28xx_warn("AC97 command still being executed: not handled properly!\n");
  191. return 0;
  192. }
  193. static int em28xx_set_audio_source(struct em28xx *dev)
  194. {
  195. static char *enable = "\x08\x08";
  196. static char *disable = "\x08\x88";
  197. char *video = enable, *line = disable;
  198. int ret;
  199. u8 input;
  200. if (dev->is_em2800) {
  201. if (dev->ctl_ainput)
  202. input = EM2800_AUDIO_SRC_LINE;
  203. else
  204. input = EM2800_AUDIO_SRC_TUNER;
  205. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  206. if (ret < 0)
  207. return ret;
  208. }
  209. if (dev->has_msp34xx)
  210. input = EM28XX_AUDIO_SRC_TUNER;
  211. else {
  212. switch (dev->ctl_ainput) {
  213. case EM28XX_AMUX_VIDEO:
  214. input = EM28XX_AUDIO_SRC_TUNER;
  215. break;
  216. case EM28XX_AMUX_LINE_IN:
  217. input = EM28XX_AUDIO_SRC_LINE;
  218. break;
  219. case EM28XX_AMUX_AC97_VIDEO:
  220. input = EM28XX_AUDIO_SRC_LINE;
  221. break;
  222. case EM28XX_AMUX_AC97_LINE_IN:
  223. input = EM28XX_AUDIO_SRC_LINE;
  224. video = disable;
  225. line = enable;
  226. break;
  227. }
  228. }
  229. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  230. if (ret < 0)
  231. return ret;
  232. msleep(5);
  233. /* Sets AC97 mixer registers
  234. This is seems to be needed, even for non-ac97 configs
  235. */
  236. ret = em28xx_write_ac97(dev, EM28XX_R14_VIDEO_AC97, video);
  237. if (ret < 0)
  238. return ret;
  239. ret = em28xx_write_ac97(dev, EM28XX_R10_LINE_IN_AC97, line);
  240. return ret;
  241. }
  242. int em28xx_audio_analog_set(struct em28xx *dev)
  243. {
  244. int ret;
  245. char s[2] = { 0x00, 0x00 };
  246. u8 xclk = 0x07;
  247. s[0] |= 0x1f - dev->volume;
  248. s[1] |= 0x1f - dev->volume;
  249. /* Mute */
  250. s[1] |= 0x80;
  251. ret = em28xx_write_ac97(dev, EM28XX_R02_MASTER_AC97, s);
  252. if (ret < 0)
  253. return ret;
  254. if (dev->has_12mhz_i2s)
  255. xclk |= 0x20;
  256. if (!dev->mute)
  257. xclk |= 0x80;
  258. ret = em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, xclk, 0xa7);
  259. if (ret < 0)
  260. return ret;
  261. msleep(10);
  262. /* Selects the proper audio input */
  263. ret = em28xx_set_audio_source(dev);
  264. /* Unmute device */
  265. if (!dev->mute)
  266. s[1] &= ~0x80;
  267. ret = em28xx_write_ac97(dev, EM28XX_R02_MASTER_AC97, s);
  268. return ret;
  269. }
  270. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  271. int em28xx_colorlevels_set_default(struct em28xx *dev)
  272. {
  273. em28xx_write_regs(dev, EM28XX_R20_YGAIN, "\x10", 1); /* contrast */
  274. em28xx_write_regs(dev, EM28XX_R21_YOFFSET, "\x00", 1); /* brightness */
  275. em28xx_write_regs(dev, EM28XX_R22_UVGAIN, "\x10", 1); /* saturation */
  276. em28xx_write_regs(dev, EM28XX_R23_UOFFSET, "\x00", 1);
  277. em28xx_write_regs(dev, EM28XX_R24_VOFFSET, "\x00", 1);
  278. em28xx_write_regs(dev, EM28XX_R25_SHARPNESS, "\x00", 1);
  279. em28xx_write_regs(dev, EM28XX_R14_GAMMA, "\x20", 1);
  280. em28xx_write_regs(dev, EM28XX_R15_RGAIN, "\x20", 1);
  281. em28xx_write_regs(dev, EM28XX_R16_GGAIN, "\x20", 1);
  282. em28xx_write_regs(dev, EM28XX_R17_BGAIN, "\x20", 1);
  283. em28xx_write_regs(dev, EM28XX_R18_ROFFSET, "\x00", 1);
  284. em28xx_write_regs(dev, EM28XX_R19_GOFFSET, "\x00", 1);
  285. return em28xx_write_regs(dev, EM28XX_R1A_BOFFSET, "\x00", 1);
  286. }
  287. int em28xx_capture_start(struct em28xx *dev, int start)
  288. {
  289. int rc;
  290. /* FIXME: which is the best order? */
  291. /* video registers are sampled by VREF */
  292. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  293. start ? 0x10 : 0x00, 0x10);
  294. if (rc < 0)
  295. return rc;
  296. if (!start) {
  297. /* disable video capture */
  298. rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x27", 1);
  299. return rc;
  300. }
  301. /* enable video capture */
  302. rc = em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1);
  303. if (dev->mode == EM28XX_ANALOG_MODE)
  304. rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x67", 1);
  305. else
  306. rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x37", 1);
  307. msleep(6);
  308. return rc;
  309. }
  310. int em28xx_outfmt_set_yuv422(struct em28xx *dev)
  311. {
  312. em28xx_write_regs(dev, EM28XX_R27_OUTFMT, "\x34", 1);
  313. em28xx_write_regs(dev, EM28XX_R10_VINMODE, "\x10", 1);
  314. return em28xx_write_regs(dev, EM28XX_R11_VINCTRL, "\x11", 1);
  315. }
  316. static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
  317. u8 ymin, u8 ymax)
  318. {
  319. em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
  320. xmin, ymin, xmax, ymax);
  321. em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
  322. em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
  323. em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
  324. return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
  325. }
  326. static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
  327. u16 width, u16 height)
  328. {
  329. u8 cwidth = width;
  330. u8 cheight = height;
  331. u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
  332. em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
  333. (width | (overflow & 2) << 7),
  334. (height | (overflow & 1) << 8));
  335. em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
  336. em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
  337. em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
  338. em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
  339. return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
  340. }
  341. static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
  342. {
  343. u8 mode;
  344. /* the em2800 scaler only supports scaling down to 50% */
  345. if (dev->is_em2800)
  346. mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
  347. else {
  348. u8 buf[2];
  349. buf[0] = h;
  350. buf[1] = h >> 8;
  351. em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
  352. buf[0] = v;
  353. buf[1] = v >> 8;
  354. em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
  355. /* it seems that both H and V scalers must be active
  356. to work correctly */
  357. mode = (h || v)? 0x30: 0x00;
  358. }
  359. return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
  360. }
  361. /* FIXME: this only function read values from dev */
  362. int em28xx_resolution_set(struct em28xx *dev)
  363. {
  364. int width, height;
  365. width = norm_maxw(dev);
  366. height = norm_maxh(dev) >> 1;
  367. em28xx_outfmt_set_yuv422(dev);
  368. em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
  369. em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
  370. return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
  371. }
  372. int em28xx_set_alternate(struct em28xx *dev)
  373. {
  374. int errCode, prev_alt = dev->alt;
  375. int i;
  376. unsigned int min_pkt_size = dev->width * 2 + 4;
  377. /* When image size is bigger than a certain value,
  378. the frame size should be increased, otherwise, only
  379. green screen will be received.
  380. */
  381. if (dev->width * 2 * dev->height > 720 * 240 * 2)
  382. min_pkt_size *= 2;
  383. for (i = 0; i < dev->num_alt; i++) {
  384. /* stop when the selected alt setting offers enough bandwidth */
  385. if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
  386. dev->alt = i;
  387. break;
  388. /* otherwise make sure that we end up with the maximum bandwidth
  389. because the min_pkt_size equation might be wrong...
  390. */
  391. } else if (dev->alt_max_pkt_size[i] >
  392. dev->alt_max_pkt_size[dev->alt])
  393. dev->alt = i;
  394. }
  395. if (dev->alt != prev_alt) {
  396. em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
  397. min_pkt_size, dev->alt);
  398. dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
  399. em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
  400. dev->alt, dev->max_pkt_size);
  401. errCode = usb_set_interface(dev->udev, 0, dev->alt);
  402. if (errCode < 0) {
  403. em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
  404. dev->alt, errCode);
  405. return errCode;
  406. }
  407. }
  408. return 0;
  409. }
  410. int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
  411. {
  412. int rc = 0;
  413. if (!gpio)
  414. return rc;
  415. dev->em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1);
  416. if (dev->mode == EM28XX_ANALOG_MODE)
  417. dev->em28xx_write_regs_req(dev, 0x00, 0x12, "\x67", 1);
  418. else
  419. dev->em28xx_write_regs_req(dev, 0x00, 0x12, "\x37", 1);
  420. msleep(6);
  421. /* Send GPIO reset sequences specified at board entry */
  422. while (gpio->sleep >= 0) {
  423. if (gpio->reg >= 0) {
  424. rc = em28xx_write_reg_bits(dev,
  425. gpio->reg,
  426. gpio->val,
  427. gpio->mask);
  428. if (rc < 0)
  429. return rc;
  430. }
  431. if (gpio->sleep > 0)
  432. msleep(gpio->sleep);
  433. gpio++;
  434. }
  435. return rc;
  436. }
  437. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  438. {
  439. if (dev->mode == set_mode)
  440. return 0;
  441. if (set_mode == EM28XX_MODE_UNDEFINED) {
  442. dev->mode = set_mode;
  443. return 0;
  444. }
  445. dev->mode = set_mode;
  446. if (dev->mode == EM28XX_DIGITAL_MODE)
  447. return em28xx_gpio_set(dev, dev->digital_gpio);
  448. else
  449. return em28xx_gpio_set(dev, dev->analog_gpio);
  450. }
  451. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  452. /* ------------------------------------------------------------------
  453. URB control
  454. ------------------------------------------------------------------*/
  455. /*
  456. * IRQ callback, called by URB callback
  457. */
  458. static void em28xx_irq_callback(struct urb *urb)
  459. {
  460. struct em28xx_dmaqueue *dma_q = urb->context;
  461. struct em28xx *dev = container_of(dma_q, struct em28xx, vidq);
  462. int rc, i;
  463. /* Copy data from URB */
  464. spin_lock(&dev->slock);
  465. rc = dev->isoc_ctl.isoc_copy(dev, urb);
  466. spin_unlock(&dev->slock);
  467. /* Reset urb buffers */
  468. for (i = 0; i < urb->number_of_packets; i++) {
  469. urb->iso_frame_desc[i].status = 0;
  470. urb->iso_frame_desc[i].actual_length = 0;
  471. }
  472. urb->status = 0;
  473. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  474. if (urb->status) {
  475. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  476. urb->status);
  477. }
  478. }
  479. /*
  480. * Stop and Deallocate URBs
  481. */
  482. void em28xx_uninit_isoc(struct em28xx *dev)
  483. {
  484. struct urb *urb;
  485. int i;
  486. em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
  487. dev->isoc_ctl.nfields = -1;
  488. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  489. urb = dev->isoc_ctl.urb[i];
  490. if (urb) {
  491. usb_kill_urb(urb);
  492. usb_unlink_urb(urb);
  493. if (dev->isoc_ctl.transfer_buffer[i]) {
  494. usb_buffer_free(dev->udev,
  495. urb->transfer_buffer_length,
  496. dev->isoc_ctl.transfer_buffer[i],
  497. urb->transfer_dma);
  498. }
  499. usb_free_urb(urb);
  500. dev->isoc_ctl.urb[i] = NULL;
  501. }
  502. dev->isoc_ctl.transfer_buffer[i] = NULL;
  503. }
  504. kfree(dev->isoc_ctl.urb);
  505. kfree(dev->isoc_ctl.transfer_buffer);
  506. dev->isoc_ctl.urb = NULL;
  507. dev->isoc_ctl.transfer_buffer = NULL;
  508. dev->isoc_ctl.num_bufs = 0;
  509. em28xx_capture_start(dev, 0);
  510. }
  511. EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
  512. /*
  513. * Allocate URBs and start IRQ
  514. */
  515. int em28xx_init_isoc(struct em28xx *dev, int max_packets,
  516. int num_bufs, int max_pkt_size,
  517. int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
  518. {
  519. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  520. int i;
  521. int sb_size, pipe;
  522. struct urb *urb;
  523. int j, k;
  524. int rc;
  525. em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
  526. /* De-allocates all pending stuff */
  527. em28xx_uninit_isoc(dev);
  528. dev->isoc_ctl.isoc_copy = isoc_copy;
  529. dev->isoc_ctl.num_bufs = num_bufs;
  530. dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
  531. if (!dev->isoc_ctl.urb) {
  532. em28xx_errdev("cannot alloc memory for usb buffers\n");
  533. return -ENOMEM;
  534. }
  535. dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
  536. GFP_KERNEL);
  537. if (!dev->isoc_ctl.transfer_buffer) {
  538. em28xx_errdev("cannot allocate memory for usbtransfer\n");
  539. kfree(dev->isoc_ctl.urb);
  540. return -ENOMEM;
  541. }
  542. dev->isoc_ctl.max_pkt_size = max_pkt_size;
  543. dev->isoc_ctl.buf = NULL;
  544. sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
  545. /* allocate urbs and transfer buffers */
  546. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  547. urb = usb_alloc_urb(max_packets, GFP_KERNEL);
  548. if (!urb) {
  549. em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
  550. em28xx_uninit_isoc(dev);
  551. return -ENOMEM;
  552. }
  553. dev->isoc_ctl.urb[i] = urb;
  554. dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
  555. sb_size, GFP_KERNEL, &urb->transfer_dma);
  556. if (!dev->isoc_ctl.transfer_buffer[i]) {
  557. em28xx_err("unable to allocate %i bytes for transfer"
  558. " buffer %i%s\n",
  559. sb_size, i,
  560. in_interrupt()?" while in int":"");
  561. em28xx_uninit_isoc(dev);
  562. return -ENOMEM;
  563. }
  564. memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
  565. /* FIXME: this is a hack - should be
  566. 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
  567. should also be using 'desc.bInterval'
  568. */
  569. pipe = usb_rcvisocpipe(dev->udev,
  570. dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
  571. usb_fill_int_urb(urb, dev->udev, pipe,
  572. dev->isoc_ctl.transfer_buffer[i], sb_size,
  573. em28xx_irq_callback, dma_q, 1);
  574. urb->number_of_packets = max_packets;
  575. urb->transfer_flags = URB_ISO_ASAP;
  576. k = 0;
  577. for (j = 0; j < max_packets; j++) {
  578. urb->iso_frame_desc[j].offset = k;
  579. urb->iso_frame_desc[j].length =
  580. dev->isoc_ctl.max_pkt_size;
  581. k += dev->isoc_ctl.max_pkt_size;
  582. }
  583. }
  584. init_waitqueue_head(&dma_q->wq);
  585. em28xx_capture_start(dev, 1);
  586. /* submit urbs and enables IRQ */
  587. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  588. rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
  589. if (rc) {
  590. em28xx_err("submit of urb %i failed (error=%i)\n", i,
  591. rc);
  592. em28xx_uninit_isoc(dev);
  593. return rc;
  594. }
  595. }
  596. return 0;
  597. }
  598. EXPORT_SYMBOL_GPL(em28xx_init_isoc);