intel_display.c 226 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <drm/drm_edid.h>
  34. #include "drmP.h"
  35. #include "intel_drv.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #include "i915_trace.h"
  39. #include "drm_dp_helper.h"
  40. #include "drm_crtc_helper.h"
  41. #include <linux/dma_remapping.h>
  42. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43. bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  44. static void intel_increase_pllclock(struct drm_crtc *crtc);
  45. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46. typedef struct {
  47. /* given values */
  48. int n;
  49. int m1, m2;
  50. int p1, p2;
  51. /* derived values */
  52. int dot;
  53. int vco;
  54. int m;
  55. int p;
  56. } intel_clock_t;
  57. typedef struct {
  58. int min, max;
  59. } intel_range_t;
  60. typedef struct {
  61. int dot_limit;
  62. int p2_slow, p2_fast;
  63. } intel_p2_t;
  64. #define INTEL_P2_NUM 2
  65. typedef struct intel_limit intel_limit_t;
  66. struct intel_limit {
  67. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  68. intel_p2_t p2;
  69. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  70. int, int, intel_clock_t *, intel_clock_t *);
  71. };
  72. /* FDI */
  73. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  74. static bool
  75. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  76. int target, int refclk, intel_clock_t *match_clock,
  77. intel_clock_t *best_clock);
  78. static bool
  79. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  80. int target, int refclk, intel_clock_t *match_clock,
  81. intel_clock_t *best_clock);
  82. static bool
  83. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  84. int target, int refclk, intel_clock_t *match_clock,
  85. intel_clock_t *best_clock);
  86. static bool
  87. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  88. int target, int refclk, intel_clock_t *match_clock,
  89. intel_clock_t *best_clock);
  90. static bool
  91. intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
  92. int target, int refclk, intel_clock_t *match_clock,
  93. intel_clock_t *best_clock);
  94. static inline u32 /* units of 100MHz */
  95. intel_fdi_link_freq(struct drm_device *dev)
  96. {
  97. if (IS_GEN5(dev)) {
  98. struct drm_i915_private *dev_priv = dev->dev_private;
  99. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  100. } else
  101. return 27;
  102. }
  103. static const intel_limit_t intel_limits_i8xx_dvo = {
  104. .dot = { .min = 25000, .max = 350000 },
  105. .vco = { .min = 930000, .max = 1400000 },
  106. .n = { .min = 3, .max = 16 },
  107. .m = { .min = 96, .max = 140 },
  108. .m1 = { .min = 18, .max = 26 },
  109. .m2 = { .min = 6, .max = 16 },
  110. .p = { .min = 4, .max = 128 },
  111. .p1 = { .min = 2, .max = 33 },
  112. .p2 = { .dot_limit = 165000,
  113. .p2_slow = 4, .p2_fast = 2 },
  114. .find_pll = intel_find_best_PLL,
  115. };
  116. static const intel_limit_t intel_limits_i8xx_lvds = {
  117. .dot = { .min = 25000, .max = 350000 },
  118. .vco = { .min = 930000, .max = 1400000 },
  119. .n = { .min = 3, .max = 16 },
  120. .m = { .min = 96, .max = 140 },
  121. .m1 = { .min = 18, .max = 26 },
  122. .m2 = { .min = 6, .max = 16 },
  123. .p = { .min = 4, .max = 128 },
  124. .p1 = { .min = 1, .max = 6 },
  125. .p2 = { .dot_limit = 165000,
  126. .p2_slow = 14, .p2_fast = 7 },
  127. .find_pll = intel_find_best_PLL,
  128. };
  129. static const intel_limit_t intel_limits_i9xx_sdvo = {
  130. .dot = { .min = 20000, .max = 400000 },
  131. .vco = { .min = 1400000, .max = 2800000 },
  132. .n = { .min = 1, .max = 6 },
  133. .m = { .min = 70, .max = 120 },
  134. .m1 = { .min = 10, .max = 22 },
  135. .m2 = { .min = 5, .max = 9 },
  136. .p = { .min = 5, .max = 80 },
  137. .p1 = { .min = 1, .max = 8 },
  138. .p2 = { .dot_limit = 200000,
  139. .p2_slow = 10, .p2_fast = 5 },
  140. .find_pll = intel_find_best_PLL,
  141. };
  142. static const intel_limit_t intel_limits_i9xx_lvds = {
  143. .dot = { .min = 20000, .max = 400000 },
  144. .vco = { .min = 1400000, .max = 2800000 },
  145. .n = { .min = 1, .max = 6 },
  146. .m = { .min = 70, .max = 120 },
  147. .m1 = { .min = 10, .max = 22 },
  148. .m2 = { .min = 5, .max = 9 },
  149. .p = { .min = 7, .max = 98 },
  150. .p1 = { .min = 1, .max = 8 },
  151. .p2 = { .dot_limit = 112000,
  152. .p2_slow = 14, .p2_fast = 7 },
  153. .find_pll = intel_find_best_PLL,
  154. };
  155. static const intel_limit_t intel_limits_g4x_sdvo = {
  156. .dot = { .min = 25000, .max = 270000 },
  157. .vco = { .min = 1750000, .max = 3500000},
  158. .n = { .min = 1, .max = 4 },
  159. .m = { .min = 104, .max = 138 },
  160. .m1 = { .min = 17, .max = 23 },
  161. .m2 = { .min = 5, .max = 11 },
  162. .p = { .min = 10, .max = 30 },
  163. .p1 = { .min = 1, .max = 3},
  164. .p2 = { .dot_limit = 270000,
  165. .p2_slow = 10,
  166. .p2_fast = 10
  167. },
  168. .find_pll = intel_g4x_find_best_PLL,
  169. };
  170. static const intel_limit_t intel_limits_g4x_hdmi = {
  171. .dot = { .min = 22000, .max = 400000 },
  172. .vco = { .min = 1750000, .max = 3500000},
  173. .n = { .min = 1, .max = 4 },
  174. .m = { .min = 104, .max = 138 },
  175. .m1 = { .min = 16, .max = 23 },
  176. .m2 = { .min = 5, .max = 11 },
  177. .p = { .min = 5, .max = 80 },
  178. .p1 = { .min = 1, .max = 8},
  179. .p2 = { .dot_limit = 165000,
  180. .p2_slow = 10, .p2_fast = 5 },
  181. .find_pll = intel_g4x_find_best_PLL,
  182. };
  183. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  184. .dot = { .min = 20000, .max = 115000 },
  185. .vco = { .min = 1750000, .max = 3500000 },
  186. .n = { .min = 1, .max = 3 },
  187. .m = { .min = 104, .max = 138 },
  188. .m1 = { .min = 17, .max = 23 },
  189. .m2 = { .min = 5, .max = 11 },
  190. .p = { .min = 28, .max = 112 },
  191. .p1 = { .min = 2, .max = 8 },
  192. .p2 = { .dot_limit = 0,
  193. .p2_slow = 14, .p2_fast = 14
  194. },
  195. .find_pll = intel_g4x_find_best_PLL,
  196. };
  197. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  198. .dot = { .min = 80000, .max = 224000 },
  199. .vco = { .min = 1750000, .max = 3500000 },
  200. .n = { .min = 1, .max = 3 },
  201. .m = { .min = 104, .max = 138 },
  202. .m1 = { .min = 17, .max = 23 },
  203. .m2 = { .min = 5, .max = 11 },
  204. .p = { .min = 14, .max = 42 },
  205. .p1 = { .min = 2, .max = 6 },
  206. .p2 = { .dot_limit = 0,
  207. .p2_slow = 7, .p2_fast = 7
  208. },
  209. .find_pll = intel_g4x_find_best_PLL,
  210. };
  211. static const intel_limit_t intel_limits_g4x_display_port = {
  212. .dot = { .min = 161670, .max = 227000 },
  213. .vco = { .min = 1750000, .max = 3500000},
  214. .n = { .min = 1, .max = 2 },
  215. .m = { .min = 97, .max = 108 },
  216. .m1 = { .min = 0x10, .max = 0x12 },
  217. .m2 = { .min = 0x05, .max = 0x06 },
  218. .p = { .min = 10, .max = 20 },
  219. .p1 = { .min = 1, .max = 2},
  220. .p2 = { .dot_limit = 0,
  221. .p2_slow = 10, .p2_fast = 10 },
  222. .find_pll = intel_find_pll_g4x_dp,
  223. };
  224. static const intel_limit_t intel_limits_pineview_sdvo = {
  225. .dot = { .min = 20000, .max = 400000},
  226. .vco = { .min = 1700000, .max = 3500000 },
  227. /* Pineview's Ncounter is a ring counter */
  228. .n = { .min = 3, .max = 6 },
  229. .m = { .min = 2, .max = 256 },
  230. /* Pineview only has one combined m divider, which we treat as m2. */
  231. .m1 = { .min = 0, .max = 0 },
  232. .m2 = { .min = 0, .max = 254 },
  233. .p = { .min = 5, .max = 80 },
  234. .p1 = { .min = 1, .max = 8 },
  235. .p2 = { .dot_limit = 200000,
  236. .p2_slow = 10, .p2_fast = 5 },
  237. .find_pll = intel_find_best_PLL,
  238. };
  239. static const intel_limit_t intel_limits_pineview_lvds = {
  240. .dot = { .min = 20000, .max = 400000 },
  241. .vco = { .min = 1700000, .max = 3500000 },
  242. .n = { .min = 3, .max = 6 },
  243. .m = { .min = 2, .max = 256 },
  244. .m1 = { .min = 0, .max = 0 },
  245. .m2 = { .min = 0, .max = 254 },
  246. .p = { .min = 7, .max = 112 },
  247. .p1 = { .min = 1, .max = 8 },
  248. .p2 = { .dot_limit = 112000,
  249. .p2_slow = 14, .p2_fast = 14 },
  250. .find_pll = intel_find_best_PLL,
  251. };
  252. /* Ironlake / Sandybridge
  253. *
  254. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  255. * the range value for them is (actual_value - 2).
  256. */
  257. static const intel_limit_t intel_limits_ironlake_dac = {
  258. .dot = { .min = 25000, .max = 350000 },
  259. .vco = { .min = 1760000, .max = 3510000 },
  260. .n = { .min = 1, .max = 5 },
  261. .m = { .min = 79, .max = 127 },
  262. .m1 = { .min = 12, .max = 22 },
  263. .m2 = { .min = 5, .max = 9 },
  264. .p = { .min = 5, .max = 80 },
  265. .p1 = { .min = 1, .max = 8 },
  266. .p2 = { .dot_limit = 225000,
  267. .p2_slow = 10, .p2_fast = 5 },
  268. .find_pll = intel_g4x_find_best_PLL,
  269. };
  270. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  271. .dot = { .min = 25000, .max = 350000 },
  272. .vco = { .min = 1760000, .max = 3510000 },
  273. .n = { .min = 1, .max = 3 },
  274. .m = { .min = 79, .max = 118 },
  275. .m1 = { .min = 12, .max = 22 },
  276. .m2 = { .min = 5, .max = 9 },
  277. .p = { .min = 28, .max = 112 },
  278. .p1 = { .min = 2, .max = 8 },
  279. .p2 = { .dot_limit = 225000,
  280. .p2_slow = 14, .p2_fast = 14 },
  281. .find_pll = intel_g4x_find_best_PLL,
  282. };
  283. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  284. .dot = { .min = 25000, .max = 350000 },
  285. .vco = { .min = 1760000, .max = 3510000 },
  286. .n = { .min = 1, .max = 3 },
  287. .m = { .min = 79, .max = 127 },
  288. .m1 = { .min = 12, .max = 22 },
  289. .m2 = { .min = 5, .max = 9 },
  290. .p = { .min = 14, .max = 56 },
  291. .p1 = { .min = 2, .max = 8 },
  292. .p2 = { .dot_limit = 225000,
  293. .p2_slow = 7, .p2_fast = 7 },
  294. .find_pll = intel_g4x_find_best_PLL,
  295. };
  296. /* LVDS 100mhz refclk limits. */
  297. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  298. .dot = { .min = 25000, .max = 350000 },
  299. .vco = { .min = 1760000, .max = 3510000 },
  300. .n = { .min = 1, .max = 2 },
  301. .m = { .min = 79, .max = 126 },
  302. .m1 = { .min = 12, .max = 22 },
  303. .m2 = { .min = 5, .max = 9 },
  304. .p = { .min = 28, .max = 112 },
  305. .p1 = { .min = 2, .max = 8 },
  306. .p2 = { .dot_limit = 225000,
  307. .p2_slow = 14, .p2_fast = 14 },
  308. .find_pll = intel_g4x_find_best_PLL,
  309. };
  310. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  311. .dot = { .min = 25000, .max = 350000 },
  312. .vco = { .min = 1760000, .max = 3510000 },
  313. .n = { .min = 1, .max = 3 },
  314. .m = { .min = 79, .max = 126 },
  315. .m1 = { .min = 12, .max = 22 },
  316. .m2 = { .min = 5, .max = 9 },
  317. .p = { .min = 14, .max = 42 },
  318. .p1 = { .min = 2, .max = 6 },
  319. .p2 = { .dot_limit = 225000,
  320. .p2_slow = 7, .p2_fast = 7 },
  321. .find_pll = intel_g4x_find_best_PLL,
  322. };
  323. static const intel_limit_t intel_limits_ironlake_display_port = {
  324. .dot = { .min = 25000, .max = 350000 },
  325. .vco = { .min = 1760000, .max = 3510000},
  326. .n = { .min = 1, .max = 2 },
  327. .m = { .min = 81, .max = 90 },
  328. .m1 = { .min = 12, .max = 22 },
  329. .m2 = { .min = 5, .max = 9 },
  330. .p = { .min = 10, .max = 20 },
  331. .p1 = { .min = 1, .max = 2},
  332. .p2 = { .dot_limit = 0,
  333. .p2_slow = 10, .p2_fast = 10 },
  334. .find_pll = intel_find_pll_ironlake_dp,
  335. };
  336. static const intel_limit_t intel_limits_vlv_dac = {
  337. .dot = { .min = 25000, .max = 270000 },
  338. .vco = { .min = 4000000, .max = 6000000 },
  339. .n = { .min = 1, .max = 7 },
  340. .m = { .min = 22, .max = 450 }, /* guess */
  341. .m1 = { .min = 2, .max = 3 },
  342. .m2 = { .min = 11, .max = 156 },
  343. .p = { .min = 10, .max = 30 },
  344. .p1 = { .min = 2, .max = 3 },
  345. .p2 = { .dot_limit = 270000,
  346. .p2_slow = 2, .p2_fast = 20 },
  347. .find_pll = intel_vlv_find_best_pll,
  348. };
  349. static const intel_limit_t intel_limits_vlv_hdmi = {
  350. .dot = { .min = 20000, .max = 165000 },
  351. .vco = { .min = 5994000, .max = 4000000 },
  352. .n = { .min = 1, .max = 7 },
  353. .m = { .min = 60, .max = 300 }, /* guess */
  354. .m1 = { .min = 2, .max = 3 },
  355. .m2 = { .min = 11, .max = 156 },
  356. .p = { .min = 10, .max = 30 },
  357. .p1 = { .min = 2, .max = 3 },
  358. .p2 = { .dot_limit = 270000,
  359. .p2_slow = 2, .p2_fast = 20 },
  360. .find_pll = intel_vlv_find_best_pll,
  361. };
  362. static const intel_limit_t intel_limits_vlv_dp = {
  363. .dot = { .min = 162000, .max = 270000 },
  364. .vco = { .min = 5994000, .max = 4000000 },
  365. .n = { .min = 1, .max = 7 },
  366. .m = { .min = 60, .max = 300 }, /* guess */
  367. .m1 = { .min = 2, .max = 3 },
  368. .m2 = { .min = 11, .max = 156 },
  369. .p = { .min = 10, .max = 30 },
  370. .p1 = { .min = 2, .max = 3 },
  371. .p2 = { .dot_limit = 270000,
  372. .p2_slow = 2, .p2_fast = 20 },
  373. .find_pll = intel_vlv_find_best_pll,
  374. };
  375. u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
  376. {
  377. unsigned long flags;
  378. u32 val = 0;
  379. spin_lock_irqsave(&dev_priv->dpio_lock, flags);
  380. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  381. DRM_ERROR("DPIO idle wait timed out\n");
  382. goto out_unlock;
  383. }
  384. I915_WRITE(DPIO_REG, reg);
  385. I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
  386. DPIO_BYTE);
  387. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  388. DRM_ERROR("DPIO read wait timed out\n");
  389. goto out_unlock;
  390. }
  391. val = I915_READ(DPIO_DATA);
  392. out_unlock:
  393. spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
  394. return val;
  395. }
  396. static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
  397. u32 val)
  398. {
  399. unsigned long flags;
  400. spin_lock_irqsave(&dev_priv->dpio_lock, flags);
  401. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  402. DRM_ERROR("DPIO idle wait timed out\n");
  403. goto out_unlock;
  404. }
  405. I915_WRITE(DPIO_DATA, val);
  406. I915_WRITE(DPIO_REG, reg);
  407. I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
  408. DPIO_BYTE);
  409. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
  410. DRM_ERROR("DPIO write wait timed out\n");
  411. out_unlock:
  412. spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
  413. }
  414. static void vlv_init_dpio(struct drm_device *dev)
  415. {
  416. struct drm_i915_private *dev_priv = dev->dev_private;
  417. /* Reset the DPIO config */
  418. I915_WRITE(DPIO_CTL, 0);
  419. POSTING_READ(DPIO_CTL);
  420. I915_WRITE(DPIO_CTL, 1);
  421. POSTING_READ(DPIO_CTL);
  422. }
  423. static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
  424. {
  425. DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
  426. return 1;
  427. }
  428. static const struct dmi_system_id intel_dual_link_lvds[] = {
  429. {
  430. .callback = intel_dual_link_lvds_callback,
  431. .ident = "Apple MacBook Pro (Core i5/i7 Series)",
  432. .matches = {
  433. DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
  434. DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
  435. },
  436. },
  437. { } /* terminating entry */
  438. };
  439. static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
  440. unsigned int reg)
  441. {
  442. unsigned int val;
  443. /* use the module option value if specified */
  444. if (i915_lvds_channel_mode > 0)
  445. return i915_lvds_channel_mode == 2;
  446. if (dmi_check_system(intel_dual_link_lvds))
  447. return true;
  448. if (dev_priv->lvds_val)
  449. val = dev_priv->lvds_val;
  450. else {
  451. /* BIOS should set the proper LVDS register value at boot, but
  452. * in reality, it doesn't set the value when the lid is closed;
  453. * we need to check "the value to be set" in VBT when LVDS
  454. * register is uninitialized.
  455. */
  456. val = I915_READ(reg);
  457. if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
  458. val = dev_priv->bios_lvds_val;
  459. dev_priv->lvds_val = val;
  460. }
  461. return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
  462. }
  463. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  464. int refclk)
  465. {
  466. struct drm_device *dev = crtc->dev;
  467. struct drm_i915_private *dev_priv = dev->dev_private;
  468. const intel_limit_t *limit;
  469. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  470. if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
  471. /* LVDS dual channel */
  472. if (refclk == 100000)
  473. limit = &intel_limits_ironlake_dual_lvds_100m;
  474. else
  475. limit = &intel_limits_ironlake_dual_lvds;
  476. } else {
  477. if (refclk == 100000)
  478. limit = &intel_limits_ironlake_single_lvds_100m;
  479. else
  480. limit = &intel_limits_ironlake_single_lvds;
  481. }
  482. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  483. HAS_eDP)
  484. limit = &intel_limits_ironlake_display_port;
  485. else
  486. limit = &intel_limits_ironlake_dac;
  487. return limit;
  488. }
  489. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  490. {
  491. struct drm_device *dev = crtc->dev;
  492. struct drm_i915_private *dev_priv = dev->dev_private;
  493. const intel_limit_t *limit;
  494. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  495. if (is_dual_link_lvds(dev_priv, LVDS))
  496. /* LVDS with dual channel */
  497. limit = &intel_limits_g4x_dual_channel_lvds;
  498. else
  499. /* LVDS with dual channel */
  500. limit = &intel_limits_g4x_single_channel_lvds;
  501. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  502. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  503. limit = &intel_limits_g4x_hdmi;
  504. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  505. limit = &intel_limits_g4x_sdvo;
  506. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  507. limit = &intel_limits_g4x_display_port;
  508. } else /* The option is for other outputs */
  509. limit = &intel_limits_i9xx_sdvo;
  510. return limit;
  511. }
  512. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  513. {
  514. struct drm_device *dev = crtc->dev;
  515. const intel_limit_t *limit;
  516. if (HAS_PCH_SPLIT(dev))
  517. limit = intel_ironlake_limit(crtc, refclk);
  518. else if (IS_G4X(dev)) {
  519. limit = intel_g4x_limit(crtc);
  520. } else if (IS_PINEVIEW(dev)) {
  521. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  522. limit = &intel_limits_pineview_lvds;
  523. else
  524. limit = &intel_limits_pineview_sdvo;
  525. } else if (IS_VALLEYVIEW(dev)) {
  526. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
  527. limit = &intel_limits_vlv_dac;
  528. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  529. limit = &intel_limits_vlv_hdmi;
  530. else
  531. limit = &intel_limits_vlv_dp;
  532. } else if (!IS_GEN2(dev)) {
  533. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  534. limit = &intel_limits_i9xx_lvds;
  535. else
  536. limit = &intel_limits_i9xx_sdvo;
  537. } else {
  538. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  539. limit = &intel_limits_i8xx_lvds;
  540. else
  541. limit = &intel_limits_i8xx_dvo;
  542. }
  543. return limit;
  544. }
  545. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  546. static void pineview_clock(int refclk, intel_clock_t *clock)
  547. {
  548. clock->m = clock->m2 + 2;
  549. clock->p = clock->p1 * clock->p2;
  550. clock->vco = refclk * clock->m / clock->n;
  551. clock->dot = clock->vco / clock->p;
  552. }
  553. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  554. {
  555. if (IS_PINEVIEW(dev)) {
  556. pineview_clock(refclk, clock);
  557. return;
  558. }
  559. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  560. clock->p = clock->p1 * clock->p2;
  561. clock->vco = refclk * clock->m / (clock->n + 2);
  562. clock->dot = clock->vco / clock->p;
  563. }
  564. /**
  565. * Returns whether any output on the specified pipe is of the specified type
  566. */
  567. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  568. {
  569. struct drm_device *dev = crtc->dev;
  570. struct intel_encoder *encoder;
  571. for_each_encoder_on_crtc(dev, crtc, encoder)
  572. if (encoder->type == type)
  573. return true;
  574. return false;
  575. }
  576. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  577. /**
  578. * Returns whether the given set of divisors are valid for a given refclk with
  579. * the given connectors.
  580. */
  581. static bool intel_PLL_is_valid(struct drm_device *dev,
  582. const intel_limit_t *limit,
  583. const intel_clock_t *clock)
  584. {
  585. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  586. INTELPllInvalid("p1 out of range\n");
  587. if (clock->p < limit->p.min || limit->p.max < clock->p)
  588. INTELPllInvalid("p out of range\n");
  589. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  590. INTELPllInvalid("m2 out of range\n");
  591. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  592. INTELPllInvalid("m1 out of range\n");
  593. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  594. INTELPllInvalid("m1 <= m2\n");
  595. if (clock->m < limit->m.min || limit->m.max < clock->m)
  596. INTELPllInvalid("m out of range\n");
  597. if (clock->n < limit->n.min || limit->n.max < clock->n)
  598. INTELPllInvalid("n out of range\n");
  599. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  600. INTELPllInvalid("vco out of range\n");
  601. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  602. * connector, etc., rather than just a single range.
  603. */
  604. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  605. INTELPllInvalid("dot out of range\n");
  606. return true;
  607. }
  608. static bool
  609. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  610. int target, int refclk, intel_clock_t *match_clock,
  611. intel_clock_t *best_clock)
  612. {
  613. struct drm_device *dev = crtc->dev;
  614. struct drm_i915_private *dev_priv = dev->dev_private;
  615. intel_clock_t clock;
  616. int err = target;
  617. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  618. (I915_READ(LVDS)) != 0) {
  619. /*
  620. * For LVDS, if the panel is on, just rely on its current
  621. * settings for dual-channel. We haven't figured out how to
  622. * reliably set up different single/dual channel state, if we
  623. * even can.
  624. */
  625. if (is_dual_link_lvds(dev_priv, LVDS))
  626. clock.p2 = limit->p2.p2_fast;
  627. else
  628. clock.p2 = limit->p2.p2_slow;
  629. } else {
  630. if (target < limit->p2.dot_limit)
  631. clock.p2 = limit->p2.p2_slow;
  632. else
  633. clock.p2 = limit->p2.p2_fast;
  634. }
  635. memset(best_clock, 0, sizeof(*best_clock));
  636. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  637. clock.m1++) {
  638. for (clock.m2 = limit->m2.min;
  639. clock.m2 <= limit->m2.max; clock.m2++) {
  640. /* m1 is always 0 in Pineview */
  641. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  642. break;
  643. for (clock.n = limit->n.min;
  644. clock.n <= limit->n.max; clock.n++) {
  645. for (clock.p1 = limit->p1.min;
  646. clock.p1 <= limit->p1.max; clock.p1++) {
  647. int this_err;
  648. intel_clock(dev, refclk, &clock);
  649. if (!intel_PLL_is_valid(dev, limit,
  650. &clock))
  651. continue;
  652. if (match_clock &&
  653. clock.p != match_clock->p)
  654. continue;
  655. this_err = abs(clock.dot - target);
  656. if (this_err < err) {
  657. *best_clock = clock;
  658. err = this_err;
  659. }
  660. }
  661. }
  662. }
  663. }
  664. return (err != target);
  665. }
  666. static bool
  667. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  668. int target, int refclk, intel_clock_t *match_clock,
  669. intel_clock_t *best_clock)
  670. {
  671. struct drm_device *dev = crtc->dev;
  672. struct drm_i915_private *dev_priv = dev->dev_private;
  673. intel_clock_t clock;
  674. int max_n;
  675. bool found;
  676. /* approximately equals target * 0.00585 */
  677. int err_most = (target >> 8) + (target >> 9);
  678. found = false;
  679. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  680. int lvds_reg;
  681. if (HAS_PCH_SPLIT(dev))
  682. lvds_reg = PCH_LVDS;
  683. else
  684. lvds_reg = LVDS;
  685. if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  686. LVDS_CLKB_POWER_UP)
  687. clock.p2 = limit->p2.p2_fast;
  688. else
  689. clock.p2 = limit->p2.p2_slow;
  690. } else {
  691. if (target < limit->p2.dot_limit)
  692. clock.p2 = limit->p2.p2_slow;
  693. else
  694. clock.p2 = limit->p2.p2_fast;
  695. }
  696. memset(best_clock, 0, sizeof(*best_clock));
  697. max_n = limit->n.max;
  698. /* based on hardware requirement, prefer smaller n to precision */
  699. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  700. /* based on hardware requirement, prefere larger m1,m2 */
  701. for (clock.m1 = limit->m1.max;
  702. clock.m1 >= limit->m1.min; clock.m1--) {
  703. for (clock.m2 = limit->m2.max;
  704. clock.m2 >= limit->m2.min; clock.m2--) {
  705. for (clock.p1 = limit->p1.max;
  706. clock.p1 >= limit->p1.min; clock.p1--) {
  707. int this_err;
  708. intel_clock(dev, refclk, &clock);
  709. if (!intel_PLL_is_valid(dev, limit,
  710. &clock))
  711. continue;
  712. if (match_clock &&
  713. clock.p != match_clock->p)
  714. continue;
  715. this_err = abs(clock.dot - target);
  716. if (this_err < err_most) {
  717. *best_clock = clock;
  718. err_most = this_err;
  719. max_n = clock.n;
  720. found = true;
  721. }
  722. }
  723. }
  724. }
  725. }
  726. return found;
  727. }
  728. static bool
  729. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  730. int target, int refclk, intel_clock_t *match_clock,
  731. intel_clock_t *best_clock)
  732. {
  733. struct drm_device *dev = crtc->dev;
  734. intel_clock_t clock;
  735. if (target < 200000) {
  736. clock.n = 1;
  737. clock.p1 = 2;
  738. clock.p2 = 10;
  739. clock.m1 = 12;
  740. clock.m2 = 9;
  741. } else {
  742. clock.n = 2;
  743. clock.p1 = 1;
  744. clock.p2 = 10;
  745. clock.m1 = 14;
  746. clock.m2 = 8;
  747. }
  748. intel_clock(dev, refclk, &clock);
  749. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  750. return true;
  751. }
  752. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  753. static bool
  754. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  755. int target, int refclk, intel_clock_t *match_clock,
  756. intel_clock_t *best_clock)
  757. {
  758. intel_clock_t clock;
  759. if (target < 200000) {
  760. clock.p1 = 2;
  761. clock.p2 = 10;
  762. clock.n = 2;
  763. clock.m1 = 23;
  764. clock.m2 = 8;
  765. } else {
  766. clock.p1 = 1;
  767. clock.p2 = 10;
  768. clock.n = 1;
  769. clock.m1 = 14;
  770. clock.m2 = 2;
  771. }
  772. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  773. clock.p = (clock.p1 * clock.p2);
  774. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  775. clock.vco = 0;
  776. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  777. return true;
  778. }
  779. static bool
  780. intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
  781. int target, int refclk, intel_clock_t *match_clock,
  782. intel_clock_t *best_clock)
  783. {
  784. u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
  785. u32 m, n, fastclk;
  786. u32 updrate, minupdate, fracbits, p;
  787. unsigned long bestppm, ppm, absppm;
  788. int dotclk, flag;
  789. flag = 0;
  790. dotclk = target * 1000;
  791. bestppm = 1000000;
  792. ppm = absppm = 0;
  793. fastclk = dotclk / (2*100);
  794. updrate = 0;
  795. minupdate = 19200;
  796. fracbits = 1;
  797. n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
  798. bestm1 = bestm2 = bestp1 = bestp2 = 0;
  799. /* based on hardware requirement, prefer smaller n to precision */
  800. for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
  801. updrate = refclk / n;
  802. for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
  803. for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
  804. if (p2 > 10)
  805. p2 = p2 - 1;
  806. p = p1 * p2;
  807. /* based on hardware requirement, prefer bigger m1,m2 values */
  808. for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
  809. m2 = (((2*(fastclk * p * n / m1 )) +
  810. refclk) / (2*refclk));
  811. m = m1 * m2;
  812. vco = updrate * m;
  813. if (vco >= limit->vco.min && vco < limit->vco.max) {
  814. ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
  815. absppm = (ppm > 0) ? ppm : (-ppm);
  816. if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
  817. bestppm = 0;
  818. flag = 1;
  819. }
  820. if (absppm < bestppm - 10) {
  821. bestppm = absppm;
  822. flag = 1;
  823. }
  824. if (flag) {
  825. bestn = n;
  826. bestm1 = m1;
  827. bestm2 = m2;
  828. bestp1 = p1;
  829. bestp2 = p2;
  830. flag = 0;
  831. }
  832. }
  833. }
  834. }
  835. }
  836. }
  837. best_clock->n = bestn;
  838. best_clock->m1 = bestm1;
  839. best_clock->m2 = bestm2;
  840. best_clock->p1 = bestp1;
  841. best_clock->p2 = bestp2;
  842. return true;
  843. }
  844. static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
  845. {
  846. struct drm_i915_private *dev_priv = dev->dev_private;
  847. u32 frame, frame_reg = PIPEFRAME(pipe);
  848. frame = I915_READ(frame_reg);
  849. if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
  850. DRM_DEBUG_KMS("vblank wait timed out\n");
  851. }
  852. /**
  853. * intel_wait_for_vblank - wait for vblank on a given pipe
  854. * @dev: drm device
  855. * @pipe: pipe to wait for
  856. *
  857. * Wait for vblank to occur on a given pipe. Needed for various bits of
  858. * mode setting code.
  859. */
  860. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  861. {
  862. struct drm_i915_private *dev_priv = dev->dev_private;
  863. int pipestat_reg = PIPESTAT(pipe);
  864. if (INTEL_INFO(dev)->gen >= 5) {
  865. ironlake_wait_for_vblank(dev, pipe);
  866. return;
  867. }
  868. /* Clear existing vblank status. Note this will clear any other
  869. * sticky status fields as well.
  870. *
  871. * This races with i915_driver_irq_handler() with the result
  872. * that either function could miss a vblank event. Here it is not
  873. * fatal, as we will either wait upon the next vblank interrupt or
  874. * timeout. Generally speaking intel_wait_for_vblank() is only
  875. * called during modeset at which time the GPU should be idle and
  876. * should *not* be performing page flips and thus not waiting on
  877. * vblanks...
  878. * Currently, the result of us stealing a vblank from the irq
  879. * handler is that a single frame will be skipped during swapbuffers.
  880. */
  881. I915_WRITE(pipestat_reg,
  882. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  883. /* Wait for vblank interrupt bit to set */
  884. if (wait_for(I915_READ(pipestat_reg) &
  885. PIPE_VBLANK_INTERRUPT_STATUS,
  886. 50))
  887. DRM_DEBUG_KMS("vblank wait timed out\n");
  888. }
  889. /*
  890. * intel_wait_for_pipe_off - wait for pipe to turn off
  891. * @dev: drm device
  892. * @pipe: pipe to wait for
  893. *
  894. * After disabling a pipe, we can't wait for vblank in the usual way,
  895. * spinning on the vblank interrupt status bit, since we won't actually
  896. * see an interrupt when the pipe is disabled.
  897. *
  898. * On Gen4 and above:
  899. * wait for the pipe register state bit to turn off
  900. *
  901. * Otherwise:
  902. * wait for the display line value to settle (it usually
  903. * ends up stopping at the start of the next frame).
  904. *
  905. */
  906. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  907. {
  908. struct drm_i915_private *dev_priv = dev->dev_private;
  909. if (INTEL_INFO(dev)->gen >= 4) {
  910. int reg = PIPECONF(pipe);
  911. /* Wait for the Pipe State to go off */
  912. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  913. 100))
  914. WARN(1, "pipe_off wait timed out\n");
  915. } else {
  916. u32 last_line, line_mask;
  917. int reg = PIPEDSL(pipe);
  918. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  919. if (IS_GEN2(dev))
  920. line_mask = DSL_LINEMASK_GEN2;
  921. else
  922. line_mask = DSL_LINEMASK_GEN3;
  923. /* Wait for the display line to settle */
  924. do {
  925. last_line = I915_READ(reg) & line_mask;
  926. mdelay(5);
  927. } while (((I915_READ(reg) & line_mask) != last_line) &&
  928. time_after(timeout, jiffies));
  929. if (time_after(jiffies, timeout))
  930. WARN(1, "pipe_off wait timed out\n");
  931. }
  932. }
  933. static const char *state_string(bool enabled)
  934. {
  935. return enabled ? "on" : "off";
  936. }
  937. /* Only for pre-ILK configs */
  938. static void assert_pll(struct drm_i915_private *dev_priv,
  939. enum pipe pipe, bool state)
  940. {
  941. int reg;
  942. u32 val;
  943. bool cur_state;
  944. reg = DPLL(pipe);
  945. val = I915_READ(reg);
  946. cur_state = !!(val & DPLL_VCO_ENABLE);
  947. WARN(cur_state != state,
  948. "PLL state assertion failure (expected %s, current %s)\n",
  949. state_string(state), state_string(cur_state));
  950. }
  951. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  952. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  953. /* For ILK+ */
  954. static void assert_pch_pll(struct drm_i915_private *dev_priv,
  955. struct intel_pch_pll *pll,
  956. struct intel_crtc *crtc,
  957. bool state)
  958. {
  959. u32 val;
  960. bool cur_state;
  961. if (HAS_PCH_LPT(dev_priv->dev)) {
  962. DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
  963. return;
  964. }
  965. if (WARN (!pll,
  966. "asserting PCH PLL %s with no PLL\n", state_string(state)))
  967. return;
  968. val = I915_READ(pll->pll_reg);
  969. cur_state = !!(val & DPLL_VCO_ENABLE);
  970. WARN(cur_state != state,
  971. "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
  972. pll->pll_reg, state_string(state), state_string(cur_state), val);
  973. /* Make sure the selected PLL is correctly attached to the transcoder */
  974. if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
  975. u32 pch_dpll;
  976. pch_dpll = I915_READ(PCH_DPLL_SEL);
  977. cur_state = pll->pll_reg == _PCH_DPLL_B;
  978. if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
  979. "PLL[%d] not attached to this transcoder %d: %08x\n",
  980. cur_state, crtc->pipe, pch_dpll)) {
  981. cur_state = !!(val >> (4*crtc->pipe + 3));
  982. WARN(cur_state != state,
  983. "PLL[%d] not %s on this transcoder %d: %08x\n",
  984. pll->pll_reg == _PCH_DPLL_B,
  985. state_string(state),
  986. crtc->pipe,
  987. val);
  988. }
  989. }
  990. }
  991. #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
  992. #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
  993. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  994. enum pipe pipe, bool state)
  995. {
  996. int reg;
  997. u32 val;
  998. bool cur_state;
  999. if (IS_HASWELL(dev_priv->dev)) {
  1000. /* On Haswell, DDI is used instead of FDI_TX_CTL */
  1001. reg = DDI_FUNC_CTL(pipe);
  1002. val = I915_READ(reg);
  1003. cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
  1004. } else {
  1005. reg = FDI_TX_CTL(pipe);
  1006. val = I915_READ(reg);
  1007. cur_state = !!(val & FDI_TX_ENABLE);
  1008. }
  1009. WARN(cur_state != state,
  1010. "FDI TX state assertion failure (expected %s, current %s)\n",
  1011. state_string(state), state_string(cur_state));
  1012. }
  1013. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  1014. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  1015. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  1016. enum pipe pipe, bool state)
  1017. {
  1018. int reg;
  1019. u32 val;
  1020. bool cur_state;
  1021. if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
  1022. DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
  1023. return;
  1024. } else {
  1025. reg = FDI_RX_CTL(pipe);
  1026. val = I915_READ(reg);
  1027. cur_state = !!(val & FDI_RX_ENABLE);
  1028. }
  1029. WARN(cur_state != state,
  1030. "FDI RX state assertion failure (expected %s, current %s)\n",
  1031. state_string(state), state_string(cur_state));
  1032. }
  1033. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  1034. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  1035. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  1036. enum pipe pipe)
  1037. {
  1038. int reg;
  1039. u32 val;
  1040. /* ILK FDI PLL is always enabled */
  1041. if (dev_priv->info->gen == 5)
  1042. return;
  1043. /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  1044. if (IS_HASWELL(dev_priv->dev))
  1045. return;
  1046. reg = FDI_TX_CTL(pipe);
  1047. val = I915_READ(reg);
  1048. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  1049. }
  1050. static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
  1051. enum pipe pipe)
  1052. {
  1053. int reg;
  1054. u32 val;
  1055. if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
  1056. DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
  1057. return;
  1058. }
  1059. reg = FDI_RX_CTL(pipe);
  1060. val = I915_READ(reg);
  1061. WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
  1062. }
  1063. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  1064. enum pipe pipe)
  1065. {
  1066. int pp_reg, lvds_reg;
  1067. u32 val;
  1068. enum pipe panel_pipe = PIPE_A;
  1069. bool locked = true;
  1070. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  1071. pp_reg = PCH_PP_CONTROL;
  1072. lvds_reg = PCH_LVDS;
  1073. } else {
  1074. pp_reg = PP_CONTROL;
  1075. lvds_reg = LVDS;
  1076. }
  1077. val = I915_READ(pp_reg);
  1078. if (!(val & PANEL_POWER_ON) ||
  1079. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  1080. locked = false;
  1081. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  1082. panel_pipe = PIPE_B;
  1083. WARN(panel_pipe == pipe && locked,
  1084. "panel assertion failure, pipe %c regs locked\n",
  1085. pipe_name(pipe));
  1086. }
  1087. void assert_pipe(struct drm_i915_private *dev_priv,
  1088. enum pipe pipe, bool state)
  1089. {
  1090. int reg;
  1091. u32 val;
  1092. bool cur_state;
  1093. /* if we need the pipe A quirk it must be always on */
  1094. if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  1095. state = true;
  1096. reg = PIPECONF(pipe);
  1097. val = I915_READ(reg);
  1098. cur_state = !!(val & PIPECONF_ENABLE);
  1099. WARN(cur_state != state,
  1100. "pipe %c assertion failure (expected %s, current %s)\n",
  1101. pipe_name(pipe), state_string(state), state_string(cur_state));
  1102. }
  1103. static void assert_plane(struct drm_i915_private *dev_priv,
  1104. enum plane plane, bool state)
  1105. {
  1106. int reg;
  1107. u32 val;
  1108. bool cur_state;
  1109. reg = DSPCNTR(plane);
  1110. val = I915_READ(reg);
  1111. cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1112. WARN(cur_state != state,
  1113. "plane %c assertion failure (expected %s, current %s)\n",
  1114. plane_name(plane), state_string(state), state_string(cur_state));
  1115. }
  1116. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1117. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1118. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1119. enum pipe pipe)
  1120. {
  1121. int reg, i;
  1122. u32 val;
  1123. int cur_pipe;
  1124. /* Planes are fixed to pipes on ILK+ */
  1125. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  1126. reg = DSPCNTR(pipe);
  1127. val = I915_READ(reg);
  1128. WARN((val & DISPLAY_PLANE_ENABLE),
  1129. "plane %c assertion failure, should be disabled but not\n",
  1130. plane_name(pipe));
  1131. return;
  1132. }
  1133. /* Need to check both planes against the pipe */
  1134. for (i = 0; i < 2; i++) {
  1135. reg = DSPCNTR(i);
  1136. val = I915_READ(reg);
  1137. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1138. DISPPLANE_SEL_PIPE_SHIFT;
  1139. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1140. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1141. plane_name(i), pipe_name(pipe));
  1142. }
  1143. }
  1144. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1145. {
  1146. u32 val;
  1147. bool enabled;
  1148. if (HAS_PCH_LPT(dev_priv->dev)) {
  1149. DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
  1150. return;
  1151. }
  1152. val = I915_READ(PCH_DREF_CONTROL);
  1153. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1154. DREF_SUPERSPREAD_SOURCE_MASK));
  1155. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1156. }
  1157. static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
  1158. enum pipe pipe)
  1159. {
  1160. int reg;
  1161. u32 val;
  1162. bool enabled;
  1163. reg = TRANSCONF(pipe);
  1164. val = I915_READ(reg);
  1165. enabled = !!(val & TRANS_ENABLE);
  1166. WARN(enabled,
  1167. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1168. pipe_name(pipe));
  1169. }
  1170. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1171. enum pipe pipe, u32 port_sel, u32 val)
  1172. {
  1173. if ((val & DP_PORT_EN) == 0)
  1174. return false;
  1175. if (HAS_PCH_CPT(dev_priv->dev)) {
  1176. u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1177. u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1178. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1179. return false;
  1180. } else {
  1181. if ((val & DP_PIPE_MASK) != (pipe << 30))
  1182. return false;
  1183. }
  1184. return true;
  1185. }
  1186. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1187. enum pipe pipe, u32 val)
  1188. {
  1189. if ((val & PORT_ENABLE) == 0)
  1190. return false;
  1191. if (HAS_PCH_CPT(dev_priv->dev)) {
  1192. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1193. return false;
  1194. } else {
  1195. if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
  1196. return false;
  1197. }
  1198. return true;
  1199. }
  1200. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1201. enum pipe pipe, u32 val)
  1202. {
  1203. if ((val & LVDS_PORT_EN) == 0)
  1204. return false;
  1205. if (HAS_PCH_CPT(dev_priv->dev)) {
  1206. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1207. return false;
  1208. } else {
  1209. if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1210. return false;
  1211. }
  1212. return true;
  1213. }
  1214. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1215. enum pipe pipe, u32 val)
  1216. {
  1217. if ((val & ADPA_DAC_ENABLE) == 0)
  1218. return false;
  1219. if (HAS_PCH_CPT(dev_priv->dev)) {
  1220. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1221. return false;
  1222. } else {
  1223. if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1224. return false;
  1225. }
  1226. return true;
  1227. }
  1228. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1229. enum pipe pipe, int reg, u32 port_sel)
  1230. {
  1231. u32 val = I915_READ(reg);
  1232. WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1233. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1234. reg, pipe_name(pipe));
  1235. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
  1236. "IBX PCH dp port still using transcoder B\n");
  1237. }
  1238. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1239. enum pipe pipe, int reg)
  1240. {
  1241. u32 val = I915_READ(reg);
  1242. WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1243. "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1244. reg, pipe_name(pipe));
  1245. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
  1246. "IBX PCH hdmi port still using transcoder B\n");
  1247. }
  1248. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1249. enum pipe pipe)
  1250. {
  1251. int reg;
  1252. u32 val;
  1253. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1254. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1255. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1256. reg = PCH_ADPA;
  1257. val = I915_READ(reg);
  1258. WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1259. "PCH VGA enabled on transcoder %c, should be disabled\n",
  1260. pipe_name(pipe));
  1261. reg = PCH_LVDS;
  1262. val = I915_READ(reg);
  1263. WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1264. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1265. pipe_name(pipe));
  1266. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
  1267. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
  1268. assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
  1269. }
  1270. /**
  1271. * intel_enable_pll - enable a PLL
  1272. * @dev_priv: i915 private structure
  1273. * @pipe: pipe PLL to enable
  1274. *
  1275. * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
  1276. * make sure the PLL reg is writable first though, since the panel write
  1277. * protect mechanism may be enabled.
  1278. *
  1279. * Note! This is for pre-ILK only.
  1280. *
  1281. * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
  1282. */
  1283. static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1284. {
  1285. int reg;
  1286. u32 val;
  1287. /* No really, not for ILK+ */
  1288. BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
  1289. /* PLL is protected by panel, make sure we can write it */
  1290. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1291. assert_panel_unlocked(dev_priv, pipe);
  1292. reg = DPLL(pipe);
  1293. val = I915_READ(reg);
  1294. val |= DPLL_VCO_ENABLE;
  1295. /* We do this three times for luck */
  1296. I915_WRITE(reg, val);
  1297. POSTING_READ(reg);
  1298. udelay(150); /* wait for warmup */
  1299. I915_WRITE(reg, val);
  1300. POSTING_READ(reg);
  1301. udelay(150); /* wait for warmup */
  1302. I915_WRITE(reg, val);
  1303. POSTING_READ(reg);
  1304. udelay(150); /* wait for warmup */
  1305. }
  1306. /**
  1307. * intel_disable_pll - disable a PLL
  1308. * @dev_priv: i915 private structure
  1309. * @pipe: pipe PLL to disable
  1310. *
  1311. * Disable the PLL for @pipe, making sure the pipe is off first.
  1312. *
  1313. * Note! This is for pre-ILK only.
  1314. */
  1315. static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1316. {
  1317. int reg;
  1318. u32 val;
  1319. /* Don't disable pipe A or pipe A PLLs if needed */
  1320. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1321. return;
  1322. /* Make sure the pipe isn't still relying on us */
  1323. assert_pipe_disabled(dev_priv, pipe);
  1324. reg = DPLL(pipe);
  1325. val = I915_READ(reg);
  1326. val &= ~DPLL_VCO_ENABLE;
  1327. I915_WRITE(reg, val);
  1328. POSTING_READ(reg);
  1329. }
  1330. /* SBI access */
  1331. static void
  1332. intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
  1333. {
  1334. unsigned long flags;
  1335. spin_lock_irqsave(&dev_priv->dpio_lock, flags);
  1336. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  1337. 100)) {
  1338. DRM_ERROR("timeout waiting for SBI to become ready\n");
  1339. goto out_unlock;
  1340. }
  1341. I915_WRITE(SBI_ADDR,
  1342. (reg << 16));
  1343. I915_WRITE(SBI_DATA,
  1344. value);
  1345. I915_WRITE(SBI_CTL_STAT,
  1346. SBI_BUSY |
  1347. SBI_CTL_OP_CRWR);
  1348. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  1349. 100)) {
  1350. DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
  1351. goto out_unlock;
  1352. }
  1353. out_unlock:
  1354. spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
  1355. }
  1356. static u32
  1357. intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
  1358. {
  1359. unsigned long flags;
  1360. u32 value = 0;
  1361. spin_lock_irqsave(&dev_priv->dpio_lock, flags);
  1362. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  1363. 100)) {
  1364. DRM_ERROR("timeout waiting for SBI to become ready\n");
  1365. goto out_unlock;
  1366. }
  1367. I915_WRITE(SBI_ADDR,
  1368. (reg << 16));
  1369. I915_WRITE(SBI_CTL_STAT,
  1370. SBI_BUSY |
  1371. SBI_CTL_OP_CRRD);
  1372. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  1373. 100)) {
  1374. DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
  1375. goto out_unlock;
  1376. }
  1377. value = I915_READ(SBI_DATA);
  1378. out_unlock:
  1379. spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
  1380. return value;
  1381. }
  1382. /**
  1383. * intel_enable_pch_pll - enable PCH PLL
  1384. * @dev_priv: i915 private structure
  1385. * @pipe: pipe PLL to enable
  1386. *
  1387. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1388. * drives the transcoder clock.
  1389. */
  1390. static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
  1391. {
  1392. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  1393. struct intel_pch_pll *pll;
  1394. int reg;
  1395. u32 val;
  1396. /* PCH PLLs only available on ILK, SNB and IVB */
  1397. BUG_ON(dev_priv->info->gen < 5);
  1398. pll = intel_crtc->pch_pll;
  1399. if (pll == NULL)
  1400. return;
  1401. if (WARN_ON(pll->refcount == 0))
  1402. return;
  1403. DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
  1404. pll->pll_reg, pll->active, pll->on,
  1405. intel_crtc->base.base.id);
  1406. /* PCH refclock must be enabled first */
  1407. assert_pch_refclk_enabled(dev_priv);
  1408. if (pll->active++ && pll->on) {
  1409. assert_pch_pll_enabled(dev_priv, pll, NULL);
  1410. return;
  1411. }
  1412. DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
  1413. reg = pll->pll_reg;
  1414. val = I915_READ(reg);
  1415. val |= DPLL_VCO_ENABLE;
  1416. I915_WRITE(reg, val);
  1417. POSTING_READ(reg);
  1418. udelay(200);
  1419. pll->on = true;
  1420. }
  1421. static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
  1422. {
  1423. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  1424. struct intel_pch_pll *pll = intel_crtc->pch_pll;
  1425. int reg;
  1426. u32 val;
  1427. /* PCH only available on ILK+ */
  1428. BUG_ON(dev_priv->info->gen < 5);
  1429. if (pll == NULL)
  1430. return;
  1431. if (WARN_ON(pll->refcount == 0))
  1432. return;
  1433. DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
  1434. pll->pll_reg, pll->active, pll->on,
  1435. intel_crtc->base.base.id);
  1436. if (WARN_ON(pll->active == 0)) {
  1437. assert_pch_pll_disabled(dev_priv, pll, NULL);
  1438. return;
  1439. }
  1440. if (--pll->active) {
  1441. assert_pch_pll_enabled(dev_priv, pll, NULL);
  1442. return;
  1443. }
  1444. DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
  1445. /* Make sure transcoder isn't still depending on us */
  1446. assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
  1447. reg = pll->pll_reg;
  1448. val = I915_READ(reg);
  1449. val &= ~DPLL_VCO_ENABLE;
  1450. I915_WRITE(reg, val);
  1451. POSTING_READ(reg);
  1452. udelay(200);
  1453. pll->on = false;
  1454. }
  1455. static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
  1456. enum pipe pipe)
  1457. {
  1458. int reg;
  1459. u32 val, pipeconf_val;
  1460. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1461. /* PCH only available on ILK+ */
  1462. BUG_ON(dev_priv->info->gen < 5);
  1463. /* Make sure PCH DPLL is enabled */
  1464. assert_pch_pll_enabled(dev_priv,
  1465. to_intel_crtc(crtc)->pch_pll,
  1466. to_intel_crtc(crtc));
  1467. /* FDI must be feeding us bits for PCH ports */
  1468. assert_fdi_tx_enabled(dev_priv, pipe);
  1469. assert_fdi_rx_enabled(dev_priv, pipe);
  1470. if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
  1471. DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
  1472. return;
  1473. }
  1474. reg = TRANSCONF(pipe);
  1475. val = I915_READ(reg);
  1476. pipeconf_val = I915_READ(PIPECONF(pipe));
  1477. if (HAS_PCH_IBX(dev_priv->dev)) {
  1478. /*
  1479. * make the BPC in transcoder be consistent with
  1480. * that in pipeconf reg.
  1481. */
  1482. val &= ~PIPE_BPC_MASK;
  1483. val |= pipeconf_val & PIPE_BPC_MASK;
  1484. }
  1485. val &= ~TRANS_INTERLACE_MASK;
  1486. if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1487. if (HAS_PCH_IBX(dev_priv->dev) &&
  1488. intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
  1489. val |= TRANS_LEGACY_INTERLACED_ILK;
  1490. else
  1491. val |= TRANS_INTERLACED;
  1492. else
  1493. val |= TRANS_PROGRESSIVE;
  1494. I915_WRITE(reg, val | TRANS_ENABLE);
  1495. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1496. DRM_ERROR("failed to enable transcoder %d\n", pipe);
  1497. }
  1498. static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
  1499. enum pipe pipe)
  1500. {
  1501. int reg;
  1502. u32 val;
  1503. /* FDI relies on the transcoder */
  1504. assert_fdi_tx_disabled(dev_priv, pipe);
  1505. assert_fdi_rx_disabled(dev_priv, pipe);
  1506. /* Ports must be off as well */
  1507. assert_pch_ports_disabled(dev_priv, pipe);
  1508. reg = TRANSCONF(pipe);
  1509. val = I915_READ(reg);
  1510. val &= ~TRANS_ENABLE;
  1511. I915_WRITE(reg, val);
  1512. /* wait for PCH transcoder off, transcoder state */
  1513. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1514. DRM_ERROR("failed to disable transcoder %d\n", pipe);
  1515. }
  1516. /**
  1517. * intel_enable_pipe - enable a pipe, asserting requirements
  1518. * @dev_priv: i915 private structure
  1519. * @pipe: pipe to enable
  1520. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1521. *
  1522. * Enable @pipe, making sure that various hardware specific requirements
  1523. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1524. *
  1525. * @pipe should be %PIPE_A or %PIPE_B.
  1526. *
  1527. * Will wait until the pipe is actually running (i.e. first vblank) before
  1528. * returning.
  1529. */
  1530. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1531. bool pch_port)
  1532. {
  1533. int reg;
  1534. u32 val;
  1535. /*
  1536. * A pipe without a PLL won't actually be able to drive bits from
  1537. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1538. * need the check.
  1539. */
  1540. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1541. assert_pll_enabled(dev_priv, pipe);
  1542. else {
  1543. if (pch_port) {
  1544. /* if driving the PCH, we need FDI enabled */
  1545. assert_fdi_rx_pll_enabled(dev_priv, pipe);
  1546. assert_fdi_tx_pll_enabled(dev_priv, pipe);
  1547. }
  1548. /* FIXME: assert CPU port conditions for SNB+ */
  1549. }
  1550. reg = PIPECONF(pipe);
  1551. val = I915_READ(reg);
  1552. if (val & PIPECONF_ENABLE)
  1553. return;
  1554. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1555. intel_wait_for_vblank(dev_priv->dev, pipe);
  1556. }
  1557. /**
  1558. * intel_disable_pipe - disable a pipe, asserting requirements
  1559. * @dev_priv: i915 private structure
  1560. * @pipe: pipe to disable
  1561. *
  1562. * Disable @pipe, making sure that various hardware specific requirements
  1563. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1564. *
  1565. * @pipe should be %PIPE_A or %PIPE_B.
  1566. *
  1567. * Will wait until the pipe has shut down before returning.
  1568. */
  1569. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1570. enum pipe pipe)
  1571. {
  1572. int reg;
  1573. u32 val;
  1574. /*
  1575. * Make sure planes won't keep trying to pump pixels to us,
  1576. * or we might hang the display.
  1577. */
  1578. assert_planes_disabled(dev_priv, pipe);
  1579. /* Don't disable pipe A or pipe A PLLs if needed */
  1580. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1581. return;
  1582. reg = PIPECONF(pipe);
  1583. val = I915_READ(reg);
  1584. if ((val & PIPECONF_ENABLE) == 0)
  1585. return;
  1586. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1587. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1588. }
  1589. /*
  1590. * Plane regs are double buffered, going from enabled->disabled needs a
  1591. * trigger in order to latch. The display address reg provides this.
  1592. */
  1593. void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1594. enum plane plane)
  1595. {
  1596. I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1597. I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1598. }
  1599. /**
  1600. * intel_enable_plane - enable a display plane on a given pipe
  1601. * @dev_priv: i915 private structure
  1602. * @plane: plane to enable
  1603. * @pipe: pipe being fed
  1604. *
  1605. * Enable @plane on @pipe, making sure that @pipe is running first.
  1606. */
  1607. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1608. enum plane plane, enum pipe pipe)
  1609. {
  1610. int reg;
  1611. u32 val;
  1612. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1613. assert_pipe_enabled(dev_priv, pipe);
  1614. reg = DSPCNTR(plane);
  1615. val = I915_READ(reg);
  1616. if (val & DISPLAY_PLANE_ENABLE)
  1617. return;
  1618. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1619. intel_flush_display_plane(dev_priv, plane);
  1620. intel_wait_for_vblank(dev_priv->dev, pipe);
  1621. }
  1622. /**
  1623. * intel_disable_plane - disable a display plane
  1624. * @dev_priv: i915 private structure
  1625. * @plane: plane to disable
  1626. * @pipe: pipe consuming the data
  1627. *
  1628. * Disable @plane; should be an independent operation.
  1629. */
  1630. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1631. enum plane plane, enum pipe pipe)
  1632. {
  1633. int reg;
  1634. u32 val;
  1635. reg = DSPCNTR(plane);
  1636. val = I915_READ(reg);
  1637. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1638. return;
  1639. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1640. intel_flush_display_plane(dev_priv, plane);
  1641. intel_wait_for_vblank(dev_priv->dev, pipe);
  1642. }
  1643. static void disable_pch_dp(struct drm_i915_private *dev_priv,
  1644. enum pipe pipe, int reg, u32 port_sel)
  1645. {
  1646. u32 val = I915_READ(reg);
  1647. if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
  1648. DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
  1649. I915_WRITE(reg, val & ~DP_PORT_EN);
  1650. }
  1651. }
  1652. static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
  1653. enum pipe pipe, int reg)
  1654. {
  1655. u32 val = I915_READ(reg);
  1656. if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
  1657. DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
  1658. reg, pipe);
  1659. I915_WRITE(reg, val & ~PORT_ENABLE);
  1660. }
  1661. }
  1662. /* Disable any ports connected to this transcoder */
  1663. static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
  1664. enum pipe pipe)
  1665. {
  1666. u32 reg, val;
  1667. val = I915_READ(PCH_PP_CONTROL);
  1668. I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
  1669. disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1670. disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1671. disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1672. reg = PCH_ADPA;
  1673. val = I915_READ(reg);
  1674. if (adpa_pipe_enabled(dev_priv, pipe, val))
  1675. I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
  1676. reg = PCH_LVDS;
  1677. val = I915_READ(reg);
  1678. if (lvds_pipe_enabled(dev_priv, pipe, val)) {
  1679. DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
  1680. I915_WRITE(reg, val & ~LVDS_PORT_EN);
  1681. POSTING_READ(reg);
  1682. udelay(100);
  1683. }
  1684. disable_pch_hdmi(dev_priv, pipe, HDMIB);
  1685. disable_pch_hdmi(dev_priv, pipe, HDMIC);
  1686. disable_pch_hdmi(dev_priv, pipe, HDMID);
  1687. }
  1688. int
  1689. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1690. struct drm_i915_gem_object *obj,
  1691. struct intel_ring_buffer *pipelined)
  1692. {
  1693. struct drm_i915_private *dev_priv = dev->dev_private;
  1694. u32 alignment;
  1695. int ret;
  1696. switch (obj->tiling_mode) {
  1697. case I915_TILING_NONE:
  1698. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1699. alignment = 128 * 1024;
  1700. else if (INTEL_INFO(dev)->gen >= 4)
  1701. alignment = 4 * 1024;
  1702. else
  1703. alignment = 64 * 1024;
  1704. break;
  1705. case I915_TILING_X:
  1706. /* pin() will align the object as required by fence */
  1707. alignment = 0;
  1708. break;
  1709. case I915_TILING_Y:
  1710. /* FIXME: Is this true? */
  1711. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1712. return -EINVAL;
  1713. default:
  1714. BUG();
  1715. }
  1716. dev_priv->mm.interruptible = false;
  1717. ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1718. if (ret)
  1719. goto err_interruptible;
  1720. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1721. * fence, whereas 965+ only requires a fence if using
  1722. * framebuffer compression. For simplicity, we always install
  1723. * a fence as the cost is not that onerous.
  1724. */
  1725. ret = i915_gem_object_get_fence(obj);
  1726. if (ret)
  1727. goto err_unpin;
  1728. i915_gem_object_pin_fence(obj);
  1729. dev_priv->mm.interruptible = true;
  1730. return 0;
  1731. err_unpin:
  1732. i915_gem_object_unpin(obj);
  1733. err_interruptible:
  1734. dev_priv->mm.interruptible = true;
  1735. return ret;
  1736. }
  1737. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1738. {
  1739. i915_gem_object_unpin_fence(obj);
  1740. i915_gem_object_unpin(obj);
  1741. }
  1742. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  1743. * is assumed to be a power-of-two. */
  1744. static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
  1745. unsigned int bpp,
  1746. unsigned int pitch)
  1747. {
  1748. int tile_rows, tiles;
  1749. tile_rows = *y / 8;
  1750. *y %= 8;
  1751. tiles = *x / (512/bpp);
  1752. *x %= 512/bpp;
  1753. return tile_rows * pitch * 8 + tiles * 4096;
  1754. }
  1755. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1756. int x, int y)
  1757. {
  1758. struct drm_device *dev = crtc->dev;
  1759. struct drm_i915_private *dev_priv = dev->dev_private;
  1760. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1761. struct intel_framebuffer *intel_fb;
  1762. struct drm_i915_gem_object *obj;
  1763. int plane = intel_crtc->plane;
  1764. unsigned long linear_offset;
  1765. u32 dspcntr;
  1766. u32 reg;
  1767. switch (plane) {
  1768. case 0:
  1769. case 1:
  1770. break;
  1771. default:
  1772. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1773. return -EINVAL;
  1774. }
  1775. intel_fb = to_intel_framebuffer(fb);
  1776. obj = intel_fb->obj;
  1777. reg = DSPCNTR(plane);
  1778. dspcntr = I915_READ(reg);
  1779. /* Mask out pixel format bits in case we change it */
  1780. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1781. switch (fb->bits_per_pixel) {
  1782. case 8:
  1783. dspcntr |= DISPPLANE_8BPP;
  1784. break;
  1785. case 16:
  1786. if (fb->depth == 15)
  1787. dspcntr |= DISPPLANE_15_16BPP;
  1788. else
  1789. dspcntr |= DISPPLANE_16BPP;
  1790. break;
  1791. case 24:
  1792. case 32:
  1793. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1794. break;
  1795. default:
  1796. DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
  1797. return -EINVAL;
  1798. }
  1799. if (INTEL_INFO(dev)->gen >= 4) {
  1800. if (obj->tiling_mode != I915_TILING_NONE)
  1801. dspcntr |= DISPPLANE_TILED;
  1802. else
  1803. dspcntr &= ~DISPPLANE_TILED;
  1804. }
  1805. I915_WRITE(reg, dspcntr);
  1806. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1807. if (INTEL_INFO(dev)->gen >= 4) {
  1808. intel_crtc->dspaddr_offset =
  1809. gen4_compute_dspaddr_offset_xtiled(&x, &y,
  1810. fb->bits_per_pixel / 8,
  1811. fb->pitches[0]);
  1812. linear_offset -= intel_crtc->dspaddr_offset;
  1813. } else {
  1814. intel_crtc->dspaddr_offset = linear_offset;
  1815. }
  1816. DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
  1817. obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
  1818. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1819. if (INTEL_INFO(dev)->gen >= 4) {
  1820. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1821. obj->gtt_offset + intel_crtc->dspaddr_offset);
  1822. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1823. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1824. } else
  1825. I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
  1826. POSTING_READ(reg);
  1827. return 0;
  1828. }
  1829. static int ironlake_update_plane(struct drm_crtc *crtc,
  1830. struct drm_framebuffer *fb, int x, int y)
  1831. {
  1832. struct drm_device *dev = crtc->dev;
  1833. struct drm_i915_private *dev_priv = dev->dev_private;
  1834. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1835. struct intel_framebuffer *intel_fb;
  1836. struct drm_i915_gem_object *obj;
  1837. int plane = intel_crtc->plane;
  1838. unsigned long linear_offset;
  1839. u32 dspcntr;
  1840. u32 reg;
  1841. switch (plane) {
  1842. case 0:
  1843. case 1:
  1844. case 2:
  1845. break;
  1846. default:
  1847. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1848. return -EINVAL;
  1849. }
  1850. intel_fb = to_intel_framebuffer(fb);
  1851. obj = intel_fb->obj;
  1852. reg = DSPCNTR(plane);
  1853. dspcntr = I915_READ(reg);
  1854. /* Mask out pixel format bits in case we change it */
  1855. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1856. switch (fb->bits_per_pixel) {
  1857. case 8:
  1858. dspcntr |= DISPPLANE_8BPP;
  1859. break;
  1860. case 16:
  1861. if (fb->depth != 16)
  1862. return -EINVAL;
  1863. dspcntr |= DISPPLANE_16BPP;
  1864. break;
  1865. case 24:
  1866. case 32:
  1867. if (fb->depth == 24)
  1868. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1869. else if (fb->depth == 30)
  1870. dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
  1871. else
  1872. return -EINVAL;
  1873. break;
  1874. default:
  1875. DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
  1876. return -EINVAL;
  1877. }
  1878. if (obj->tiling_mode != I915_TILING_NONE)
  1879. dspcntr |= DISPPLANE_TILED;
  1880. else
  1881. dspcntr &= ~DISPPLANE_TILED;
  1882. /* must disable */
  1883. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1884. I915_WRITE(reg, dspcntr);
  1885. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1886. intel_crtc->dspaddr_offset =
  1887. gen4_compute_dspaddr_offset_xtiled(&x, &y,
  1888. fb->bits_per_pixel / 8,
  1889. fb->pitches[0]);
  1890. linear_offset -= intel_crtc->dspaddr_offset;
  1891. DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
  1892. obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
  1893. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1894. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1895. obj->gtt_offset + intel_crtc->dspaddr_offset);
  1896. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1897. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1898. POSTING_READ(reg);
  1899. return 0;
  1900. }
  1901. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1902. static int
  1903. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1904. int x, int y, enum mode_set_atomic state)
  1905. {
  1906. struct drm_device *dev = crtc->dev;
  1907. struct drm_i915_private *dev_priv = dev->dev_private;
  1908. if (dev_priv->display.disable_fbc)
  1909. dev_priv->display.disable_fbc(dev);
  1910. intel_increase_pllclock(crtc);
  1911. return dev_priv->display.update_plane(crtc, fb, x, y);
  1912. }
  1913. static int
  1914. intel_finish_fb(struct drm_framebuffer *old_fb)
  1915. {
  1916. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1917. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1918. bool was_interruptible = dev_priv->mm.interruptible;
  1919. int ret;
  1920. wait_event(dev_priv->pending_flip_queue,
  1921. atomic_read(&dev_priv->mm.wedged) ||
  1922. atomic_read(&obj->pending_flip) == 0);
  1923. /* Big Hammer, we also need to ensure that any pending
  1924. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  1925. * current scanout is retired before unpinning the old
  1926. * framebuffer.
  1927. *
  1928. * This should only fail upon a hung GPU, in which case we
  1929. * can safely continue.
  1930. */
  1931. dev_priv->mm.interruptible = false;
  1932. ret = i915_gem_object_finish_gpu(obj);
  1933. dev_priv->mm.interruptible = was_interruptible;
  1934. return ret;
  1935. }
  1936. static int
  1937. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1938. struct drm_framebuffer *fb)
  1939. {
  1940. struct drm_device *dev = crtc->dev;
  1941. struct drm_i915_private *dev_priv = dev->dev_private;
  1942. struct drm_i915_master_private *master_priv;
  1943. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1944. struct drm_framebuffer *old_fb;
  1945. int ret;
  1946. /* no fb bound */
  1947. if (!fb) {
  1948. DRM_ERROR("No FB bound\n");
  1949. return 0;
  1950. }
  1951. if(intel_crtc->plane > dev_priv->num_pipe) {
  1952. DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
  1953. intel_crtc->plane,
  1954. dev_priv->num_pipe);
  1955. return -EINVAL;
  1956. }
  1957. mutex_lock(&dev->struct_mutex);
  1958. ret = intel_pin_and_fence_fb_obj(dev,
  1959. to_intel_framebuffer(fb)->obj,
  1960. NULL);
  1961. if (ret != 0) {
  1962. mutex_unlock(&dev->struct_mutex);
  1963. DRM_ERROR("pin & fence failed\n");
  1964. return ret;
  1965. }
  1966. if (crtc->fb)
  1967. intel_finish_fb(crtc->fb);
  1968. ret = dev_priv->display.update_plane(crtc, fb, x, y);
  1969. if (ret) {
  1970. intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
  1971. mutex_unlock(&dev->struct_mutex);
  1972. DRM_ERROR("failed to update base address\n");
  1973. return ret;
  1974. }
  1975. old_fb = crtc->fb;
  1976. crtc->fb = fb;
  1977. crtc->x = x;
  1978. crtc->y = y;
  1979. if (old_fb) {
  1980. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1981. intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  1982. }
  1983. intel_update_fbc(dev);
  1984. mutex_unlock(&dev->struct_mutex);
  1985. if (!dev->primary->master)
  1986. return 0;
  1987. master_priv = dev->primary->master->driver_priv;
  1988. if (!master_priv->sarea_priv)
  1989. return 0;
  1990. if (intel_crtc->pipe) {
  1991. master_priv->sarea_priv->pipeB_x = x;
  1992. master_priv->sarea_priv->pipeB_y = y;
  1993. } else {
  1994. master_priv->sarea_priv->pipeA_x = x;
  1995. master_priv->sarea_priv->pipeA_y = y;
  1996. }
  1997. return 0;
  1998. }
  1999. static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
  2000. {
  2001. struct drm_device *dev = crtc->dev;
  2002. struct drm_i915_private *dev_priv = dev->dev_private;
  2003. u32 dpa_ctl;
  2004. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  2005. dpa_ctl = I915_READ(DP_A);
  2006. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  2007. if (clock < 200000) {
  2008. u32 temp;
  2009. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  2010. /* workaround for 160Mhz:
  2011. 1) program 0x4600c bits 15:0 = 0x8124
  2012. 2) program 0x46010 bit 0 = 1
  2013. 3) program 0x46034 bit 24 = 1
  2014. 4) program 0x64000 bit 14 = 1
  2015. */
  2016. temp = I915_READ(0x4600c);
  2017. temp &= 0xffff0000;
  2018. I915_WRITE(0x4600c, temp | 0x8124);
  2019. temp = I915_READ(0x46010);
  2020. I915_WRITE(0x46010, temp | 1);
  2021. temp = I915_READ(0x46034);
  2022. I915_WRITE(0x46034, temp | (1 << 24));
  2023. } else {
  2024. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  2025. }
  2026. I915_WRITE(DP_A, dpa_ctl);
  2027. POSTING_READ(DP_A);
  2028. udelay(500);
  2029. }
  2030. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2031. {
  2032. struct drm_device *dev = crtc->dev;
  2033. struct drm_i915_private *dev_priv = dev->dev_private;
  2034. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2035. int pipe = intel_crtc->pipe;
  2036. u32 reg, temp;
  2037. /* enable normal train */
  2038. reg = FDI_TX_CTL(pipe);
  2039. temp = I915_READ(reg);
  2040. if (IS_IVYBRIDGE(dev)) {
  2041. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2042. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2043. } else {
  2044. temp &= ~FDI_LINK_TRAIN_NONE;
  2045. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2046. }
  2047. I915_WRITE(reg, temp);
  2048. reg = FDI_RX_CTL(pipe);
  2049. temp = I915_READ(reg);
  2050. if (HAS_PCH_CPT(dev)) {
  2051. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2052. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2053. } else {
  2054. temp &= ~FDI_LINK_TRAIN_NONE;
  2055. temp |= FDI_LINK_TRAIN_NONE;
  2056. }
  2057. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2058. /* wait one idle pattern time */
  2059. POSTING_READ(reg);
  2060. udelay(1000);
  2061. /* IVB wants error correction enabled */
  2062. if (IS_IVYBRIDGE(dev))
  2063. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2064. FDI_FE_ERRC_ENABLE);
  2065. }
  2066. static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
  2067. {
  2068. struct drm_i915_private *dev_priv = dev->dev_private;
  2069. u32 flags = I915_READ(SOUTH_CHICKEN1);
  2070. flags |= FDI_PHASE_SYNC_OVR(pipe);
  2071. I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
  2072. flags |= FDI_PHASE_SYNC_EN(pipe);
  2073. I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
  2074. POSTING_READ(SOUTH_CHICKEN1);
  2075. }
  2076. /* The FDI link training functions for ILK/Ibexpeak. */
  2077. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2078. {
  2079. struct drm_device *dev = crtc->dev;
  2080. struct drm_i915_private *dev_priv = dev->dev_private;
  2081. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2082. int pipe = intel_crtc->pipe;
  2083. int plane = intel_crtc->plane;
  2084. u32 reg, temp, tries;
  2085. /* FDI needs bits from pipe & plane first */
  2086. assert_pipe_enabled(dev_priv, pipe);
  2087. assert_plane_enabled(dev_priv, plane);
  2088. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2089. for train result */
  2090. reg = FDI_RX_IMR(pipe);
  2091. temp = I915_READ(reg);
  2092. temp &= ~FDI_RX_SYMBOL_LOCK;
  2093. temp &= ~FDI_RX_BIT_LOCK;
  2094. I915_WRITE(reg, temp);
  2095. I915_READ(reg);
  2096. udelay(150);
  2097. /* enable CPU FDI TX and PCH FDI RX */
  2098. reg = FDI_TX_CTL(pipe);
  2099. temp = I915_READ(reg);
  2100. temp &= ~(7 << 19);
  2101. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2102. temp &= ~FDI_LINK_TRAIN_NONE;
  2103. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2104. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2105. reg = FDI_RX_CTL(pipe);
  2106. temp = I915_READ(reg);
  2107. temp &= ~FDI_LINK_TRAIN_NONE;
  2108. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2109. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2110. POSTING_READ(reg);
  2111. udelay(150);
  2112. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2113. if (HAS_PCH_IBX(dev)) {
  2114. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2115. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2116. FDI_RX_PHASE_SYNC_POINTER_EN);
  2117. }
  2118. reg = FDI_RX_IIR(pipe);
  2119. for (tries = 0; tries < 5; tries++) {
  2120. temp = I915_READ(reg);
  2121. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2122. if ((temp & FDI_RX_BIT_LOCK)) {
  2123. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2124. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2125. break;
  2126. }
  2127. }
  2128. if (tries == 5)
  2129. DRM_ERROR("FDI train 1 fail!\n");
  2130. /* Train 2 */
  2131. reg = FDI_TX_CTL(pipe);
  2132. temp = I915_READ(reg);
  2133. temp &= ~FDI_LINK_TRAIN_NONE;
  2134. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2135. I915_WRITE(reg, temp);
  2136. reg = FDI_RX_CTL(pipe);
  2137. temp = I915_READ(reg);
  2138. temp &= ~FDI_LINK_TRAIN_NONE;
  2139. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2140. I915_WRITE(reg, temp);
  2141. POSTING_READ(reg);
  2142. udelay(150);
  2143. reg = FDI_RX_IIR(pipe);
  2144. for (tries = 0; tries < 5; tries++) {
  2145. temp = I915_READ(reg);
  2146. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2147. if (temp & FDI_RX_SYMBOL_LOCK) {
  2148. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2149. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2150. break;
  2151. }
  2152. }
  2153. if (tries == 5)
  2154. DRM_ERROR("FDI train 2 fail!\n");
  2155. DRM_DEBUG_KMS("FDI train done\n");
  2156. }
  2157. static const int snb_b_fdi_train_param[] = {
  2158. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2159. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2160. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2161. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2162. };
  2163. /* The FDI link training functions for SNB/Cougarpoint. */
  2164. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2165. {
  2166. struct drm_device *dev = crtc->dev;
  2167. struct drm_i915_private *dev_priv = dev->dev_private;
  2168. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2169. int pipe = intel_crtc->pipe;
  2170. u32 reg, temp, i, retry;
  2171. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2172. for train result */
  2173. reg = FDI_RX_IMR(pipe);
  2174. temp = I915_READ(reg);
  2175. temp &= ~FDI_RX_SYMBOL_LOCK;
  2176. temp &= ~FDI_RX_BIT_LOCK;
  2177. I915_WRITE(reg, temp);
  2178. POSTING_READ(reg);
  2179. udelay(150);
  2180. /* enable CPU FDI TX and PCH FDI RX */
  2181. reg = FDI_TX_CTL(pipe);
  2182. temp = I915_READ(reg);
  2183. temp &= ~(7 << 19);
  2184. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2185. temp &= ~FDI_LINK_TRAIN_NONE;
  2186. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2187. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2188. /* SNB-B */
  2189. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2190. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2191. reg = FDI_RX_CTL(pipe);
  2192. temp = I915_READ(reg);
  2193. if (HAS_PCH_CPT(dev)) {
  2194. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2195. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2196. } else {
  2197. temp &= ~FDI_LINK_TRAIN_NONE;
  2198. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2199. }
  2200. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2201. POSTING_READ(reg);
  2202. udelay(150);
  2203. if (HAS_PCH_CPT(dev))
  2204. cpt_phase_pointer_enable(dev, pipe);
  2205. for (i = 0; i < 4; i++) {
  2206. reg = FDI_TX_CTL(pipe);
  2207. temp = I915_READ(reg);
  2208. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2209. temp |= snb_b_fdi_train_param[i];
  2210. I915_WRITE(reg, temp);
  2211. POSTING_READ(reg);
  2212. udelay(500);
  2213. for (retry = 0; retry < 5; retry++) {
  2214. reg = FDI_RX_IIR(pipe);
  2215. temp = I915_READ(reg);
  2216. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2217. if (temp & FDI_RX_BIT_LOCK) {
  2218. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2219. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2220. break;
  2221. }
  2222. udelay(50);
  2223. }
  2224. if (retry < 5)
  2225. break;
  2226. }
  2227. if (i == 4)
  2228. DRM_ERROR("FDI train 1 fail!\n");
  2229. /* Train 2 */
  2230. reg = FDI_TX_CTL(pipe);
  2231. temp = I915_READ(reg);
  2232. temp &= ~FDI_LINK_TRAIN_NONE;
  2233. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2234. if (IS_GEN6(dev)) {
  2235. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2236. /* SNB-B */
  2237. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2238. }
  2239. I915_WRITE(reg, temp);
  2240. reg = FDI_RX_CTL(pipe);
  2241. temp = I915_READ(reg);
  2242. if (HAS_PCH_CPT(dev)) {
  2243. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2244. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2245. } else {
  2246. temp &= ~FDI_LINK_TRAIN_NONE;
  2247. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2248. }
  2249. I915_WRITE(reg, temp);
  2250. POSTING_READ(reg);
  2251. udelay(150);
  2252. for (i = 0; i < 4; i++) {
  2253. reg = FDI_TX_CTL(pipe);
  2254. temp = I915_READ(reg);
  2255. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2256. temp |= snb_b_fdi_train_param[i];
  2257. I915_WRITE(reg, temp);
  2258. POSTING_READ(reg);
  2259. udelay(500);
  2260. for (retry = 0; retry < 5; retry++) {
  2261. reg = FDI_RX_IIR(pipe);
  2262. temp = I915_READ(reg);
  2263. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2264. if (temp & FDI_RX_SYMBOL_LOCK) {
  2265. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2266. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2267. break;
  2268. }
  2269. udelay(50);
  2270. }
  2271. if (retry < 5)
  2272. break;
  2273. }
  2274. if (i == 4)
  2275. DRM_ERROR("FDI train 2 fail!\n");
  2276. DRM_DEBUG_KMS("FDI train done.\n");
  2277. }
  2278. /* Manual link training for Ivy Bridge A0 parts */
  2279. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2280. {
  2281. struct drm_device *dev = crtc->dev;
  2282. struct drm_i915_private *dev_priv = dev->dev_private;
  2283. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2284. int pipe = intel_crtc->pipe;
  2285. u32 reg, temp, i;
  2286. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2287. for train result */
  2288. reg = FDI_RX_IMR(pipe);
  2289. temp = I915_READ(reg);
  2290. temp &= ~FDI_RX_SYMBOL_LOCK;
  2291. temp &= ~FDI_RX_BIT_LOCK;
  2292. I915_WRITE(reg, temp);
  2293. POSTING_READ(reg);
  2294. udelay(150);
  2295. /* enable CPU FDI TX and PCH FDI RX */
  2296. reg = FDI_TX_CTL(pipe);
  2297. temp = I915_READ(reg);
  2298. temp &= ~(7 << 19);
  2299. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2300. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2301. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2302. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2303. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2304. temp |= FDI_COMPOSITE_SYNC;
  2305. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2306. reg = FDI_RX_CTL(pipe);
  2307. temp = I915_READ(reg);
  2308. temp &= ~FDI_LINK_TRAIN_AUTO;
  2309. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2310. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2311. temp |= FDI_COMPOSITE_SYNC;
  2312. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2313. POSTING_READ(reg);
  2314. udelay(150);
  2315. if (HAS_PCH_CPT(dev))
  2316. cpt_phase_pointer_enable(dev, pipe);
  2317. for (i = 0; i < 4; i++) {
  2318. reg = FDI_TX_CTL(pipe);
  2319. temp = I915_READ(reg);
  2320. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2321. temp |= snb_b_fdi_train_param[i];
  2322. I915_WRITE(reg, temp);
  2323. POSTING_READ(reg);
  2324. udelay(500);
  2325. reg = FDI_RX_IIR(pipe);
  2326. temp = I915_READ(reg);
  2327. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2328. if (temp & FDI_RX_BIT_LOCK ||
  2329. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2330. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2331. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2332. break;
  2333. }
  2334. }
  2335. if (i == 4)
  2336. DRM_ERROR("FDI train 1 fail!\n");
  2337. /* Train 2 */
  2338. reg = FDI_TX_CTL(pipe);
  2339. temp = I915_READ(reg);
  2340. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2341. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2342. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2343. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2344. I915_WRITE(reg, temp);
  2345. reg = FDI_RX_CTL(pipe);
  2346. temp = I915_READ(reg);
  2347. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2348. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2349. I915_WRITE(reg, temp);
  2350. POSTING_READ(reg);
  2351. udelay(150);
  2352. for (i = 0; i < 4; i++) {
  2353. reg = FDI_TX_CTL(pipe);
  2354. temp = I915_READ(reg);
  2355. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2356. temp |= snb_b_fdi_train_param[i];
  2357. I915_WRITE(reg, temp);
  2358. POSTING_READ(reg);
  2359. udelay(500);
  2360. reg = FDI_RX_IIR(pipe);
  2361. temp = I915_READ(reg);
  2362. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2363. if (temp & FDI_RX_SYMBOL_LOCK) {
  2364. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2365. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2366. break;
  2367. }
  2368. }
  2369. if (i == 4)
  2370. DRM_ERROR("FDI train 2 fail!\n");
  2371. DRM_DEBUG_KMS("FDI train done.\n");
  2372. }
  2373. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  2374. {
  2375. struct drm_device *dev = intel_crtc->base.dev;
  2376. struct drm_i915_private *dev_priv = dev->dev_private;
  2377. int pipe = intel_crtc->pipe;
  2378. u32 reg, temp;
  2379. /* Write the TU size bits so error detection works */
  2380. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2381. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2382. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2383. reg = FDI_RX_CTL(pipe);
  2384. temp = I915_READ(reg);
  2385. temp &= ~((0x7 << 19) | (0x7 << 16));
  2386. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2387. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2388. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2389. POSTING_READ(reg);
  2390. udelay(200);
  2391. /* Switch from Rawclk to PCDclk */
  2392. temp = I915_READ(reg);
  2393. I915_WRITE(reg, temp | FDI_PCDCLK);
  2394. POSTING_READ(reg);
  2395. udelay(200);
  2396. /* On Haswell, the PLL configuration for ports and pipes is handled
  2397. * separately, as part of DDI setup */
  2398. if (!IS_HASWELL(dev)) {
  2399. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2400. reg = FDI_TX_CTL(pipe);
  2401. temp = I915_READ(reg);
  2402. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2403. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2404. POSTING_READ(reg);
  2405. udelay(100);
  2406. }
  2407. }
  2408. }
  2409. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  2410. {
  2411. struct drm_device *dev = intel_crtc->base.dev;
  2412. struct drm_i915_private *dev_priv = dev->dev_private;
  2413. int pipe = intel_crtc->pipe;
  2414. u32 reg, temp;
  2415. /* Switch from PCDclk to Rawclk */
  2416. reg = FDI_RX_CTL(pipe);
  2417. temp = I915_READ(reg);
  2418. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2419. /* Disable CPU FDI TX PLL */
  2420. reg = FDI_TX_CTL(pipe);
  2421. temp = I915_READ(reg);
  2422. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2423. POSTING_READ(reg);
  2424. udelay(100);
  2425. reg = FDI_RX_CTL(pipe);
  2426. temp = I915_READ(reg);
  2427. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2428. /* Wait for the clocks to turn off. */
  2429. POSTING_READ(reg);
  2430. udelay(100);
  2431. }
  2432. static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
  2433. {
  2434. struct drm_i915_private *dev_priv = dev->dev_private;
  2435. u32 flags = I915_READ(SOUTH_CHICKEN1);
  2436. flags &= ~(FDI_PHASE_SYNC_EN(pipe));
  2437. I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
  2438. flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
  2439. I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
  2440. POSTING_READ(SOUTH_CHICKEN1);
  2441. }
  2442. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2443. {
  2444. struct drm_device *dev = crtc->dev;
  2445. struct drm_i915_private *dev_priv = dev->dev_private;
  2446. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2447. int pipe = intel_crtc->pipe;
  2448. u32 reg, temp;
  2449. /* disable CPU FDI tx and PCH FDI rx */
  2450. reg = FDI_TX_CTL(pipe);
  2451. temp = I915_READ(reg);
  2452. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2453. POSTING_READ(reg);
  2454. reg = FDI_RX_CTL(pipe);
  2455. temp = I915_READ(reg);
  2456. temp &= ~(0x7 << 16);
  2457. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2458. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2459. POSTING_READ(reg);
  2460. udelay(100);
  2461. /* Ironlake workaround, disable clock pointer after downing FDI */
  2462. if (HAS_PCH_IBX(dev)) {
  2463. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2464. I915_WRITE(FDI_RX_CHICKEN(pipe),
  2465. I915_READ(FDI_RX_CHICKEN(pipe) &
  2466. ~FDI_RX_PHASE_SYNC_POINTER_EN));
  2467. } else if (HAS_PCH_CPT(dev)) {
  2468. cpt_phase_pointer_disable(dev, pipe);
  2469. }
  2470. /* still set train pattern 1 */
  2471. reg = FDI_TX_CTL(pipe);
  2472. temp = I915_READ(reg);
  2473. temp &= ~FDI_LINK_TRAIN_NONE;
  2474. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2475. I915_WRITE(reg, temp);
  2476. reg = FDI_RX_CTL(pipe);
  2477. temp = I915_READ(reg);
  2478. if (HAS_PCH_CPT(dev)) {
  2479. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2480. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2481. } else {
  2482. temp &= ~FDI_LINK_TRAIN_NONE;
  2483. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2484. }
  2485. /* BPC in FDI rx is consistent with that in PIPECONF */
  2486. temp &= ~(0x07 << 16);
  2487. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2488. I915_WRITE(reg, temp);
  2489. POSTING_READ(reg);
  2490. udelay(100);
  2491. }
  2492. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2493. {
  2494. struct drm_device *dev = crtc->dev;
  2495. if (crtc->fb == NULL)
  2496. return;
  2497. mutex_lock(&dev->struct_mutex);
  2498. intel_finish_fb(crtc->fb);
  2499. mutex_unlock(&dev->struct_mutex);
  2500. }
  2501. static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
  2502. {
  2503. struct drm_device *dev = crtc->dev;
  2504. struct intel_encoder *intel_encoder;
  2505. /*
  2506. * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
  2507. * must be driven by its own crtc; no sharing is possible.
  2508. */
  2509. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  2510. /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
  2511. * CPU handles all others */
  2512. if (IS_HASWELL(dev)) {
  2513. /* It is still unclear how this will work on PPT, so throw up a warning */
  2514. WARN_ON(!HAS_PCH_LPT(dev));
  2515. if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
  2516. DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
  2517. return true;
  2518. } else {
  2519. DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
  2520. intel_encoder->type);
  2521. return false;
  2522. }
  2523. }
  2524. switch (intel_encoder->type) {
  2525. case INTEL_OUTPUT_EDP:
  2526. if (!intel_encoder_is_pch_edp(&intel_encoder->base))
  2527. return false;
  2528. continue;
  2529. }
  2530. }
  2531. return true;
  2532. }
  2533. /* Program iCLKIP clock to the desired frequency */
  2534. static void lpt_program_iclkip(struct drm_crtc *crtc)
  2535. {
  2536. struct drm_device *dev = crtc->dev;
  2537. struct drm_i915_private *dev_priv = dev->dev_private;
  2538. u32 divsel, phaseinc, auxdiv, phasedir = 0;
  2539. u32 temp;
  2540. /* It is necessary to ungate the pixclk gate prior to programming
  2541. * the divisors, and gate it back when it is done.
  2542. */
  2543. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  2544. /* Disable SSCCTL */
  2545. intel_sbi_write(dev_priv, SBI_SSCCTL6,
  2546. intel_sbi_read(dev_priv, SBI_SSCCTL6) |
  2547. SBI_SSCCTL_DISABLE);
  2548. /* 20MHz is a corner case which is out of range for the 7-bit divisor */
  2549. if (crtc->mode.clock == 20000) {
  2550. auxdiv = 1;
  2551. divsel = 0x41;
  2552. phaseinc = 0x20;
  2553. } else {
  2554. /* The iCLK virtual clock root frequency is in MHz,
  2555. * but the crtc->mode.clock in in KHz. To get the divisors,
  2556. * it is necessary to divide one by another, so we
  2557. * convert the virtual clock precision to KHz here for higher
  2558. * precision.
  2559. */
  2560. u32 iclk_virtual_root_freq = 172800 * 1000;
  2561. u32 iclk_pi_range = 64;
  2562. u32 desired_divisor, msb_divisor_value, pi_value;
  2563. desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
  2564. msb_divisor_value = desired_divisor / iclk_pi_range;
  2565. pi_value = desired_divisor % iclk_pi_range;
  2566. auxdiv = 0;
  2567. divsel = msb_divisor_value - 2;
  2568. phaseinc = pi_value;
  2569. }
  2570. /* This should not happen with any sane values */
  2571. WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  2572. ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  2573. WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  2574. ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  2575. DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  2576. crtc->mode.clock,
  2577. auxdiv,
  2578. divsel,
  2579. phasedir,
  2580. phaseinc);
  2581. /* Program SSCDIVINTPHASE6 */
  2582. temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
  2583. temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  2584. temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  2585. temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  2586. temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  2587. temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  2588. temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  2589. intel_sbi_write(dev_priv,
  2590. SBI_SSCDIVINTPHASE6,
  2591. temp);
  2592. /* Program SSCAUXDIV */
  2593. temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
  2594. temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  2595. temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  2596. intel_sbi_write(dev_priv,
  2597. SBI_SSCAUXDIV6,
  2598. temp);
  2599. /* Enable modulator and associated divider */
  2600. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
  2601. temp &= ~SBI_SSCCTL_DISABLE;
  2602. intel_sbi_write(dev_priv,
  2603. SBI_SSCCTL6,
  2604. temp);
  2605. /* Wait for initialization time */
  2606. udelay(24);
  2607. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  2608. }
  2609. /*
  2610. * Enable PCH resources required for PCH ports:
  2611. * - PCH PLLs
  2612. * - FDI training & RX/TX
  2613. * - update transcoder timings
  2614. * - DP transcoding bits
  2615. * - transcoder
  2616. */
  2617. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2618. {
  2619. struct drm_device *dev = crtc->dev;
  2620. struct drm_i915_private *dev_priv = dev->dev_private;
  2621. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2622. int pipe = intel_crtc->pipe;
  2623. u32 reg, temp;
  2624. assert_transcoder_disabled(dev_priv, pipe);
  2625. /* For PCH output, training FDI link */
  2626. dev_priv->display.fdi_link_train(crtc);
  2627. intel_enable_pch_pll(intel_crtc);
  2628. if (HAS_PCH_LPT(dev)) {
  2629. DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
  2630. lpt_program_iclkip(crtc);
  2631. } else if (HAS_PCH_CPT(dev)) {
  2632. u32 sel;
  2633. temp = I915_READ(PCH_DPLL_SEL);
  2634. switch (pipe) {
  2635. default:
  2636. case 0:
  2637. temp |= TRANSA_DPLL_ENABLE;
  2638. sel = TRANSA_DPLLB_SEL;
  2639. break;
  2640. case 1:
  2641. temp |= TRANSB_DPLL_ENABLE;
  2642. sel = TRANSB_DPLLB_SEL;
  2643. break;
  2644. case 2:
  2645. temp |= TRANSC_DPLL_ENABLE;
  2646. sel = TRANSC_DPLLB_SEL;
  2647. break;
  2648. }
  2649. if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
  2650. temp |= sel;
  2651. else
  2652. temp &= ~sel;
  2653. I915_WRITE(PCH_DPLL_SEL, temp);
  2654. }
  2655. /* set transcoder timing, panel must allow it */
  2656. assert_panel_unlocked(dev_priv, pipe);
  2657. I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
  2658. I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
  2659. I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
  2660. I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
  2661. I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
  2662. I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
  2663. I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
  2664. if (!IS_HASWELL(dev))
  2665. intel_fdi_normal_train(crtc);
  2666. /* For PCH DP, enable TRANS_DP_CTL */
  2667. if (HAS_PCH_CPT(dev) &&
  2668. (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  2669. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2670. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
  2671. reg = TRANS_DP_CTL(pipe);
  2672. temp = I915_READ(reg);
  2673. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2674. TRANS_DP_SYNC_MASK |
  2675. TRANS_DP_BPC_MASK);
  2676. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2677. TRANS_DP_ENH_FRAMING);
  2678. temp |= bpc << 9; /* same format but at 11:9 */
  2679. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2680. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2681. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2682. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2683. switch (intel_trans_dp_port_sel(crtc)) {
  2684. case PCH_DP_B:
  2685. temp |= TRANS_DP_PORT_SEL_B;
  2686. break;
  2687. case PCH_DP_C:
  2688. temp |= TRANS_DP_PORT_SEL_C;
  2689. break;
  2690. case PCH_DP_D:
  2691. temp |= TRANS_DP_PORT_SEL_D;
  2692. break;
  2693. default:
  2694. DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
  2695. temp |= TRANS_DP_PORT_SEL_B;
  2696. break;
  2697. }
  2698. I915_WRITE(reg, temp);
  2699. }
  2700. intel_enable_transcoder(dev_priv, pipe);
  2701. }
  2702. static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
  2703. {
  2704. struct intel_pch_pll *pll = intel_crtc->pch_pll;
  2705. if (pll == NULL)
  2706. return;
  2707. if (pll->refcount == 0) {
  2708. WARN(1, "bad PCH PLL refcount\n");
  2709. return;
  2710. }
  2711. --pll->refcount;
  2712. intel_crtc->pch_pll = NULL;
  2713. }
  2714. static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
  2715. {
  2716. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  2717. struct intel_pch_pll *pll;
  2718. int i;
  2719. pll = intel_crtc->pch_pll;
  2720. if (pll) {
  2721. DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
  2722. intel_crtc->base.base.id, pll->pll_reg);
  2723. goto prepare;
  2724. }
  2725. if (HAS_PCH_IBX(dev_priv->dev)) {
  2726. /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
  2727. i = intel_crtc->pipe;
  2728. pll = &dev_priv->pch_plls[i];
  2729. DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
  2730. intel_crtc->base.base.id, pll->pll_reg);
  2731. goto found;
  2732. }
  2733. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  2734. pll = &dev_priv->pch_plls[i];
  2735. /* Only want to check enabled timings first */
  2736. if (pll->refcount == 0)
  2737. continue;
  2738. if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
  2739. fp == I915_READ(pll->fp0_reg)) {
  2740. DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
  2741. intel_crtc->base.base.id,
  2742. pll->pll_reg, pll->refcount, pll->active);
  2743. goto found;
  2744. }
  2745. }
  2746. /* Ok no matching timings, maybe there's a free one? */
  2747. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  2748. pll = &dev_priv->pch_plls[i];
  2749. if (pll->refcount == 0) {
  2750. DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
  2751. intel_crtc->base.base.id, pll->pll_reg);
  2752. goto found;
  2753. }
  2754. }
  2755. return NULL;
  2756. found:
  2757. intel_crtc->pch_pll = pll;
  2758. pll->refcount++;
  2759. DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
  2760. prepare: /* separate function? */
  2761. DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
  2762. /* Wait for the clocks to stabilize before rewriting the regs */
  2763. I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
  2764. POSTING_READ(pll->pll_reg);
  2765. udelay(150);
  2766. I915_WRITE(pll->fp0_reg, fp);
  2767. I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
  2768. pll->on = false;
  2769. return pll;
  2770. }
  2771. void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
  2772. {
  2773. struct drm_i915_private *dev_priv = dev->dev_private;
  2774. int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
  2775. u32 temp;
  2776. temp = I915_READ(dslreg);
  2777. udelay(500);
  2778. if (wait_for(I915_READ(dslreg) != temp, 5)) {
  2779. /* Without this, mode sets may fail silently on FDI */
  2780. I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
  2781. udelay(250);
  2782. I915_WRITE(tc2reg, 0);
  2783. if (wait_for(I915_READ(dslreg) != temp, 5))
  2784. DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
  2785. }
  2786. }
  2787. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2788. {
  2789. struct drm_device *dev = crtc->dev;
  2790. struct drm_i915_private *dev_priv = dev->dev_private;
  2791. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2792. struct intel_encoder *encoder;
  2793. int pipe = intel_crtc->pipe;
  2794. int plane = intel_crtc->plane;
  2795. u32 temp;
  2796. bool is_pch_port;
  2797. WARN_ON(!crtc->enabled);
  2798. if (intel_crtc->active)
  2799. return;
  2800. intel_crtc->active = true;
  2801. intel_update_watermarks(dev);
  2802. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  2803. temp = I915_READ(PCH_LVDS);
  2804. if ((temp & LVDS_PORT_EN) == 0)
  2805. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  2806. }
  2807. is_pch_port = intel_crtc_driving_pch(crtc);
  2808. if (is_pch_port)
  2809. ironlake_fdi_pll_enable(intel_crtc);
  2810. else
  2811. ironlake_fdi_disable(crtc);
  2812. /* Enable panel fitting for LVDS */
  2813. if (dev_priv->pch_pf_size &&
  2814. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
  2815. /* Force use of hard-coded filter coefficients
  2816. * as some pre-programmed values are broken,
  2817. * e.g. x201.
  2818. */
  2819. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2820. I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
  2821. I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
  2822. }
  2823. /*
  2824. * On ILK+ LUT must be loaded before the pipe is running but with
  2825. * clocks enabled
  2826. */
  2827. intel_crtc_load_lut(crtc);
  2828. intel_enable_pipe(dev_priv, pipe, is_pch_port);
  2829. intel_enable_plane(dev_priv, plane, pipe);
  2830. if (is_pch_port)
  2831. ironlake_pch_enable(crtc);
  2832. mutex_lock(&dev->struct_mutex);
  2833. intel_update_fbc(dev);
  2834. mutex_unlock(&dev->struct_mutex);
  2835. intel_crtc_update_cursor(crtc, true);
  2836. for_each_encoder_on_crtc(dev, crtc, encoder)
  2837. encoder->enable(encoder);
  2838. if (HAS_PCH_CPT(dev))
  2839. intel_cpt_verify_modeset(dev, intel_crtc->pipe);
  2840. }
  2841. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  2842. {
  2843. struct drm_device *dev = crtc->dev;
  2844. struct drm_i915_private *dev_priv = dev->dev_private;
  2845. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2846. struct intel_encoder *encoder;
  2847. int pipe = intel_crtc->pipe;
  2848. int plane = intel_crtc->plane;
  2849. u32 reg, temp;
  2850. if (!intel_crtc->active)
  2851. return;
  2852. for_each_encoder_on_crtc(dev, crtc, encoder)
  2853. encoder->disable(encoder);
  2854. intel_crtc_wait_for_pending_flips(crtc);
  2855. drm_vblank_off(dev, pipe);
  2856. intel_crtc_update_cursor(crtc, false);
  2857. intel_disable_plane(dev_priv, plane, pipe);
  2858. if (dev_priv->cfb_plane == plane)
  2859. intel_disable_fbc(dev);
  2860. intel_disable_pipe(dev_priv, pipe);
  2861. /* Disable PF */
  2862. I915_WRITE(PF_CTL(pipe), 0);
  2863. I915_WRITE(PF_WIN_SZ(pipe), 0);
  2864. ironlake_fdi_disable(crtc);
  2865. /* This is a horrible layering violation; we should be doing this in
  2866. * the connector/encoder ->prepare instead, but we don't always have
  2867. * enough information there about the config to know whether it will
  2868. * actually be necessary or just cause undesired flicker.
  2869. */
  2870. intel_disable_pch_ports(dev_priv, pipe);
  2871. intel_disable_transcoder(dev_priv, pipe);
  2872. if (HAS_PCH_CPT(dev)) {
  2873. /* disable TRANS_DP_CTL */
  2874. reg = TRANS_DP_CTL(pipe);
  2875. temp = I915_READ(reg);
  2876. temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  2877. temp |= TRANS_DP_PORT_SEL_NONE;
  2878. I915_WRITE(reg, temp);
  2879. /* disable DPLL_SEL */
  2880. temp = I915_READ(PCH_DPLL_SEL);
  2881. switch (pipe) {
  2882. case 0:
  2883. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
  2884. break;
  2885. case 1:
  2886. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  2887. break;
  2888. case 2:
  2889. /* C shares PLL A or B */
  2890. temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
  2891. break;
  2892. default:
  2893. BUG(); /* wtf */
  2894. }
  2895. I915_WRITE(PCH_DPLL_SEL, temp);
  2896. }
  2897. /* disable PCH DPLL */
  2898. intel_disable_pch_pll(intel_crtc);
  2899. ironlake_fdi_pll_disable(intel_crtc);
  2900. intel_crtc->active = false;
  2901. intel_update_watermarks(dev);
  2902. mutex_lock(&dev->struct_mutex);
  2903. intel_update_fbc(dev);
  2904. mutex_unlock(&dev->struct_mutex);
  2905. }
  2906. static void ironlake_crtc_off(struct drm_crtc *crtc)
  2907. {
  2908. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2909. intel_put_pch_pll(intel_crtc);
  2910. }
  2911. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  2912. {
  2913. if (!enable && intel_crtc->overlay) {
  2914. struct drm_device *dev = intel_crtc->base.dev;
  2915. struct drm_i915_private *dev_priv = dev->dev_private;
  2916. mutex_lock(&dev->struct_mutex);
  2917. dev_priv->mm.interruptible = false;
  2918. (void) intel_overlay_switch_off(intel_crtc->overlay);
  2919. dev_priv->mm.interruptible = true;
  2920. mutex_unlock(&dev->struct_mutex);
  2921. }
  2922. /* Let userspace switch the overlay on again. In most cases userspace
  2923. * has to recompute where to put it anyway.
  2924. */
  2925. }
  2926. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  2927. {
  2928. struct drm_device *dev = crtc->dev;
  2929. struct drm_i915_private *dev_priv = dev->dev_private;
  2930. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2931. struct intel_encoder *encoder;
  2932. int pipe = intel_crtc->pipe;
  2933. int plane = intel_crtc->plane;
  2934. WARN_ON(!crtc->enabled);
  2935. if (intel_crtc->active)
  2936. return;
  2937. intel_crtc->active = true;
  2938. intel_update_watermarks(dev);
  2939. intel_enable_pll(dev_priv, pipe);
  2940. intel_enable_pipe(dev_priv, pipe, false);
  2941. intel_enable_plane(dev_priv, plane, pipe);
  2942. intel_crtc_load_lut(crtc);
  2943. intel_update_fbc(dev);
  2944. /* Give the overlay scaler a chance to enable if it's on this pipe */
  2945. intel_crtc_dpms_overlay(intel_crtc, true);
  2946. intel_crtc_update_cursor(crtc, true);
  2947. for_each_encoder_on_crtc(dev, crtc, encoder)
  2948. encoder->enable(encoder);
  2949. }
  2950. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  2951. {
  2952. struct drm_device *dev = crtc->dev;
  2953. struct drm_i915_private *dev_priv = dev->dev_private;
  2954. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2955. struct intel_encoder *encoder;
  2956. int pipe = intel_crtc->pipe;
  2957. int plane = intel_crtc->plane;
  2958. if (!intel_crtc->active)
  2959. return;
  2960. for_each_encoder_on_crtc(dev, crtc, encoder)
  2961. encoder->disable(encoder);
  2962. /* Give the overlay scaler a chance to disable if it's on this pipe */
  2963. intel_crtc_wait_for_pending_flips(crtc);
  2964. drm_vblank_off(dev, pipe);
  2965. intel_crtc_dpms_overlay(intel_crtc, false);
  2966. intel_crtc_update_cursor(crtc, false);
  2967. if (dev_priv->cfb_plane == plane)
  2968. intel_disable_fbc(dev);
  2969. intel_disable_plane(dev_priv, plane, pipe);
  2970. intel_disable_pipe(dev_priv, pipe);
  2971. intel_disable_pll(dev_priv, pipe);
  2972. intel_crtc->active = false;
  2973. intel_update_fbc(dev);
  2974. intel_update_watermarks(dev);
  2975. }
  2976. static void i9xx_crtc_off(struct drm_crtc *crtc)
  2977. {
  2978. }
  2979. static void intel_crtc_update_sarea(struct drm_crtc *crtc,
  2980. bool enabled)
  2981. {
  2982. struct drm_device *dev = crtc->dev;
  2983. struct drm_i915_master_private *master_priv;
  2984. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2985. int pipe = intel_crtc->pipe;
  2986. if (!dev->primary->master)
  2987. return;
  2988. master_priv = dev->primary->master->driver_priv;
  2989. if (!master_priv->sarea_priv)
  2990. return;
  2991. switch (pipe) {
  2992. case 0:
  2993. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  2994. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  2995. break;
  2996. case 1:
  2997. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  2998. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  2999. break;
  3000. default:
  3001. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  3002. break;
  3003. }
  3004. }
  3005. /**
  3006. * Sets the power management mode of the pipe and plane.
  3007. */
  3008. void intel_crtc_update_dpms(struct drm_crtc *crtc)
  3009. {
  3010. struct drm_device *dev = crtc->dev;
  3011. struct drm_i915_private *dev_priv = dev->dev_private;
  3012. struct intel_encoder *intel_encoder;
  3013. bool enable = false;
  3014. for_each_encoder_on_crtc(dev, crtc, intel_encoder)
  3015. enable |= intel_encoder->connectors_active;
  3016. if (enable)
  3017. dev_priv->display.crtc_enable(crtc);
  3018. else
  3019. dev_priv->display.crtc_disable(crtc);
  3020. intel_crtc_update_sarea(crtc, enable);
  3021. }
  3022. static void intel_crtc_noop(struct drm_crtc *crtc)
  3023. {
  3024. }
  3025. static void intel_crtc_disable(struct drm_crtc *crtc)
  3026. {
  3027. struct drm_device *dev = crtc->dev;
  3028. struct drm_connector *connector;
  3029. struct drm_i915_private *dev_priv = dev->dev_private;
  3030. /* crtc should still be enabled when we disable it. */
  3031. WARN_ON(!crtc->enabled);
  3032. dev_priv->display.crtc_disable(crtc);
  3033. intel_crtc_update_sarea(crtc, false);
  3034. dev_priv->display.off(crtc);
  3035. assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
  3036. assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
  3037. if (crtc->fb) {
  3038. mutex_lock(&dev->struct_mutex);
  3039. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  3040. mutex_unlock(&dev->struct_mutex);
  3041. crtc->fb = NULL;
  3042. }
  3043. /* Update computed state. */
  3044. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3045. if (!connector->encoder || !connector->encoder->crtc)
  3046. continue;
  3047. if (connector->encoder->crtc != crtc)
  3048. continue;
  3049. connector->dpms = DRM_MODE_DPMS_OFF;
  3050. to_intel_encoder(connector->encoder)->connectors_active = false;
  3051. }
  3052. }
  3053. void intel_modeset_disable(struct drm_device *dev)
  3054. {
  3055. struct drm_crtc *crtc;
  3056. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3057. if (crtc->enabled)
  3058. intel_crtc_disable(crtc);
  3059. }
  3060. }
  3061. void intel_encoder_noop(struct drm_encoder *encoder)
  3062. {
  3063. }
  3064. void intel_encoder_destroy(struct drm_encoder *encoder)
  3065. {
  3066. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3067. drm_encoder_cleanup(encoder);
  3068. kfree(intel_encoder);
  3069. }
  3070. /* Simple dpms helper for encodres with just one connector, no cloning and only
  3071. * one kind of off state. It clamps all !ON modes to fully OFF and changes the
  3072. * state of the entire output pipe. */
  3073. void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
  3074. {
  3075. if (mode == DRM_MODE_DPMS_ON) {
  3076. encoder->connectors_active = true;
  3077. intel_crtc_update_dpms(encoder->base.crtc);
  3078. } else {
  3079. encoder->connectors_active = false;
  3080. intel_crtc_update_dpms(encoder->base.crtc);
  3081. }
  3082. }
  3083. /* Cross check the actual hw state with our own modeset state tracking (and it's
  3084. * internal consistency). */
  3085. static void intel_connector_check_state(struct intel_connector *connector)
  3086. {
  3087. if (connector->get_hw_state(connector)) {
  3088. struct intel_encoder *encoder = connector->encoder;
  3089. struct drm_crtc *crtc;
  3090. bool encoder_enabled;
  3091. enum pipe pipe;
  3092. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  3093. connector->base.base.id,
  3094. drm_get_connector_name(&connector->base));
  3095. WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
  3096. "wrong connector dpms state\n");
  3097. WARN(connector->base.encoder != &encoder->base,
  3098. "active connector not linked to encoder\n");
  3099. WARN(!encoder->connectors_active,
  3100. "encoder->connectors_active not set\n");
  3101. encoder_enabled = encoder->get_hw_state(encoder, &pipe);
  3102. WARN(!encoder_enabled, "encoder not enabled\n");
  3103. if (WARN_ON(!encoder->base.crtc))
  3104. return;
  3105. crtc = encoder->base.crtc;
  3106. WARN(!crtc->enabled, "crtc not enabled\n");
  3107. WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
  3108. WARN(pipe != to_intel_crtc(crtc)->pipe,
  3109. "encoder active on the wrong pipe\n");
  3110. }
  3111. }
  3112. /* Even simpler default implementation, if there's really no special case to
  3113. * consider. */
  3114. void intel_connector_dpms(struct drm_connector *connector, int mode)
  3115. {
  3116. struct intel_encoder *encoder = intel_attached_encoder(connector);
  3117. /* All the simple cases only support two dpms states. */
  3118. if (mode != DRM_MODE_DPMS_ON)
  3119. mode = DRM_MODE_DPMS_OFF;
  3120. if (mode == connector->dpms)
  3121. return;
  3122. connector->dpms = mode;
  3123. /* Only need to change hw state when actually enabled */
  3124. if (encoder->base.crtc)
  3125. intel_encoder_dpms(encoder, mode);
  3126. else
  3127. WARN_ON(encoder->connectors_active != false);
  3128. intel_modeset_check_state(connector->dev);
  3129. }
  3130. /* Simple connector->get_hw_state implementation for encoders that support only
  3131. * one connector and no cloning and hence the encoder state determines the state
  3132. * of the connector. */
  3133. bool intel_connector_get_hw_state(struct intel_connector *connector)
  3134. {
  3135. enum pipe pipe = 0;
  3136. struct intel_encoder *encoder = connector->encoder;
  3137. return encoder->get_hw_state(encoder, &pipe);
  3138. }
  3139. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  3140. const struct drm_display_mode *mode,
  3141. struct drm_display_mode *adjusted_mode)
  3142. {
  3143. struct drm_device *dev = crtc->dev;
  3144. if (HAS_PCH_SPLIT(dev)) {
  3145. /* FDI link clock is fixed at 2.7G */
  3146. if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
  3147. return false;
  3148. }
  3149. /* All interlaced capable intel hw wants timings in frames. Note though
  3150. * that intel_lvds_mode_fixup does some funny tricks with the crtc
  3151. * timings, so we need to be careful not to clobber these.*/
  3152. if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
  3153. drm_mode_set_crtcinfo(adjusted_mode, 0);
  3154. /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
  3155. * with a hsync front porch of 0.
  3156. */
  3157. if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
  3158. adjusted_mode->hsync_start == adjusted_mode->hdisplay)
  3159. return false;
  3160. return true;
  3161. }
  3162. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  3163. {
  3164. return 400000; /* FIXME */
  3165. }
  3166. static int i945_get_display_clock_speed(struct drm_device *dev)
  3167. {
  3168. return 400000;
  3169. }
  3170. static int i915_get_display_clock_speed(struct drm_device *dev)
  3171. {
  3172. return 333000;
  3173. }
  3174. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  3175. {
  3176. return 200000;
  3177. }
  3178. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  3179. {
  3180. u16 gcfgc = 0;
  3181. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3182. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  3183. return 133000;
  3184. else {
  3185. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3186. case GC_DISPLAY_CLOCK_333_MHZ:
  3187. return 333000;
  3188. default:
  3189. case GC_DISPLAY_CLOCK_190_200_MHZ:
  3190. return 190000;
  3191. }
  3192. }
  3193. }
  3194. static int i865_get_display_clock_speed(struct drm_device *dev)
  3195. {
  3196. return 266000;
  3197. }
  3198. static int i855_get_display_clock_speed(struct drm_device *dev)
  3199. {
  3200. u16 hpllcc = 0;
  3201. /* Assume that the hardware is in the high speed state. This
  3202. * should be the default.
  3203. */
  3204. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  3205. case GC_CLOCK_133_200:
  3206. case GC_CLOCK_100_200:
  3207. return 200000;
  3208. case GC_CLOCK_166_250:
  3209. return 250000;
  3210. case GC_CLOCK_100_133:
  3211. return 133000;
  3212. }
  3213. /* Shouldn't happen */
  3214. return 0;
  3215. }
  3216. static int i830_get_display_clock_speed(struct drm_device *dev)
  3217. {
  3218. return 133000;
  3219. }
  3220. struct fdi_m_n {
  3221. u32 tu;
  3222. u32 gmch_m;
  3223. u32 gmch_n;
  3224. u32 link_m;
  3225. u32 link_n;
  3226. };
  3227. static void
  3228. fdi_reduce_ratio(u32 *num, u32 *den)
  3229. {
  3230. while (*num > 0xffffff || *den > 0xffffff) {
  3231. *num >>= 1;
  3232. *den >>= 1;
  3233. }
  3234. }
  3235. static void
  3236. ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
  3237. int link_clock, struct fdi_m_n *m_n)
  3238. {
  3239. m_n->tu = 64; /* default size */
  3240. /* BUG_ON(pixel_clock > INT_MAX / 36); */
  3241. m_n->gmch_m = bits_per_pixel * pixel_clock;
  3242. m_n->gmch_n = link_clock * nlanes * 8;
  3243. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  3244. m_n->link_m = pixel_clock;
  3245. m_n->link_n = link_clock;
  3246. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  3247. }
  3248. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  3249. {
  3250. if (i915_panel_use_ssc >= 0)
  3251. return i915_panel_use_ssc != 0;
  3252. return dev_priv->lvds_use_ssc
  3253. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  3254. }
  3255. /**
  3256. * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
  3257. * @crtc: CRTC structure
  3258. * @mode: requested mode
  3259. *
  3260. * A pipe may be connected to one or more outputs. Based on the depth of the
  3261. * attached framebuffer, choose a good color depth to use on the pipe.
  3262. *
  3263. * If possible, match the pipe depth to the fb depth. In some cases, this
  3264. * isn't ideal, because the connected output supports a lesser or restricted
  3265. * set of depths. Resolve that here:
  3266. * LVDS typically supports only 6bpc, so clamp down in that case
  3267. * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
  3268. * Displays may support a restricted set as well, check EDID and clamp as
  3269. * appropriate.
  3270. * DP may want to dither down to 6bpc to fit larger modes
  3271. *
  3272. * RETURNS:
  3273. * Dithering requirement (i.e. false if display bpc and pipe bpc match,
  3274. * true if they don't match).
  3275. */
  3276. static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
  3277. struct drm_framebuffer *fb,
  3278. unsigned int *pipe_bpp,
  3279. struct drm_display_mode *mode)
  3280. {
  3281. struct drm_device *dev = crtc->dev;
  3282. struct drm_i915_private *dev_priv = dev->dev_private;
  3283. struct drm_connector *connector;
  3284. struct intel_encoder *intel_encoder;
  3285. unsigned int display_bpc = UINT_MAX, bpc;
  3286. /* Walk the encoders & connectors on this crtc, get min bpc */
  3287. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  3288. if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
  3289. unsigned int lvds_bpc;
  3290. if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
  3291. LVDS_A3_POWER_UP)
  3292. lvds_bpc = 8;
  3293. else
  3294. lvds_bpc = 6;
  3295. if (lvds_bpc < display_bpc) {
  3296. DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
  3297. display_bpc = lvds_bpc;
  3298. }
  3299. continue;
  3300. }
  3301. /* Not one of the known troublemakers, check the EDID */
  3302. list_for_each_entry(connector, &dev->mode_config.connector_list,
  3303. head) {
  3304. if (connector->encoder != &intel_encoder->base)
  3305. continue;
  3306. /* Don't use an invalid EDID bpc value */
  3307. if (connector->display_info.bpc &&
  3308. connector->display_info.bpc < display_bpc) {
  3309. DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
  3310. display_bpc = connector->display_info.bpc;
  3311. }
  3312. }
  3313. /*
  3314. * HDMI is either 12 or 8, so if the display lets 10bpc sneak
  3315. * through, clamp it down. (Note: >12bpc will be caught below.)
  3316. */
  3317. if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
  3318. if (display_bpc > 8 && display_bpc < 12) {
  3319. DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
  3320. display_bpc = 12;
  3321. } else {
  3322. DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
  3323. display_bpc = 8;
  3324. }
  3325. }
  3326. }
  3327. if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
  3328. DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
  3329. display_bpc = 6;
  3330. }
  3331. /*
  3332. * We could just drive the pipe at the highest bpc all the time and
  3333. * enable dithering as needed, but that costs bandwidth. So choose
  3334. * the minimum value that expresses the full color range of the fb but
  3335. * also stays within the max display bpc discovered above.
  3336. */
  3337. switch (fb->depth) {
  3338. case 8:
  3339. bpc = 8; /* since we go through a colormap */
  3340. break;
  3341. case 15:
  3342. case 16:
  3343. bpc = 6; /* min is 18bpp */
  3344. break;
  3345. case 24:
  3346. bpc = 8;
  3347. break;
  3348. case 30:
  3349. bpc = 10;
  3350. break;
  3351. case 48:
  3352. bpc = 12;
  3353. break;
  3354. default:
  3355. DRM_DEBUG("unsupported depth, assuming 24 bits\n");
  3356. bpc = min((unsigned int)8, display_bpc);
  3357. break;
  3358. }
  3359. display_bpc = min(display_bpc, bpc);
  3360. DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
  3361. bpc, display_bpc);
  3362. *pipe_bpp = display_bpc * 3;
  3363. return display_bpc != bpc;
  3364. }
  3365. static int vlv_get_refclk(struct drm_crtc *crtc)
  3366. {
  3367. struct drm_device *dev = crtc->dev;
  3368. struct drm_i915_private *dev_priv = dev->dev_private;
  3369. int refclk = 27000; /* for DP & HDMI */
  3370. return 100000; /* only one validated so far */
  3371. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  3372. refclk = 96000;
  3373. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  3374. if (intel_panel_use_ssc(dev_priv))
  3375. refclk = 100000;
  3376. else
  3377. refclk = 96000;
  3378. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
  3379. refclk = 100000;
  3380. }
  3381. return refclk;
  3382. }
  3383. static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
  3384. {
  3385. struct drm_device *dev = crtc->dev;
  3386. struct drm_i915_private *dev_priv = dev->dev_private;
  3387. int refclk;
  3388. if (IS_VALLEYVIEW(dev)) {
  3389. refclk = vlv_get_refclk(crtc);
  3390. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3391. intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3392. refclk = dev_priv->lvds_ssc_freq * 1000;
  3393. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3394. refclk / 1000);
  3395. } else if (!IS_GEN2(dev)) {
  3396. refclk = 96000;
  3397. } else {
  3398. refclk = 48000;
  3399. }
  3400. return refclk;
  3401. }
  3402. static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
  3403. intel_clock_t *clock)
  3404. {
  3405. /* SDVO TV has fixed PLL values depend on its clock range,
  3406. this mirrors vbios setting. */
  3407. if (adjusted_mode->clock >= 100000
  3408. && adjusted_mode->clock < 140500) {
  3409. clock->p1 = 2;
  3410. clock->p2 = 10;
  3411. clock->n = 3;
  3412. clock->m1 = 16;
  3413. clock->m2 = 8;
  3414. } else if (adjusted_mode->clock >= 140500
  3415. && adjusted_mode->clock <= 200000) {
  3416. clock->p1 = 1;
  3417. clock->p2 = 10;
  3418. clock->n = 6;
  3419. clock->m1 = 12;
  3420. clock->m2 = 8;
  3421. }
  3422. }
  3423. static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
  3424. intel_clock_t *clock,
  3425. intel_clock_t *reduced_clock)
  3426. {
  3427. struct drm_device *dev = crtc->dev;
  3428. struct drm_i915_private *dev_priv = dev->dev_private;
  3429. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3430. int pipe = intel_crtc->pipe;
  3431. u32 fp, fp2 = 0;
  3432. if (IS_PINEVIEW(dev)) {
  3433. fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
  3434. if (reduced_clock)
  3435. fp2 = (1 << reduced_clock->n) << 16 |
  3436. reduced_clock->m1 << 8 | reduced_clock->m2;
  3437. } else {
  3438. fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
  3439. if (reduced_clock)
  3440. fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
  3441. reduced_clock->m2;
  3442. }
  3443. I915_WRITE(FP0(pipe), fp);
  3444. intel_crtc->lowfreq_avail = false;
  3445. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3446. reduced_clock && i915_powersave) {
  3447. I915_WRITE(FP1(pipe), fp2);
  3448. intel_crtc->lowfreq_avail = true;
  3449. } else {
  3450. I915_WRITE(FP1(pipe), fp);
  3451. }
  3452. }
  3453. static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
  3454. struct drm_display_mode *adjusted_mode)
  3455. {
  3456. struct drm_device *dev = crtc->dev;
  3457. struct drm_i915_private *dev_priv = dev->dev_private;
  3458. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3459. int pipe = intel_crtc->pipe;
  3460. u32 temp;
  3461. temp = I915_READ(LVDS);
  3462. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  3463. if (pipe == 1) {
  3464. temp |= LVDS_PIPEB_SELECT;
  3465. } else {
  3466. temp &= ~LVDS_PIPEB_SELECT;
  3467. }
  3468. /* set the corresponsding LVDS_BORDER bit */
  3469. temp |= dev_priv->lvds_border_bits;
  3470. /* Set the B0-B3 data pairs corresponding to whether we're going to
  3471. * set the DPLLs for dual-channel mode or not.
  3472. */
  3473. if (clock->p2 == 7)
  3474. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  3475. else
  3476. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  3477. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  3478. * appropriately here, but we need to look more thoroughly into how
  3479. * panels behave in the two modes.
  3480. */
  3481. /* set the dithering flag on LVDS as needed */
  3482. if (INTEL_INFO(dev)->gen >= 4) {
  3483. if (dev_priv->lvds_dither)
  3484. temp |= LVDS_ENABLE_DITHER;
  3485. else
  3486. temp &= ~LVDS_ENABLE_DITHER;
  3487. }
  3488. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  3489. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  3490. temp |= LVDS_HSYNC_POLARITY;
  3491. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  3492. temp |= LVDS_VSYNC_POLARITY;
  3493. I915_WRITE(LVDS, temp);
  3494. }
  3495. static void vlv_update_pll(struct drm_crtc *crtc,
  3496. struct drm_display_mode *mode,
  3497. struct drm_display_mode *adjusted_mode,
  3498. intel_clock_t *clock, intel_clock_t *reduced_clock,
  3499. int refclk, int num_connectors)
  3500. {
  3501. struct drm_device *dev = crtc->dev;
  3502. struct drm_i915_private *dev_priv = dev->dev_private;
  3503. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3504. int pipe = intel_crtc->pipe;
  3505. u32 dpll, mdiv, pdiv;
  3506. u32 bestn, bestm1, bestm2, bestp1, bestp2;
  3507. bool is_hdmi;
  3508. is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
  3509. bestn = clock->n;
  3510. bestm1 = clock->m1;
  3511. bestm2 = clock->m2;
  3512. bestp1 = clock->p1;
  3513. bestp2 = clock->p2;
  3514. /* Enable DPIO clock input */
  3515. dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
  3516. DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
  3517. I915_WRITE(DPLL(pipe), dpll);
  3518. POSTING_READ(DPLL(pipe));
  3519. mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  3520. mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  3521. mdiv |= ((bestn << DPIO_N_SHIFT));
  3522. mdiv |= (1 << DPIO_POST_DIV_SHIFT);
  3523. mdiv |= (1 << DPIO_K_SHIFT);
  3524. mdiv |= DPIO_ENABLE_CALIBRATION;
  3525. intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
  3526. intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
  3527. pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
  3528. (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
  3529. (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
  3530. intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
  3531. intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
  3532. dpll |= DPLL_VCO_ENABLE;
  3533. I915_WRITE(DPLL(pipe), dpll);
  3534. POSTING_READ(DPLL(pipe));
  3535. if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  3536. DRM_ERROR("DPLL %d failed to lock\n", pipe);
  3537. if (is_hdmi) {
  3538. u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
  3539. if (temp > 1)
  3540. temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3541. else
  3542. temp = 0;
  3543. I915_WRITE(DPLL_MD(pipe), temp);
  3544. POSTING_READ(DPLL_MD(pipe));
  3545. }
  3546. intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
  3547. }
  3548. static void i9xx_update_pll(struct drm_crtc *crtc,
  3549. struct drm_display_mode *mode,
  3550. struct drm_display_mode *adjusted_mode,
  3551. intel_clock_t *clock, intel_clock_t *reduced_clock,
  3552. int num_connectors)
  3553. {
  3554. struct drm_device *dev = crtc->dev;
  3555. struct drm_i915_private *dev_priv = dev->dev_private;
  3556. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3557. int pipe = intel_crtc->pipe;
  3558. u32 dpll;
  3559. bool is_sdvo;
  3560. is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
  3561. intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
  3562. dpll = DPLL_VGA_MODE_DIS;
  3563. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  3564. dpll |= DPLLB_MODE_LVDS;
  3565. else
  3566. dpll |= DPLLB_MODE_DAC_SERIAL;
  3567. if (is_sdvo) {
  3568. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  3569. if (pixel_multiplier > 1) {
  3570. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  3571. dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  3572. }
  3573. dpll |= DPLL_DVO_HIGH_SPEED;
  3574. }
  3575. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
  3576. dpll |= DPLL_DVO_HIGH_SPEED;
  3577. /* compute bitmask from p1 value */
  3578. if (IS_PINEVIEW(dev))
  3579. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3580. else {
  3581. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3582. if (IS_G4X(dev) && reduced_clock)
  3583. dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3584. }
  3585. switch (clock->p2) {
  3586. case 5:
  3587. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3588. break;
  3589. case 7:
  3590. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3591. break;
  3592. case 10:
  3593. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3594. break;
  3595. case 14:
  3596. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3597. break;
  3598. }
  3599. if (INTEL_INFO(dev)->gen >= 4)
  3600. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3601. if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
  3602. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3603. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
  3604. /* XXX: just matching BIOS for now */
  3605. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3606. dpll |= 3;
  3607. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3608. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3609. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3610. else
  3611. dpll |= PLL_REF_INPUT_DREFCLK;
  3612. dpll |= DPLL_VCO_ENABLE;
  3613. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  3614. POSTING_READ(DPLL(pipe));
  3615. udelay(150);
  3616. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  3617. * This is an exception to the general rule that mode_set doesn't turn
  3618. * things on.
  3619. */
  3620. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  3621. intel_update_lvds(crtc, clock, adjusted_mode);
  3622. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
  3623. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  3624. I915_WRITE(DPLL(pipe), dpll);
  3625. /* Wait for the clocks to stabilize. */
  3626. POSTING_READ(DPLL(pipe));
  3627. udelay(150);
  3628. if (INTEL_INFO(dev)->gen >= 4) {
  3629. u32 temp = 0;
  3630. if (is_sdvo) {
  3631. temp = intel_mode_get_pixel_multiplier(adjusted_mode);
  3632. if (temp > 1)
  3633. temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3634. else
  3635. temp = 0;
  3636. }
  3637. I915_WRITE(DPLL_MD(pipe), temp);
  3638. } else {
  3639. /* The pixel multiplier can only be updated once the
  3640. * DPLL is enabled and the clocks are stable.
  3641. *
  3642. * So write it again.
  3643. */
  3644. I915_WRITE(DPLL(pipe), dpll);
  3645. }
  3646. }
  3647. static void i8xx_update_pll(struct drm_crtc *crtc,
  3648. struct drm_display_mode *adjusted_mode,
  3649. intel_clock_t *clock,
  3650. int num_connectors)
  3651. {
  3652. struct drm_device *dev = crtc->dev;
  3653. struct drm_i915_private *dev_priv = dev->dev_private;
  3654. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3655. int pipe = intel_crtc->pipe;
  3656. u32 dpll;
  3657. dpll = DPLL_VGA_MODE_DIS;
  3658. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  3659. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3660. } else {
  3661. if (clock->p1 == 2)
  3662. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3663. else
  3664. dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3665. if (clock->p2 == 4)
  3666. dpll |= PLL_P2_DIVIDE_BY_4;
  3667. }
  3668. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
  3669. /* XXX: just matching BIOS for now */
  3670. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3671. dpll |= 3;
  3672. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3673. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3674. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3675. else
  3676. dpll |= PLL_REF_INPUT_DREFCLK;
  3677. dpll |= DPLL_VCO_ENABLE;
  3678. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  3679. POSTING_READ(DPLL(pipe));
  3680. udelay(150);
  3681. I915_WRITE(DPLL(pipe), dpll);
  3682. /* Wait for the clocks to stabilize. */
  3683. POSTING_READ(DPLL(pipe));
  3684. udelay(150);
  3685. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  3686. * This is an exception to the general rule that mode_set doesn't turn
  3687. * things on.
  3688. */
  3689. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  3690. intel_update_lvds(crtc, clock, adjusted_mode);
  3691. /* The pixel multiplier can only be updated once the
  3692. * DPLL is enabled and the clocks are stable.
  3693. *
  3694. * So write it again.
  3695. */
  3696. I915_WRITE(DPLL(pipe), dpll);
  3697. }
  3698. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  3699. struct drm_display_mode *mode,
  3700. struct drm_display_mode *adjusted_mode,
  3701. int x, int y,
  3702. struct drm_framebuffer *fb)
  3703. {
  3704. struct drm_device *dev = crtc->dev;
  3705. struct drm_i915_private *dev_priv = dev->dev_private;
  3706. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3707. int pipe = intel_crtc->pipe;
  3708. int plane = intel_crtc->plane;
  3709. int refclk, num_connectors = 0;
  3710. intel_clock_t clock, reduced_clock;
  3711. u32 dspcntr, pipeconf, vsyncshift;
  3712. bool ok, has_reduced_clock = false, is_sdvo = false;
  3713. bool is_lvds = false, is_tv = false, is_dp = false;
  3714. struct intel_encoder *encoder;
  3715. const intel_limit_t *limit;
  3716. int ret;
  3717. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3718. switch (encoder->type) {
  3719. case INTEL_OUTPUT_LVDS:
  3720. is_lvds = true;
  3721. break;
  3722. case INTEL_OUTPUT_SDVO:
  3723. case INTEL_OUTPUT_HDMI:
  3724. is_sdvo = true;
  3725. if (encoder->needs_tv_clock)
  3726. is_tv = true;
  3727. break;
  3728. case INTEL_OUTPUT_TVOUT:
  3729. is_tv = true;
  3730. break;
  3731. case INTEL_OUTPUT_DISPLAYPORT:
  3732. is_dp = true;
  3733. break;
  3734. }
  3735. num_connectors++;
  3736. }
  3737. refclk = i9xx_get_refclk(crtc, num_connectors);
  3738. /*
  3739. * Returns a set of divisors for the desired target clock with the given
  3740. * refclk, or FALSE. The returned values represent the clock equation:
  3741. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  3742. */
  3743. limit = intel_limit(crtc, refclk);
  3744. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
  3745. &clock);
  3746. if (!ok) {
  3747. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  3748. return -EINVAL;
  3749. }
  3750. /* Ensure that the cursor is valid for the new mode before changing... */
  3751. intel_crtc_update_cursor(crtc, true);
  3752. if (is_lvds && dev_priv->lvds_downclock_avail) {
  3753. /*
  3754. * Ensure we match the reduced clock's P to the target clock.
  3755. * If the clocks don't match, we can't switch the display clock
  3756. * by using the FP0/FP1. In such case we will disable the LVDS
  3757. * downclock feature.
  3758. */
  3759. has_reduced_clock = limit->find_pll(limit, crtc,
  3760. dev_priv->lvds_downclock,
  3761. refclk,
  3762. &clock,
  3763. &reduced_clock);
  3764. }
  3765. if (is_sdvo && is_tv)
  3766. i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
  3767. i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
  3768. &reduced_clock : NULL);
  3769. if (IS_GEN2(dev))
  3770. i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
  3771. else if (IS_VALLEYVIEW(dev))
  3772. vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
  3773. refclk, num_connectors);
  3774. else
  3775. i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
  3776. has_reduced_clock ? &reduced_clock : NULL,
  3777. num_connectors);
  3778. /* setup pipeconf */
  3779. pipeconf = I915_READ(PIPECONF(pipe));
  3780. /* Set up the display plane register */
  3781. dspcntr = DISPPLANE_GAMMA_ENABLE;
  3782. if (pipe == 0)
  3783. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  3784. else
  3785. dspcntr |= DISPPLANE_SEL_PIPE_B;
  3786. if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
  3787. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  3788. * core speed.
  3789. *
  3790. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  3791. * pipe == 0 check?
  3792. */
  3793. if (mode->clock >
  3794. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  3795. pipeconf |= PIPECONF_DOUBLE_WIDE;
  3796. else
  3797. pipeconf &= ~PIPECONF_DOUBLE_WIDE;
  3798. }
  3799. /* default to 8bpc */
  3800. pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
  3801. if (is_dp) {
  3802. if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
  3803. pipeconf |= PIPECONF_BPP_6 |
  3804. PIPECONF_DITHER_EN |
  3805. PIPECONF_DITHER_TYPE_SP;
  3806. }
  3807. }
  3808. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  3809. drm_mode_debug_printmodeline(mode);
  3810. if (HAS_PIPE_CXSR(dev)) {
  3811. if (intel_crtc->lowfreq_avail) {
  3812. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  3813. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  3814. } else {
  3815. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  3816. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  3817. }
  3818. }
  3819. pipeconf &= ~PIPECONF_INTERLACE_MASK;
  3820. if (!IS_GEN2(dev) &&
  3821. adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  3822. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  3823. /* the chip adds 2 halflines automatically */
  3824. adjusted_mode->crtc_vtotal -= 1;
  3825. adjusted_mode->crtc_vblank_end -= 1;
  3826. vsyncshift = adjusted_mode->crtc_hsync_start
  3827. - adjusted_mode->crtc_htotal/2;
  3828. } else {
  3829. pipeconf |= PIPECONF_PROGRESSIVE;
  3830. vsyncshift = 0;
  3831. }
  3832. if (!IS_GEN3(dev))
  3833. I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
  3834. I915_WRITE(HTOTAL(pipe),
  3835. (adjusted_mode->crtc_hdisplay - 1) |
  3836. ((adjusted_mode->crtc_htotal - 1) << 16));
  3837. I915_WRITE(HBLANK(pipe),
  3838. (adjusted_mode->crtc_hblank_start - 1) |
  3839. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  3840. I915_WRITE(HSYNC(pipe),
  3841. (adjusted_mode->crtc_hsync_start - 1) |
  3842. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  3843. I915_WRITE(VTOTAL(pipe),
  3844. (adjusted_mode->crtc_vdisplay - 1) |
  3845. ((adjusted_mode->crtc_vtotal - 1) << 16));
  3846. I915_WRITE(VBLANK(pipe),
  3847. (adjusted_mode->crtc_vblank_start - 1) |
  3848. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  3849. I915_WRITE(VSYNC(pipe),
  3850. (adjusted_mode->crtc_vsync_start - 1) |
  3851. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  3852. /* pipesrc and dspsize control the size that is scaled from,
  3853. * which should always be the user's requested size.
  3854. */
  3855. I915_WRITE(DSPSIZE(plane),
  3856. ((mode->vdisplay - 1) << 16) |
  3857. (mode->hdisplay - 1));
  3858. I915_WRITE(DSPPOS(plane), 0);
  3859. I915_WRITE(PIPESRC(pipe),
  3860. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  3861. I915_WRITE(PIPECONF(pipe), pipeconf);
  3862. POSTING_READ(PIPECONF(pipe));
  3863. intel_enable_pipe(dev_priv, pipe, false);
  3864. intel_wait_for_vblank(dev, pipe);
  3865. I915_WRITE(DSPCNTR(plane), dspcntr);
  3866. POSTING_READ(DSPCNTR(plane));
  3867. ret = intel_pipe_set_base(crtc, x, y, fb);
  3868. intel_update_watermarks(dev);
  3869. return ret;
  3870. }
  3871. /*
  3872. * Initialize reference clocks when the driver loads
  3873. */
  3874. void ironlake_init_pch_refclk(struct drm_device *dev)
  3875. {
  3876. struct drm_i915_private *dev_priv = dev->dev_private;
  3877. struct drm_mode_config *mode_config = &dev->mode_config;
  3878. struct intel_encoder *encoder;
  3879. u32 temp;
  3880. bool has_lvds = false;
  3881. bool has_cpu_edp = false;
  3882. bool has_pch_edp = false;
  3883. bool has_panel = false;
  3884. bool has_ck505 = false;
  3885. bool can_ssc = false;
  3886. /* We need to take the global config into account */
  3887. list_for_each_entry(encoder, &mode_config->encoder_list,
  3888. base.head) {
  3889. switch (encoder->type) {
  3890. case INTEL_OUTPUT_LVDS:
  3891. has_panel = true;
  3892. has_lvds = true;
  3893. break;
  3894. case INTEL_OUTPUT_EDP:
  3895. has_panel = true;
  3896. if (intel_encoder_is_pch_edp(&encoder->base))
  3897. has_pch_edp = true;
  3898. else
  3899. has_cpu_edp = true;
  3900. break;
  3901. }
  3902. }
  3903. if (HAS_PCH_IBX(dev)) {
  3904. has_ck505 = dev_priv->display_clock_mode;
  3905. can_ssc = has_ck505;
  3906. } else {
  3907. has_ck505 = false;
  3908. can_ssc = true;
  3909. }
  3910. DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
  3911. has_panel, has_lvds, has_pch_edp, has_cpu_edp,
  3912. has_ck505);
  3913. /* Ironlake: try to setup display ref clock before DPLL
  3914. * enabling. This is only under driver's control after
  3915. * PCH B stepping, previous chipset stepping should be
  3916. * ignoring this setting.
  3917. */
  3918. temp = I915_READ(PCH_DREF_CONTROL);
  3919. /* Always enable nonspread source */
  3920. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  3921. if (has_ck505)
  3922. temp |= DREF_NONSPREAD_CK505_ENABLE;
  3923. else
  3924. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  3925. if (has_panel) {
  3926. temp &= ~DREF_SSC_SOURCE_MASK;
  3927. temp |= DREF_SSC_SOURCE_ENABLE;
  3928. /* SSC must be turned on before enabling the CPU output */
  3929. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  3930. DRM_DEBUG_KMS("Using SSC on panel\n");
  3931. temp |= DREF_SSC1_ENABLE;
  3932. } else
  3933. temp &= ~DREF_SSC1_ENABLE;
  3934. /* Get SSC going before enabling the outputs */
  3935. I915_WRITE(PCH_DREF_CONTROL, temp);
  3936. POSTING_READ(PCH_DREF_CONTROL);
  3937. udelay(200);
  3938. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  3939. /* Enable CPU source on CPU attached eDP */
  3940. if (has_cpu_edp) {
  3941. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  3942. DRM_DEBUG_KMS("Using SSC on eDP\n");
  3943. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  3944. }
  3945. else
  3946. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  3947. } else
  3948. temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  3949. I915_WRITE(PCH_DREF_CONTROL, temp);
  3950. POSTING_READ(PCH_DREF_CONTROL);
  3951. udelay(200);
  3952. } else {
  3953. DRM_DEBUG_KMS("Disabling SSC entirely\n");
  3954. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  3955. /* Turn off CPU output */
  3956. temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  3957. I915_WRITE(PCH_DREF_CONTROL, temp);
  3958. POSTING_READ(PCH_DREF_CONTROL);
  3959. udelay(200);
  3960. /* Turn off the SSC source */
  3961. temp &= ~DREF_SSC_SOURCE_MASK;
  3962. temp |= DREF_SSC_SOURCE_DISABLE;
  3963. /* Turn off SSC1 */
  3964. temp &= ~ DREF_SSC1_ENABLE;
  3965. I915_WRITE(PCH_DREF_CONTROL, temp);
  3966. POSTING_READ(PCH_DREF_CONTROL);
  3967. udelay(200);
  3968. }
  3969. }
  3970. static int ironlake_get_refclk(struct drm_crtc *crtc)
  3971. {
  3972. struct drm_device *dev = crtc->dev;
  3973. struct drm_i915_private *dev_priv = dev->dev_private;
  3974. struct intel_encoder *encoder;
  3975. struct intel_encoder *edp_encoder = NULL;
  3976. int num_connectors = 0;
  3977. bool is_lvds = false;
  3978. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3979. switch (encoder->type) {
  3980. case INTEL_OUTPUT_LVDS:
  3981. is_lvds = true;
  3982. break;
  3983. case INTEL_OUTPUT_EDP:
  3984. edp_encoder = encoder;
  3985. break;
  3986. }
  3987. num_connectors++;
  3988. }
  3989. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3990. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3991. dev_priv->lvds_ssc_freq);
  3992. return dev_priv->lvds_ssc_freq * 1000;
  3993. }
  3994. return 120000;
  3995. }
  3996. static void ironlake_set_pipeconf(struct drm_crtc *crtc,
  3997. struct drm_display_mode *adjusted_mode,
  3998. bool dither)
  3999. {
  4000. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4001. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4002. int pipe = intel_crtc->pipe;
  4003. uint32_t val;
  4004. val = I915_READ(PIPECONF(pipe));
  4005. val &= ~PIPE_BPC_MASK;
  4006. switch (intel_crtc->bpp) {
  4007. case 18:
  4008. val |= PIPE_6BPC;
  4009. break;
  4010. case 24:
  4011. val |= PIPE_8BPC;
  4012. break;
  4013. case 30:
  4014. val |= PIPE_10BPC;
  4015. break;
  4016. case 36:
  4017. val |= PIPE_12BPC;
  4018. break;
  4019. default:
  4020. val |= PIPE_8BPC;
  4021. break;
  4022. }
  4023. val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
  4024. if (dither)
  4025. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4026. val &= ~PIPECONF_INTERLACE_MASK;
  4027. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  4028. val |= PIPECONF_INTERLACED_ILK;
  4029. else
  4030. val |= PIPECONF_PROGRESSIVE;
  4031. I915_WRITE(PIPECONF(pipe), val);
  4032. POSTING_READ(PIPECONF(pipe));
  4033. }
  4034. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  4035. struct drm_display_mode *mode,
  4036. struct drm_display_mode *adjusted_mode,
  4037. int x, int y,
  4038. struct drm_framebuffer *fb)
  4039. {
  4040. struct drm_device *dev = crtc->dev;
  4041. struct drm_i915_private *dev_priv = dev->dev_private;
  4042. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4043. int pipe = intel_crtc->pipe;
  4044. int plane = intel_crtc->plane;
  4045. int refclk, num_connectors = 0;
  4046. intel_clock_t clock, reduced_clock;
  4047. u32 dpll, fp = 0, fp2 = 0, dspcntr;
  4048. bool ok, has_reduced_clock = false, is_sdvo = false;
  4049. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  4050. struct intel_encoder *encoder, *edp_encoder = NULL;
  4051. const intel_limit_t *limit;
  4052. int ret;
  4053. struct fdi_m_n m_n = {0};
  4054. u32 temp;
  4055. int target_clock, pixel_multiplier, lane, link_bw, factor;
  4056. unsigned int pipe_bpp;
  4057. bool dither;
  4058. bool is_cpu_edp = false, is_pch_edp = false;
  4059. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4060. switch (encoder->type) {
  4061. case INTEL_OUTPUT_LVDS:
  4062. is_lvds = true;
  4063. break;
  4064. case INTEL_OUTPUT_SDVO:
  4065. case INTEL_OUTPUT_HDMI:
  4066. is_sdvo = true;
  4067. if (encoder->needs_tv_clock)
  4068. is_tv = true;
  4069. break;
  4070. case INTEL_OUTPUT_TVOUT:
  4071. is_tv = true;
  4072. break;
  4073. case INTEL_OUTPUT_ANALOG:
  4074. is_crt = true;
  4075. break;
  4076. case INTEL_OUTPUT_DISPLAYPORT:
  4077. is_dp = true;
  4078. break;
  4079. case INTEL_OUTPUT_EDP:
  4080. is_dp = true;
  4081. if (intel_encoder_is_pch_edp(&encoder->base))
  4082. is_pch_edp = true;
  4083. else
  4084. is_cpu_edp = true;
  4085. edp_encoder = encoder;
  4086. break;
  4087. }
  4088. num_connectors++;
  4089. }
  4090. refclk = ironlake_get_refclk(crtc);
  4091. /*
  4092. * Returns a set of divisors for the desired target clock with the given
  4093. * refclk, or FALSE. The returned values represent the clock equation:
  4094. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4095. */
  4096. limit = intel_limit(crtc, refclk);
  4097. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
  4098. &clock);
  4099. if (!ok) {
  4100. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4101. return -EINVAL;
  4102. }
  4103. /* Ensure that the cursor is valid for the new mode before changing... */
  4104. intel_crtc_update_cursor(crtc, true);
  4105. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4106. /*
  4107. * Ensure we match the reduced clock's P to the target clock.
  4108. * If the clocks don't match, we can't switch the display clock
  4109. * by using the FP0/FP1. In such case we will disable the LVDS
  4110. * downclock feature.
  4111. */
  4112. has_reduced_clock = limit->find_pll(limit, crtc,
  4113. dev_priv->lvds_downclock,
  4114. refclk,
  4115. &clock,
  4116. &reduced_clock);
  4117. }
  4118. if (is_sdvo && is_tv)
  4119. i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
  4120. /* FDI link */
  4121. pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4122. lane = 0;
  4123. /* CPU eDP doesn't require FDI link, so just set DP M/N
  4124. according to current link config */
  4125. if (is_cpu_edp) {
  4126. intel_edp_link_config(edp_encoder, &lane, &link_bw);
  4127. } else {
  4128. /* FDI is a binary signal running at ~2.7GHz, encoding
  4129. * each output octet as 10 bits. The actual frequency
  4130. * is stored as a divider into a 100MHz clock, and the
  4131. * mode pixel clock is stored in units of 1KHz.
  4132. * Hence the bw of each lane in terms of the mode signal
  4133. * is:
  4134. */
  4135. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  4136. }
  4137. /* [e]DP over FDI requires target mode clock instead of link clock. */
  4138. if (edp_encoder)
  4139. target_clock = intel_edp_target_clock(edp_encoder, mode);
  4140. else if (is_dp)
  4141. target_clock = mode->clock;
  4142. else
  4143. target_clock = adjusted_mode->clock;
  4144. /* determine panel color depth */
  4145. dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
  4146. if (is_lvds && dev_priv->lvds_dither)
  4147. dither = true;
  4148. if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
  4149. pipe_bpp != 36) {
  4150. WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
  4151. pipe_bpp);
  4152. pipe_bpp = 24;
  4153. }
  4154. intel_crtc->bpp = pipe_bpp;
  4155. if (!lane) {
  4156. /*
  4157. * Account for spread spectrum to avoid
  4158. * oversubscribing the link. Max center spread
  4159. * is 2.5%; use 5% for safety's sake.
  4160. */
  4161. u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
  4162. lane = bps / (link_bw * 8) + 1;
  4163. }
  4164. intel_crtc->fdi_lanes = lane;
  4165. if (pixel_multiplier > 1)
  4166. link_bw *= pixel_multiplier;
  4167. ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
  4168. &m_n);
  4169. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  4170. if (has_reduced_clock)
  4171. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  4172. reduced_clock.m2;
  4173. /* Enable autotuning of the PLL clock (if permissible) */
  4174. factor = 21;
  4175. if (is_lvds) {
  4176. if ((intel_panel_use_ssc(dev_priv) &&
  4177. dev_priv->lvds_ssc_freq == 100) ||
  4178. (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
  4179. factor = 25;
  4180. } else if (is_sdvo && is_tv)
  4181. factor = 20;
  4182. if (clock.m < factor * clock.n)
  4183. fp |= FP_CB_TUNE;
  4184. dpll = 0;
  4185. if (is_lvds)
  4186. dpll |= DPLLB_MODE_LVDS;
  4187. else
  4188. dpll |= DPLLB_MODE_DAC_SERIAL;
  4189. if (is_sdvo) {
  4190. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4191. if (pixel_multiplier > 1) {
  4192. dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  4193. }
  4194. dpll |= DPLL_DVO_HIGH_SPEED;
  4195. }
  4196. if (is_dp && !is_cpu_edp)
  4197. dpll |= DPLL_DVO_HIGH_SPEED;
  4198. /* compute bitmask from p1 value */
  4199. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4200. /* also FPA1 */
  4201. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4202. switch (clock.p2) {
  4203. case 5:
  4204. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4205. break;
  4206. case 7:
  4207. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4208. break;
  4209. case 10:
  4210. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4211. break;
  4212. case 14:
  4213. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4214. break;
  4215. }
  4216. if (is_sdvo && is_tv)
  4217. dpll |= PLL_REF_INPUT_TVCLKINBC;
  4218. else if (is_tv)
  4219. /* XXX: just matching BIOS for now */
  4220. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  4221. dpll |= 3;
  4222. else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4223. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4224. else
  4225. dpll |= PLL_REF_INPUT_DREFCLK;
  4226. /* Set up the display plane register */
  4227. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4228. DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
  4229. drm_mode_debug_printmodeline(mode);
  4230. /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
  4231. * pre-Haswell/LPT generation */
  4232. if (HAS_PCH_LPT(dev)) {
  4233. DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
  4234. pipe);
  4235. } else if (!is_cpu_edp) {
  4236. struct intel_pch_pll *pll;
  4237. pll = intel_get_pch_pll(intel_crtc, dpll, fp);
  4238. if (pll == NULL) {
  4239. DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
  4240. pipe);
  4241. return -EINVAL;
  4242. }
  4243. } else
  4244. intel_put_pch_pll(intel_crtc);
  4245. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  4246. * This is an exception to the general rule that mode_set doesn't turn
  4247. * things on.
  4248. */
  4249. if (is_lvds) {
  4250. temp = I915_READ(PCH_LVDS);
  4251. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  4252. if (HAS_PCH_CPT(dev)) {
  4253. temp &= ~PORT_TRANS_SEL_MASK;
  4254. temp |= PORT_TRANS_SEL_CPT(pipe);
  4255. } else {
  4256. if (pipe == 1)
  4257. temp |= LVDS_PIPEB_SELECT;
  4258. else
  4259. temp &= ~LVDS_PIPEB_SELECT;
  4260. }
  4261. /* set the corresponsding LVDS_BORDER bit */
  4262. temp |= dev_priv->lvds_border_bits;
  4263. /* Set the B0-B3 data pairs corresponding to whether we're going to
  4264. * set the DPLLs for dual-channel mode or not.
  4265. */
  4266. if (clock.p2 == 7)
  4267. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  4268. else
  4269. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  4270. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  4271. * appropriately here, but we need to look more thoroughly into how
  4272. * panels behave in the two modes.
  4273. */
  4274. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  4275. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  4276. temp |= LVDS_HSYNC_POLARITY;
  4277. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  4278. temp |= LVDS_VSYNC_POLARITY;
  4279. I915_WRITE(PCH_LVDS, temp);
  4280. }
  4281. if (is_dp && !is_cpu_edp) {
  4282. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  4283. } else {
  4284. /* For non-DP output, clear any trans DP clock recovery setting.*/
  4285. I915_WRITE(TRANSDATA_M1(pipe), 0);
  4286. I915_WRITE(TRANSDATA_N1(pipe), 0);
  4287. I915_WRITE(TRANSDPLINK_M1(pipe), 0);
  4288. I915_WRITE(TRANSDPLINK_N1(pipe), 0);
  4289. }
  4290. if (intel_crtc->pch_pll) {
  4291. I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
  4292. /* Wait for the clocks to stabilize. */
  4293. POSTING_READ(intel_crtc->pch_pll->pll_reg);
  4294. udelay(150);
  4295. /* The pixel multiplier can only be updated once the
  4296. * DPLL is enabled and the clocks are stable.
  4297. *
  4298. * So write it again.
  4299. */
  4300. I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
  4301. }
  4302. intel_crtc->lowfreq_avail = false;
  4303. if (intel_crtc->pch_pll) {
  4304. if (is_lvds && has_reduced_clock && i915_powersave) {
  4305. I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
  4306. intel_crtc->lowfreq_avail = true;
  4307. } else {
  4308. I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
  4309. }
  4310. }
  4311. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  4312. /* the chip adds 2 halflines automatically */
  4313. adjusted_mode->crtc_vtotal -= 1;
  4314. adjusted_mode->crtc_vblank_end -= 1;
  4315. I915_WRITE(VSYNCSHIFT(pipe),
  4316. adjusted_mode->crtc_hsync_start
  4317. - adjusted_mode->crtc_htotal/2);
  4318. } else {
  4319. I915_WRITE(VSYNCSHIFT(pipe), 0);
  4320. }
  4321. I915_WRITE(HTOTAL(pipe),
  4322. (adjusted_mode->crtc_hdisplay - 1) |
  4323. ((adjusted_mode->crtc_htotal - 1) << 16));
  4324. I915_WRITE(HBLANK(pipe),
  4325. (adjusted_mode->crtc_hblank_start - 1) |
  4326. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4327. I915_WRITE(HSYNC(pipe),
  4328. (adjusted_mode->crtc_hsync_start - 1) |
  4329. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4330. I915_WRITE(VTOTAL(pipe),
  4331. (adjusted_mode->crtc_vdisplay - 1) |
  4332. ((adjusted_mode->crtc_vtotal - 1) << 16));
  4333. I915_WRITE(VBLANK(pipe),
  4334. (adjusted_mode->crtc_vblank_start - 1) |
  4335. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  4336. I915_WRITE(VSYNC(pipe),
  4337. (adjusted_mode->crtc_vsync_start - 1) |
  4338. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4339. /* pipesrc controls the size that is scaled from, which should
  4340. * always be the user's requested size.
  4341. */
  4342. I915_WRITE(PIPESRC(pipe),
  4343. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  4344. I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
  4345. I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
  4346. I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
  4347. I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
  4348. if (is_cpu_edp)
  4349. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  4350. ironlake_set_pipeconf(crtc, adjusted_mode, dither);
  4351. intel_wait_for_vblank(dev, pipe);
  4352. I915_WRITE(DSPCNTR(plane), dspcntr);
  4353. POSTING_READ(DSPCNTR(plane));
  4354. ret = intel_pipe_set_base(crtc, x, y, fb);
  4355. intel_update_watermarks(dev);
  4356. intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
  4357. return ret;
  4358. }
  4359. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  4360. struct drm_display_mode *mode,
  4361. struct drm_display_mode *adjusted_mode,
  4362. int x, int y,
  4363. struct drm_framebuffer *fb)
  4364. {
  4365. struct drm_device *dev = crtc->dev;
  4366. struct drm_i915_private *dev_priv = dev->dev_private;
  4367. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4368. int pipe = intel_crtc->pipe;
  4369. int ret;
  4370. drm_vblank_pre_modeset(dev, pipe);
  4371. ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
  4372. x, y, fb);
  4373. drm_vblank_post_modeset(dev, pipe);
  4374. return ret;
  4375. }
  4376. static bool intel_eld_uptodate(struct drm_connector *connector,
  4377. int reg_eldv, uint32_t bits_eldv,
  4378. int reg_elda, uint32_t bits_elda,
  4379. int reg_edid)
  4380. {
  4381. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4382. uint8_t *eld = connector->eld;
  4383. uint32_t i;
  4384. i = I915_READ(reg_eldv);
  4385. i &= bits_eldv;
  4386. if (!eld[0])
  4387. return !i;
  4388. if (!i)
  4389. return false;
  4390. i = I915_READ(reg_elda);
  4391. i &= ~bits_elda;
  4392. I915_WRITE(reg_elda, i);
  4393. for (i = 0; i < eld[2]; i++)
  4394. if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  4395. return false;
  4396. return true;
  4397. }
  4398. static void g4x_write_eld(struct drm_connector *connector,
  4399. struct drm_crtc *crtc)
  4400. {
  4401. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4402. uint8_t *eld = connector->eld;
  4403. uint32_t eldv;
  4404. uint32_t len;
  4405. uint32_t i;
  4406. i = I915_READ(G4X_AUD_VID_DID);
  4407. if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
  4408. eldv = G4X_ELDV_DEVCL_DEVBLC;
  4409. else
  4410. eldv = G4X_ELDV_DEVCTG;
  4411. if (intel_eld_uptodate(connector,
  4412. G4X_AUD_CNTL_ST, eldv,
  4413. G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
  4414. G4X_HDMIW_HDMIEDID))
  4415. return;
  4416. i = I915_READ(G4X_AUD_CNTL_ST);
  4417. i &= ~(eldv | G4X_ELD_ADDR);
  4418. len = (i >> 9) & 0x1f; /* ELD buffer size */
  4419. I915_WRITE(G4X_AUD_CNTL_ST, i);
  4420. if (!eld[0])
  4421. return;
  4422. len = min_t(uint8_t, eld[2], len);
  4423. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  4424. for (i = 0; i < len; i++)
  4425. I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
  4426. i = I915_READ(G4X_AUD_CNTL_ST);
  4427. i |= eldv;
  4428. I915_WRITE(G4X_AUD_CNTL_ST, i);
  4429. }
  4430. static void haswell_write_eld(struct drm_connector *connector,
  4431. struct drm_crtc *crtc)
  4432. {
  4433. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4434. uint8_t *eld = connector->eld;
  4435. struct drm_device *dev = crtc->dev;
  4436. uint32_t eldv;
  4437. uint32_t i;
  4438. int len;
  4439. int pipe = to_intel_crtc(crtc)->pipe;
  4440. int tmp;
  4441. int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
  4442. int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
  4443. int aud_config = HSW_AUD_CFG(pipe);
  4444. int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
  4445. DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
  4446. /* Audio output enable */
  4447. DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
  4448. tmp = I915_READ(aud_cntrl_st2);
  4449. tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
  4450. I915_WRITE(aud_cntrl_st2, tmp);
  4451. /* Wait for 1 vertical blank */
  4452. intel_wait_for_vblank(dev, pipe);
  4453. /* Set ELD valid state */
  4454. tmp = I915_READ(aud_cntrl_st2);
  4455. DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
  4456. tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
  4457. I915_WRITE(aud_cntrl_st2, tmp);
  4458. tmp = I915_READ(aud_cntrl_st2);
  4459. DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
  4460. /* Enable HDMI mode */
  4461. tmp = I915_READ(aud_config);
  4462. DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
  4463. /* clear N_programing_enable and N_value_index */
  4464. tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
  4465. I915_WRITE(aud_config, tmp);
  4466. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  4467. eldv = AUDIO_ELD_VALID_A << (pipe * 4);
  4468. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  4469. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  4470. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  4471. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  4472. } else
  4473. I915_WRITE(aud_config, 0);
  4474. if (intel_eld_uptodate(connector,
  4475. aud_cntrl_st2, eldv,
  4476. aud_cntl_st, IBX_ELD_ADDRESS,
  4477. hdmiw_hdmiedid))
  4478. return;
  4479. i = I915_READ(aud_cntrl_st2);
  4480. i &= ~eldv;
  4481. I915_WRITE(aud_cntrl_st2, i);
  4482. if (!eld[0])
  4483. return;
  4484. i = I915_READ(aud_cntl_st);
  4485. i &= ~IBX_ELD_ADDRESS;
  4486. I915_WRITE(aud_cntl_st, i);
  4487. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  4488. DRM_DEBUG_DRIVER("port num:%d\n", i);
  4489. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  4490. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  4491. for (i = 0; i < len; i++)
  4492. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  4493. i = I915_READ(aud_cntrl_st2);
  4494. i |= eldv;
  4495. I915_WRITE(aud_cntrl_st2, i);
  4496. }
  4497. static void ironlake_write_eld(struct drm_connector *connector,
  4498. struct drm_crtc *crtc)
  4499. {
  4500. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4501. uint8_t *eld = connector->eld;
  4502. uint32_t eldv;
  4503. uint32_t i;
  4504. int len;
  4505. int hdmiw_hdmiedid;
  4506. int aud_config;
  4507. int aud_cntl_st;
  4508. int aud_cntrl_st2;
  4509. int pipe = to_intel_crtc(crtc)->pipe;
  4510. if (HAS_PCH_IBX(connector->dev)) {
  4511. hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
  4512. aud_config = IBX_AUD_CFG(pipe);
  4513. aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
  4514. aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
  4515. } else {
  4516. hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
  4517. aud_config = CPT_AUD_CFG(pipe);
  4518. aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
  4519. aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
  4520. }
  4521. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  4522. i = I915_READ(aud_cntl_st);
  4523. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  4524. if (!i) {
  4525. DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  4526. /* operate blindly on all ports */
  4527. eldv = IBX_ELD_VALIDB;
  4528. eldv |= IBX_ELD_VALIDB << 4;
  4529. eldv |= IBX_ELD_VALIDB << 8;
  4530. } else {
  4531. DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
  4532. eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
  4533. }
  4534. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  4535. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  4536. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  4537. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  4538. } else
  4539. I915_WRITE(aud_config, 0);
  4540. if (intel_eld_uptodate(connector,
  4541. aud_cntrl_st2, eldv,
  4542. aud_cntl_st, IBX_ELD_ADDRESS,
  4543. hdmiw_hdmiedid))
  4544. return;
  4545. i = I915_READ(aud_cntrl_st2);
  4546. i &= ~eldv;
  4547. I915_WRITE(aud_cntrl_st2, i);
  4548. if (!eld[0])
  4549. return;
  4550. i = I915_READ(aud_cntl_st);
  4551. i &= ~IBX_ELD_ADDRESS;
  4552. I915_WRITE(aud_cntl_st, i);
  4553. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  4554. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  4555. for (i = 0; i < len; i++)
  4556. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  4557. i = I915_READ(aud_cntrl_st2);
  4558. i |= eldv;
  4559. I915_WRITE(aud_cntrl_st2, i);
  4560. }
  4561. void intel_write_eld(struct drm_encoder *encoder,
  4562. struct drm_display_mode *mode)
  4563. {
  4564. struct drm_crtc *crtc = encoder->crtc;
  4565. struct drm_connector *connector;
  4566. struct drm_device *dev = encoder->dev;
  4567. struct drm_i915_private *dev_priv = dev->dev_private;
  4568. connector = drm_select_eld(encoder, mode);
  4569. if (!connector)
  4570. return;
  4571. DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  4572. connector->base.id,
  4573. drm_get_connector_name(connector),
  4574. connector->encoder->base.id,
  4575. drm_get_encoder_name(connector->encoder));
  4576. connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
  4577. if (dev_priv->display.write_eld)
  4578. dev_priv->display.write_eld(connector, crtc);
  4579. }
  4580. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  4581. void intel_crtc_load_lut(struct drm_crtc *crtc)
  4582. {
  4583. struct drm_device *dev = crtc->dev;
  4584. struct drm_i915_private *dev_priv = dev->dev_private;
  4585. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4586. int palreg = PALETTE(intel_crtc->pipe);
  4587. int i;
  4588. /* The clocks have to be on to load the palette. */
  4589. if (!crtc->enabled || !intel_crtc->active)
  4590. return;
  4591. /* use legacy palette for Ironlake */
  4592. if (HAS_PCH_SPLIT(dev))
  4593. palreg = LGC_PALETTE(intel_crtc->pipe);
  4594. for (i = 0; i < 256; i++) {
  4595. I915_WRITE(palreg + 4 * i,
  4596. (intel_crtc->lut_r[i] << 16) |
  4597. (intel_crtc->lut_g[i] << 8) |
  4598. intel_crtc->lut_b[i]);
  4599. }
  4600. }
  4601. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  4602. {
  4603. struct drm_device *dev = crtc->dev;
  4604. struct drm_i915_private *dev_priv = dev->dev_private;
  4605. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4606. bool visible = base != 0;
  4607. u32 cntl;
  4608. if (intel_crtc->cursor_visible == visible)
  4609. return;
  4610. cntl = I915_READ(_CURACNTR);
  4611. if (visible) {
  4612. /* On these chipsets we can only modify the base whilst
  4613. * the cursor is disabled.
  4614. */
  4615. I915_WRITE(_CURABASE, base);
  4616. cntl &= ~(CURSOR_FORMAT_MASK);
  4617. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  4618. cntl |= CURSOR_ENABLE |
  4619. CURSOR_GAMMA_ENABLE |
  4620. CURSOR_FORMAT_ARGB;
  4621. } else
  4622. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  4623. I915_WRITE(_CURACNTR, cntl);
  4624. intel_crtc->cursor_visible = visible;
  4625. }
  4626. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  4627. {
  4628. struct drm_device *dev = crtc->dev;
  4629. struct drm_i915_private *dev_priv = dev->dev_private;
  4630. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4631. int pipe = intel_crtc->pipe;
  4632. bool visible = base != 0;
  4633. if (intel_crtc->cursor_visible != visible) {
  4634. uint32_t cntl = I915_READ(CURCNTR(pipe));
  4635. if (base) {
  4636. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  4637. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  4638. cntl |= pipe << 28; /* Connect to correct pipe */
  4639. } else {
  4640. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  4641. cntl |= CURSOR_MODE_DISABLE;
  4642. }
  4643. I915_WRITE(CURCNTR(pipe), cntl);
  4644. intel_crtc->cursor_visible = visible;
  4645. }
  4646. /* and commit changes on next vblank */
  4647. I915_WRITE(CURBASE(pipe), base);
  4648. }
  4649. static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
  4650. {
  4651. struct drm_device *dev = crtc->dev;
  4652. struct drm_i915_private *dev_priv = dev->dev_private;
  4653. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4654. int pipe = intel_crtc->pipe;
  4655. bool visible = base != 0;
  4656. if (intel_crtc->cursor_visible != visible) {
  4657. uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
  4658. if (base) {
  4659. cntl &= ~CURSOR_MODE;
  4660. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  4661. } else {
  4662. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  4663. cntl |= CURSOR_MODE_DISABLE;
  4664. }
  4665. I915_WRITE(CURCNTR_IVB(pipe), cntl);
  4666. intel_crtc->cursor_visible = visible;
  4667. }
  4668. /* and commit changes on next vblank */
  4669. I915_WRITE(CURBASE_IVB(pipe), base);
  4670. }
  4671. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  4672. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  4673. bool on)
  4674. {
  4675. struct drm_device *dev = crtc->dev;
  4676. struct drm_i915_private *dev_priv = dev->dev_private;
  4677. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4678. int pipe = intel_crtc->pipe;
  4679. int x = intel_crtc->cursor_x;
  4680. int y = intel_crtc->cursor_y;
  4681. u32 base, pos;
  4682. bool visible;
  4683. pos = 0;
  4684. if (on && crtc->enabled && crtc->fb) {
  4685. base = intel_crtc->cursor_addr;
  4686. if (x > (int) crtc->fb->width)
  4687. base = 0;
  4688. if (y > (int) crtc->fb->height)
  4689. base = 0;
  4690. } else
  4691. base = 0;
  4692. if (x < 0) {
  4693. if (x + intel_crtc->cursor_width < 0)
  4694. base = 0;
  4695. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  4696. x = -x;
  4697. }
  4698. pos |= x << CURSOR_X_SHIFT;
  4699. if (y < 0) {
  4700. if (y + intel_crtc->cursor_height < 0)
  4701. base = 0;
  4702. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  4703. y = -y;
  4704. }
  4705. pos |= y << CURSOR_Y_SHIFT;
  4706. visible = base != 0;
  4707. if (!visible && !intel_crtc->cursor_visible)
  4708. return;
  4709. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  4710. I915_WRITE(CURPOS_IVB(pipe), pos);
  4711. ivb_update_cursor(crtc, base);
  4712. } else {
  4713. I915_WRITE(CURPOS(pipe), pos);
  4714. if (IS_845G(dev) || IS_I865G(dev))
  4715. i845_update_cursor(crtc, base);
  4716. else
  4717. i9xx_update_cursor(crtc, base);
  4718. }
  4719. }
  4720. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  4721. struct drm_file *file,
  4722. uint32_t handle,
  4723. uint32_t width, uint32_t height)
  4724. {
  4725. struct drm_device *dev = crtc->dev;
  4726. struct drm_i915_private *dev_priv = dev->dev_private;
  4727. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4728. struct drm_i915_gem_object *obj;
  4729. uint32_t addr;
  4730. int ret;
  4731. /* if we want to turn off the cursor ignore width and height */
  4732. if (!handle) {
  4733. DRM_DEBUG_KMS("cursor off\n");
  4734. addr = 0;
  4735. obj = NULL;
  4736. mutex_lock(&dev->struct_mutex);
  4737. goto finish;
  4738. }
  4739. /* Currently we only support 64x64 cursors */
  4740. if (width != 64 || height != 64) {
  4741. DRM_ERROR("we currently only support 64x64 cursors\n");
  4742. return -EINVAL;
  4743. }
  4744. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  4745. if (&obj->base == NULL)
  4746. return -ENOENT;
  4747. if (obj->base.size < width * height * 4) {
  4748. DRM_ERROR("buffer is to small\n");
  4749. ret = -ENOMEM;
  4750. goto fail;
  4751. }
  4752. /* we only need to pin inside GTT if cursor is non-phy */
  4753. mutex_lock(&dev->struct_mutex);
  4754. if (!dev_priv->info->cursor_needs_physical) {
  4755. if (obj->tiling_mode) {
  4756. DRM_ERROR("cursor cannot be tiled\n");
  4757. ret = -EINVAL;
  4758. goto fail_locked;
  4759. }
  4760. ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
  4761. if (ret) {
  4762. DRM_ERROR("failed to move cursor bo into the GTT\n");
  4763. goto fail_locked;
  4764. }
  4765. ret = i915_gem_object_put_fence(obj);
  4766. if (ret) {
  4767. DRM_ERROR("failed to release fence for cursor");
  4768. goto fail_unpin;
  4769. }
  4770. addr = obj->gtt_offset;
  4771. } else {
  4772. int align = IS_I830(dev) ? 16 * 1024 : 256;
  4773. ret = i915_gem_attach_phys_object(dev, obj,
  4774. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  4775. align);
  4776. if (ret) {
  4777. DRM_ERROR("failed to attach phys object\n");
  4778. goto fail_locked;
  4779. }
  4780. addr = obj->phys_obj->handle->busaddr;
  4781. }
  4782. if (IS_GEN2(dev))
  4783. I915_WRITE(CURSIZE, (height << 12) | width);
  4784. finish:
  4785. if (intel_crtc->cursor_bo) {
  4786. if (dev_priv->info->cursor_needs_physical) {
  4787. if (intel_crtc->cursor_bo != obj)
  4788. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  4789. } else
  4790. i915_gem_object_unpin(intel_crtc->cursor_bo);
  4791. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  4792. }
  4793. mutex_unlock(&dev->struct_mutex);
  4794. intel_crtc->cursor_addr = addr;
  4795. intel_crtc->cursor_bo = obj;
  4796. intel_crtc->cursor_width = width;
  4797. intel_crtc->cursor_height = height;
  4798. intel_crtc_update_cursor(crtc, true);
  4799. return 0;
  4800. fail_unpin:
  4801. i915_gem_object_unpin(obj);
  4802. fail_locked:
  4803. mutex_unlock(&dev->struct_mutex);
  4804. fail:
  4805. drm_gem_object_unreference_unlocked(&obj->base);
  4806. return ret;
  4807. }
  4808. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  4809. {
  4810. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4811. intel_crtc->cursor_x = x;
  4812. intel_crtc->cursor_y = y;
  4813. intel_crtc_update_cursor(crtc, true);
  4814. return 0;
  4815. }
  4816. /** Sets the color ramps on behalf of RandR */
  4817. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  4818. u16 blue, int regno)
  4819. {
  4820. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4821. intel_crtc->lut_r[regno] = red >> 8;
  4822. intel_crtc->lut_g[regno] = green >> 8;
  4823. intel_crtc->lut_b[regno] = blue >> 8;
  4824. }
  4825. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  4826. u16 *blue, int regno)
  4827. {
  4828. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4829. *red = intel_crtc->lut_r[regno] << 8;
  4830. *green = intel_crtc->lut_g[regno] << 8;
  4831. *blue = intel_crtc->lut_b[regno] << 8;
  4832. }
  4833. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  4834. u16 *blue, uint32_t start, uint32_t size)
  4835. {
  4836. int end = (start + size > 256) ? 256 : start + size, i;
  4837. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4838. for (i = start; i < end; i++) {
  4839. intel_crtc->lut_r[i] = red[i] >> 8;
  4840. intel_crtc->lut_g[i] = green[i] >> 8;
  4841. intel_crtc->lut_b[i] = blue[i] >> 8;
  4842. }
  4843. intel_crtc_load_lut(crtc);
  4844. }
  4845. /**
  4846. * Get a pipe with a simple mode set on it for doing load-based monitor
  4847. * detection.
  4848. *
  4849. * It will be up to the load-detect code to adjust the pipe as appropriate for
  4850. * its requirements. The pipe will be connected to no other encoders.
  4851. *
  4852. * Currently this code will only succeed if there is a pipe with no encoders
  4853. * configured for it. In the future, it could choose to temporarily disable
  4854. * some outputs to free up a pipe for its use.
  4855. *
  4856. * \return crtc, or NULL if no pipes are available.
  4857. */
  4858. /* VESA 640x480x72Hz mode to set on the pipe */
  4859. static struct drm_display_mode load_detect_mode = {
  4860. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  4861. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  4862. };
  4863. static struct drm_framebuffer *
  4864. intel_framebuffer_create(struct drm_device *dev,
  4865. struct drm_mode_fb_cmd2 *mode_cmd,
  4866. struct drm_i915_gem_object *obj)
  4867. {
  4868. struct intel_framebuffer *intel_fb;
  4869. int ret;
  4870. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  4871. if (!intel_fb) {
  4872. drm_gem_object_unreference_unlocked(&obj->base);
  4873. return ERR_PTR(-ENOMEM);
  4874. }
  4875. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  4876. if (ret) {
  4877. drm_gem_object_unreference_unlocked(&obj->base);
  4878. kfree(intel_fb);
  4879. return ERR_PTR(ret);
  4880. }
  4881. return &intel_fb->base;
  4882. }
  4883. static u32
  4884. intel_framebuffer_pitch_for_width(int width, int bpp)
  4885. {
  4886. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  4887. return ALIGN(pitch, 64);
  4888. }
  4889. static u32
  4890. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  4891. {
  4892. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  4893. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  4894. }
  4895. static struct drm_framebuffer *
  4896. intel_framebuffer_create_for_mode(struct drm_device *dev,
  4897. struct drm_display_mode *mode,
  4898. int depth, int bpp)
  4899. {
  4900. struct drm_i915_gem_object *obj;
  4901. struct drm_mode_fb_cmd2 mode_cmd;
  4902. obj = i915_gem_alloc_object(dev,
  4903. intel_framebuffer_size_for_mode(mode, bpp));
  4904. if (obj == NULL)
  4905. return ERR_PTR(-ENOMEM);
  4906. mode_cmd.width = mode->hdisplay;
  4907. mode_cmd.height = mode->vdisplay;
  4908. mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  4909. bpp);
  4910. mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
  4911. return intel_framebuffer_create(dev, &mode_cmd, obj);
  4912. }
  4913. static struct drm_framebuffer *
  4914. mode_fits_in_fbdev(struct drm_device *dev,
  4915. struct drm_display_mode *mode)
  4916. {
  4917. struct drm_i915_private *dev_priv = dev->dev_private;
  4918. struct drm_i915_gem_object *obj;
  4919. struct drm_framebuffer *fb;
  4920. if (dev_priv->fbdev == NULL)
  4921. return NULL;
  4922. obj = dev_priv->fbdev->ifb.obj;
  4923. if (obj == NULL)
  4924. return NULL;
  4925. fb = &dev_priv->fbdev->ifb.base;
  4926. if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  4927. fb->bits_per_pixel))
  4928. return NULL;
  4929. if (obj->base.size < mode->vdisplay * fb->pitches[0])
  4930. return NULL;
  4931. return fb;
  4932. }
  4933. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  4934. struct drm_display_mode *mode,
  4935. struct intel_load_detect_pipe *old)
  4936. {
  4937. struct intel_crtc *intel_crtc;
  4938. struct intel_encoder *intel_encoder =
  4939. intel_attached_encoder(connector);
  4940. struct drm_crtc *possible_crtc;
  4941. struct drm_encoder *encoder = &intel_encoder->base;
  4942. struct drm_crtc *crtc = NULL;
  4943. struct drm_device *dev = encoder->dev;
  4944. struct drm_framebuffer *fb;
  4945. int i = -1;
  4946. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  4947. connector->base.id, drm_get_connector_name(connector),
  4948. encoder->base.id, drm_get_encoder_name(encoder));
  4949. /*
  4950. * Algorithm gets a little messy:
  4951. *
  4952. * - if the connector already has an assigned crtc, use it (but make
  4953. * sure it's on first)
  4954. *
  4955. * - try to find the first unused crtc that can drive this connector,
  4956. * and use that if we find one
  4957. */
  4958. /* See if we already have a CRTC for this connector */
  4959. if (encoder->crtc) {
  4960. crtc = encoder->crtc;
  4961. old->dpms_mode = connector->dpms;
  4962. old->load_detect_temp = false;
  4963. /* Make sure the crtc and connector are running */
  4964. if (connector->dpms != DRM_MODE_DPMS_ON)
  4965. connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  4966. return true;
  4967. }
  4968. /* Find an unused one (if possible) */
  4969. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  4970. i++;
  4971. if (!(encoder->possible_crtcs & (1 << i)))
  4972. continue;
  4973. if (!possible_crtc->enabled) {
  4974. crtc = possible_crtc;
  4975. break;
  4976. }
  4977. }
  4978. /*
  4979. * If we didn't find an unused CRTC, don't use any.
  4980. */
  4981. if (!crtc) {
  4982. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  4983. return false;
  4984. }
  4985. intel_encoder->new_crtc = to_intel_crtc(crtc);
  4986. to_intel_connector(connector)->new_encoder = intel_encoder;
  4987. intel_crtc = to_intel_crtc(crtc);
  4988. old->dpms_mode = connector->dpms;
  4989. old->load_detect_temp = true;
  4990. old->release_fb = NULL;
  4991. if (!mode)
  4992. mode = &load_detect_mode;
  4993. /* We need a framebuffer large enough to accommodate all accesses
  4994. * that the plane may generate whilst we perform load detection.
  4995. * We can not rely on the fbcon either being present (we get called
  4996. * during its initialisation to detect all boot displays, or it may
  4997. * not even exist) or that it is large enough to satisfy the
  4998. * requested mode.
  4999. */
  5000. fb = mode_fits_in_fbdev(dev, mode);
  5001. if (fb == NULL) {
  5002. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  5003. fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  5004. old->release_fb = fb;
  5005. } else
  5006. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  5007. if (IS_ERR(fb)) {
  5008. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  5009. goto fail;
  5010. }
  5011. if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
  5012. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  5013. if (old->release_fb)
  5014. old->release_fb->funcs->destroy(old->release_fb);
  5015. goto fail;
  5016. }
  5017. /* let the connector get through one full cycle before testing */
  5018. intel_wait_for_vblank(dev, intel_crtc->pipe);
  5019. return true;
  5020. fail:
  5021. connector->encoder = NULL;
  5022. encoder->crtc = NULL;
  5023. return false;
  5024. }
  5025. void intel_release_load_detect_pipe(struct drm_connector *connector,
  5026. struct intel_load_detect_pipe *old)
  5027. {
  5028. struct intel_encoder *intel_encoder =
  5029. intel_attached_encoder(connector);
  5030. struct drm_encoder *encoder = &intel_encoder->base;
  5031. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5032. connector->base.id, drm_get_connector_name(connector),
  5033. encoder->base.id, drm_get_encoder_name(encoder));
  5034. if (old->load_detect_temp) {
  5035. struct drm_crtc *crtc = encoder->crtc;
  5036. to_intel_connector(connector)->new_encoder = NULL;
  5037. intel_encoder->new_crtc = NULL;
  5038. intel_set_mode(crtc, NULL, 0, 0, NULL);
  5039. if (old->release_fb)
  5040. old->release_fb->funcs->destroy(old->release_fb);
  5041. return;
  5042. }
  5043. /* Switch crtc and encoder back off if necessary */
  5044. if (old->dpms_mode != DRM_MODE_DPMS_ON)
  5045. connector->funcs->dpms(connector, old->dpms_mode);
  5046. }
  5047. /* Returns the clock of the currently programmed mode of the given pipe. */
  5048. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  5049. {
  5050. struct drm_i915_private *dev_priv = dev->dev_private;
  5051. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5052. int pipe = intel_crtc->pipe;
  5053. u32 dpll = I915_READ(DPLL(pipe));
  5054. u32 fp;
  5055. intel_clock_t clock;
  5056. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  5057. fp = I915_READ(FP0(pipe));
  5058. else
  5059. fp = I915_READ(FP1(pipe));
  5060. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  5061. if (IS_PINEVIEW(dev)) {
  5062. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  5063. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5064. } else {
  5065. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  5066. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5067. }
  5068. if (!IS_GEN2(dev)) {
  5069. if (IS_PINEVIEW(dev))
  5070. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  5071. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  5072. else
  5073. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  5074. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5075. switch (dpll & DPLL_MODE_MASK) {
  5076. case DPLLB_MODE_DAC_SERIAL:
  5077. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  5078. 5 : 10;
  5079. break;
  5080. case DPLLB_MODE_LVDS:
  5081. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  5082. 7 : 14;
  5083. break;
  5084. default:
  5085. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  5086. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  5087. return 0;
  5088. }
  5089. /* XXX: Handle the 100Mhz refclk */
  5090. intel_clock(dev, 96000, &clock);
  5091. } else {
  5092. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  5093. if (is_lvds) {
  5094. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  5095. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5096. clock.p2 = 14;
  5097. if ((dpll & PLL_REF_INPUT_MASK) ==
  5098. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  5099. /* XXX: might not be 66MHz */
  5100. intel_clock(dev, 66000, &clock);
  5101. } else
  5102. intel_clock(dev, 48000, &clock);
  5103. } else {
  5104. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  5105. clock.p1 = 2;
  5106. else {
  5107. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  5108. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  5109. }
  5110. if (dpll & PLL_P2_DIVIDE_BY_4)
  5111. clock.p2 = 4;
  5112. else
  5113. clock.p2 = 2;
  5114. intel_clock(dev, 48000, &clock);
  5115. }
  5116. }
  5117. /* XXX: It would be nice to validate the clocks, but we can't reuse
  5118. * i830PllIsValid() because it relies on the xf86_config connector
  5119. * configuration being accurate, which it isn't necessarily.
  5120. */
  5121. return clock.dot;
  5122. }
  5123. /** Returns the currently programmed mode of the given pipe. */
  5124. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  5125. struct drm_crtc *crtc)
  5126. {
  5127. struct drm_i915_private *dev_priv = dev->dev_private;
  5128. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5129. int pipe = intel_crtc->pipe;
  5130. struct drm_display_mode *mode;
  5131. int htot = I915_READ(HTOTAL(pipe));
  5132. int hsync = I915_READ(HSYNC(pipe));
  5133. int vtot = I915_READ(VTOTAL(pipe));
  5134. int vsync = I915_READ(VSYNC(pipe));
  5135. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  5136. if (!mode)
  5137. return NULL;
  5138. mode->clock = intel_crtc_clock_get(dev, crtc);
  5139. mode->hdisplay = (htot & 0xffff) + 1;
  5140. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  5141. mode->hsync_start = (hsync & 0xffff) + 1;
  5142. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  5143. mode->vdisplay = (vtot & 0xffff) + 1;
  5144. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  5145. mode->vsync_start = (vsync & 0xffff) + 1;
  5146. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  5147. drm_mode_set_name(mode);
  5148. return mode;
  5149. }
  5150. static void intel_increase_pllclock(struct drm_crtc *crtc)
  5151. {
  5152. struct drm_device *dev = crtc->dev;
  5153. drm_i915_private_t *dev_priv = dev->dev_private;
  5154. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5155. int pipe = intel_crtc->pipe;
  5156. int dpll_reg = DPLL(pipe);
  5157. int dpll;
  5158. if (HAS_PCH_SPLIT(dev))
  5159. return;
  5160. if (!dev_priv->lvds_downclock_avail)
  5161. return;
  5162. dpll = I915_READ(dpll_reg);
  5163. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  5164. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  5165. assert_panel_unlocked(dev_priv, pipe);
  5166. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  5167. I915_WRITE(dpll_reg, dpll);
  5168. intel_wait_for_vblank(dev, pipe);
  5169. dpll = I915_READ(dpll_reg);
  5170. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  5171. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  5172. }
  5173. }
  5174. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  5175. {
  5176. struct drm_device *dev = crtc->dev;
  5177. drm_i915_private_t *dev_priv = dev->dev_private;
  5178. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5179. if (HAS_PCH_SPLIT(dev))
  5180. return;
  5181. if (!dev_priv->lvds_downclock_avail)
  5182. return;
  5183. /*
  5184. * Since this is called by a timer, we should never get here in
  5185. * the manual case.
  5186. */
  5187. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  5188. int pipe = intel_crtc->pipe;
  5189. int dpll_reg = DPLL(pipe);
  5190. int dpll;
  5191. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  5192. assert_panel_unlocked(dev_priv, pipe);
  5193. dpll = I915_READ(dpll_reg);
  5194. dpll |= DISPLAY_RATE_SELECT_FPA1;
  5195. I915_WRITE(dpll_reg, dpll);
  5196. intel_wait_for_vblank(dev, pipe);
  5197. dpll = I915_READ(dpll_reg);
  5198. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  5199. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  5200. }
  5201. }
  5202. void intel_mark_busy(struct drm_device *dev)
  5203. {
  5204. i915_update_gfx_val(dev->dev_private);
  5205. }
  5206. void intel_mark_idle(struct drm_device *dev)
  5207. {
  5208. }
  5209. void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
  5210. {
  5211. struct drm_device *dev = obj->base.dev;
  5212. struct drm_crtc *crtc;
  5213. if (!i915_powersave)
  5214. return;
  5215. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5216. if (!crtc->fb)
  5217. continue;
  5218. if (to_intel_framebuffer(crtc->fb)->obj == obj)
  5219. intel_increase_pllclock(crtc);
  5220. }
  5221. }
  5222. void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
  5223. {
  5224. struct drm_device *dev = obj->base.dev;
  5225. struct drm_crtc *crtc;
  5226. if (!i915_powersave)
  5227. return;
  5228. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5229. if (!crtc->fb)
  5230. continue;
  5231. if (to_intel_framebuffer(crtc->fb)->obj == obj)
  5232. intel_decrease_pllclock(crtc);
  5233. }
  5234. }
  5235. static void intel_crtc_destroy(struct drm_crtc *crtc)
  5236. {
  5237. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5238. struct drm_device *dev = crtc->dev;
  5239. struct intel_unpin_work *work;
  5240. unsigned long flags;
  5241. spin_lock_irqsave(&dev->event_lock, flags);
  5242. work = intel_crtc->unpin_work;
  5243. intel_crtc->unpin_work = NULL;
  5244. spin_unlock_irqrestore(&dev->event_lock, flags);
  5245. if (work) {
  5246. cancel_work_sync(&work->work);
  5247. kfree(work);
  5248. }
  5249. drm_crtc_cleanup(crtc);
  5250. kfree(intel_crtc);
  5251. }
  5252. static void intel_unpin_work_fn(struct work_struct *__work)
  5253. {
  5254. struct intel_unpin_work *work =
  5255. container_of(__work, struct intel_unpin_work, work);
  5256. mutex_lock(&work->dev->struct_mutex);
  5257. intel_unpin_fb_obj(work->old_fb_obj);
  5258. drm_gem_object_unreference(&work->pending_flip_obj->base);
  5259. drm_gem_object_unreference(&work->old_fb_obj->base);
  5260. intel_update_fbc(work->dev);
  5261. mutex_unlock(&work->dev->struct_mutex);
  5262. kfree(work);
  5263. }
  5264. static void do_intel_finish_page_flip(struct drm_device *dev,
  5265. struct drm_crtc *crtc)
  5266. {
  5267. drm_i915_private_t *dev_priv = dev->dev_private;
  5268. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5269. struct intel_unpin_work *work;
  5270. struct drm_i915_gem_object *obj;
  5271. struct drm_pending_vblank_event *e;
  5272. struct timeval tnow, tvbl;
  5273. unsigned long flags;
  5274. /* Ignore early vblank irqs */
  5275. if (intel_crtc == NULL)
  5276. return;
  5277. do_gettimeofday(&tnow);
  5278. spin_lock_irqsave(&dev->event_lock, flags);
  5279. work = intel_crtc->unpin_work;
  5280. if (work == NULL || !work->pending) {
  5281. spin_unlock_irqrestore(&dev->event_lock, flags);
  5282. return;
  5283. }
  5284. intel_crtc->unpin_work = NULL;
  5285. if (work->event) {
  5286. e = work->event;
  5287. e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
  5288. /* Called before vblank count and timestamps have
  5289. * been updated for the vblank interval of flip
  5290. * completion? Need to increment vblank count and
  5291. * add one videorefresh duration to returned timestamp
  5292. * to account for this. We assume this happened if we
  5293. * get called over 0.9 frame durations after the last
  5294. * timestamped vblank.
  5295. *
  5296. * This calculation can not be used with vrefresh rates
  5297. * below 5Hz (10Hz to be on the safe side) without
  5298. * promoting to 64 integers.
  5299. */
  5300. if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
  5301. 9 * crtc->framedur_ns) {
  5302. e->event.sequence++;
  5303. tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
  5304. crtc->framedur_ns);
  5305. }
  5306. e->event.tv_sec = tvbl.tv_sec;
  5307. e->event.tv_usec = tvbl.tv_usec;
  5308. list_add_tail(&e->base.link,
  5309. &e->base.file_priv->event_list);
  5310. wake_up_interruptible(&e->base.file_priv->event_wait);
  5311. }
  5312. drm_vblank_put(dev, intel_crtc->pipe);
  5313. spin_unlock_irqrestore(&dev->event_lock, flags);
  5314. obj = work->old_fb_obj;
  5315. atomic_clear_mask(1 << intel_crtc->plane,
  5316. &obj->pending_flip.counter);
  5317. if (atomic_read(&obj->pending_flip) == 0)
  5318. wake_up(&dev_priv->pending_flip_queue);
  5319. schedule_work(&work->work);
  5320. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  5321. }
  5322. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  5323. {
  5324. drm_i915_private_t *dev_priv = dev->dev_private;
  5325. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  5326. do_intel_finish_page_flip(dev, crtc);
  5327. }
  5328. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  5329. {
  5330. drm_i915_private_t *dev_priv = dev->dev_private;
  5331. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  5332. do_intel_finish_page_flip(dev, crtc);
  5333. }
  5334. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  5335. {
  5336. drm_i915_private_t *dev_priv = dev->dev_private;
  5337. struct intel_crtc *intel_crtc =
  5338. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  5339. unsigned long flags;
  5340. spin_lock_irqsave(&dev->event_lock, flags);
  5341. if (intel_crtc->unpin_work) {
  5342. if ((++intel_crtc->unpin_work->pending) > 1)
  5343. DRM_ERROR("Prepared flip multiple times\n");
  5344. } else {
  5345. DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
  5346. }
  5347. spin_unlock_irqrestore(&dev->event_lock, flags);
  5348. }
  5349. static int intel_gen2_queue_flip(struct drm_device *dev,
  5350. struct drm_crtc *crtc,
  5351. struct drm_framebuffer *fb,
  5352. struct drm_i915_gem_object *obj)
  5353. {
  5354. struct drm_i915_private *dev_priv = dev->dev_private;
  5355. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5356. u32 flip_mask;
  5357. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5358. int ret;
  5359. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5360. if (ret)
  5361. goto err;
  5362. ret = intel_ring_begin(ring, 6);
  5363. if (ret)
  5364. goto err_unpin;
  5365. /* Can't queue multiple flips, so wait for the previous
  5366. * one to finish before executing the next.
  5367. */
  5368. if (intel_crtc->plane)
  5369. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  5370. else
  5371. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  5372. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  5373. intel_ring_emit(ring, MI_NOOP);
  5374. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  5375. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5376. intel_ring_emit(ring, fb->pitches[0]);
  5377. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5378. intel_ring_emit(ring, 0); /* aux display base address, unused */
  5379. intel_ring_advance(ring);
  5380. return 0;
  5381. err_unpin:
  5382. intel_unpin_fb_obj(obj);
  5383. err:
  5384. return ret;
  5385. }
  5386. static int intel_gen3_queue_flip(struct drm_device *dev,
  5387. struct drm_crtc *crtc,
  5388. struct drm_framebuffer *fb,
  5389. struct drm_i915_gem_object *obj)
  5390. {
  5391. struct drm_i915_private *dev_priv = dev->dev_private;
  5392. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5393. u32 flip_mask;
  5394. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5395. int ret;
  5396. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5397. if (ret)
  5398. goto err;
  5399. ret = intel_ring_begin(ring, 6);
  5400. if (ret)
  5401. goto err_unpin;
  5402. if (intel_crtc->plane)
  5403. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  5404. else
  5405. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  5406. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  5407. intel_ring_emit(ring, MI_NOOP);
  5408. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
  5409. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5410. intel_ring_emit(ring, fb->pitches[0]);
  5411. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5412. intel_ring_emit(ring, MI_NOOP);
  5413. intel_ring_advance(ring);
  5414. return 0;
  5415. err_unpin:
  5416. intel_unpin_fb_obj(obj);
  5417. err:
  5418. return ret;
  5419. }
  5420. static int intel_gen4_queue_flip(struct drm_device *dev,
  5421. struct drm_crtc *crtc,
  5422. struct drm_framebuffer *fb,
  5423. struct drm_i915_gem_object *obj)
  5424. {
  5425. struct drm_i915_private *dev_priv = dev->dev_private;
  5426. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5427. uint32_t pf, pipesrc;
  5428. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5429. int ret;
  5430. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5431. if (ret)
  5432. goto err;
  5433. ret = intel_ring_begin(ring, 4);
  5434. if (ret)
  5435. goto err_unpin;
  5436. /* i965+ uses the linear or tiled offsets from the
  5437. * Display Registers (which do not change across a page-flip)
  5438. * so we need only reprogram the base address.
  5439. */
  5440. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  5441. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5442. intel_ring_emit(ring, fb->pitches[0]);
  5443. intel_ring_emit(ring,
  5444. (obj->gtt_offset + intel_crtc->dspaddr_offset) |
  5445. obj->tiling_mode);
  5446. /* XXX Enabling the panel-fitter across page-flip is so far
  5447. * untested on non-native modes, so ignore it for now.
  5448. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  5449. */
  5450. pf = 0;
  5451. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  5452. intel_ring_emit(ring, pf | pipesrc);
  5453. intel_ring_advance(ring);
  5454. return 0;
  5455. err_unpin:
  5456. intel_unpin_fb_obj(obj);
  5457. err:
  5458. return ret;
  5459. }
  5460. static int intel_gen6_queue_flip(struct drm_device *dev,
  5461. struct drm_crtc *crtc,
  5462. struct drm_framebuffer *fb,
  5463. struct drm_i915_gem_object *obj)
  5464. {
  5465. struct drm_i915_private *dev_priv = dev->dev_private;
  5466. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5467. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5468. uint32_t pf, pipesrc;
  5469. int ret;
  5470. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5471. if (ret)
  5472. goto err;
  5473. ret = intel_ring_begin(ring, 4);
  5474. if (ret)
  5475. goto err_unpin;
  5476. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  5477. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5478. intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
  5479. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5480. /* Contrary to the suggestions in the documentation,
  5481. * "Enable Panel Fitter" does not seem to be required when page
  5482. * flipping with a non-native mode, and worse causes a normal
  5483. * modeset to fail.
  5484. * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  5485. */
  5486. pf = 0;
  5487. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  5488. intel_ring_emit(ring, pf | pipesrc);
  5489. intel_ring_advance(ring);
  5490. return 0;
  5491. err_unpin:
  5492. intel_unpin_fb_obj(obj);
  5493. err:
  5494. return ret;
  5495. }
  5496. /*
  5497. * On gen7 we currently use the blit ring because (in early silicon at least)
  5498. * the render ring doesn't give us interrpts for page flip completion, which
  5499. * means clients will hang after the first flip is queued. Fortunately the
  5500. * blit ring generates interrupts properly, so use it instead.
  5501. */
  5502. static int intel_gen7_queue_flip(struct drm_device *dev,
  5503. struct drm_crtc *crtc,
  5504. struct drm_framebuffer *fb,
  5505. struct drm_i915_gem_object *obj)
  5506. {
  5507. struct drm_i915_private *dev_priv = dev->dev_private;
  5508. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5509. struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
  5510. uint32_t plane_bit = 0;
  5511. int ret;
  5512. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5513. if (ret)
  5514. goto err;
  5515. switch(intel_crtc->plane) {
  5516. case PLANE_A:
  5517. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  5518. break;
  5519. case PLANE_B:
  5520. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  5521. break;
  5522. case PLANE_C:
  5523. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  5524. break;
  5525. default:
  5526. WARN_ONCE(1, "unknown plane in flip command\n");
  5527. ret = -ENODEV;
  5528. goto err_unpin;
  5529. }
  5530. ret = intel_ring_begin(ring, 4);
  5531. if (ret)
  5532. goto err_unpin;
  5533. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
  5534. intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  5535. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5536. intel_ring_emit(ring, (MI_NOOP));
  5537. intel_ring_advance(ring);
  5538. return 0;
  5539. err_unpin:
  5540. intel_unpin_fb_obj(obj);
  5541. err:
  5542. return ret;
  5543. }
  5544. static int intel_default_queue_flip(struct drm_device *dev,
  5545. struct drm_crtc *crtc,
  5546. struct drm_framebuffer *fb,
  5547. struct drm_i915_gem_object *obj)
  5548. {
  5549. return -ENODEV;
  5550. }
  5551. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  5552. struct drm_framebuffer *fb,
  5553. struct drm_pending_vblank_event *event)
  5554. {
  5555. struct drm_device *dev = crtc->dev;
  5556. struct drm_i915_private *dev_priv = dev->dev_private;
  5557. struct intel_framebuffer *intel_fb;
  5558. struct drm_i915_gem_object *obj;
  5559. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5560. struct intel_unpin_work *work;
  5561. unsigned long flags;
  5562. int ret;
  5563. /* Can't change pixel format via MI display flips. */
  5564. if (fb->pixel_format != crtc->fb->pixel_format)
  5565. return -EINVAL;
  5566. /*
  5567. * TILEOFF/LINOFF registers can't be changed via MI display flips.
  5568. * Note that pitch changes could also affect these register.
  5569. */
  5570. if (INTEL_INFO(dev)->gen > 3 &&
  5571. (fb->offsets[0] != crtc->fb->offsets[0] ||
  5572. fb->pitches[0] != crtc->fb->pitches[0]))
  5573. return -EINVAL;
  5574. work = kzalloc(sizeof *work, GFP_KERNEL);
  5575. if (work == NULL)
  5576. return -ENOMEM;
  5577. work->event = event;
  5578. work->dev = crtc->dev;
  5579. intel_fb = to_intel_framebuffer(crtc->fb);
  5580. work->old_fb_obj = intel_fb->obj;
  5581. INIT_WORK(&work->work, intel_unpin_work_fn);
  5582. ret = drm_vblank_get(dev, intel_crtc->pipe);
  5583. if (ret)
  5584. goto free_work;
  5585. /* We borrow the event spin lock for protecting unpin_work */
  5586. spin_lock_irqsave(&dev->event_lock, flags);
  5587. if (intel_crtc->unpin_work) {
  5588. spin_unlock_irqrestore(&dev->event_lock, flags);
  5589. kfree(work);
  5590. drm_vblank_put(dev, intel_crtc->pipe);
  5591. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  5592. return -EBUSY;
  5593. }
  5594. intel_crtc->unpin_work = work;
  5595. spin_unlock_irqrestore(&dev->event_lock, flags);
  5596. intel_fb = to_intel_framebuffer(fb);
  5597. obj = intel_fb->obj;
  5598. ret = i915_mutex_lock_interruptible(dev);
  5599. if (ret)
  5600. goto cleanup;
  5601. /* Reference the objects for the scheduled work. */
  5602. drm_gem_object_reference(&work->old_fb_obj->base);
  5603. drm_gem_object_reference(&obj->base);
  5604. crtc->fb = fb;
  5605. work->pending_flip_obj = obj;
  5606. work->enable_stall_check = true;
  5607. /* Block clients from rendering to the new back buffer until
  5608. * the flip occurs and the object is no longer visible.
  5609. */
  5610. atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
  5611. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
  5612. if (ret)
  5613. goto cleanup_pending;
  5614. intel_disable_fbc(dev);
  5615. intel_mark_fb_busy(obj);
  5616. mutex_unlock(&dev->struct_mutex);
  5617. trace_i915_flip_request(intel_crtc->plane, obj);
  5618. return 0;
  5619. cleanup_pending:
  5620. atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
  5621. drm_gem_object_unreference(&work->old_fb_obj->base);
  5622. drm_gem_object_unreference(&obj->base);
  5623. mutex_unlock(&dev->struct_mutex);
  5624. cleanup:
  5625. spin_lock_irqsave(&dev->event_lock, flags);
  5626. intel_crtc->unpin_work = NULL;
  5627. spin_unlock_irqrestore(&dev->event_lock, flags);
  5628. drm_vblank_put(dev, intel_crtc->pipe);
  5629. free_work:
  5630. kfree(work);
  5631. return ret;
  5632. }
  5633. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  5634. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  5635. .load_lut = intel_crtc_load_lut,
  5636. .disable = intel_crtc_noop,
  5637. };
  5638. bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
  5639. {
  5640. struct intel_encoder *other_encoder;
  5641. struct drm_crtc *crtc = &encoder->new_crtc->base;
  5642. if (WARN_ON(!crtc))
  5643. return false;
  5644. list_for_each_entry(other_encoder,
  5645. &crtc->dev->mode_config.encoder_list,
  5646. base.head) {
  5647. if (&other_encoder->new_crtc->base != crtc ||
  5648. encoder == other_encoder)
  5649. continue;
  5650. else
  5651. return true;
  5652. }
  5653. return false;
  5654. }
  5655. static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
  5656. struct drm_crtc *crtc)
  5657. {
  5658. struct drm_device *dev;
  5659. struct drm_crtc *tmp;
  5660. int crtc_mask = 1;
  5661. WARN(!crtc, "checking null crtc?\n");
  5662. dev = crtc->dev;
  5663. list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
  5664. if (tmp == crtc)
  5665. break;
  5666. crtc_mask <<= 1;
  5667. }
  5668. if (encoder->possible_crtcs & crtc_mask)
  5669. return true;
  5670. return false;
  5671. }
  5672. /**
  5673. * intel_modeset_update_staged_output_state
  5674. *
  5675. * Updates the staged output configuration state, e.g. after we've read out the
  5676. * current hw state.
  5677. */
  5678. static void intel_modeset_update_staged_output_state(struct drm_device *dev)
  5679. {
  5680. struct intel_encoder *encoder;
  5681. struct intel_connector *connector;
  5682. list_for_each_entry(connector, &dev->mode_config.connector_list,
  5683. base.head) {
  5684. connector->new_encoder =
  5685. to_intel_encoder(connector->base.encoder);
  5686. }
  5687. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  5688. base.head) {
  5689. encoder->new_crtc =
  5690. to_intel_crtc(encoder->base.crtc);
  5691. }
  5692. }
  5693. /**
  5694. * intel_modeset_commit_output_state
  5695. *
  5696. * This function copies the stage display pipe configuration to the real one.
  5697. */
  5698. static void intel_modeset_commit_output_state(struct drm_device *dev)
  5699. {
  5700. struct intel_encoder *encoder;
  5701. struct intel_connector *connector;
  5702. list_for_each_entry(connector, &dev->mode_config.connector_list,
  5703. base.head) {
  5704. connector->base.encoder = &connector->new_encoder->base;
  5705. }
  5706. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  5707. base.head) {
  5708. encoder->base.crtc = &encoder->new_crtc->base;
  5709. }
  5710. }
  5711. static struct drm_display_mode *
  5712. intel_modeset_adjusted_mode(struct drm_crtc *crtc,
  5713. struct drm_display_mode *mode)
  5714. {
  5715. struct drm_device *dev = crtc->dev;
  5716. struct drm_display_mode *adjusted_mode;
  5717. struct drm_encoder_helper_funcs *encoder_funcs;
  5718. struct intel_encoder *encoder;
  5719. adjusted_mode = drm_mode_duplicate(dev, mode);
  5720. if (!adjusted_mode)
  5721. return ERR_PTR(-ENOMEM);
  5722. /* Pass our mode to the connectors and the CRTC to give them a chance to
  5723. * adjust it according to limitations or connector properties, and also
  5724. * a chance to reject the mode entirely.
  5725. */
  5726. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  5727. base.head) {
  5728. if (&encoder->new_crtc->base != crtc)
  5729. continue;
  5730. encoder_funcs = encoder->base.helper_private;
  5731. if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
  5732. adjusted_mode))) {
  5733. DRM_DEBUG_KMS("Encoder fixup failed\n");
  5734. goto fail;
  5735. }
  5736. }
  5737. if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
  5738. DRM_DEBUG_KMS("CRTC fixup failed\n");
  5739. goto fail;
  5740. }
  5741. DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
  5742. return adjusted_mode;
  5743. fail:
  5744. drm_mode_destroy(dev, adjusted_mode);
  5745. return ERR_PTR(-EINVAL);
  5746. }
  5747. /* Computes which crtcs are affected and sets the relevant bits in the mask. For
  5748. * simplicity we use the crtc's pipe number (because it's easier to obtain). */
  5749. static void
  5750. intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
  5751. unsigned *prepare_pipes, unsigned *disable_pipes)
  5752. {
  5753. struct intel_crtc *intel_crtc;
  5754. struct drm_device *dev = crtc->dev;
  5755. struct intel_encoder *encoder;
  5756. struct intel_connector *connector;
  5757. struct drm_crtc *tmp_crtc;
  5758. *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
  5759. /* Check which crtcs have changed outputs connected to them, these need
  5760. * to be part of the prepare_pipes mask. We don't (yet) support global
  5761. * modeset across multiple crtcs, so modeset_pipes will only have one
  5762. * bit set at most. */
  5763. list_for_each_entry(connector, &dev->mode_config.connector_list,
  5764. base.head) {
  5765. if (connector->base.encoder == &connector->new_encoder->base)
  5766. continue;
  5767. if (connector->base.encoder) {
  5768. tmp_crtc = connector->base.encoder->crtc;
  5769. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  5770. }
  5771. if (connector->new_encoder)
  5772. *prepare_pipes |=
  5773. 1 << connector->new_encoder->new_crtc->pipe;
  5774. }
  5775. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  5776. base.head) {
  5777. if (encoder->base.crtc == &encoder->new_crtc->base)
  5778. continue;
  5779. if (encoder->base.crtc) {
  5780. tmp_crtc = encoder->base.crtc;
  5781. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  5782. }
  5783. if (encoder->new_crtc)
  5784. *prepare_pipes |= 1 << encoder->new_crtc->pipe;
  5785. }
  5786. /* Check for any pipes that will be fully disabled ... */
  5787. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  5788. base.head) {
  5789. bool used = false;
  5790. /* Don't try to disable disabled crtcs. */
  5791. if (!intel_crtc->base.enabled)
  5792. continue;
  5793. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  5794. base.head) {
  5795. if (encoder->new_crtc == intel_crtc)
  5796. used = true;
  5797. }
  5798. if (!used)
  5799. *disable_pipes |= 1 << intel_crtc->pipe;
  5800. }
  5801. /* set_mode is also used to update properties on life display pipes. */
  5802. intel_crtc = to_intel_crtc(crtc);
  5803. if (crtc->enabled)
  5804. *prepare_pipes |= 1 << intel_crtc->pipe;
  5805. /* We only support modeset on one single crtc, hence we need to do that
  5806. * only for the passed in crtc iff we change anything else than just
  5807. * disable crtcs.
  5808. *
  5809. * This is actually not true, to be fully compatible with the old crtc
  5810. * helper we automatically disable _any_ output (i.e. doesn't need to be
  5811. * connected to the crtc we're modesetting on) if it's disconnected.
  5812. * Which is a rather nutty api (since changed the output configuration
  5813. * without userspace's explicit request can lead to confusion), but
  5814. * alas. Hence we currently need to modeset on all pipes we prepare. */
  5815. if (*prepare_pipes)
  5816. *modeset_pipes = *prepare_pipes;
  5817. /* ... and mask these out. */
  5818. *modeset_pipes &= ~(*disable_pipes);
  5819. *prepare_pipes &= ~(*disable_pipes);
  5820. }
  5821. static bool intel_crtc_in_use(struct drm_crtc *crtc)
  5822. {
  5823. struct drm_encoder *encoder;
  5824. struct drm_device *dev = crtc->dev;
  5825. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
  5826. if (encoder->crtc == crtc)
  5827. return true;
  5828. return false;
  5829. }
  5830. static void
  5831. intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
  5832. {
  5833. struct intel_encoder *intel_encoder;
  5834. struct intel_crtc *intel_crtc;
  5835. struct drm_connector *connector;
  5836. list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
  5837. base.head) {
  5838. if (!intel_encoder->base.crtc)
  5839. continue;
  5840. intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
  5841. if (prepare_pipes & (1 << intel_crtc->pipe))
  5842. intel_encoder->connectors_active = false;
  5843. }
  5844. intel_modeset_commit_output_state(dev);
  5845. /* Update computed state. */
  5846. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  5847. base.head) {
  5848. intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
  5849. }
  5850. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  5851. if (!connector->encoder || !connector->encoder->crtc)
  5852. continue;
  5853. intel_crtc = to_intel_crtc(connector->encoder->crtc);
  5854. if (prepare_pipes & (1 << intel_crtc->pipe)) {
  5855. connector->dpms = DRM_MODE_DPMS_ON;
  5856. intel_encoder = to_intel_encoder(connector->encoder);
  5857. intel_encoder->connectors_active = true;
  5858. }
  5859. }
  5860. }
  5861. #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
  5862. list_for_each_entry((intel_crtc), \
  5863. &(dev)->mode_config.crtc_list, \
  5864. base.head) \
  5865. if (mask & (1 <<(intel_crtc)->pipe)) \
  5866. void
  5867. intel_modeset_check_state(struct drm_device *dev)
  5868. {
  5869. struct intel_crtc *crtc;
  5870. struct intel_encoder *encoder;
  5871. struct intel_connector *connector;
  5872. list_for_each_entry(connector, &dev->mode_config.connector_list,
  5873. base.head) {
  5874. /* This also checks the encoder/connector hw state with the
  5875. * ->get_hw_state callbacks. */
  5876. intel_connector_check_state(connector);
  5877. WARN(&connector->new_encoder->base != connector->base.encoder,
  5878. "connector's staged encoder doesn't match current encoder\n");
  5879. }
  5880. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  5881. base.head) {
  5882. bool enabled = false;
  5883. bool active = false;
  5884. enum pipe pipe, tracked_pipe;
  5885. DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
  5886. encoder->base.base.id,
  5887. drm_get_encoder_name(&encoder->base));
  5888. WARN(&encoder->new_crtc->base != encoder->base.crtc,
  5889. "encoder's stage crtc doesn't match current crtc\n");
  5890. WARN(encoder->connectors_active && !encoder->base.crtc,
  5891. "encoder's active_connectors set, but no crtc\n");
  5892. list_for_each_entry(connector, &dev->mode_config.connector_list,
  5893. base.head) {
  5894. if (connector->base.encoder != &encoder->base)
  5895. continue;
  5896. enabled = true;
  5897. if (connector->base.dpms != DRM_MODE_DPMS_OFF)
  5898. active = true;
  5899. }
  5900. WARN(!!encoder->base.crtc != enabled,
  5901. "encoder's enabled state mismatch "
  5902. "(expected %i, found %i)\n",
  5903. !!encoder->base.crtc, enabled);
  5904. WARN(active && !encoder->base.crtc,
  5905. "active encoder with no crtc\n");
  5906. WARN(encoder->connectors_active != active,
  5907. "encoder's computed active state doesn't match tracked active state "
  5908. "(expected %i, found %i)\n", active, encoder->connectors_active);
  5909. active = encoder->get_hw_state(encoder, &pipe);
  5910. WARN(active != encoder->connectors_active,
  5911. "encoder's hw state doesn't match sw tracking "
  5912. "(expected %i, found %i)\n",
  5913. encoder->connectors_active, active);
  5914. if (!encoder->base.crtc)
  5915. continue;
  5916. tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
  5917. WARN(active && pipe != tracked_pipe,
  5918. "active encoder's pipe doesn't match"
  5919. "(expected %i, found %i)\n",
  5920. tracked_pipe, pipe);
  5921. }
  5922. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  5923. base.head) {
  5924. bool enabled = false;
  5925. bool active = false;
  5926. DRM_DEBUG_KMS("[CRTC:%d]\n",
  5927. crtc->base.base.id);
  5928. WARN(crtc->active && !crtc->base.enabled,
  5929. "active crtc, but not enabled in sw tracking\n");
  5930. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  5931. base.head) {
  5932. if (encoder->base.crtc != &crtc->base)
  5933. continue;
  5934. enabled = true;
  5935. if (encoder->connectors_active)
  5936. active = true;
  5937. }
  5938. WARN(active != crtc->active,
  5939. "crtc's computed active state doesn't match tracked active state "
  5940. "(expected %i, found %i)\n", active, crtc->active);
  5941. WARN(enabled != crtc->base.enabled,
  5942. "crtc's computed enabled state doesn't match tracked enabled state "
  5943. "(expected %i, found %i)\n", enabled, crtc->base.enabled);
  5944. assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
  5945. }
  5946. }
  5947. bool intel_set_mode(struct drm_crtc *crtc,
  5948. struct drm_display_mode *mode,
  5949. int x, int y, struct drm_framebuffer *fb)
  5950. {
  5951. struct drm_device *dev = crtc->dev;
  5952. drm_i915_private_t *dev_priv = dev->dev_private;
  5953. struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
  5954. struct drm_encoder_helper_funcs *encoder_funcs;
  5955. struct drm_encoder *encoder;
  5956. struct intel_crtc *intel_crtc;
  5957. unsigned disable_pipes, prepare_pipes, modeset_pipes;
  5958. bool ret = true;
  5959. intel_modeset_affected_pipes(crtc, &modeset_pipes,
  5960. &prepare_pipes, &disable_pipes);
  5961. DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
  5962. modeset_pipes, prepare_pipes, disable_pipes);
  5963. for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
  5964. intel_crtc_disable(&intel_crtc->base);
  5965. saved_hwmode = crtc->hwmode;
  5966. saved_mode = crtc->mode;
  5967. /* Hack: Because we don't (yet) support global modeset on multiple
  5968. * crtcs, we don't keep track of the new mode for more than one crtc.
  5969. * Hence simply check whether any bit is set in modeset_pipes in all the
  5970. * pieces of code that are not yet converted to deal with mutliple crtcs
  5971. * changing their mode at the same time. */
  5972. adjusted_mode = NULL;
  5973. if (modeset_pipes) {
  5974. adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
  5975. if (IS_ERR(adjusted_mode)) {
  5976. return false;
  5977. }
  5978. }
  5979. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
  5980. if (intel_crtc->base.enabled)
  5981. dev_priv->display.crtc_disable(&intel_crtc->base);
  5982. }
  5983. /* crtc->mode is already used by the ->mode_set callbacks, hence we need
  5984. * to set it here already despite that we pass it down the callchain.
  5985. */
  5986. if (modeset_pipes)
  5987. crtc->mode = *mode;
  5988. /* Only after disabling all output pipelines that will be changed can we
  5989. * update the the output configuration. */
  5990. intel_modeset_update_state(dev, prepare_pipes);
  5991. /* Set up the DPLL and any encoders state that needs to adjust or depend
  5992. * on the DPLL.
  5993. */
  5994. for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
  5995. ret = !intel_crtc_mode_set(&intel_crtc->base,
  5996. mode, adjusted_mode,
  5997. x, y, fb);
  5998. if (!ret)
  5999. goto done;
  6000. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  6001. if (encoder->crtc != &intel_crtc->base)
  6002. continue;
  6003. DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
  6004. encoder->base.id, drm_get_encoder_name(encoder),
  6005. mode->base.id, mode->name);
  6006. encoder_funcs = encoder->helper_private;
  6007. encoder_funcs->mode_set(encoder, mode, adjusted_mode);
  6008. }
  6009. }
  6010. /* Now enable the clocks, plane, pipe, and connectors that we set up. */
  6011. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
  6012. dev_priv->display.crtc_enable(&intel_crtc->base);
  6013. if (modeset_pipes) {
  6014. /* Store real post-adjustment hardware mode. */
  6015. crtc->hwmode = *adjusted_mode;
  6016. /* Calculate and store various constants which
  6017. * are later needed by vblank and swap-completion
  6018. * timestamping. They are derived from true hwmode.
  6019. */
  6020. drm_calc_timestamping_constants(crtc);
  6021. }
  6022. /* FIXME: add subpixel order */
  6023. done:
  6024. drm_mode_destroy(dev, adjusted_mode);
  6025. if (!ret && crtc->enabled) {
  6026. crtc->hwmode = saved_hwmode;
  6027. crtc->mode = saved_mode;
  6028. } else {
  6029. intel_modeset_check_state(dev);
  6030. }
  6031. return ret;
  6032. }
  6033. #undef for_each_intel_crtc_masked
  6034. static void intel_set_config_free(struct intel_set_config *config)
  6035. {
  6036. if (!config)
  6037. return;
  6038. kfree(config->save_connector_encoders);
  6039. kfree(config->save_encoder_crtcs);
  6040. kfree(config);
  6041. }
  6042. static int intel_set_config_save_state(struct drm_device *dev,
  6043. struct intel_set_config *config)
  6044. {
  6045. struct drm_encoder *encoder;
  6046. struct drm_connector *connector;
  6047. int count;
  6048. config->save_encoder_crtcs =
  6049. kcalloc(dev->mode_config.num_encoder,
  6050. sizeof(struct drm_crtc *), GFP_KERNEL);
  6051. if (!config->save_encoder_crtcs)
  6052. return -ENOMEM;
  6053. config->save_connector_encoders =
  6054. kcalloc(dev->mode_config.num_connector,
  6055. sizeof(struct drm_encoder *), GFP_KERNEL);
  6056. if (!config->save_connector_encoders)
  6057. return -ENOMEM;
  6058. /* Copy data. Note that driver private data is not affected.
  6059. * Should anything bad happen only the expected state is
  6060. * restored, not the drivers personal bookkeeping.
  6061. */
  6062. count = 0;
  6063. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  6064. config->save_encoder_crtcs[count++] = encoder->crtc;
  6065. }
  6066. count = 0;
  6067. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  6068. config->save_connector_encoders[count++] = connector->encoder;
  6069. }
  6070. return 0;
  6071. }
  6072. static void intel_set_config_restore_state(struct drm_device *dev,
  6073. struct intel_set_config *config)
  6074. {
  6075. struct intel_encoder *encoder;
  6076. struct intel_connector *connector;
  6077. int count;
  6078. count = 0;
  6079. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  6080. encoder->new_crtc =
  6081. to_intel_crtc(config->save_encoder_crtcs[count++]);
  6082. }
  6083. count = 0;
  6084. list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
  6085. connector->new_encoder =
  6086. to_intel_encoder(config->save_connector_encoders[count++]);
  6087. }
  6088. }
  6089. static void
  6090. intel_set_config_compute_mode_changes(struct drm_mode_set *set,
  6091. struct intel_set_config *config)
  6092. {
  6093. /* We should be able to check here if the fb has the same properties
  6094. * and then just flip_or_move it */
  6095. if (set->crtc->fb != set->fb) {
  6096. /* If we have no fb then treat it as a full mode set */
  6097. if (set->crtc->fb == NULL) {
  6098. DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
  6099. config->mode_changed = true;
  6100. } else if (set->fb == NULL) {
  6101. config->mode_changed = true;
  6102. } else if (set->fb->depth != set->crtc->fb->depth) {
  6103. config->mode_changed = true;
  6104. } else if (set->fb->bits_per_pixel !=
  6105. set->crtc->fb->bits_per_pixel) {
  6106. config->mode_changed = true;
  6107. } else
  6108. config->fb_changed = true;
  6109. }
  6110. if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
  6111. config->fb_changed = true;
  6112. if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
  6113. DRM_DEBUG_KMS("modes are different, full mode set\n");
  6114. drm_mode_debug_printmodeline(&set->crtc->mode);
  6115. drm_mode_debug_printmodeline(set->mode);
  6116. config->mode_changed = true;
  6117. }
  6118. }
  6119. static int
  6120. intel_modeset_stage_output_state(struct drm_device *dev,
  6121. struct drm_mode_set *set,
  6122. struct intel_set_config *config)
  6123. {
  6124. struct drm_crtc *new_crtc;
  6125. struct intel_connector *connector;
  6126. struct intel_encoder *encoder;
  6127. int count, ro;
  6128. /* The upper layers ensure that we either disabl a crtc or have a list
  6129. * of connectors. For paranoia, double-check this. */
  6130. WARN_ON(!set->fb && (set->num_connectors != 0));
  6131. WARN_ON(set->fb && (set->num_connectors == 0));
  6132. count = 0;
  6133. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6134. base.head) {
  6135. /* Otherwise traverse passed in connector list and get encoders
  6136. * for them. */
  6137. for (ro = 0; ro < set->num_connectors; ro++) {
  6138. if (set->connectors[ro] == &connector->base) {
  6139. connector->new_encoder = connector->encoder;
  6140. break;
  6141. }
  6142. }
  6143. /* If we disable the crtc, disable all its connectors. Also, if
  6144. * the connector is on the changing crtc but not on the new
  6145. * connector list, disable it. */
  6146. if ((!set->fb || ro == set->num_connectors) &&
  6147. connector->base.encoder &&
  6148. connector->base.encoder->crtc == set->crtc) {
  6149. connector->new_encoder = NULL;
  6150. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
  6151. connector->base.base.id,
  6152. drm_get_connector_name(&connector->base));
  6153. }
  6154. if (&connector->new_encoder->base != connector->base.encoder) {
  6155. DRM_DEBUG_KMS("encoder changed, full mode switch\n");
  6156. config->mode_changed = true;
  6157. }
  6158. /* Disable all disconnected encoders. */
  6159. if (connector->base.status == connector_status_disconnected)
  6160. connector->new_encoder = NULL;
  6161. }
  6162. /* connector->new_encoder is now updated for all connectors. */
  6163. /* Update crtc of enabled connectors. */
  6164. count = 0;
  6165. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6166. base.head) {
  6167. if (!connector->new_encoder)
  6168. continue;
  6169. new_crtc = connector->new_encoder->base.crtc;
  6170. for (ro = 0; ro < set->num_connectors; ro++) {
  6171. if (set->connectors[ro] == &connector->base)
  6172. new_crtc = set->crtc;
  6173. }
  6174. /* Make sure the new CRTC will work with the encoder */
  6175. if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
  6176. new_crtc)) {
  6177. return -EINVAL;
  6178. }
  6179. connector->encoder->new_crtc = to_intel_crtc(new_crtc);
  6180. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
  6181. connector->base.base.id,
  6182. drm_get_connector_name(&connector->base),
  6183. new_crtc->base.id);
  6184. }
  6185. /* Check for any encoders that needs to be disabled. */
  6186. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6187. base.head) {
  6188. list_for_each_entry(connector,
  6189. &dev->mode_config.connector_list,
  6190. base.head) {
  6191. if (connector->new_encoder == encoder) {
  6192. WARN_ON(!connector->new_encoder->new_crtc);
  6193. goto next_encoder;
  6194. }
  6195. }
  6196. encoder->new_crtc = NULL;
  6197. next_encoder:
  6198. /* Only now check for crtc changes so we don't miss encoders
  6199. * that will be disabled. */
  6200. if (&encoder->new_crtc->base != encoder->base.crtc) {
  6201. DRM_DEBUG_KMS("crtc changed, full mode switch\n");
  6202. config->mode_changed = true;
  6203. }
  6204. }
  6205. /* Now we've also updated encoder->new_crtc for all encoders. */
  6206. return 0;
  6207. }
  6208. static int intel_crtc_set_config(struct drm_mode_set *set)
  6209. {
  6210. struct drm_device *dev;
  6211. struct drm_mode_set save_set;
  6212. struct intel_set_config *config;
  6213. int ret;
  6214. int i;
  6215. BUG_ON(!set);
  6216. BUG_ON(!set->crtc);
  6217. BUG_ON(!set->crtc->helper_private);
  6218. if (!set->mode)
  6219. set->fb = NULL;
  6220. /* The fb helper likes to play gross jokes with ->mode_set_config.
  6221. * Unfortunately the crtc helper doesn't do much at all for this case,
  6222. * so we have to cope with this madness until the fb helper is fixed up. */
  6223. if (set->fb && set->num_connectors == 0)
  6224. return 0;
  6225. if (set->fb) {
  6226. DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
  6227. set->crtc->base.id, set->fb->base.id,
  6228. (int)set->num_connectors, set->x, set->y);
  6229. } else {
  6230. DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
  6231. }
  6232. dev = set->crtc->dev;
  6233. ret = -ENOMEM;
  6234. config = kzalloc(sizeof(*config), GFP_KERNEL);
  6235. if (!config)
  6236. goto out_config;
  6237. ret = intel_set_config_save_state(dev, config);
  6238. if (ret)
  6239. goto out_config;
  6240. save_set.crtc = set->crtc;
  6241. save_set.mode = &set->crtc->mode;
  6242. save_set.x = set->crtc->x;
  6243. save_set.y = set->crtc->y;
  6244. save_set.fb = set->crtc->fb;
  6245. /* Compute whether we need a full modeset, only an fb base update or no
  6246. * change at all. In the future we might also check whether only the
  6247. * mode changed, e.g. for LVDS where we only change the panel fitter in
  6248. * such cases. */
  6249. intel_set_config_compute_mode_changes(set, config);
  6250. ret = intel_modeset_stage_output_state(dev, set, config);
  6251. if (ret)
  6252. goto fail;
  6253. if (config->mode_changed) {
  6254. if (set->mode) {
  6255. DRM_DEBUG_KMS("attempting to set mode from"
  6256. " userspace\n");
  6257. drm_mode_debug_printmodeline(set->mode);
  6258. }
  6259. if (!intel_set_mode(set->crtc, set->mode,
  6260. set->x, set->y, set->fb)) {
  6261. DRM_ERROR("failed to set mode on [CRTC:%d]\n",
  6262. set->crtc->base.id);
  6263. ret = -EINVAL;
  6264. goto fail;
  6265. }
  6266. if (set->crtc->enabled) {
  6267. DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
  6268. for (i = 0; i < set->num_connectors; i++) {
  6269. DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
  6270. drm_get_connector_name(set->connectors[i]));
  6271. set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
  6272. }
  6273. }
  6274. } else if (config->fb_changed) {
  6275. ret = intel_pipe_set_base(set->crtc,
  6276. set->x, set->y, set->fb);
  6277. }
  6278. intel_set_config_free(config);
  6279. return 0;
  6280. fail:
  6281. intel_set_config_restore_state(dev, config);
  6282. /* Try to restore the config */
  6283. if (config->mode_changed &&
  6284. !intel_set_mode(save_set.crtc, save_set.mode,
  6285. save_set.x, save_set.y, save_set.fb))
  6286. DRM_ERROR("failed to restore config after modeset failure\n");
  6287. out_config:
  6288. intel_set_config_free(config);
  6289. return ret;
  6290. }
  6291. static const struct drm_crtc_funcs intel_crtc_funcs = {
  6292. .cursor_set = intel_crtc_cursor_set,
  6293. .cursor_move = intel_crtc_cursor_move,
  6294. .gamma_set = intel_crtc_gamma_set,
  6295. .set_config = intel_crtc_set_config,
  6296. .destroy = intel_crtc_destroy,
  6297. .page_flip = intel_crtc_page_flip,
  6298. };
  6299. static void intel_pch_pll_init(struct drm_device *dev)
  6300. {
  6301. drm_i915_private_t *dev_priv = dev->dev_private;
  6302. int i;
  6303. if (dev_priv->num_pch_pll == 0) {
  6304. DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
  6305. return;
  6306. }
  6307. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  6308. dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
  6309. dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
  6310. dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
  6311. }
  6312. }
  6313. static void intel_crtc_init(struct drm_device *dev, int pipe)
  6314. {
  6315. drm_i915_private_t *dev_priv = dev->dev_private;
  6316. struct intel_crtc *intel_crtc;
  6317. int i;
  6318. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  6319. if (intel_crtc == NULL)
  6320. return;
  6321. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  6322. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  6323. for (i = 0; i < 256; i++) {
  6324. intel_crtc->lut_r[i] = i;
  6325. intel_crtc->lut_g[i] = i;
  6326. intel_crtc->lut_b[i] = i;
  6327. }
  6328. /* Swap pipes & planes for FBC on pre-965 */
  6329. intel_crtc->pipe = pipe;
  6330. intel_crtc->plane = pipe;
  6331. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  6332. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  6333. intel_crtc->plane = !pipe;
  6334. }
  6335. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  6336. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  6337. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  6338. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  6339. intel_crtc->bpp = 24; /* default for pre-Ironlake */
  6340. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  6341. }
  6342. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  6343. struct drm_file *file)
  6344. {
  6345. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  6346. struct drm_mode_object *drmmode_obj;
  6347. struct intel_crtc *crtc;
  6348. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  6349. return -ENODEV;
  6350. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  6351. DRM_MODE_OBJECT_CRTC);
  6352. if (!drmmode_obj) {
  6353. DRM_ERROR("no such CRTC id\n");
  6354. return -EINVAL;
  6355. }
  6356. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  6357. pipe_from_crtc_id->pipe = crtc->pipe;
  6358. return 0;
  6359. }
  6360. static int intel_encoder_clones(struct intel_encoder *encoder)
  6361. {
  6362. struct drm_device *dev = encoder->base.dev;
  6363. struct intel_encoder *source_encoder;
  6364. int index_mask = 0;
  6365. int entry = 0;
  6366. list_for_each_entry(source_encoder,
  6367. &dev->mode_config.encoder_list, base.head) {
  6368. if (encoder == source_encoder)
  6369. index_mask |= (1 << entry);
  6370. /* Intel hw has only one MUX where enocoders could be cloned. */
  6371. if (encoder->cloneable && source_encoder->cloneable)
  6372. index_mask |= (1 << entry);
  6373. entry++;
  6374. }
  6375. return index_mask;
  6376. }
  6377. static bool has_edp_a(struct drm_device *dev)
  6378. {
  6379. struct drm_i915_private *dev_priv = dev->dev_private;
  6380. if (!IS_MOBILE(dev))
  6381. return false;
  6382. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  6383. return false;
  6384. if (IS_GEN5(dev) &&
  6385. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  6386. return false;
  6387. return true;
  6388. }
  6389. static void intel_setup_outputs(struct drm_device *dev)
  6390. {
  6391. struct drm_i915_private *dev_priv = dev->dev_private;
  6392. struct intel_encoder *encoder;
  6393. bool dpd_is_edp = false;
  6394. bool has_lvds;
  6395. has_lvds = intel_lvds_init(dev);
  6396. if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
  6397. /* disable the panel fitter on everything but LVDS */
  6398. I915_WRITE(PFIT_CONTROL, 0);
  6399. }
  6400. if (HAS_PCH_SPLIT(dev)) {
  6401. dpd_is_edp = intel_dpd_is_edp(dev);
  6402. if (has_edp_a(dev))
  6403. intel_dp_init(dev, DP_A, PORT_A);
  6404. if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  6405. intel_dp_init(dev, PCH_DP_D, PORT_D);
  6406. }
  6407. intel_crt_init(dev);
  6408. if (IS_HASWELL(dev)) {
  6409. int found;
  6410. /* Haswell uses DDI functions to detect digital outputs */
  6411. found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
  6412. /* DDI A only supports eDP */
  6413. if (found)
  6414. intel_ddi_init(dev, PORT_A);
  6415. /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  6416. * register */
  6417. found = I915_READ(SFUSE_STRAP);
  6418. if (found & SFUSE_STRAP_DDIB_DETECTED)
  6419. intel_ddi_init(dev, PORT_B);
  6420. if (found & SFUSE_STRAP_DDIC_DETECTED)
  6421. intel_ddi_init(dev, PORT_C);
  6422. if (found & SFUSE_STRAP_DDID_DETECTED)
  6423. intel_ddi_init(dev, PORT_D);
  6424. } else if (HAS_PCH_SPLIT(dev)) {
  6425. int found;
  6426. if (I915_READ(HDMIB) & PORT_DETECTED) {
  6427. /* PCH SDVOB multiplex with HDMIB */
  6428. found = intel_sdvo_init(dev, PCH_SDVOB, true);
  6429. if (!found)
  6430. intel_hdmi_init(dev, HDMIB, PORT_B);
  6431. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  6432. intel_dp_init(dev, PCH_DP_B, PORT_B);
  6433. }
  6434. if (I915_READ(HDMIC) & PORT_DETECTED)
  6435. intel_hdmi_init(dev, HDMIC, PORT_C);
  6436. if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
  6437. intel_hdmi_init(dev, HDMID, PORT_D);
  6438. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  6439. intel_dp_init(dev, PCH_DP_C, PORT_C);
  6440. if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  6441. intel_dp_init(dev, PCH_DP_D, PORT_D);
  6442. } else if (IS_VALLEYVIEW(dev)) {
  6443. int found;
  6444. if (I915_READ(SDVOB) & PORT_DETECTED) {
  6445. /* SDVOB multiplex with HDMIB */
  6446. found = intel_sdvo_init(dev, SDVOB, true);
  6447. if (!found)
  6448. intel_hdmi_init(dev, SDVOB, PORT_B);
  6449. if (!found && (I915_READ(DP_B) & DP_DETECTED))
  6450. intel_dp_init(dev, DP_B, PORT_B);
  6451. }
  6452. if (I915_READ(SDVOC) & PORT_DETECTED)
  6453. intel_hdmi_init(dev, SDVOC, PORT_C);
  6454. /* Shares lanes with HDMI on SDVOC */
  6455. if (I915_READ(DP_C) & DP_DETECTED)
  6456. intel_dp_init(dev, DP_C, PORT_C);
  6457. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  6458. bool found = false;
  6459. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  6460. DRM_DEBUG_KMS("probing SDVOB\n");
  6461. found = intel_sdvo_init(dev, SDVOB, true);
  6462. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  6463. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  6464. intel_hdmi_init(dev, SDVOB, PORT_B);
  6465. }
  6466. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  6467. DRM_DEBUG_KMS("probing DP_B\n");
  6468. intel_dp_init(dev, DP_B, PORT_B);
  6469. }
  6470. }
  6471. /* Before G4X SDVOC doesn't have its own detect register */
  6472. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  6473. DRM_DEBUG_KMS("probing SDVOC\n");
  6474. found = intel_sdvo_init(dev, SDVOC, false);
  6475. }
  6476. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  6477. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  6478. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  6479. intel_hdmi_init(dev, SDVOC, PORT_C);
  6480. }
  6481. if (SUPPORTS_INTEGRATED_DP(dev)) {
  6482. DRM_DEBUG_KMS("probing DP_C\n");
  6483. intel_dp_init(dev, DP_C, PORT_C);
  6484. }
  6485. }
  6486. if (SUPPORTS_INTEGRATED_DP(dev) &&
  6487. (I915_READ(DP_D) & DP_DETECTED)) {
  6488. DRM_DEBUG_KMS("probing DP_D\n");
  6489. intel_dp_init(dev, DP_D, PORT_D);
  6490. }
  6491. } else if (IS_GEN2(dev))
  6492. intel_dvo_init(dev);
  6493. if (SUPPORTS_TV(dev))
  6494. intel_tv_init(dev);
  6495. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  6496. encoder->base.possible_crtcs = encoder->crtc_mask;
  6497. encoder->base.possible_clones =
  6498. intel_encoder_clones(encoder);
  6499. }
  6500. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  6501. ironlake_init_pch_refclk(dev);
  6502. }
  6503. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  6504. {
  6505. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  6506. drm_framebuffer_cleanup(fb);
  6507. drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
  6508. kfree(intel_fb);
  6509. }
  6510. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  6511. struct drm_file *file,
  6512. unsigned int *handle)
  6513. {
  6514. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  6515. struct drm_i915_gem_object *obj = intel_fb->obj;
  6516. return drm_gem_handle_create(file, &obj->base, handle);
  6517. }
  6518. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  6519. .destroy = intel_user_framebuffer_destroy,
  6520. .create_handle = intel_user_framebuffer_create_handle,
  6521. };
  6522. int intel_framebuffer_init(struct drm_device *dev,
  6523. struct intel_framebuffer *intel_fb,
  6524. struct drm_mode_fb_cmd2 *mode_cmd,
  6525. struct drm_i915_gem_object *obj)
  6526. {
  6527. int ret;
  6528. if (obj->tiling_mode == I915_TILING_Y)
  6529. return -EINVAL;
  6530. if (mode_cmd->pitches[0] & 63)
  6531. return -EINVAL;
  6532. switch (mode_cmd->pixel_format) {
  6533. case DRM_FORMAT_RGB332:
  6534. case DRM_FORMAT_RGB565:
  6535. case DRM_FORMAT_XRGB8888:
  6536. case DRM_FORMAT_XBGR8888:
  6537. case DRM_FORMAT_ARGB8888:
  6538. case DRM_FORMAT_XRGB2101010:
  6539. case DRM_FORMAT_ARGB2101010:
  6540. /* RGB formats are common across chipsets */
  6541. break;
  6542. case DRM_FORMAT_YUYV:
  6543. case DRM_FORMAT_UYVY:
  6544. case DRM_FORMAT_YVYU:
  6545. case DRM_FORMAT_VYUY:
  6546. break;
  6547. default:
  6548. DRM_DEBUG_KMS("unsupported pixel format %u\n",
  6549. mode_cmd->pixel_format);
  6550. return -EINVAL;
  6551. }
  6552. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  6553. if (ret) {
  6554. DRM_ERROR("framebuffer init failed %d\n", ret);
  6555. return ret;
  6556. }
  6557. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  6558. intel_fb->obj = obj;
  6559. return 0;
  6560. }
  6561. static struct drm_framebuffer *
  6562. intel_user_framebuffer_create(struct drm_device *dev,
  6563. struct drm_file *filp,
  6564. struct drm_mode_fb_cmd2 *mode_cmd)
  6565. {
  6566. struct drm_i915_gem_object *obj;
  6567. obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  6568. mode_cmd->handles[0]));
  6569. if (&obj->base == NULL)
  6570. return ERR_PTR(-ENOENT);
  6571. return intel_framebuffer_create(dev, mode_cmd, obj);
  6572. }
  6573. static const struct drm_mode_config_funcs intel_mode_funcs = {
  6574. .fb_create = intel_user_framebuffer_create,
  6575. .output_poll_changed = intel_fb_output_poll_changed,
  6576. };
  6577. /* Set up chip specific display functions */
  6578. static void intel_init_display(struct drm_device *dev)
  6579. {
  6580. struct drm_i915_private *dev_priv = dev->dev_private;
  6581. /* We always want a DPMS function */
  6582. if (HAS_PCH_SPLIT(dev)) {
  6583. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  6584. dev_priv->display.crtc_enable = ironlake_crtc_enable;
  6585. dev_priv->display.crtc_disable = ironlake_crtc_disable;
  6586. dev_priv->display.off = ironlake_crtc_off;
  6587. dev_priv->display.update_plane = ironlake_update_plane;
  6588. } else {
  6589. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  6590. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  6591. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  6592. dev_priv->display.off = i9xx_crtc_off;
  6593. dev_priv->display.update_plane = i9xx_update_plane;
  6594. }
  6595. /* Returns the core display clock speed */
  6596. if (IS_VALLEYVIEW(dev))
  6597. dev_priv->display.get_display_clock_speed =
  6598. valleyview_get_display_clock_speed;
  6599. else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
  6600. dev_priv->display.get_display_clock_speed =
  6601. i945_get_display_clock_speed;
  6602. else if (IS_I915G(dev))
  6603. dev_priv->display.get_display_clock_speed =
  6604. i915_get_display_clock_speed;
  6605. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  6606. dev_priv->display.get_display_clock_speed =
  6607. i9xx_misc_get_display_clock_speed;
  6608. else if (IS_I915GM(dev))
  6609. dev_priv->display.get_display_clock_speed =
  6610. i915gm_get_display_clock_speed;
  6611. else if (IS_I865G(dev))
  6612. dev_priv->display.get_display_clock_speed =
  6613. i865_get_display_clock_speed;
  6614. else if (IS_I85X(dev))
  6615. dev_priv->display.get_display_clock_speed =
  6616. i855_get_display_clock_speed;
  6617. else /* 852, 830 */
  6618. dev_priv->display.get_display_clock_speed =
  6619. i830_get_display_clock_speed;
  6620. if (HAS_PCH_SPLIT(dev)) {
  6621. if (IS_GEN5(dev)) {
  6622. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  6623. dev_priv->display.write_eld = ironlake_write_eld;
  6624. } else if (IS_GEN6(dev)) {
  6625. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  6626. dev_priv->display.write_eld = ironlake_write_eld;
  6627. } else if (IS_IVYBRIDGE(dev)) {
  6628. /* FIXME: detect B0+ stepping and use auto training */
  6629. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  6630. dev_priv->display.write_eld = ironlake_write_eld;
  6631. } else if (IS_HASWELL(dev)) {
  6632. dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  6633. dev_priv->display.write_eld = haswell_write_eld;
  6634. } else
  6635. dev_priv->display.update_wm = NULL;
  6636. } else if (IS_G4X(dev)) {
  6637. dev_priv->display.write_eld = g4x_write_eld;
  6638. }
  6639. /* Default just returns -ENODEV to indicate unsupported */
  6640. dev_priv->display.queue_flip = intel_default_queue_flip;
  6641. switch (INTEL_INFO(dev)->gen) {
  6642. case 2:
  6643. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  6644. break;
  6645. case 3:
  6646. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  6647. break;
  6648. case 4:
  6649. case 5:
  6650. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  6651. break;
  6652. case 6:
  6653. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  6654. break;
  6655. case 7:
  6656. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  6657. break;
  6658. }
  6659. }
  6660. /*
  6661. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  6662. * resume, or other times. This quirk makes sure that's the case for
  6663. * affected systems.
  6664. */
  6665. static void quirk_pipea_force(struct drm_device *dev)
  6666. {
  6667. struct drm_i915_private *dev_priv = dev->dev_private;
  6668. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  6669. DRM_INFO("applying pipe a force quirk\n");
  6670. }
  6671. /*
  6672. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  6673. */
  6674. static void quirk_ssc_force_disable(struct drm_device *dev)
  6675. {
  6676. struct drm_i915_private *dev_priv = dev->dev_private;
  6677. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  6678. DRM_INFO("applying lvds SSC disable quirk\n");
  6679. }
  6680. /*
  6681. * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  6682. * brightness value
  6683. */
  6684. static void quirk_invert_brightness(struct drm_device *dev)
  6685. {
  6686. struct drm_i915_private *dev_priv = dev->dev_private;
  6687. dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  6688. DRM_INFO("applying inverted panel brightness quirk\n");
  6689. }
  6690. struct intel_quirk {
  6691. int device;
  6692. int subsystem_vendor;
  6693. int subsystem_device;
  6694. void (*hook)(struct drm_device *dev);
  6695. };
  6696. static struct intel_quirk intel_quirks[] = {
  6697. /* HP Mini needs pipe A force quirk (LP: #322104) */
  6698. { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  6699. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  6700. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  6701. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  6702. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  6703. /* 855 & before need to leave pipe A & dpll A up */
  6704. { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  6705. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  6706. { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  6707. /* Lenovo U160 cannot use SSC on LVDS */
  6708. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  6709. /* Sony Vaio Y cannot use SSC on LVDS */
  6710. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  6711. /* Acer Aspire 5734Z must invert backlight brightness */
  6712. { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
  6713. };
  6714. static void intel_init_quirks(struct drm_device *dev)
  6715. {
  6716. struct pci_dev *d = dev->pdev;
  6717. int i;
  6718. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  6719. struct intel_quirk *q = &intel_quirks[i];
  6720. if (d->device == q->device &&
  6721. (d->subsystem_vendor == q->subsystem_vendor ||
  6722. q->subsystem_vendor == PCI_ANY_ID) &&
  6723. (d->subsystem_device == q->subsystem_device ||
  6724. q->subsystem_device == PCI_ANY_ID))
  6725. q->hook(dev);
  6726. }
  6727. }
  6728. /* Disable the VGA plane that we never use */
  6729. static void i915_disable_vga(struct drm_device *dev)
  6730. {
  6731. struct drm_i915_private *dev_priv = dev->dev_private;
  6732. u8 sr1;
  6733. u32 vga_reg;
  6734. if (HAS_PCH_SPLIT(dev))
  6735. vga_reg = CPU_VGACNTRL;
  6736. else
  6737. vga_reg = VGACNTRL;
  6738. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  6739. outb(SR01, VGA_SR_INDEX);
  6740. sr1 = inb(VGA_SR_DATA);
  6741. outb(sr1 | 1<<5, VGA_SR_DATA);
  6742. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  6743. udelay(300);
  6744. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  6745. POSTING_READ(vga_reg);
  6746. }
  6747. void intel_modeset_init_hw(struct drm_device *dev)
  6748. {
  6749. /* We attempt to init the necessary power wells early in the initialization
  6750. * time, so the subsystems that expect power to be enabled can work.
  6751. */
  6752. intel_init_power_wells(dev);
  6753. intel_prepare_ddi(dev);
  6754. intel_init_clock_gating(dev);
  6755. mutex_lock(&dev->struct_mutex);
  6756. intel_enable_gt_powersave(dev);
  6757. mutex_unlock(&dev->struct_mutex);
  6758. }
  6759. void intel_modeset_init(struct drm_device *dev)
  6760. {
  6761. struct drm_i915_private *dev_priv = dev->dev_private;
  6762. int i, ret;
  6763. drm_mode_config_init(dev);
  6764. dev->mode_config.min_width = 0;
  6765. dev->mode_config.min_height = 0;
  6766. dev->mode_config.preferred_depth = 24;
  6767. dev->mode_config.prefer_shadow = 1;
  6768. dev->mode_config.funcs = &intel_mode_funcs;
  6769. intel_init_quirks(dev);
  6770. intel_init_pm(dev);
  6771. intel_init_display(dev);
  6772. if (IS_GEN2(dev)) {
  6773. dev->mode_config.max_width = 2048;
  6774. dev->mode_config.max_height = 2048;
  6775. } else if (IS_GEN3(dev)) {
  6776. dev->mode_config.max_width = 4096;
  6777. dev->mode_config.max_height = 4096;
  6778. } else {
  6779. dev->mode_config.max_width = 8192;
  6780. dev->mode_config.max_height = 8192;
  6781. }
  6782. dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
  6783. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  6784. dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
  6785. for (i = 0; i < dev_priv->num_pipe; i++) {
  6786. intel_crtc_init(dev, i);
  6787. ret = intel_plane_init(dev, i);
  6788. if (ret)
  6789. DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
  6790. }
  6791. intel_pch_pll_init(dev);
  6792. /* Just disable it once at startup */
  6793. i915_disable_vga(dev);
  6794. intel_setup_outputs(dev);
  6795. }
  6796. static void
  6797. intel_connector_break_all_links(struct intel_connector *connector)
  6798. {
  6799. connector->base.dpms = DRM_MODE_DPMS_OFF;
  6800. connector->base.encoder = NULL;
  6801. connector->encoder->connectors_active = false;
  6802. connector->encoder->base.crtc = NULL;
  6803. }
  6804. static void intel_enable_pipe_a(struct drm_device *dev)
  6805. {
  6806. struct intel_connector *connector;
  6807. struct drm_connector *crt = NULL;
  6808. struct intel_load_detect_pipe load_detect_temp;
  6809. /* We can't just switch on the pipe A, we need to set things up with a
  6810. * proper mode and output configuration. As a gross hack, enable pipe A
  6811. * by enabling the load detect pipe once. */
  6812. list_for_each_entry(connector,
  6813. &dev->mode_config.connector_list,
  6814. base.head) {
  6815. if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
  6816. crt = &connector->base;
  6817. break;
  6818. }
  6819. }
  6820. if (!crt)
  6821. return;
  6822. if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
  6823. intel_release_load_detect_pipe(crt, &load_detect_temp);
  6824. }
  6825. static void intel_sanitize_crtc(struct intel_crtc *crtc)
  6826. {
  6827. struct drm_device *dev = crtc->base.dev;
  6828. struct drm_i915_private *dev_priv = dev->dev_private;
  6829. u32 reg, val;
  6830. /* Clear any frame start delays used for debugging left by the BIOS */
  6831. reg = PIPECONF(crtc->pipe);
  6832. I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  6833. /* We need to sanitize the plane -> pipe mapping first because this will
  6834. * disable the crtc (and hence change the state) if it is wrong. */
  6835. if (!HAS_PCH_SPLIT(dev)) {
  6836. struct intel_connector *connector;
  6837. bool plane;
  6838. reg = DSPCNTR(crtc->plane);
  6839. val = I915_READ(reg);
  6840. if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
  6841. (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
  6842. goto ok;
  6843. DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
  6844. crtc->base.base.id);
  6845. /* Pipe has the wrong plane attached and the plane is active.
  6846. * Temporarily change the plane mapping and disable everything
  6847. * ... */
  6848. plane = crtc->plane;
  6849. crtc->plane = !plane;
  6850. dev_priv->display.crtc_disable(&crtc->base);
  6851. crtc->plane = plane;
  6852. /* ... and break all links. */
  6853. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6854. base.head) {
  6855. if (connector->encoder->base.crtc != &crtc->base)
  6856. continue;
  6857. intel_connector_break_all_links(connector);
  6858. }
  6859. WARN_ON(crtc->active);
  6860. crtc->base.enabled = false;
  6861. }
  6862. ok:
  6863. if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  6864. crtc->pipe == PIPE_A && !crtc->active) {
  6865. /* BIOS forgot to enable pipe A, this mostly happens after
  6866. * resume. Force-enable the pipe to fix this, the update_dpms
  6867. * call below we restore the pipe to the right state, but leave
  6868. * the required bits on. */
  6869. intel_enable_pipe_a(dev);
  6870. }
  6871. /* Adjust the state of the output pipe according to whether we
  6872. * have active connectors/encoders. */
  6873. intel_crtc_update_dpms(&crtc->base);
  6874. if (crtc->active != crtc->base.enabled) {
  6875. struct intel_encoder *encoder;
  6876. /* This can happen either due to bugs in the get_hw_state
  6877. * functions or because the pipe is force-enabled due to the
  6878. * pipe A quirk. */
  6879. DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
  6880. crtc->base.base.id,
  6881. crtc->base.enabled ? "enabled" : "disabled",
  6882. crtc->active ? "enabled" : "disabled");
  6883. crtc->base.enabled = crtc->active;
  6884. /* Because we only establish the connector -> encoder ->
  6885. * crtc links if something is active, this means the
  6886. * crtc is now deactivated. Break the links. connector
  6887. * -> encoder links are only establish when things are
  6888. * actually up, hence no need to break them. */
  6889. WARN_ON(crtc->active);
  6890. for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
  6891. WARN_ON(encoder->connectors_active);
  6892. encoder->base.crtc = NULL;
  6893. }
  6894. }
  6895. }
  6896. static void intel_sanitize_encoder(struct intel_encoder *encoder)
  6897. {
  6898. struct intel_connector *connector;
  6899. struct drm_device *dev = encoder->base.dev;
  6900. /* We need to check both for a crtc link (meaning that the
  6901. * encoder is active and trying to read from a pipe) and the
  6902. * pipe itself being active. */
  6903. bool has_active_crtc = encoder->base.crtc &&
  6904. to_intel_crtc(encoder->base.crtc)->active;
  6905. if (encoder->connectors_active && !has_active_crtc) {
  6906. DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
  6907. encoder->base.base.id,
  6908. drm_get_encoder_name(&encoder->base));
  6909. /* Connector is active, but has no active pipe. This is
  6910. * fallout from our resume register restoring. Disable
  6911. * the encoder manually again. */
  6912. if (encoder->base.crtc) {
  6913. DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
  6914. encoder->base.base.id,
  6915. drm_get_encoder_name(&encoder->base));
  6916. encoder->disable(encoder);
  6917. }
  6918. /* Inconsistent output/port/pipe state happens presumably due to
  6919. * a bug in one of the get_hw_state functions. Or someplace else
  6920. * in our code, like the register restore mess on resume. Clamp
  6921. * things to off as a safer default. */
  6922. list_for_each_entry(connector,
  6923. &dev->mode_config.connector_list,
  6924. base.head) {
  6925. if (connector->encoder != encoder)
  6926. continue;
  6927. intel_connector_break_all_links(connector);
  6928. }
  6929. }
  6930. /* Enabled encoders without active connectors will be fixed in
  6931. * the crtc fixup. */
  6932. }
  6933. /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
  6934. * and i915 state tracking structures. */
  6935. void intel_modeset_setup_hw_state(struct drm_device *dev)
  6936. {
  6937. struct drm_i915_private *dev_priv = dev->dev_private;
  6938. enum pipe pipe;
  6939. u32 tmp;
  6940. struct intel_crtc *crtc;
  6941. struct intel_encoder *encoder;
  6942. struct intel_connector *connector;
  6943. for_each_pipe(pipe) {
  6944. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  6945. tmp = I915_READ(PIPECONF(pipe));
  6946. if (tmp & PIPECONF_ENABLE)
  6947. crtc->active = true;
  6948. else
  6949. crtc->active = false;
  6950. crtc->base.enabled = crtc->active;
  6951. DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
  6952. crtc->base.base.id,
  6953. crtc->active ? "enabled" : "disabled");
  6954. }
  6955. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6956. base.head) {
  6957. pipe = 0;
  6958. if (encoder->get_hw_state(encoder, &pipe)) {
  6959. encoder->base.crtc =
  6960. dev_priv->pipe_to_crtc_mapping[pipe];
  6961. } else {
  6962. encoder->base.crtc = NULL;
  6963. }
  6964. encoder->connectors_active = false;
  6965. DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
  6966. encoder->base.base.id,
  6967. drm_get_encoder_name(&encoder->base),
  6968. encoder->base.crtc ? "enabled" : "disabled",
  6969. pipe);
  6970. }
  6971. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6972. base.head) {
  6973. if (connector->get_hw_state(connector)) {
  6974. connector->base.dpms = DRM_MODE_DPMS_ON;
  6975. connector->encoder->connectors_active = true;
  6976. connector->base.encoder = &connector->encoder->base;
  6977. } else {
  6978. connector->base.dpms = DRM_MODE_DPMS_OFF;
  6979. connector->base.encoder = NULL;
  6980. }
  6981. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
  6982. connector->base.base.id,
  6983. drm_get_connector_name(&connector->base),
  6984. connector->base.encoder ? "enabled" : "disabled");
  6985. }
  6986. /* HW state is read out, now we need to sanitize this mess. */
  6987. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6988. base.head) {
  6989. intel_sanitize_encoder(encoder);
  6990. }
  6991. for_each_pipe(pipe) {
  6992. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  6993. intel_sanitize_crtc(crtc);
  6994. }
  6995. intel_modeset_update_staged_output_state(dev);
  6996. intel_modeset_check_state(dev);
  6997. }
  6998. void intel_modeset_gem_init(struct drm_device *dev)
  6999. {
  7000. intel_modeset_init_hw(dev);
  7001. intel_setup_overlay(dev);
  7002. intel_modeset_setup_hw_state(dev);
  7003. }
  7004. void intel_modeset_cleanup(struct drm_device *dev)
  7005. {
  7006. struct drm_i915_private *dev_priv = dev->dev_private;
  7007. struct drm_crtc *crtc;
  7008. struct intel_crtc *intel_crtc;
  7009. drm_kms_helper_poll_fini(dev);
  7010. mutex_lock(&dev->struct_mutex);
  7011. intel_unregister_dsm_handler();
  7012. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  7013. /* Skip inactive CRTCs */
  7014. if (!crtc->fb)
  7015. continue;
  7016. intel_crtc = to_intel_crtc(crtc);
  7017. intel_increase_pllclock(crtc);
  7018. }
  7019. intel_disable_fbc(dev);
  7020. intel_disable_gt_powersave(dev);
  7021. ironlake_teardown_rc6(dev);
  7022. if (IS_VALLEYVIEW(dev))
  7023. vlv_init_dpio(dev);
  7024. mutex_unlock(&dev->struct_mutex);
  7025. /* Disable the irq before mode object teardown, for the irq might
  7026. * enqueue unpin/hotplug work. */
  7027. drm_irq_uninstall(dev);
  7028. cancel_work_sync(&dev_priv->hotplug_work);
  7029. cancel_work_sync(&dev_priv->rps.work);
  7030. /* flush any delayed tasks or pending work */
  7031. flush_scheduled_work();
  7032. drm_mode_config_cleanup(dev);
  7033. }
  7034. /*
  7035. * Return which encoder is currently attached for connector.
  7036. */
  7037. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  7038. {
  7039. return &intel_attached_encoder(connector)->base;
  7040. }
  7041. void intel_connector_attach_encoder(struct intel_connector *connector,
  7042. struct intel_encoder *encoder)
  7043. {
  7044. connector->encoder = encoder;
  7045. drm_mode_connector_attach_encoder(&connector->base,
  7046. &encoder->base);
  7047. }
  7048. /*
  7049. * set vga decode state - true == enable VGA decode
  7050. */
  7051. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  7052. {
  7053. struct drm_i915_private *dev_priv = dev->dev_private;
  7054. u16 gmch_ctrl;
  7055. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  7056. if (state)
  7057. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  7058. else
  7059. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  7060. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  7061. return 0;
  7062. }
  7063. #ifdef CONFIG_DEBUG_FS
  7064. #include <linux/seq_file.h>
  7065. struct intel_display_error_state {
  7066. struct intel_cursor_error_state {
  7067. u32 control;
  7068. u32 position;
  7069. u32 base;
  7070. u32 size;
  7071. } cursor[I915_MAX_PIPES];
  7072. struct intel_pipe_error_state {
  7073. u32 conf;
  7074. u32 source;
  7075. u32 htotal;
  7076. u32 hblank;
  7077. u32 hsync;
  7078. u32 vtotal;
  7079. u32 vblank;
  7080. u32 vsync;
  7081. } pipe[I915_MAX_PIPES];
  7082. struct intel_plane_error_state {
  7083. u32 control;
  7084. u32 stride;
  7085. u32 size;
  7086. u32 pos;
  7087. u32 addr;
  7088. u32 surface;
  7089. u32 tile_offset;
  7090. } plane[I915_MAX_PIPES];
  7091. };
  7092. struct intel_display_error_state *
  7093. intel_display_capture_error_state(struct drm_device *dev)
  7094. {
  7095. drm_i915_private_t *dev_priv = dev->dev_private;
  7096. struct intel_display_error_state *error;
  7097. int i;
  7098. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  7099. if (error == NULL)
  7100. return NULL;
  7101. for_each_pipe(i) {
  7102. error->cursor[i].control = I915_READ(CURCNTR(i));
  7103. error->cursor[i].position = I915_READ(CURPOS(i));
  7104. error->cursor[i].base = I915_READ(CURBASE(i));
  7105. error->plane[i].control = I915_READ(DSPCNTR(i));
  7106. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  7107. error->plane[i].size = I915_READ(DSPSIZE(i));
  7108. error->plane[i].pos = I915_READ(DSPPOS(i));
  7109. error->plane[i].addr = I915_READ(DSPADDR(i));
  7110. if (INTEL_INFO(dev)->gen >= 4) {
  7111. error->plane[i].surface = I915_READ(DSPSURF(i));
  7112. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  7113. }
  7114. error->pipe[i].conf = I915_READ(PIPECONF(i));
  7115. error->pipe[i].source = I915_READ(PIPESRC(i));
  7116. error->pipe[i].htotal = I915_READ(HTOTAL(i));
  7117. error->pipe[i].hblank = I915_READ(HBLANK(i));
  7118. error->pipe[i].hsync = I915_READ(HSYNC(i));
  7119. error->pipe[i].vtotal = I915_READ(VTOTAL(i));
  7120. error->pipe[i].vblank = I915_READ(VBLANK(i));
  7121. error->pipe[i].vsync = I915_READ(VSYNC(i));
  7122. }
  7123. return error;
  7124. }
  7125. void
  7126. intel_display_print_error_state(struct seq_file *m,
  7127. struct drm_device *dev,
  7128. struct intel_display_error_state *error)
  7129. {
  7130. drm_i915_private_t *dev_priv = dev->dev_private;
  7131. int i;
  7132. seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
  7133. for_each_pipe(i) {
  7134. seq_printf(m, "Pipe [%d]:\n", i);
  7135. seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
  7136. seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
  7137. seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
  7138. seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
  7139. seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
  7140. seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
  7141. seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
  7142. seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
  7143. seq_printf(m, "Plane [%d]:\n", i);
  7144. seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
  7145. seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  7146. seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
  7147. seq_printf(m, " POS: %08x\n", error->plane[i].pos);
  7148. seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  7149. if (INTEL_INFO(dev)->gen >= 4) {
  7150. seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
  7151. seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  7152. }
  7153. seq_printf(m, "Cursor [%d]:\n", i);
  7154. seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  7155. seq_printf(m, " POS: %08x\n", error->cursor[i].position);
  7156. seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
  7157. }
  7158. }
  7159. #endif