sdhci.c 34 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. /*
  11. * Note that PIO transfer is rather crappy atm. The buffer full/empty
  12. * interrupts aren't reliable so we currently transfer the entire buffer
  13. * directly. Patches to solve the problem are welcome.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/highmem.h>
  17. #include <linux/pci.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/protocol.h>
  21. #include <asm/scatterlist.h>
  22. #include "sdhci.h"
  23. #define DRIVER_NAME "sdhci"
  24. #define DRIVER_VERSION "0.11"
  25. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  26. #define DBG(f, x...) \
  27. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  28. static const struct pci_device_id pci_ids[] __devinitdata = {
  29. /* handle any SD host controller */
  30. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  31. { /* end: all zeroes */ },
  32. };
  33. MODULE_DEVICE_TABLE(pci, pci_ids);
  34. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  35. static void sdhci_finish_data(struct sdhci_host *);
  36. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  37. static void sdhci_finish_command(struct sdhci_host *);
  38. static void sdhci_dumpregs(struct sdhci_host *host)
  39. {
  40. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  41. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  42. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  43. readw(host->ioaddr + SDHCI_HOST_VERSION));
  44. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  45. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  46. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  47. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  48. readl(host->ioaddr + SDHCI_ARGUMENT),
  49. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  50. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  51. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  52. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  53. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  54. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  55. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  56. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  57. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  58. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  59. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  60. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  61. readl(host->ioaddr + SDHCI_INT_STATUS));
  62. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  63. readl(host->ioaddr + SDHCI_INT_ENABLE),
  64. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  65. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  66. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  67. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  68. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  69. readl(host->ioaddr + SDHCI_CAPABILITIES),
  70. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  71. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  72. }
  73. /*****************************************************************************\
  74. * *
  75. * Low level functions *
  76. * *
  77. \*****************************************************************************/
  78. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  79. {
  80. unsigned long timeout;
  81. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  82. if (mask & SDHCI_RESET_ALL)
  83. host->clock = 0;
  84. /* Wait max 100 ms */
  85. timeout = 100;
  86. /* hw clears the bit when it's done */
  87. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  88. if (timeout == 0) {
  89. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  90. "Please report this to " BUGMAIL ".\n",
  91. mmc_hostname(host->mmc), (int)mask);
  92. sdhci_dumpregs(host);
  93. return;
  94. }
  95. timeout--;
  96. mdelay(1);
  97. }
  98. }
  99. static void sdhci_init(struct sdhci_host *host)
  100. {
  101. u32 intmask;
  102. sdhci_reset(host, SDHCI_RESET_ALL);
  103. intmask = ~(SDHCI_INT_CARD_INT | SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  104. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  105. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  106. }
  107. static void sdhci_activate_led(struct sdhci_host *host)
  108. {
  109. u8 ctrl;
  110. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  111. ctrl |= SDHCI_CTRL_LED;
  112. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  113. }
  114. static void sdhci_deactivate_led(struct sdhci_host *host)
  115. {
  116. u8 ctrl;
  117. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  118. ctrl &= ~SDHCI_CTRL_LED;
  119. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  120. }
  121. /*****************************************************************************\
  122. * *
  123. * Core functions *
  124. * *
  125. \*****************************************************************************/
  126. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  127. {
  128. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  129. return host->mapped_sg + host->cur_sg->offset;
  130. }
  131. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  132. {
  133. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  134. }
  135. static inline int sdhci_next_sg(struct sdhci_host* host)
  136. {
  137. /*
  138. * Skip to next SG entry.
  139. */
  140. host->cur_sg++;
  141. host->num_sg--;
  142. /*
  143. * Any entries left?
  144. */
  145. if (host->num_sg > 0) {
  146. host->offset = 0;
  147. host->remain = host->cur_sg->length;
  148. }
  149. return host->num_sg;
  150. }
  151. static void sdhci_transfer_pio(struct sdhci_host *host)
  152. {
  153. char *buffer;
  154. u32 mask;
  155. int bytes, size;
  156. unsigned long max_jiffies;
  157. BUG_ON(!host->data);
  158. if (host->num_sg == 0)
  159. return;
  160. bytes = 0;
  161. if (host->data->flags & MMC_DATA_READ)
  162. mask = SDHCI_DATA_AVAILABLE;
  163. else
  164. mask = SDHCI_SPACE_AVAILABLE;
  165. buffer = sdhci_kmap_sg(host) + host->offset;
  166. /* Transfer shouldn't take more than 5 s */
  167. max_jiffies = jiffies + HZ * 5;
  168. while (host->size > 0) {
  169. if (time_after(jiffies, max_jiffies)) {
  170. printk(KERN_ERR "%s: PIO transfer stalled. "
  171. "Please report this to "
  172. BUGMAIL ".\n", mmc_hostname(host->mmc));
  173. sdhci_dumpregs(host);
  174. sdhci_kunmap_sg(host);
  175. host->data->error = MMC_ERR_FAILED;
  176. sdhci_finish_data(host);
  177. return;
  178. }
  179. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask))
  180. continue;
  181. size = min(host->size, host->remain);
  182. if (size >= 4) {
  183. if (host->data->flags & MMC_DATA_READ)
  184. *(u32*)buffer = readl(host->ioaddr + SDHCI_BUFFER);
  185. else
  186. writel(*(u32*)buffer, host->ioaddr + SDHCI_BUFFER);
  187. size = 4;
  188. } else if (size >= 2) {
  189. if (host->data->flags & MMC_DATA_READ)
  190. *(u16*)buffer = readw(host->ioaddr + SDHCI_BUFFER);
  191. else
  192. writew(*(u16*)buffer, host->ioaddr + SDHCI_BUFFER);
  193. size = 2;
  194. } else {
  195. if (host->data->flags & MMC_DATA_READ)
  196. *(u8*)buffer = readb(host->ioaddr + SDHCI_BUFFER);
  197. else
  198. writeb(*(u8*)buffer, host->ioaddr + SDHCI_BUFFER);
  199. size = 1;
  200. }
  201. buffer += size;
  202. host->offset += size;
  203. host->remain -= size;
  204. bytes += size;
  205. host->size -= size;
  206. if (host->remain == 0) {
  207. sdhci_kunmap_sg(host);
  208. if (sdhci_next_sg(host) == 0) {
  209. DBG("PIO transfer: %d bytes\n", bytes);
  210. return;
  211. }
  212. buffer = sdhci_kmap_sg(host);
  213. }
  214. }
  215. sdhci_kunmap_sg(host);
  216. DBG("PIO transfer: %d bytes\n", bytes);
  217. }
  218. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  219. {
  220. u8 count;
  221. unsigned target_timeout, current_timeout;
  222. WARN_ON(host->data);
  223. if (data == NULL)
  224. return;
  225. DBG("blksz %04x blks %04x flags %08x\n",
  226. data->blksz, data->blocks, data->flags);
  227. DBG("tsac %d ms nsac %d clk\n",
  228. data->timeout_ns / 1000000, data->timeout_clks);
  229. /* timeout in us */
  230. target_timeout = data->timeout_ns / 1000 +
  231. data->timeout_clks / host->clock;
  232. /*
  233. * Figure out needed cycles.
  234. * We do this in steps in order to fit inside a 32 bit int.
  235. * The first step is the minimum timeout, which will have a
  236. * minimum resolution of 6 bits:
  237. * (1) 2^13*1000 > 2^22,
  238. * (2) host->timeout_clk < 2^16
  239. * =>
  240. * (1) / (2) > 2^6
  241. */
  242. count = 0;
  243. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  244. while (current_timeout < target_timeout) {
  245. count++;
  246. current_timeout <<= 1;
  247. if (count >= 0xF)
  248. break;
  249. }
  250. if (count >= 0xF) {
  251. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  252. mmc_hostname(host->mmc));
  253. count = 0xE;
  254. }
  255. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  256. if (host->flags & SDHCI_USE_DMA) {
  257. int count;
  258. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  259. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  260. BUG_ON(count != 1);
  261. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  262. } else {
  263. host->size = data->blksz * data->blocks;
  264. host->cur_sg = data->sg;
  265. host->num_sg = data->sg_len;
  266. host->offset = 0;
  267. host->remain = host->cur_sg->length;
  268. }
  269. writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE);
  270. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  271. }
  272. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  273. struct mmc_data *data)
  274. {
  275. u16 mode;
  276. WARN_ON(host->data);
  277. if (data == NULL)
  278. return;
  279. mode = SDHCI_TRNS_BLK_CNT_EN;
  280. if (data->blocks > 1)
  281. mode |= SDHCI_TRNS_MULTI;
  282. if (data->flags & MMC_DATA_READ)
  283. mode |= SDHCI_TRNS_READ;
  284. if (host->flags & SDHCI_USE_DMA)
  285. mode |= SDHCI_TRNS_DMA;
  286. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  287. }
  288. static void sdhci_finish_data(struct sdhci_host *host)
  289. {
  290. struct mmc_data *data;
  291. u32 intmask;
  292. u16 blocks;
  293. BUG_ON(!host->data);
  294. data = host->data;
  295. host->data = NULL;
  296. if (host->flags & SDHCI_USE_DMA) {
  297. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  298. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  299. } else {
  300. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  301. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  302. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  303. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  304. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  305. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  306. }
  307. /*
  308. * Controller doesn't count down when in single block mode.
  309. */
  310. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  311. blocks = 0;
  312. else
  313. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  314. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  315. if ((data->error == MMC_ERR_NONE) && blocks) {
  316. printk(KERN_ERR "%s: Controller signalled completion even "
  317. "though there were blocks left. Please report this "
  318. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  319. data->error = MMC_ERR_FAILED;
  320. }
  321. if (host->size != 0) {
  322. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  323. "Please report this to " BUGMAIL ".\n",
  324. mmc_hostname(host->mmc), host->size);
  325. data->error = MMC_ERR_FAILED;
  326. }
  327. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  328. if (data->stop) {
  329. /*
  330. * The controller needs a reset of internal state machines
  331. * upon error conditions.
  332. */
  333. if (data->error != MMC_ERR_NONE) {
  334. sdhci_reset(host, SDHCI_RESET_CMD);
  335. sdhci_reset(host, SDHCI_RESET_DATA);
  336. }
  337. sdhci_send_command(host, data->stop);
  338. } else
  339. tasklet_schedule(&host->finish_tasklet);
  340. }
  341. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  342. {
  343. int flags;
  344. unsigned long timeout;
  345. WARN_ON(host->cmd);
  346. DBG("Sending cmd (%x)\n", cmd->opcode);
  347. /* Wait max 10 ms */
  348. timeout = 10;
  349. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  350. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  351. if (timeout == 0) {
  352. printk(KERN_ERR "%s: Controller never released "
  353. "inhibit bits. Please report this to "
  354. BUGMAIL ".\n", mmc_hostname(host->mmc));
  355. sdhci_dumpregs(host);
  356. cmd->error = MMC_ERR_FAILED;
  357. tasklet_schedule(&host->finish_tasklet);
  358. return;
  359. }
  360. timeout--;
  361. mdelay(1);
  362. }
  363. mod_timer(&host->timer, jiffies + 10 * HZ);
  364. host->cmd = cmd;
  365. sdhci_prepare_data(host, cmd->data);
  366. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  367. sdhci_set_transfer_mode(host, cmd->data);
  368. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  369. printk(KERN_ERR "%s: Unsupported response type! "
  370. "Please report this to " BUGMAIL ".\n",
  371. mmc_hostname(host->mmc));
  372. cmd->error = MMC_ERR_INVALID;
  373. tasklet_schedule(&host->finish_tasklet);
  374. return;
  375. }
  376. if (!(cmd->flags & MMC_RSP_PRESENT))
  377. flags = SDHCI_CMD_RESP_NONE;
  378. else if (cmd->flags & MMC_RSP_136)
  379. flags = SDHCI_CMD_RESP_LONG;
  380. else if (cmd->flags & MMC_RSP_BUSY)
  381. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  382. else
  383. flags = SDHCI_CMD_RESP_SHORT;
  384. if (cmd->flags & MMC_RSP_CRC)
  385. flags |= SDHCI_CMD_CRC;
  386. if (cmd->flags & MMC_RSP_OPCODE)
  387. flags |= SDHCI_CMD_INDEX;
  388. if (cmd->data)
  389. flags |= SDHCI_CMD_DATA;
  390. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  391. host->ioaddr + SDHCI_COMMAND);
  392. }
  393. static void sdhci_finish_command(struct sdhci_host *host)
  394. {
  395. int i;
  396. BUG_ON(host->cmd == NULL);
  397. if (host->cmd->flags & MMC_RSP_PRESENT) {
  398. if (host->cmd->flags & MMC_RSP_136) {
  399. /* CRC is stripped so we need to do some shifting. */
  400. for (i = 0;i < 4;i++) {
  401. host->cmd->resp[i] = readl(host->ioaddr +
  402. SDHCI_RESPONSE + (3-i)*4) << 8;
  403. if (i != 3)
  404. host->cmd->resp[i] |=
  405. readb(host->ioaddr +
  406. SDHCI_RESPONSE + (3-i)*4-1);
  407. }
  408. } else {
  409. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  410. }
  411. }
  412. host->cmd->error = MMC_ERR_NONE;
  413. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  414. if (host->cmd->data) {
  415. u32 intmask;
  416. host->data = host->cmd->data;
  417. if (!(host->flags & SDHCI_USE_DMA)) {
  418. /*
  419. * Don't enable the interrupts until now to make sure we
  420. * get stable handling of the FIFO.
  421. */
  422. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  423. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  424. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  425. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  426. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  427. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  428. /*
  429. * The buffer interrupts are to unreliable so we
  430. * start the transfer immediatly.
  431. */
  432. sdhci_transfer_pio(host);
  433. }
  434. } else
  435. tasklet_schedule(&host->finish_tasklet);
  436. host->cmd = NULL;
  437. }
  438. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  439. {
  440. int div;
  441. u16 clk;
  442. unsigned long timeout;
  443. if (clock == host->clock)
  444. return;
  445. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  446. if (clock == 0)
  447. goto out;
  448. for (div = 1;div < 256;div *= 2) {
  449. if ((host->max_clk / div) <= clock)
  450. break;
  451. }
  452. div >>= 1;
  453. clk = div << SDHCI_DIVIDER_SHIFT;
  454. clk |= SDHCI_CLOCK_INT_EN;
  455. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  456. /* Wait max 10 ms */
  457. timeout = 10;
  458. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  459. & SDHCI_CLOCK_INT_STABLE)) {
  460. if (timeout == 0) {
  461. printk(KERN_ERR "%s: Internal clock never stabilised. "
  462. "Please report this to " BUGMAIL ".\n",
  463. mmc_hostname(host->mmc));
  464. sdhci_dumpregs(host);
  465. return;
  466. }
  467. timeout--;
  468. mdelay(1);
  469. }
  470. clk |= SDHCI_CLOCK_CARD_EN;
  471. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  472. out:
  473. host->clock = clock;
  474. }
  475. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  476. {
  477. u8 pwr;
  478. if (host->power == power)
  479. return;
  480. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  481. if (power == (unsigned short)-1)
  482. goto out;
  483. pwr = SDHCI_POWER_ON;
  484. switch (power) {
  485. case MMC_VDD_170:
  486. case MMC_VDD_180:
  487. case MMC_VDD_190:
  488. pwr |= SDHCI_POWER_180;
  489. break;
  490. case MMC_VDD_290:
  491. case MMC_VDD_300:
  492. case MMC_VDD_310:
  493. pwr |= SDHCI_POWER_300;
  494. break;
  495. case MMC_VDD_320:
  496. case MMC_VDD_330:
  497. case MMC_VDD_340:
  498. pwr |= SDHCI_POWER_330;
  499. break;
  500. default:
  501. BUG();
  502. }
  503. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  504. out:
  505. host->power = power;
  506. }
  507. /*****************************************************************************\
  508. * *
  509. * MMC callbacks *
  510. * *
  511. \*****************************************************************************/
  512. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  513. {
  514. struct sdhci_host *host;
  515. unsigned long flags;
  516. host = mmc_priv(mmc);
  517. spin_lock_irqsave(&host->lock, flags);
  518. WARN_ON(host->mrq != NULL);
  519. sdhci_activate_led(host);
  520. host->mrq = mrq;
  521. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  522. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  523. tasklet_schedule(&host->finish_tasklet);
  524. } else
  525. sdhci_send_command(host, mrq->cmd);
  526. spin_unlock_irqrestore(&host->lock, flags);
  527. }
  528. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  529. {
  530. struct sdhci_host *host;
  531. unsigned long flags;
  532. u8 ctrl;
  533. host = mmc_priv(mmc);
  534. spin_lock_irqsave(&host->lock, flags);
  535. /*
  536. * Reset the chip on each power off.
  537. * Should clear out any weird states.
  538. */
  539. if (ios->power_mode == MMC_POWER_OFF) {
  540. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  541. sdhci_init(host);
  542. }
  543. sdhci_set_clock(host, ios->clock);
  544. if (ios->power_mode == MMC_POWER_OFF)
  545. sdhci_set_power(host, -1);
  546. else
  547. sdhci_set_power(host, ios->vdd);
  548. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  549. if (ios->bus_width == MMC_BUS_WIDTH_4)
  550. ctrl |= SDHCI_CTRL_4BITBUS;
  551. else
  552. ctrl &= ~SDHCI_CTRL_4BITBUS;
  553. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  554. spin_unlock_irqrestore(&host->lock, flags);
  555. }
  556. static int sdhci_get_ro(struct mmc_host *mmc)
  557. {
  558. struct sdhci_host *host;
  559. unsigned long flags;
  560. int present;
  561. host = mmc_priv(mmc);
  562. spin_lock_irqsave(&host->lock, flags);
  563. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  564. spin_unlock_irqrestore(&host->lock, flags);
  565. return !(present & SDHCI_WRITE_PROTECT);
  566. }
  567. static struct mmc_host_ops sdhci_ops = {
  568. .request = sdhci_request,
  569. .set_ios = sdhci_set_ios,
  570. .get_ro = sdhci_get_ro,
  571. };
  572. /*****************************************************************************\
  573. * *
  574. * Tasklets *
  575. * *
  576. \*****************************************************************************/
  577. static void sdhci_tasklet_card(unsigned long param)
  578. {
  579. struct sdhci_host *host;
  580. unsigned long flags;
  581. host = (struct sdhci_host*)param;
  582. spin_lock_irqsave(&host->lock, flags);
  583. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  584. if (host->mrq) {
  585. printk(KERN_ERR "%s: Card removed during transfer!\n",
  586. mmc_hostname(host->mmc));
  587. printk(KERN_ERR "%s: Resetting controller.\n",
  588. mmc_hostname(host->mmc));
  589. sdhci_reset(host, SDHCI_RESET_CMD);
  590. sdhci_reset(host, SDHCI_RESET_DATA);
  591. host->mrq->cmd->error = MMC_ERR_FAILED;
  592. tasklet_schedule(&host->finish_tasklet);
  593. }
  594. }
  595. spin_unlock_irqrestore(&host->lock, flags);
  596. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  597. }
  598. static void sdhci_tasklet_finish(unsigned long param)
  599. {
  600. struct sdhci_host *host;
  601. unsigned long flags;
  602. struct mmc_request *mrq;
  603. host = (struct sdhci_host*)param;
  604. spin_lock_irqsave(&host->lock, flags);
  605. del_timer(&host->timer);
  606. mrq = host->mrq;
  607. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  608. /*
  609. * The controller needs a reset of internal state machines
  610. * upon error conditions.
  611. */
  612. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  613. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  614. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  615. sdhci_reset(host, SDHCI_RESET_CMD);
  616. sdhci_reset(host, SDHCI_RESET_DATA);
  617. }
  618. host->mrq = NULL;
  619. host->cmd = NULL;
  620. host->data = NULL;
  621. sdhci_deactivate_led(host);
  622. spin_unlock_irqrestore(&host->lock, flags);
  623. mmc_request_done(host->mmc, mrq);
  624. }
  625. static void sdhci_timeout_timer(unsigned long data)
  626. {
  627. struct sdhci_host *host;
  628. unsigned long flags;
  629. host = (struct sdhci_host*)data;
  630. spin_lock_irqsave(&host->lock, flags);
  631. if (host->mrq) {
  632. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  633. "Please report this to " BUGMAIL ".\n",
  634. mmc_hostname(host->mmc));
  635. sdhci_dumpregs(host);
  636. if (host->data) {
  637. host->data->error = MMC_ERR_TIMEOUT;
  638. sdhci_finish_data(host);
  639. } else {
  640. if (host->cmd)
  641. host->cmd->error = MMC_ERR_TIMEOUT;
  642. else
  643. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  644. tasklet_schedule(&host->finish_tasklet);
  645. }
  646. }
  647. spin_unlock_irqrestore(&host->lock, flags);
  648. }
  649. /*****************************************************************************\
  650. * *
  651. * Interrupt handling *
  652. * *
  653. \*****************************************************************************/
  654. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  655. {
  656. BUG_ON(intmask == 0);
  657. if (!host->cmd) {
  658. printk(KERN_ERR "%s: Got command interrupt even though no "
  659. "command operation was in progress.\n",
  660. mmc_hostname(host->mmc));
  661. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  662. mmc_hostname(host->mmc));
  663. sdhci_dumpregs(host);
  664. return;
  665. }
  666. if (intmask & SDHCI_INT_RESPONSE)
  667. sdhci_finish_command(host);
  668. else {
  669. if (intmask & SDHCI_INT_TIMEOUT)
  670. host->cmd->error = MMC_ERR_TIMEOUT;
  671. else if (intmask & SDHCI_INT_CRC)
  672. host->cmd->error = MMC_ERR_BADCRC;
  673. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  674. host->cmd->error = MMC_ERR_FAILED;
  675. else
  676. host->cmd->error = MMC_ERR_INVALID;
  677. tasklet_schedule(&host->finish_tasklet);
  678. }
  679. }
  680. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  681. {
  682. BUG_ON(intmask == 0);
  683. if (!host->data) {
  684. /*
  685. * A data end interrupt is sent together with the response
  686. * for the stop command.
  687. */
  688. if (intmask & SDHCI_INT_DATA_END)
  689. return;
  690. printk(KERN_ERR "%s: Got data interrupt even though no "
  691. "data operation was in progress.\n",
  692. mmc_hostname(host->mmc));
  693. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  694. mmc_hostname(host->mmc));
  695. sdhci_dumpregs(host);
  696. return;
  697. }
  698. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  699. host->data->error = MMC_ERR_TIMEOUT;
  700. else if (intmask & SDHCI_INT_DATA_CRC)
  701. host->data->error = MMC_ERR_BADCRC;
  702. else if (intmask & SDHCI_INT_DATA_END_BIT)
  703. host->data->error = MMC_ERR_FAILED;
  704. if (host->data->error != MMC_ERR_NONE)
  705. sdhci_finish_data(host);
  706. else {
  707. if (intmask & (SDHCI_INT_BUF_FULL | SDHCI_INT_BUF_EMPTY))
  708. sdhci_transfer_pio(host);
  709. if (intmask & SDHCI_INT_DATA_END)
  710. sdhci_finish_data(host);
  711. }
  712. }
  713. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  714. {
  715. irqreturn_t result;
  716. struct sdhci_host* host = dev_id;
  717. u32 intmask;
  718. spin_lock(&host->lock);
  719. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  720. if (!intmask) {
  721. result = IRQ_NONE;
  722. goto out;
  723. }
  724. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  725. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE))
  726. tasklet_schedule(&host->card_tasklet);
  727. if (intmask & SDHCI_INT_CMD_MASK) {
  728. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  729. writel(intmask & SDHCI_INT_CMD_MASK,
  730. host->ioaddr + SDHCI_INT_STATUS);
  731. }
  732. if (intmask & SDHCI_INT_DATA_MASK) {
  733. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  734. writel(intmask & SDHCI_INT_DATA_MASK,
  735. host->ioaddr + SDHCI_INT_STATUS);
  736. }
  737. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  738. if (intmask & SDHCI_INT_CARD_INT) {
  739. printk(KERN_ERR "%s: Unexpected card interrupt. Please "
  740. "report this to " BUGMAIL ".\n",
  741. mmc_hostname(host->mmc));
  742. sdhci_dumpregs(host);
  743. }
  744. if (intmask & SDHCI_INT_BUS_POWER) {
  745. printk(KERN_ERR "%s: Unexpected bus power interrupt. Please "
  746. "report this to " BUGMAIL ".\n",
  747. mmc_hostname(host->mmc));
  748. sdhci_dumpregs(host);
  749. }
  750. if (intmask & SDHCI_INT_ACMD12ERR) {
  751. printk(KERN_ERR "%s: Unexpected auto CMD12 error. Please "
  752. "report this to " BUGMAIL ".\n",
  753. mmc_hostname(host->mmc));
  754. sdhci_dumpregs(host);
  755. writew(~0, host->ioaddr + SDHCI_ACMD12_ERR);
  756. }
  757. if (intmask)
  758. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  759. result = IRQ_HANDLED;
  760. out:
  761. spin_unlock(&host->lock);
  762. return result;
  763. }
  764. /*****************************************************************************\
  765. * *
  766. * Suspend/resume *
  767. * *
  768. \*****************************************************************************/
  769. #ifdef CONFIG_PM
  770. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  771. {
  772. struct sdhci_chip *chip;
  773. int i, ret;
  774. chip = pci_get_drvdata(pdev);
  775. if (!chip)
  776. return 0;
  777. DBG("Suspending...\n");
  778. for (i = 0;i < chip->num_slots;i++) {
  779. if (!chip->hosts[i])
  780. continue;
  781. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  782. if (ret) {
  783. for (i--;i >= 0;i--)
  784. mmc_resume_host(chip->hosts[i]->mmc);
  785. return ret;
  786. }
  787. }
  788. pci_save_state(pdev);
  789. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  790. pci_disable_device(pdev);
  791. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  792. return 0;
  793. }
  794. static int sdhci_resume (struct pci_dev *pdev)
  795. {
  796. struct sdhci_chip *chip;
  797. int i, ret;
  798. chip = pci_get_drvdata(pdev);
  799. if (!chip)
  800. return 0;
  801. DBG("Resuming...\n");
  802. pci_set_power_state(pdev, PCI_D0);
  803. pci_restore_state(pdev);
  804. pci_enable_device(pdev);
  805. for (i = 0;i < chip->num_slots;i++) {
  806. if (!chip->hosts[i])
  807. continue;
  808. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  809. pci_set_master(pdev);
  810. sdhci_init(chip->hosts[i]);
  811. ret = mmc_resume_host(chip->hosts[i]->mmc);
  812. if (ret)
  813. return ret;
  814. }
  815. return 0;
  816. }
  817. #else /* CONFIG_PM */
  818. #define sdhci_suspend NULL
  819. #define sdhci_resume NULL
  820. #endif /* CONFIG_PM */
  821. /*****************************************************************************\
  822. * *
  823. * Device probing/removal *
  824. * *
  825. \*****************************************************************************/
  826. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  827. {
  828. int ret;
  829. struct sdhci_chip *chip;
  830. struct mmc_host *mmc;
  831. struct sdhci_host *host;
  832. u8 first_bar;
  833. unsigned int caps;
  834. chip = pci_get_drvdata(pdev);
  835. BUG_ON(!chip);
  836. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  837. if (ret)
  838. return ret;
  839. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  840. if (first_bar > 5) {
  841. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  842. return -ENODEV;
  843. }
  844. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  845. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  846. return -ENODEV;
  847. }
  848. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  849. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  850. return -ENODEV;
  851. }
  852. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  853. if (!mmc)
  854. return -ENOMEM;
  855. host = mmc_priv(mmc);
  856. host->mmc = mmc;
  857. host->bar = first_bar + slot;
  858. host->addr = pci_resource_start(pdev, host->bar);
  859. host->irq = pdev->irq;
  860. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  861. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  862. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  863. if (ret)
  864. goto free;
  865. host->ioaddr = ioremap_nocache(host->addr,
  866. pci_resource_len(pdev, host->bar));
  867. if (!host->ioaddr) {
  868. ret = -ENOMEM;
  869. goto release;
  870. }
  871. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  872. if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
  873. host->flags |= SDHCI_USE_DMA;
  874. if (host->flags & SDHCI_USE_DMA) {
  875. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  876. printk(KERN_WARNING "%s: No suitable DMA available. "
  877. "Falling back to PIO.\n", host->slot_descr);
  878. host->flags &= ~SDHCI_USE_DMA;
  879. }
  880. }
  881. if (host->flags & SDHCI_USE_DMA)
  882. pci_set_master(pdev);
  883. else /* XXX: Hack to get MMC layer to avoid highmem */
  884. pdev->dma_mask = 0;
  885. host->max_clk =
  886. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  887. if (host->max_clk == 0) {
  888. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  889. "frequency.\n", host->slot_descr);
  890. ret = -ENODEV;
  891. goto unmap;
  892. }
  893. host->max_clk *= 1000000;
  894. host->timeout_clk =
  895. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  896. if (host->timeout_clk == 0) {
  897. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  898. "frequency.\n", host->slot_descr);
  899. ret = -ENODEV;
  900. goto unmap;
  901. }
  902. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  903. host->timeout_clk *= 1000;
  904. /*
  905. * Set host parameters.
  906. */
  907. mmc->ops = &sdhci_ops;
  908. mmc->f_min = host->max_clk / 256;
  909. mmc->f_max = host->max_clk;
  910. mmc->caps = MMC_CAP_4_BIT_DATA;
  911. mmc->ocr_avail = 0;
  912. if (caps & SDHCI_CAN_VDD_330)
  913. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  914. else if (caps & SDHCI_CAN_VDD_300)
  915. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  916. else if (caps & SDHCI_CAN_VDD_180)
  917. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  918. if (mmc->ocr_avail == 0) {
  919. printk(KERN_ERR "%s: Hardware doesn't report any "
  920. "support voltages.\n", host->slot_descr);
  921. ret = -ENODEV;
  922. goto unmap;
  923. }
  924. spin_lock_init(&host->lock);
  925. /*
  926. * Maximum number of segments. Hardware cannot do scatter lists.
  927. */
  928. if (host->flags & SDHCI_USE_DMA)
  929. mmc->max_hw_segs = 1;
  930. else
  931. mmc->max_hw_segs = 16;
  932. mmc->max_phys_segs = 16;
  933. /*
  934. * Maximum number of sectors in one transfer. Limited by sector
  935. * count register.
  936. */
  937. mmc->max_sectors = 0x3FFF;
  938. /*
  939. * Maximum segment size. Could be one segment with the maximum number
  940. * of sectors.
  941. */
  942. mmc->max_seg_size = mmc->max_sectors * 512;
  943. /*
  944. * Init tasklets.
  945. */
  946. tasklet_init(&host->card_tasklet,
  947. sdhci_tasklet_card, (unsigned long)host);
  948. tasklet_init(&host->finish_tasklet,
  949. sdhci_tasklet_finish, (unsigned long)host);
  950. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  951. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  952. host->slot_descr, host);
  953. if (ret)
  954. goto untasklet;
  955. sdhci_init(host);
  956. #ifdef CONFIG_MMC_DEBUG
  957. sdhci_dumpregs(host);
  958. #endif
  959. host->chip = chip;
  960. chip->hosts[slot] = host;
  961. mmc_add_host(mmc);
  962. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  963. host->addr, host->irq,
  964. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  965. return 0;
  966. untasklet:
  967. tasklet_kill(&host->card_tasklet);
  968. tasklet_kill(&host->finish_tasklet);
  969. unmap:
  970. iounmap(host->ioaddr);
  971. release:
  972. pci_release_region(pdev, host->bar);
  973. free:
  974. mmc_free_host(mmc);
  975. return ret;
  976. }
  977. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  978. {
  979. struct sdhci_chip *chip;
  980. struct mmc_host *mmc;
  981. struct sdhci_host *host;
  982. chip = pci_get_drvdata(pdev);
  983. host = chip->hosts[slot];
  984. mmc = host->mmc;
  985. chip->hosts[slot] = NULL;
  986. mmc_remove_host(mmc);
  987. sdhci_reset(host, SDHCI_RESET_ALL);
  988. free_irq(host->irq, host);
  989. del_timer_sync(&host->timer);
  990. tasklet_kill(&host->card_tasklet);
  991. tasklet_kill(&host->finish_tasklet);
  992. iounmap(host->ioaddr);
  993. pci_release_region(pdev, host->bar);
  994. mmc_free_host(mmc);
  995. }
  996. static int __devinit sdhci_probe(struct pci_dev *pdev,
  997. const struct pci_device_id *ent)
  998. {
  999. int ret, i;
  1000. u8 slots, rev;
  1001. struct sdhci_chip *chip;
  1002. BUG_ON(pdev == NULL);
  1003. BUG_ON(ent == NULL);
  1004. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  1005. printk(KERN_INFO DRIVER_NAME
  1006. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  1007. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  1008. (int)rev);
  1009. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  1010. if (ret)
  1011. return ret;
  1012. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  1013. DBG("found %d slot(s)\n", slots);
  1014. if (slots == 0)
  1015. return -ENODEV;
  1016. ret = pci_enable_device(pdev);
  1017. if (ret)
  1018. return ret;
  1019. chip = kzalloc(sizeof(struct sdhci_chip) +
  1020. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  1021. if (!chip) {
  1022. ret = -ENOMEM;
  1023. goto err;
  1024. }
  1025. chip->pdev = pdev;
  1026. chip->num_slots = slots;
  1027. pci_set_drvdata(pdev, chip);
  1028. for (i = 0;i < slots;i++) {
  1029. ret = sdhci_probe_slot(pdev, i);
  1030. if (ret) {
  1031. for (i--;i >= 0;i--)
  1032. sdhci_remove_slot(pdev, i);
  1033. goto free;
  1034. }
  1035. }
  1036. return 0;
  1037. free:
  1038. pci_set_drvdata(pdev, NULL);
  1039. kfree(chip);
  1040. err:
  1041. pci_disable_device(pdev);
  1042. return ret;
  1043. }
  1044. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1045. {
  1046. int i;
  1047. struct sdhci_chip *chip;
  1048. chip = pci_get_drvdata(pdev);
  1049. if (chip) {
  1050. for (i = 0;i < chip->num_slots;i++)
  1051. sdhci_remove_slot(pdev, i);
  1052. pci_set_drvdata(pdev, NULL);
  1053. kfree(chip);
  1054. }
  1055. pci_disable_device(pdev);
  1056. }
  1057. static struct pci_driver sdhci_driver = {
  1058. .name = DRIVER_NAME,
  1059. .id_table = pci_ids,
  1060. .probe = sdhci_probe,
  1061. .remove = __devexit_p(sdhci_remove),
  1062. .suspend = sdhci_suspend,
  1063. .resume = sdhci_resume,
  1064. };
  1065. /*****************************************************************************\
  1066. * *
  1067. * Driver init/exit *
  1068. * *
  1069. \*****************************************************************************/
  1070. static int __init sdhci_drv_init(void)
  1071. {
  1072. printk(KERN_INFO DRIVER_NAME
  1073. ": Secure Digital Host Controller Interface driver, "
  1074. DRIVER_VERSION "\n");
  1075. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1076. return pci_register_driver(&sdhci_driver);
  1077. }
  1078. static void __exit sdhci_drv_exit(void)
  1079. {
  1080. DBG("Exiting\n");
  1081. pci_unregister_driver(&sdhci_driver);
  1082. }
  1083. module_init(sdhci_drv_init);
  1084. module_exit(sdhci_drv_exit);
  1085. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1086. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1087. MODULE_VERSION(DRIVER_VERSION);
  1088. MODULE_LICENSE("GPL");