pcie_pme.c 13 KB

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  1. /*
  2. * PCIe Native PME support
  3. *
  4. * Copyright (C) 2007 - 2009 Intel Corp
  5. * Copyright (C) 2007 - 2009 Shaohua Li <shaohua.li@intel.com>
  6. * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License V2. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/pci.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/init.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/device.h>
  19. #include <linux/pcieport_if.h>
  20. #include <linux/acpi.h>
  21. #include <linux/pci-acpi.h>
  22. #include <linux/pm_runtime.h>
  23. #include "../../pci.h"
  24. #include "pcie_pme.h"
  25. #define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
  26. #define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
  27. /*
  28. * If set, this switch will prevent the PCIe root port PME service driver from
  29. * being registered. Consequently, the interrupt-based PCIe PME signaling will
  30. * not be used by any PCIe root ports in that case.
  31. */
  32. static bool pcie_pme_disabled;
  33. /*
  34. * The PCI Express Base Specification 2.0, Section 6.1.8, states the following:
  35. * "In order to maintain compatibility with non-PCI Express-aware system
  36. * software, system power management logic must be configured by firmware to use
  37. * the legacy mechanism of signaling PME by default. PCI Express-aware system
  38. * software must notify the firmware prior to enabling native, interrupt-based
  39. * PME signaling." However, if the platform doesn't provide us with a suitable
  40. * notification mechanism or the notification fails, it is not clear whether or
  41. * not we are supposed to use the interrupt-based PCIe PME signaling. The
  42. * switch below can be used to indicate the desired behaviour. When set, it
  43. * will make the kernel use the interrupt-based PCIe PME signaling regardless of
  44. * the platform notification status, although the kernel will attempt to notify
  45. * the platform anyway. When unset, it will prevent the kernel from using the
  46. * the interrupt-based PCIe PME signaling if the platform notification fails,
  47. * which is the default.
  48. */
  49. static bool pcie_pme_force_enable;
  50. static int __init pcie_pme_setup(char *str)
  51. {
  52. if (!strcmp(str, "off"))
  53. pcie_pme_disabled = true;
  54. else if (!strcmp(str, "force"))
  55. pcie_pme_force_enable = true;
  56. return 1;
  57. }
  58. __setup("pcie_pme=", pcie_pme_setup);
  59. /**
  60. * pcie_pme_platform_setup - Ensure that the kernel controls the PCIe PME.
  61. * @srv: PCIe PME root port service to use for carrying out the check.
  62. *
  63. * Notify the platform that the native PCIe PME is going to be used and return
  64. * 'true' if the control of the PCIe PME registers has been acquired from the
  65. * platform.
  66. */
  67. static bool pcie_pme_platform_setup(struct pcie_device *srv)
  68. {
  69. return !pcie_pme_platform_notify(srv) || pcie_pme_force_enable;
  70. }
  71. struct pcie_pme_service_data {
  72. spinlock_t lock;
  73. struct pcie_device *srv;
  74. struct work_struct work;
  75. bool noirq; /* Don't enable the PME interrupt used by this service. */
  76. };
  77. /**
  78. * pcie_pme_interrupt_enable - Enable/disable PCIe PME interrupt generation.
  79. * @dev: PCIe root port or event collector.
  80. * @enable: Enable or disable the interrupt.
  81. */
  82. static void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable)
  83. {
  84. int rtctl_pos;
  85. u16 rtctl;
  86. rtctl_pos = pci_find_capability(dev, PCI_CAP_ID_EXP) + PCI_EXP_RTCTL;
  87. pci_read_config_word(dev, rtctl_pos, &rtctl);
  88. if (enable)
  89. rtctl |= PCI_EXP_RTCTL_PMEIE;
  90. else
  91. rtctl &= ~PCI_EXP_RTCTL_PMEIE;
  92. pci_write_config_word(dev, rtctl_pos, rtctl);
  93. }
  94. /**
  95. * pcie_pme_clear_status - Clear root port PME interrupt status.
  96. * @dev: PCIe root port or event collector.
  97. */
  98. static void pcie_pme_clear_status(struct pci_dev *dev)
  99. {
  100. int rtsta_pos;
  101. u32 rtsta;
  102. rtsta_pos = pci_find_capability(dev, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA;
  103. pci_read_config_dword(dev, rtsta_pos, &rtsta);
  104. rtsta |= PCI_EXP_RTSTA_PME;
  105. pci_write_config_dword(dev, rtsta_pos, rtsta);
  106. }
  107. /**
  108. * pcie_pme_walk_bus - Scan a PCI bus for devices asserting PME#.
  109. * @bus: PCI bus to scan.
  110. *
  111. * Scan given PCI bus and all buses under it for devices asserting PME#.
  112. */
  113. static bool pcie_pme_walk_bus(struct pci_bus *bus)
  114. {
  115. struct pci_dev *dev;
  116. bool ret = false;
  117. list_for_each_entry(dev, &bus->devices, bus_list) {
  118. /* Skip PCIe devices in case we started from a root port. */
  119. if (!dev->is_pcie && pci_check_pme_status(dev)) {
  120. pm_request_resume(&dev->dev);
  121. ret = true;
  122. }
  123. if (dev->subordinate && pcie_pme_walk_bus(dev->subordinate))
  124. ret = true;
  125. }
  126. return ret;
  127. }
  128. /**
  129. * pcie_pme_from_pci_bridge - Check if PCIe-PCI bridge generated a PME.
  130. * @bus: Secondary bus of the bridge.
  131. * @devfn: Device/function number to check.
  132. *
  133. * PME from PCI devices under a PCIe-PCI bridge may be converted to an in-band
  134. * PCIe PME message. In such that case the bridge should use the Requester ID
  135. * of device/function number 0 on its secondary bus.
  136. */
  137. static bool pcie_pme_from_pci_bridge(struct pci_bus *bus, u8 devfn)
  138. {
  139. struct pci_dev *dev;
  140. bool found = false;
  141. if (devfn)
  142. return false;
  143. dev = pci_dev_get(bus->self);
  144. if (!dev)
  145. return false;
  146. if (dev->is_pcie && dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
  147. down_read(&pci_bus_sem);
  148. if (pcie_pme_walk_bus(bus))
  149. found = true;
  150. up_read(&pci_bus_sem);
  151. }
  152. pci_dev_put(dev);
  153. return found;
  154. }
  155. /**
  156. * pcie_pme_handle_request - Find device that generated PME and handle it.
  157. * @port: Root port or event collector that generated the PME interrupt.
  158. * @req_id: PCIe Requester ID of the device that generated the PME.
  159. */
  160. static void pcie_pme_handle_request(struct pci_dev *port, u16 req_id)
  161. {
  162. u8 busnr = req_id >> 8, devfn = req_id & 0xff;
  163. struct pci_bus *bus;
  164. struct pci_dev *dev;
  165. bool found = false;
  166. /* First, check if the PME is from the root port itself. */
  167. if (port->devfn == devfn && port->bus->number == busnr) {
  168. if (pci_check_pme_status(port)) {
  169. pm_request_resume(&port->dev);
  170. found = true;
  171. } else {
  172. /*
  173. * Apparently, the root port generated the PME on behalf
  174. * of a non-PCIe device downstream. If this is done by
  175. * a root port, the Requester ID field in its status
  176. * register may contain either the root port's, or the
  177. * source device's information (PCI Express Base
  178. * Specification, Rev. 2.0, Section 6.1.9).
  179. */
  180. down_read(&pci_bus_sem);
  181. found = pcie_pme_walk_bus(port->subordinate);
  182. up_read(&pci_bus_sem);
  183. }
  184. goto out;
  185. }
  186. /* Second, find the bus the source device is on. */
  187. bus = pci_find_bus(pci_domain_nr(port->bus), busnr);
  188. if (!bus)
  189. goto out;
  190. /* Next, check if the PME is from a PCIe-PCI bridge. */
  191. found = pcie_pme_from_pci_bridge(bus, devfn);
  192. if (found)
  193. goto out;
  194. /* Finally, try to find the PME source on the bus. */
  195. down_read(&pci_bus_sem);
  196. list_for_each_entry(dev, &bus->devices, bus_list) {
  197. pci_dev_get(dev);
  198. if (dev->devfn == devfn) {
  199. found = true;
  200. break;
  201. }
  202. pci_dev_put(dev);
  203. }
  204. up_read(&pci_bus_sem);
  205. if (found) {
  206. /* The device is there, but we have to check its PME status. */
  207. found = pci_check_pme_status(dev);
  208. if (found)
  209. pm_request_resume(&dev->dev);
  210. pci_dev_put(dev);
  211. } else if (devfn) {
  212. /*
  213. * The device is not there, but we can still try to recover by
  214. * assuming that the PME was reported by a PCIe-PCI bridge that
  215. * used devfn different from zero.
  216. */
  217. dev_dbg(&port->dev, "PME interrupt generated for "
  218. "non-existent device %02x:%02x.%d\n",
  219. busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));
  220. found = pcie_pme_from_pci_bridge(bus, 0);
  221. }
  222. out:
  223. if (!found)
  224. dev_dbg(&port->dev, "Spurious native PME interrupt!\n");
  225. }
  226. /**
  227. * pcie_pme_work_fn - Work handler for PCIe PME interrupt.
  228. * @work: Work structure giving access to service data.
  229. */
  230. static void pcie_pme_work_fn(struct work_struct *work)
  231. {
  232. struct pcie_pme_service_data *data =
  233. container_of(work, struct pcie_pme_service_data, work);
  234. struct pci_dev *port = data->srv->port;
  235. int rtsta_pos;
  236. u32 rtsta;
  237. rtsta_pos = pci_find_capability(port, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA;
  238. spin_lock_irq(&data->lock);
  239. for (;;) {
  240. if (data->noirq)
  241. break;
  242. pci_read_config_dword(port, rtsta_pos, &rtsta);
  243. if (rtsta & PCI_EXP_RTSTA_PME) {
  244. /*
  245. * Clear PME status of the port. If there are other
  246. * pending PMEs, the status will be set again.
  247. */
  248. pcie_pme_clear_status(port);
  249. spin_unlock_irq(&data->lock);
  250. pcie_pme_handle_request(port, rtsta & 0xffff);
  251. spin_lock_irq(&data->lock);
  252. continue;
  253. }
  254. /* No need to loop if there are no more PMEs pending. */
  255. if (!(rtsta & PCI_EXP_RTSTA_PENDING))
  256. break;
  257. spin_unlock_irq(&data->lock);
  258. cpu_relax();
  259. spin_lock_irq(&data->lock);
  260. }
  261. if (!data->noirq)
  262. pcie_pme_interrupt_enable(port, true);
  263. spin_unlock_irq(&data->lock);
  264. }
  265. /**
  266. * pcie_pme_irq - Interrupt handler for PCIe root port PME interrupt.
  267. * @irq: Interrupt vector.
  268. * @context: Interrupt context pointer.
  269. */
  270. static irqreturn_t pcie_pme_irq(int irq, void *context)
  271. {
  272. struct pci_dev *port;
  273. struct pcie_pme_service_data *data;
  274. int rtsta_pos;
  275. u32 rtsta;
  276. unsigned long flags;
  277. port = ((struct pcie_device *)context)->port;
  278. data = get_service_data((struct pcie_device *)context);
  279. rtsta_pos = pci_find_capability(port, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA;
  280. spin_lock_irqsave(&data->lock, flags);
  281. pci_read_config_dword(port, rtsta_pos, &rtsta);
  282. if (!(rtsta & PCI_EXP_RTSTA_PME)) {
  283. spin_unlock_irqrestore(&data->lock, flags);
  284. return IRQ_NONE;
  285. }
  286. pcie_pme_interrupt_enable(port, false);
  287. spin_unlock_irqrestore(&data->lock, flags);
  288. /* We don't use pm_wq, because it's freezable. */
  289. schedule_work(&data->work);
  290. return IRQ_HANDLED;
  291. }
  292. /**
  293. * pcie_pme_set_native - Set the PME interrupt flag for given device.
  294. * @dev: PCI device to handle.
  295. * @ign: Ignored.
  296. */
  297. static int pcie_pme_set_native(struct pci_dev *dev, void *ign)
  298. {
  299. dev_info(&dev->dev, "Signaling PME through PCIe PME interrupt\n");
  300. device_set_run_wake(&dev->dev, true);
  301. dev->pme_interrupt = true;
  302. return 0;
  303. }
  304. /**
  305. * pcie_pme_mark_devices - Set the PME interrupt flag for devices below a port.
  306. * @port: PCIe root port or event collector to handle.
  307. *
  308. * For each device below given root port, including the port itself (or for each
  309. * root complex integrated endpoint if @port is a root complex event collector)
  310. * set the flag indicating that it can signal run-time wake-up events via PCIe
  311. * PME interrupts.
  312. */
  313. static void pcie_pme_mark_devices(struct pci_dev *port)
  314. {
  315. pcie_pme_set_native(port, NULL);
  316. if (port->subordinate) {
  317. pci_walk_bus(port->subordinate, pcie_pme_set_native, NULL);
  318. } else {
  319. struct pci_bus *bus = port->bus;
  320. struct pci_dev *dev;
  321. /* Check if this is a root port event collector. */
  322. if (port->pcie_type != PCI_EXP_TYPE_RC_EC || !bus)
  323. return;
  324. down_read(&pci_bus_sem);
  325. list_for_each_entry(dev, &bus->devices, bus_list)
  326. if (dev->is_pcie
  327. && dev->pcie_type == PCI_EXP_TYPE_RC_END)
  328. pcie_pme_set_native(dev, NULL);
  329. up_read(&pci_bus_sem);
  330. }
  331. }
  332. /**
  333. * pcie_pme_probe - Initialize PCIe PME service for given root port.
  334. * @srv: PCIe service to initialize.
  335. */
  336. static int pcie_pme_probe(struct pcie_device *srv)
  337. {
  338. struct pci_dev *port;
  339. struct pcie_pme_service_data *data;
  340. int ret;
  341. if (!pcie_pme_platform_setup(srv))
  342. return -EACCES;
  343. data = kzalloc(sizeof(*data), GFP_KERNEL);
  344. if (!data)
  345. return -ENOMEM;
  346. spin_lock_init(&data->lock);
  347. INIT_WORK(&data->work, pcie_pme_work_fn);
  348. data->srv = srv;
  349. set_service_data(srv, data);
  350. port = srv->port;
  351. pcie_pme_interrupt_enable(port, false);
  352. pcie_pme_clear_status(port);
  353. ret = request_irq(srv->irq, pcie_pme_irq, IRQF_SHARED, "PCIe PME", srv);
  354. if (ret) {
  355. kfree(data);
  356. } else {
  357. pcie_pme_mark_devices(port);
  358. pcie_pme_interrupt_enable(port, true);
  359. }
  360. return ret;
  361. }
  362. /**
  363. * pcie_pme_suspend - Suspend PCIe PME service device.
  364. * @srv: PCIe service device to suspend.
  365. */
  366. static int pcie_pme_suspend(struct pcie_device *srv)
  367. {
  368. struct pcie_pme_service_data *data = get_service_data(srv);
  369. struct pci_dev *port = srv->port;
  370. spin_lock_irq(&data->lock);
  371. pcie_pme_interrupt_enable(port, false);
  372. pcie_pme_clear_status(port);
  373. data->noirq = true;
  374. spin_unlock_irq(&data->lock);
  375. synchronize_irq(srv->irq);
  376. return 0;
  377. }
  378. /**
  379. * pcie_pme_resume - Resume PCIe PME service device.
  380. * @srv - PCIe service device to resume.
  381. */
  382. static int pcie_pme_resume(struct pcie_device *srv)
  383. {
  384. struct pcie_pme_service_data *data = get_service_data(srv);
  385. struct pci_dev *port = srv->port;
  386. spin_lock_irq(&data->lock);
  387. data->noirq = false;
  388. pcie_pme_clear_status(port);
  389. pcie_pme_interrupt_enable(port, true);
  390. spin_unlock_irq(&data->lock);
  391. return 0;
  392. }
  393. /**
  394. * pcie_pme_remove - Prepare PCIe PME service device for removal.
  395. * @srv - PCIe service device to resume.
  396. */
  397. static void pcie_pme_remove(struct pcie_device *srv)
  398. {
  399. pcie_pme_suspend(srv);
  400. free_irq(srv->irq, srv);
  401. kfree(get_service_data(srv));
  402. }
  403. static struct pcie_port_service_driver pcie_pme_driver = {
  404. .name = "pcie_pme",
  405. .port_type = PCI_EXP_TYPE_ROOT_PORT,
  406. .service = PCIE_PORT_SERVICE_PME,
  407. .probe = pcie_pme_probe,
  408. .suspend = pcie_pme_suspend,
  409. .resume = pcie_pme_resume,
  410. .remove = pcie_pme_remove,
  411. };
  412. /**
  413. * pcie_pme_service_init - Register the PCIe PME service driver.
  414. */
  415. static int __init pcie_pme_service_init(void)
  416. {
  417. return pcie_pme_disabled ?
  418. -ENODEV : pcie_port_service_register(&pcie_pme_driver);
  419. }
  420. module_init(pcie_pme_service_init);