cx88-mpeg.c 14 KB

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  1. /*
  2. *
  3. * Support for the mpeg transport stream transfers
  4. * PCI function #2 of the cx2388x.
  5. *
  6. * (c) 2004 Jelle Foks <jelle@foks.8m.com>
  7. * (c) 2004 Chris Pascoe <c.pascoe@itee.uq.edu.au>
  8. * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23. */
  24. #include <linux/module.h>
  25. #include <linux/moduleparam.h>
  26. #include <linux/init.h>
  27. #include <linux/device.h>
  28. #include <linux/interrupt.h>
  29. #include <asm/delay.h>
  30. #include "cx88.h"
  31. /* ------------------------------------------------------------------ */
  32. MODULE_DESCRIPTION("mpeg driver for cx2388x based TV cards");
  33. MODULE_AUTHOR("Jelle Foks <jelle@foks.8m.com>");
  34. MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  35. MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  36. MODULE_LICENSE("GPL");
  37. static unsigned int debug = 0;
  38. module_param(debug,int,0644);
  39. MODULE_PARM_DESC(debug,"enable debug messages [mpeg]");
  40. #define dprintk(level,fmt, arg...) if (debug >= level) \
  41. printk(KERN_DEBUG "%s/2: " fmt, dev->core->name , ## arg)
  42. /* ------------------------------------------------------------------ */
  43. static int cx8802_start_dma(struct cx8802_dev *dev,
  44. struct cx88_dmaqueue *q,
  45. struct cx88_buffer *buf)
  46. {
  47. struct cx88_core *core = dev->core;
  48. dprintk(0, "cx8802_start_dma w: %d, h: %d, f: %d\n", dev->width, dev->height, buf->vb.field);
  49. /* setup fifo + format */
  50. cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
  51. dev->ts_packet_size, buf->risc.dma);
  52. /* write TS length to chip */
  53. cx_write(MO_TS_LNGTH, buf->vb.width);
  54. /* FIXME: this needs a review.
  55. * also: move to cx88-blackbird + cx88-dvb source files? */
  56. if (cx88_boards[core->board].dvb) {
  57. /* negedge driven & software reset */
  58. cx_write(TS_GEN_CNTRL, 0x0040 | dev->ts_gen_cntrl);
  59. udelay(100);
  60. cx_write(MO_PINMUX_IO, 0x00);
  61. cx_write(TS_HW_SOP_CNTRL,0x47<<16|188<<4|0x01);
  62. switch (core->board) {
  63. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
  64. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
  65. case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
  66. cx_write(TS_SOP_STAT, 1<<13);
  67. break;
  68. case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
  69. case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
  70. cx_write(MO_PINMUX_IO, 0x88); /* Enable MPEG parallel IO and video signal pins */
  71. udelay(100);
  72. break;
  73. default:
  74. cx_write(TS_SOP_STAT, 0x00);
  75. break;
  76. }
  77. cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl);
  78. udelay(100);
  79. }
  80. if (cx88_boards[core->board].blackbird) {
  81. cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */
  82. cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */
  83. udelay(100);
  84. cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */
  85. cx_write(TS_VALERR_CNTRL, 0x2000);
  86. cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */
  87. udelay(100);
  88. }
  89. /* reset counter */
  90. cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);
  91. q->count = 1;
  92. /* enable irqs */
  93. dprintk( 0, "setting the interrupt mask\n" );
  94. cx_set(MO_PCI_INTMSK, core->pci_irqmask | 0x04);
  95. cx_set(MO_TS_INTMSK, 0x1f0011);
  96. /* start dma */
  97. cx_set(MO_DEV_CNTRL2, (1<<5));
  98. cx_set(MO_TS_DMACNTRL, 0x11);
  99. return 0;
  100. }
  101. static int cx8802_stop_dma(struct cx8802_dev *dev)
  102. {
  103. struct cx88_core *core = dev->core;
  104. dprintk( 0, "cx8802_stop_dma\n" );
  105. /* stop dma */
  106. cx_clear(MO_TS_DMACNTRL, 0x11);
  107. /* disable irqs */
  108. cx_clear(MO_PCI_INTMSK, 0x000004);
  109. cx_clear(MO_TS_INTMSK, 0x1f0011);
  110. /* Reset the controller */
  111. cx_write(TS_GEN_CNTRL, 0xcd);
  112. return 0;
  113. }
  114. static int cx8802_restart_queue(struct cx8802_dev *dev,
  115. struct cx88_dmaqueue *q)
  116. {
  117. struct cx88_buffer *buf;
  118. struct list_head *item;
  119. dprintk( 0, "cx8802_restart_queue\n" );
  120. if (list_empty(&q->active))
  121. {
  122. dprintk( 0, "cx8802_restart_queue: queue is empty\n" );
  123. return 0;
  124. }
  125. buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
  126. dprintk(2,"restart_queue [%p/%d]: restart dma\n",
  127. buf, buf->vb.i);
  128. cx8802_start_dma(dev, q, buf);
  129. list_for_each(item,&q->active) {
  130. buf = list_entry(item, struct cx88_buffer, vb.queue);
  131. buf->count = q->count++;
  132. }
  133. mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
  134. return 0;
  135. }
  136. /* ------------------------------------------------------------------ */
  137. int cx8802_buf_prepare(struct videobuf_queue *q, struct cx8802_dev *dev,
  138. struct cx88_buffer *buf, enum v4l2_field field)
  139. {
  140. int size = dev->ts_packet_size * dev->ts_packet_count;
  141. int rc;
  142. dprintk(1, "%s: %p\n", __FUNCTION__, buf);
  143. if (0 != buf->vb.baddr && buf->vb.bsize < size)
  144. return -EINVAL;
  145. if (STATE_NEEDS_INIT == buf->vb.state) {
  146. buf->vb.width = dev->ts_packet_size;
  147. buf->vb.height = dev->ts_packet_count;
  148. buf->vb.size = size;
  149. buf->vb.field = field /*V4L2_FIELD_TOP*/;
  150. if (0 != (rc = videobuf_iolock(q,&buf->vb,NULL)))
  151. goto fail;
  152. cx88_risc_databuffer(dev->pci, &buf->risc,
  153. buf->vb.dma.sglist,
  154. buf->vb.width, buf->vb.height);
  155. }
  156. buf->vb.state = STATE_PREPARED;
  157. return 0;
  158. fail:
  159. cx88_free_buffer(q,buf);
  160. return rc;
  161. }
  162. void cx8802_buf_queue(struct cx8802_dev *dev, struct cx88_buffer *buf)
  163. {
  164. struct cx88_buffer *prev;
  165. struct cx88_dmaqueue *cx88q = &dev->mpegq;
  166. dprintk( 1, "cx8802_buf_queue\n" );
  167. /* add jump to stopper */
  168. buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
  169. buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
  170. if (list_empty(&cx88q->active)) {
  171. dprintk( 0, "queue is empty - first active\n" );
  172. list_add_tail(&buf->vb.queue,&cx88q->active);
  173. cx8802_start_dma(dev, cx88q, buf);
  174. buf->vb.state = STATE_ACTIVE;
  175. buf->count = cx88q->count++;
  176. mod_timer(&cx88q->timeout, jiffies+BUFFER_TIMEOUT);
  177. dprintk(0,"[%p/%d] %s - first active\n",
  178. buf, buf->vb.i, __FUNCTION__);
  179. } else {
  180. dprintk( 1, "queue is not empty - append to active\n" );
  181. prev = list_entry(cx88q->active.prev, struct cx88_buffer, vb.queue);
  182. list_add_tail(&buf->vb.queue,&cx88q->active);
  183. buf->vb.state = STATE_ACTIVE;
  184. buf->count = cx88q->count++;
  185. prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
  186. dprintk( 1, "[%p/%d] %s - append to active\n",
  187. buf, buf->vb.i, __FUNCTION__);
  188. }
  189. }
  190. /* ----------------------------------------------------------- */
  191. static void do_cancel_buffers(struct cx8802_dev *dev, char *reason, int restart)
  192. {
  193. struct cx88_dmaqueue *q = &dev->mpegq;
  194. struct cx88_buffer *buf;
  195. unsigned long flags;
  196. spin_lock_irqsave(&dev->slock,flags);
  197. while (!list_empty(&q->active)) {
  198. buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
  199. list_del(&buf->vb.queue);
  200. buf->vb.state = STATE_ERROR;
  201. wake_up(&buf->vb.done);
  202. dprintk(1,"[%p/%d] %s - dma=0x%08lx\n",
  203. buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
  204. }
  205. if (restart)
  206. {
  207. dprintk(0, "restarting queue\n" );
  208. cx8802_restart_queue(dev,q);
  209. }
  210. spin_unlock_irqrestore(&dev->slock,flags);
  211. }
  212. void cx8802_cancel_buffers(struct cx8802_dev *dev)
  213. {
  214. struct cx88_dmaqueue *q = &dev->mpegq;
  215. dprintk( 1, "cx8802_cancel_buffers" );
  216. del_timer_sync(&q->timeout);
  217. cx8802_stop_dma(dev);
  218. do_cancel_buffers(dev,"cancel",0);
  219. }
  220. static void cx8802_timeout(unsigned long data)
  221. {
  222. struct cx8802_dev *dev = (struct cx8802_dev*)data;
  223. dprintk(0, "%s\n",__FUNCTION__);
  224. if (debug)
  225. cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
  226. cx8802_stop_dma(dev);
  227. do_cancel_buffers(dev,"timeout",1);
  228. }
  229. static char *cx88_mpeg_irqs[32] = {
  230. "ts_risci1", NULL, NULL, NULL,
  231. "ts_risci2", NULL, NULL, NULL,
  232. "ts_oflow", NULL, NULL, NULL,
  233. "ts_sync", NULL, NULL, NULL,
  234. "opc_err", "par_err", "rip_err", "pci_abort",
  235. "ts_err?",
  236. };
  237. static void cx8802_mpeg_irq(struct cx8802_dev *dev)
  238. {
  239. struct cx88_core *core = dev->core;
  240. u32 status, mask, count;
  241. dprintk( 1, "cx8802_mpeg_irq\n" );
  242. status = cx_read(MO_TS_INTSTAT);
  243. mask = cx_read(MO_TS_INTMSK);
  244. if (0 == (status & mask))
  245. return;
  246. cx_write(MO_TS_INTSTAT, status);
  247. if (debug || (status & mask & ~0xff))
  248. cx88_print_irqbits(core->name, "irq mpeg ",
  249. cx88_mpeg_irqs, status, mask);
  250. /* risc op code error */
  251. if (status & (1 << 16)) {
  252. printk(KERN_WARNING "%s: mpeg risc op code error\n",core->name);
  253. cx_clear(MO_TS_DMACNTRL, 0x11);
  254. cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
  255. }
  256. /* risc1 y */
  257. if (status & 0x01) {
  258. dprintk( 1, "wake up\n" );
  259. spin_lock(&dev->slock);
  260. count = cx_read(MO_TS_GPCNT);
  261. cx88_wakeup(dev->core, &dev->mpegq, count);
  262. spin_unlock(&dev->slock);
  263. }
  264. /* risc2 y */
  265. if (status & 0x10) {
  266. spin_lock(&dev->slock);
  267. cx8802_restart_queue(dev,&dev->mpegq);
  268. spin_unlock(&dev->slock);
  269. }
  270. /* other general errors */
  271. if (status & 0x1f0100) {
  272. dprintk( 0, "general errors: 0x%08x\n", status & 0x1f0100 );
  273. spin_lock(&dev->slock);
  274. cx8802_stop_dma(dev);
  275. cx8802_restart_queue(dev,&dev->mpegq);
  276. spin_unlock(&dev->slock);
  277. }
  278. }
  279. #define MAX_IRQ_LOOP 10
  280. static irqreturn_t cx8802_irq(int irq, void *dev_id, struct pt_regs *regs)
  281. {
  282. struct cx8802_dev *dev = dev_id;
  283. struct cx88_core *core = dev->core;
  284. u32 status;
  285. int loop, handled = 0;
  286. for (loop = 0; loop < MAX_IRQ_LOOP; loop++) {
  287. status = cx_read(MO_PCI_INTSTAT) & (core->pci_irqmask | 0x04);
  288. if (0 == status)
  289. goto out;
  290. dprintk( 1, "cx8802_irq\n" );
  291. dprintk( 1, " loop: %d/%d\n", loop, MAX_IRQ_LOOP );
  292. dprintk( 1, " status: %d\n", status );
  293. handled = 1;
  294. cx_write(MO_PCI_INTSTAT, status);
  295. if (status & core->pci_irqmask)
  296. cx88_core_irq(core,status);
  297. if (status & 0x04)
  298. cx8802_mpeg_irq(dev);
  299. };
  300. if (MAX_IRQ_LOOP == loop) {
  301. dprintk( 0, "clearing mask\n" );
  302. printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
  303. core->name);
  304. cx_write(MO_PCI_INTMSK,0);
  305. }
  306. out:
  307. return IRQ_RETVAL(handled);
  308. }
  309. /* ----------------------------------------------------------- */
  310. /* exported stuff */
  311. int cx8802_init_common(struct cx8802_dev *dev)
  312. {
  313. struct cx88_core *core = dev->core;
  314. int err;
  315. /* pci init */
  316. if (pci_enable_device(dev->pci))
  317. return -EIO;
  318. pci_set_master(dev->pci);
  319. if (!pci_dma_supported(dev->pci,0xffffffff)) {
  320. printk("%s/2: Oops: no 32bit PCI DMA ???\n",dev->core->name);
  321. return -EIO;
  322. }
  323. pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev);
  324. pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER, &dev->pci_lat);
  325. printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, "
  326. "latency: %d, mmio: 0x%lx\n", dev->core->name,
  327. pci_name(dev->pci), dev->pci_rev, dev->pci->irq,
  328. dev->pci_lat,pci_resource_start(dev->pci,0));
  329. /* initialize driver struct */
  330. spin_lock_init(&dev->slock);
  331. /* init dma queue */
  332. INIT_LIST_HEAD(&dev->mpegq.active);
  333. INIT_LIST_HEAD(&dev->mpegq.queued);
  334. dev->mpegq.timeout.function = cx8802_timeout;
  335. dev->mpegq.timeout.data = (unsigned long)dev;
  336. init_timer(&dev->mpegq.timeout);
  337. cx88_risc_stopper(dev->pci,&dev->mpegq.stopper,
  338. MO_TS_DMACNTRL,0x11,0x00);
  339. /* get irq */
  340. err = request_irq(dev->pci->irq, cx8802_irq,
  341. SA_SHIRQ | SA_INTERRUPT, dev->core->name, dev);
  342. if (err < 0) {
  343. printk(KERN_ERR "%s: can't get IRQ %d\n",
  344. dev->core->name, dev->pci->irq);
  345. return err;
  346. }
  347. cx_set(MO_PCI_INTMSK, core->pci_irqmask);
  348. /* everything worked */
  349. pci_set_drvdata(dev->pci,dev);
  350. return 0;
  351. }
  352. void cx8802_fini_common(struct cx8802_dev *dev)
  353. {
  354. dprintk( 2, "cx8802_fini_common\n" );
  355. cx8802_stop_dma(dev);
  356. pci_disable_device(dev->pci);
  357. /* unregister stuff */
  358. free_irq(dev->pci->irq, dev);
  359. pci_set_drvdata(dev->pci, NULL);
  360. /* free memory */
  361. btcx_riscmem_free(dev->pci,&dev->mpegq.stopper);
  362. }
  363. /* ----------------------------------------------------------- */
  364. int cx8802_suspend_common(struct pci_dev *pci_dev, pm_message_t state)
  365. {
  366. struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
  367. struct cx88_core *core = dev->core;
  368. /* stop mpeg dma */
  369. spin_lock(&dev->slock);
  370. if (!list_empty(&dev->mpegq.active)) {
  371. dprintk( 2, "suspend\n" );
  372. printk("%s: suspend mpeg\n", core->name);
  373. cx8802_stop_dma(dev);
  374. del_timer(&dev->mpegq.timeout);
  375. }
  376. spin_unlock(&dev->slock);
  377. /* FIXME -- shutdown device */
  378. cx88_shutdown(dev->core);
  379. pci_save_state(pci_dev);
  380. if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) {
  381. pci_disable_device(pci_dev);
  382. dev->state.disabled = 1;
  383. }
  384. return 0;
  385. }
  386. int cx8802_resume_common(struct pci_dev *pci_dev)
  387. {
  388. struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
  389. struct cx88_core *core = dev->core;
  390. int err;
  391. if (dev->state.disabled) {
  392. err=pci_enable_device(pci_dev);
  393. if (err) {
  394. printk(KERN_ERR "%s: can't enable device\n",
  395. dev->core->name);
  396. return err;
  397. }
  398. dev->state.disabled = 0;
  399. }
  400. err=pci_set_power_state(pci_dev, PCI_D0);
  401. if (err) {
  402. printk(KERN_ERR "%s: can't enable device\n",
  403. dev->core->name);
  404. pci_disable_device(pci_dev);
  405. dev->state.disabled = 1;
  406. return err;
  407. }
  408. pci_restore_state(pci_dev);
  409. /* FIXME: re-initialize hardware */
  410. cx88_reset(dev->core);
  411. /* restart video+vbi capture */
  412. spin_lock(&dev->slock);
  413. if (!list_empty(&dev->mpegq.active)) {
  414. printk("%s: resume mpeg\n", core->name);
  415. cx8802_restart_queue(dev,&dev->mpegq);
  416. }
  417. spin_unlock(&dev->slock);
  418. return 0;
  419. }
  420. /* ----------------------------------------------------------- */
  421. EXPORT_SYMBOL(cx8802_buf_prepare);
  422. EXPORT_SYMBOL(cx8802_buf_queue);
  423. EXPORT_SYMBOL(cx8802_cancel_buffers);
  424. EXPORT_SYMBOL(cx8802_init_common);
  425. EXPORT_SYMBOL(cx8802_fini_common);
  426. EXPORT_SYMBOL(cx8802_suspend_common);
  427. EXPORT_SYMBOL(cx8802_resume_common);
  428. /* ----------------------------------------------------------- */
  429. /*
  430. * Local variables:
  431. * c-basic-offset: 8
  432. * End:
  433. * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
  434. */