radeon_fence.c 11 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <asm/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include "drmP.h"
  37. #include "drm.h"
  38. #include "radeon_reg.h"
  39. #include "radeon.h"
  40. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  41. {
  42. unsigned long irq_flags;
  43. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  44. if (fence->emited) {
  45. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  46. return 0;
  47. }
  48. fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
  49. if (!rdev->cp.ready) {
  50. /* FIXME: cp is not running assume everythings is done right
  51. * away
  52. */
  53. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  54. } else
  55. radeon_fence_ring_emit(rdev, fence);
  56. fence->emited = true;
  57. fence->timeout = jiffies + ((2000 * HZ) / 1000);
  58. list_del(&fence->list);
  59. list_add_tail(&fence->list, &rdev->fence_drv.emited);
  60. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  61. return 0;
  62. }
  63. static bool radeon_fence_poll_locked(struct radeon_device *rdev)
  64. {
  65. struct radeon_fence *fence;
  66. struct list_head *i, *n;
  67. uint32_t seq;
  68. bool wake = false;
  69. if (rdev == NULL) {
  70. return true;
  71. }
  72. if (rdev->shutdown) {
  73. return true;
  74. }
  75. seq = RREG32(rdev->fence_drv.scratch_reg);
  76. rdev->fence_drv.last_seq = seq;
  77. n = NULL;
  78. list_for_each(i, &rdev->fence_drv.emited) {
  79. fence = list_entry(i, struct radeon_fence, list);
  80. if (fence->seq == seq) {
  81. n = i;
  82. break;
  83. }
  84. }
  85. /* all fence previous to this one are considered as signaled */
  86. if (n) {
  87. i = n;
  88. do {
  89. n = i->prev;
  90. list_del(i);
  91. list_add_tail(i, &rdev->fence_drv.signaled);
  92. fence = list_entry(i, struct radeon_fence, list);
  93. fence->signaled = true;
  94. i = n;
  95. } while (i != &rdev->fence_drv.emited);
  96. wake = true;
  97. }
  98. return wake;
  99. }
  100. static void radeon_fence_destroy(struct kref *kref)
  101. {
  102. unsigned long irq_flags;
  103. struct radeon_fence *fence;
  104. fence = container_of(kref, struct radeon_fence, kref);
  105. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  106. list_del(&fence->list);
  107. fence->emited = false;
  108. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  109. kfree(fence);
  110. }
  111. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
  112. {
  113. unsigned long irq_flags;
  114. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  115. if ((*fence) == NULL) {
  116. return -ENOMEM;
  117. }
  118. kref_init(&((*fence)->kref));
  119. (*fence)->rdev = rdev;
  120. (*fence)->emited = false;
  121. (*fence)->signaled = false;
  122. (*fence)->seq = 0;
  123. INIT_LIST_HEAD(&(*fence)->list);
  124. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  125. list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
  126. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  127. return 0;
  128. }
  129. bool radeon_fence_signaled(struct radeon_fence *fence)
  130. {
  131. struct radeon_device *rdev = fence->rdev;
  132. unsigned long irq_flags;
  133. bool signaled = false;
  134. if (rdev->gpu_lockup) {
  135. return true;
  136. }
  137. if (fence == NULL) {
  138. return true;
  139. }
  140. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  141. signaled = fence->signaled;
  142. /* if we are shuting down report all fence as signaled */
  143. if (fence->rdev->shutdown) {
  144. signaled = true;
  145. }
  146. if (!fence->emited) {
  147. WARN(1, "Querying an unemited fence : %p !\n", fence);
  148. signaled = true;
  149. }
  150. if (!signaled) {
  151. radeon_fence_poll_locked(fence->rdev);
  152. signaled = fence->signaled;
  153. }
  154. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  155. return signaled;
  156. }
  157. int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy)
  158. {
  159. struct radeon_device *rdev;
  160. unsigned long cur_jiffies;
  161. unsigned long timeout;
  162. int ret = 0;
  163. cur_jiffies = jiffies;
  164. timeout = HZ / 100;
  165. if (time_after(fence->timeout, cur_jiffies)) {
  166. timeout = fence->timeout - cur_jiffies;
  167. }
  168. rdev = fence->rdev;
  169. __set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
  170. while (1) {
  171. if (radeon_fence_signaled(fence))
  172. break;
  173. if (time_after_eq(jiffies, timeout)) {
  174. ret = -EBUSY;
  175. break;
  176. }
  177. if (lazy)
  178. schedule_timeout(1);
  179. if (intr && signal_pending(current)) {
  180. ret = -ERESTARTSYS;
  181. break;
  182. }
  183. }
  184. __set_current_state(TASK_RUNNING);
  185. return ret;
  186. }
  187. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  188. {
  189. struct radeon_device *rdev;
  190. unsigned long cur_jiffies;
  191. unsigned long timeout;
  192. bool expired = false;
  193. int r;
  194. if (fence == NULL) {
  195. WARN(1, "Querying an invalid fence : %p !\n", fence);
  196. return 0;
  197. }
  198. rdev = fence->rdev;
  199. if (radeon_fence_signaled(fence)) {
  200. return 0;
  201. }
  202. if (rdev->family >= CHIP_R600) {
  203. r = r600_fence_wait(fence, intr, 0);
  204. if (r == -ERESTARTSYS)
  205. return -EBUSY;
  206. return r;
  207. }
  208. retry:
  209. cur_jiffies = jiffies;
  210. timeout = HZ / 100;
  211. if (time_after(fence->timeout, cur_jiffies)) {
  212. timeout = fence->timeout - cur_jiffies;
  213. }
  214. if (intr) {
  215. r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
  216. radeon_fence_signaled(fence), timeout);
  217. if (unlikely(r == -ERESTARTSYS)) {
  218. return -EBUSY;
  219. }
  220. } else {
  221. r = wait_event_timeout(rdev->fence_drv.queue,
  222. radeon_fence_signaled(fence), timeout);
  223. }
  224. if (unlikely(!radeon_fence_signaled(fence))) {
  225. if (unlikely(r == 0)) {
  226. expired = true;
  227. }
  228. if (unlikely(expired)) {
  229. timeout = 1;
  230. if (time_after(cur_jiffies, fence->timeout)) {
  231. timeout = cur_jiffies - fence->timeout;
  232. }
  233. timeout = jiffies_to_msecs(timeout);
  234. if (timeout > 500) {
  235. DRM_ERROR("fence(%p:0x%08X) %lums timeout "
  236. "going to reset GPU\n",
  237. fence, fence->seq, timeout);
  238. radeon_gpu_reset(rdev);
  239. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  240. }
  241. }
  242. goto retry;
  243. }
  244. if (unlikely(expired)) {
  245. rdev->fence_drv.count_timeout++;
  246. cur_jiffies = jiffies;
  247. timeout = 1;
  248. if (time_after(cur_jiffies, fence->timeout)) {
  249. timeout = cur_jiffies - fence->timeout;
  250. }
  251. timeout = jiffies_to_msecs(timeout);
  252. DRM_ERROR("fence(%p:0x%08X) %lums timeout\n",
  253. fence, fence->seq, timeout);
  254. DRM_ERROR("last signaled fence(0x%08X)\n",
  255. rdev->fence_drv.last_seq);
  256. }
  257. return 0;
  258. }
  259. int radeon_fence_wait_next(struct radeon_device *rdev)
  260. {
  261. unsigned long irq_flags;
  262. struct radeon_fence *fence;
  263. int r;
  264. if (rdev->gpu_lockup) {
  265. return 0;
  266. }
  267. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  268. if (list_empty(&rdev->fence_drv.emited)) {
  269. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  270. return 0;
  271. }
  272. fence = list_entry(rdev->fence_drv.emited.next,
  273. struct radeon_fence, list);
  274. radeon_fence_ref(fence);
  275. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  276. r = radeon_fence_wait(fence, false);
  277. radeon_fence_unref(&fence);
  278. return r;
  279. }
  280. int radeon_fence_wait_last(struct radeon_device *rdev)
  281. {
  282. unsigned long irq_flags;
  283. struct radeon_fence *fence;
  284. int r;
  285. if (rdev->gpu_lockup) {
  286. return 0;
  287. }
  288. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  289. if (list_empty(&rdev->fence_drv.emited)) {
  290. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  291. return 0;
  292. }
  293. fence = list_entry(rdev->fence_drv.emited.prev,
  294. struct radeon_fence, list);
  295. radeon_fence_ref(fence);
  296. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  297. r = radeon_fence_wait(fence, false);
  298. radeon_fence_unref(&fence);
  299. return r;
  300. }
  301. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  302. {
  303. kref_get(&fence->kref);
  304. return fence;
  305. }
  306. void radeon_fence_unref(struct radeon_fence **fence)
  307. {
  308. struct radeon_fence *tmp = *fence;
  309. *fence = NULL;
  310. if (tmp) {
  311. kref_put(&tmp->kref, &radeon_fence_destroy);
  312. }
  313. }
  314. void radeon_fence_process(struct radeon_device *rdev)
  315. {
  316. unsigned long irq_flags;
  317. bool wake;
  318. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  319. wake = radeon_fence_poll_locked(rdev);
  320. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  321. if (wake) {
  322. wake_up_all(&rdev->fence_drv.queue);
  323. }
  324. }
  325. int radeon_fence_driver_init(struct radeon_device *rdev)
  326. {
  327. unsigned long irq_flags;
  328. int r;
  329. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  330. r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
  331. if (r) {
  332. DRM_ERROR("Fence failed to get a scratch register.");
  333. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  334. return r;
  335. }
  336. WREG32(rdev->fence_drv.scratch_reg, 0);
  337. atomic_set(&rdev->fence_drv.seq, 0);
  338. INIT_LIST_HEAD(&rdev->fence_drv.created);
  339. INIT_LIST_HEAD(&rdev->fence_drv.emited);
  340. INIT_LIST_HEAD(&rdev->fence_drv.signaled);
  341. rdev->fence_drv.count_timeout = 0;
  342. init_waitqueue_head(&rdev->fence_drv.queue);
  343. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  344. if (radeon_debugfs_fence_init(rdev)) {
  345. DRM_ERROR("Failed to register debugfs file for fence !\n");
  346. }
  347. return 0;
  348. }
  349. void radeon_fence_driver_fini(struct radeon_device *rdev)
  350. {
  351. unsigned long irq_flags;
  352. wake_up_all(&rdev->fence_drv.queue);
  353. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  354. radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
  355. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  356. DRM_INFO("radeon: fence finalized\n");
  357. }
  358. /*
  359. * Fence debugfs
  360. */
  361. #if defined(CONFIG_DEBUG_FS)
  362. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  363. {
  364. struct drm_info_node *node = (struct drm_info_node *)m->private;
  365. struct drm_device *dev = node->minor->dev;
  366. struct radeon_device *rdev = dev->dev_private;
  367. struct radeon_fence *fence;
  368. seq_printf(m, "Last signaled fence 0x%08X\n",
  369. RREG32(rdev->fence_drv.scratch_reg));
  370. if (!list_empty(&rdev->fence_drv.emited)) {
  371. fence = list_entry(rdev->fence_drv.emited.prev,
  372. struct radeon_fence, list);
  373. seq_printf(m, "Last emited fence %p with 0x%08X\n",
  374. fence, fence->seq);
  375. }
  376. return 0;
  377. }
  378. static struct drm_info_list radeon_debugfs_fence_list[] = {
  379. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  380. };
  381. #endif
  382. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  383. {
  384. #if defined(CONFIG_DEBUG_FS)
  385. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  386. #else
  387. return 0;
  388. #endif
  389. }