iwl-agn.c 95 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. ret = iwl_check_rxon_cmd(priv);
  101. if (ret) {
  102. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  103. return -EINVAL;
  104. }
  105. /* If we don't need to send a full RXON, we can use
  106. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  107. * and other flags for the current radio configuration. */
  108. if (!iwl_full_rxon_required(priv)) {
  109. ret = iwl_send_rxon_assoc(priv);
  110. if (ret) {
  111. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  112. return ret;
  113. }
  114. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  115. return 0;
  116. }
  117. /* station table will be cleared */
  118. priv->assoc_station_added = 0;
  119. /* If we are currently associated and the new config requires
  120. * an RXON_ASSOC and the new config wants the associated mask enabled,
  121. * we must clear the associated from the active configuration
  122. * before we apply the new config */
  123. if (iwl_is_associated(priv) && new_assoc) {
  124. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  125. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  126. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  127. sizeof(struct iwl_rxon_cmd),
  128. &priv->active_rxon);
  129. /* If the mask clearing failed then we set
  130. * active_rxon back to what it was previously */
  131. if (ret) {
  132. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  133. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  134. return ret;
  135. }
  136. }
  137. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  138. "* with%s RXON_FILTER_ASSOC_MSK\n"
  139. "* channel = %d\n"
  140. "* bssid = %pM\n",
  141. (new_assoc ? "" : "out"),
  142. le16_to_cpu(priv->staging_rxon.channel),
  143. priv->staging_rxon.bssid_addr);
  144. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  145. /* Apply the new configuration
  146. * RXON unassoc clears the station table in uCode, send it before
  147. * we add the bcast station. If assoc bit is set, we will send RXON
  148. * after having added the bcast and bssid station.
  149. */
  150. if (!new_assoc) {
  151. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  152. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  153. if (ret) {
  154. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  155. return ret;
  156. }
  157. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  158. }
  159. iwl_clear_stations_table(priv);
  160. priv->start_calib = 0;
  161. /* Add the broadcast address so we can send broadcast frames */
  162. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  163. IWL_INVALID_STATION) {
  164. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  165. return -EIO;
  166. }
  167. /* If we have set the ASSOC_MSK and we are in BSS mode then
  168. * add the IWL_AP_ID to the station rate table */
  169. if (new_assoc) {
  170. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  171. ret = iwl_rxon_add_station(priv,
  172. priv->active_rxon.bssid_addr, 1);
  173. if (ret == IWL_INVALID_STATION) {
  174. IWL_ERR(priv,
  175. "Error adding AP address for TX.\n");
  176. return -EIO;
  177. }
  178. priv->assoc_station_added = 1;
  179. if (priv->default_wep_key &&
  180. iwl_send_static_wepkey_cmd(priv, 0))
  181. IWL_ERR(priv,
  182. "Could not send WEP static key.\n");
  183. }
  184. /*
  185. * allow CTS-to-self if possible for new association.
  186. * this is relevant only for 5000 series and up,
  187. * but will not damage 4965
  188. */
  189. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  190. /* Apply the new configuration
  191. * RXON assoc doesn't clear the station table in uCode,
  192. */
  193. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  194. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  195. if (ret) {
  196. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  197. return ret;
  198. }
  199. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  200. }
  201. iwl_init_sensitivity(priv);
  202. /* If we issue a new RXON command which required a tune then we must
  203. * send a new TXPOWER command or we won't be able to Tx any frames */
  204. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  205. if (ret) {
  206. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  207. return ret;
  208. }
  209. return 0;
  210. }
  211. void iwl_update_chain_flags(struct iwl_priv *priv)
  212. {
  213. if (priv->cfg->ops->hcmd->set_rxon_chain)
  214. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  215. iwlcore_commit_rxon(priv);
  216. }
  217. static void iwl_clear_free_frames(struct iwl_priv *priv)
  218. {
  219. struct list_head *element;
  220. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  221. priv->frames_count);
  222. while (!list_empty(&priv->free_frames)) {
  223. element = priv->free_frames.next;
  224. list_del(element);
  225. kfree(list_entry(element, struct iwl_frame, list));
  226. priv->frames_count--;
  227. }
  228. if (priv->frames_count) {
  229. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  230. priv->frames_count);
  231. priv->frames_count = 0;
  232. }
  233. }
  234. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  235. {
  236. struct iwl_frame *frame;
  237. struct list_head *element;
  238. if (list_empty(&priv->free_frames)) {
  239. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  240. if (!frame) {
  241. IWL_ERR(priv, "Could not allocate frame!\n");
  242. return NULL;
  243. }
  244. priv->frames_count++;
  245. return frame;
  246. }
  247. element = priv->free_frames.next;
  248. list_del(element);
  249. return list_entry(element, struct iwl_frame, list);
  250. }
  251. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  252. {
  253. memset(frame, 0, sizeof(*frame));
  254. list_add(&frame->list, &priv->free_frames);
  255. }
  256. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  257. struct ieee80211_hdr *hdr,
  258. int left)
  259. {
  260. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  261. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  262. (priv->iw_mode != NL80211_IFTYPE_AP)))
  263. return 0;
  264. if (priv->ibss_beacon->len > left)
  265. return 0;
  266. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  267. return priv->ibss_beacon->len;
  268. }
  269. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  270. struct iwl_frame *frame, u8 rate)
  271. {
  272. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  273. unsigned int frame_size;
  274. tx_beacon_cmd = &frame->u.beacon;
  275. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  276. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  277. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  278. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  279. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  280. BUG_ON(frame_size > MAX_MPDU_SIZE);
  281. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  282. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  285. else
  286. tx_beacon_cmd->tx.rate_n_flags =
  287. iwl_hw_set_rate_n_flags(rate, 0);
  288. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  289. TX_CMD_FLG_TSF_MSK |
  290. TX_CMD_FLG_STA_RATE_MSK;
  291. return sizeof(*tx_beacon_cmd) + frame_size;
  292. }
  293. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  294. {
  295. struct iwl_frame *frame;
  296. unsigned int frame_size;
  297. int rc;
  298. u8 rate;
  299. frame = iwl_get_free_frame(priv);
  300. if (!frame) {
  301. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  302. "command.\n");
  303. return -ENOMEM;
  304. }
  305. rate = iwl_rate_get_lowest_plcp(priv);
  306. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  307. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  308. &frame->u.cmd[0]);
  309. iwl_free_frame(priv, frame);
  310. return rc;
  311. }
  312. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  313. {
  314. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  315. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  316. if (sizeof(dma_addr_t) > sizeof(u32))
  317. addr |=
  318. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  319. return addr;
  320. }
  321. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  322. {
  323. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  324. return le16_to_cpu(tb->hi_n_len) >> 4;
  325. }
  326. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  327. dma_addr_t addr, u16 len)
  328. {
  329. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  330. u16 hi_n_len = len << 4;
  331. put_unaligned_le32(addr, &tb->lo);
  332. if (sizeof(dma_addr_t) > sizeof(u32))
  333. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  334. tb->hi_n_len = cpu_to_le16(hi_n_len);
  335. tfd->num_tbs = idx + 1;
  336. }
  337. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  338. {
  339. return tfd->num_tbs & 0x1f;
  340. }
  341. /**
  342. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  343. * @priv - driver private data
  344. * @txq - tx queue
  345. *
  346. * Does NOT advance any TFD circular buffer read/write indexes
  347. * Does NOT free the TFD itself (which is within circular buffer)
  348. */
  349. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  350. {
  351. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  352. struct iwl_tfd *tfd;
  353. struct pci_dev *dev = priv->pci_dev;
  354. int index = txq->q.read_ptr;
  355. int i;
  356. int num_tbs;
  357. tfd = &tfd_tmp[index];
  358. /* Sanity check on number of chunks */
  359. num_tbs = iwl_tfd_get_num_tbs(tfd);
  360. if (num_tbs >= IWL_NUM_OF_TBS) {
  361. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  362. /* @todo issue fatal error, it is quite serious situation */
  363. return;
  364. }
  365. /* Unmap tx_cmd */
  366. if (num_tbs)
  367. pci_unmap_single(dev,
  368. pci_unmap_addr(&txq->meta[index], mapping),
  369. pci_unmap_len(&txq->meta[index], len),
  370. PCI_DMA_BIDIRECTIONAL);
  371. /* Unmap chunks, if any. */
  372. for (i = 1; i < num_tbs; i++) {
  373. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  374. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  375. if (txq->txb) {
  376. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  377. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  378. }
  379. }
  380. }
  381. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  382. struct iwl_tx_queue *txq,
  383. dma_addr_t addr, u16 len,
  384. u8 reset, u8 pad)
  385. {
  386. struct iwl_queue *q;
  387. struct iwl_tfd *tfd, *tfd_tmp;
  388. u32 num_tbs;
  389. q = &txq->q;
  390. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  391. tfd = &tfd_tmp[q->write_ptr];
  392. if (reset)
  393. memset(tfd, 0, sizeof(*tfd));
  394. num_tbs = iwl_tfd_get_num_tbs(tfd);
  395. /* Each TFD can point to a maximum 20 Tx buffers */
  396. if (num_tbs >= IWL_NUM_OF_TBS) {
  397. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  398. IWL_NUM_OF_TBS);
  399. return -EINVAL;
  400. }
  401. BUG_ON(addr & ~DMA_BIT_MASK(36));
  402. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  403. IWL_ERR(priv, "Unaligned address = %llx\n",
  404. (unsigned long long)addr);
  405. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  406. return 0;
  407. }
  408. /*
  409. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  410. * given Tx queue, and enable the DMA channel used for that queue.
  411. *
  412. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  413. * channels supported in hardware.
  414. */
  415. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  416. struct iwl_tx_queue *txq)
  417. {
  418. int txq_id = txq->q.id;
  419. /* Circular buffer (TFD queue in DRAM) physical base address */
  420. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  421. txq->q.dma_addr >> 8);
  422. return 0;
  423. }
  424. /******************************************************************************
  425. *
  426. * Generic RX handler implementations
  427. *
  428. ******************************************************************************/
  429. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  430. struct iwl_rx_mem_buffer *rxb)
  431. {
  432. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  433. struct iwl_alive_resp *palive;
  434. struct delayed_work *pwork;
  435. palive = &pkt->u.alive_frame;
  436. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  437. "0x%01X 0x%01X\n",
  438. palive->is_valid, palive->ver_type,
  439. palive->ver_subtype);
  440. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  441. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  442. memcpy(&priv->card_alive_init,
  443. &pkt->u.alive_frame,
  444. sizeof(struct iwl_init_alive_resp));
  445. pwork = &priv->init_alive_start;
  446. } else {
  447. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  448. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  449. sizeof(struct iwl_alive_resp));
  450. pwork = &priv->alive_start;
  451. }
  452. /* We delay the ALIVE response by 5ms to
  453. * give the HW RF Kill time to activate... */
  454. if (palive->is_valid == UCODE_VALID_OK)
  455. queue_delayed_work(priv->workqueue, pwork,
  456. msecs_to_jiffies(5));
  457. else
  458. IWL_WARN(priv, "uCode did not respond OK.\n");
  459. }
  460. static void iwl_bg_beacon_update(struct work_struct *work)
  461. {
  462. struct iwl_priv *priv =
  463. container_of(work, struct iwl_priv, beacon_update);
  464. struct sk_buff *beacon;
  465. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  466. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  467. if (!beacon) {
  468. IWL_ERR(priv, "update beacon failed\n");
  469. return;
  470. }
  471. mutex_lock(&priv->mutex);
  472. /* new beacon skb is allocated every time; dispose previous.*/
  473. if (priv->ibss_beacon)
  474. dev_kfree_skb(priv->ibss_beacon);
  475. priv->ibss_beacon = beacon;
  476. mutex_unlock(&priv->mutex);
  477. iwl_send_beacon_cmd(priv);
  478. }
  479. /**
  480. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  481. *
  482. * This callback is provided in order to send a statistics request.
  483. *
  484. * This timer function is continually reset to execute within
  485. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  486. * was received. We need to ensure we receive the statistics in order
  487. * to update the temperature used for calibrating the TXPOWER.
  488. */
  489. static void iwl_bg_statistics_periodic(unsigned long data)
  490. {
  491. struct iwl_priv *priv = (struct iwl_priv *)data;
  492. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  493. return;
  494. /* dont send host command if rf-kill is on */
  495. if (!iwl_is_ready_rf(priv))
  496. return;
  497. iwl_send_statistics_request(priv, CMD_ASYNC);
  498. }
  499. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  500. struct iwl_rx_mem_buffer *rxb)
  501. {
  502. #ifdef CONFIG_IWLWIFI_DEBUG
  503. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  504. struct iwl4965_beacon_notif *beacon =
  505. (struct iwl4965_beacon_notif *)pkt->u.raw;
  506. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  507. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  508. "tsf %d %d rate %d\n",
  509. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  510. beacon->beacon_notify_hdr.failure_frame,
  511. le32_to_cpu(beacon->ibss_mgr_status),
  512. le32_to_cpu(beacon->high_tsf),
  513. le32_to_cpu(beacon->low_tsf), rate);
  514. #endif
  515. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  516. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  517. queue_work(priv->workqueue, &priv->beacon_update);
  518. }
  519. /* Handle notification from uCode that card's power state is changing
  520. * due to software, hardware, or critical temperature RFKILL */
  521. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  522. struct iwl_rx_mem_buffer *rxb)
  523. {
  524. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  525. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  526. unsigned long status = priv->status;
  527. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  528. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  529. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  530. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  531. RF_CARD_DISABLED)) {
  532. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  533. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  534. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  535. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  536. if (!(flags & RXON_CARD_DISABLED)) {
  537. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  538. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  539. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  540. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  541. }
  542. if (flags & RF_CARD_DISABLED)
  543. iwl_tt_enter_ct_kill(priv);
  544. }
  545. if (!(flags & RF_CARD_DISABLED))
  546. iwl_tt_exit_ct_kill(priv);
  547. if (flags & HW_CARD_DISABLED)
  548. set_bit(STATUS_RF_KILL_HW, &priv->status);
  549. else
  550. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  551. if (!(flags & RXON_CARD_DISABLED))
  552. iwl_scan_cancel(priv);
  553. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  554. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  555. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  556. test_bit(STATUS_RF_KILL_HW, &priv->status));
  557. else
  558. wake_up_interruptible(&priv->wait_command_queue);
  559. }
  560. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  561. {
  562. if (src == IWL_PWR_SRC_VAUX) {
  563. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  564. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  565. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  566. ~APMG_PS_CTRL_MSK_PWR_SRC);
  567. } else {
  568. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  569. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  570. ~APMG_PS_CTRL_MSK_PWR_SRC);
  571. }
  572. return 0;
  573. }
  574. /**
  575. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  576. *
  577. * Setup the RX handlers for each of the reply types sent from the uCode
  578. * to the host.
  579. *
  580. * This function chains into the hardware specific files for them to setup
  581. * any hardware specific handlers as well.
  582. */
  583. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  584. {
  585. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  586. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  587. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  588. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  589. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  590. iwl_rx_pm_debug_statistics_notif;
  591. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  592. /*
  593. * The same handler is used for both the REPLY to a discrete
  594. * statistics request from the host as well as for the periodic
  595. * statistics notifications (after received beacons) from the uCode.
  596. */
  597. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  598. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  599. iwl_setup_spectrum_handlers(priv);
  600. iwl_setup_rx_scan_handlers(priv);
  601. /* status change handler */
  602. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  603. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  604. iwl_rx_missed_beacon_notif;
  605. /* Rx handlers */
  606. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  607. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  608. /* block ack */
  609. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  610. /* Set up hardware specific Rx handlers */
  611. priv->cfg->ops->lib->rx_handler_setup(priv);
  612. }
  613. /**
  614. * iwl_rx_handle - Main entry function for receiving responses from uCode
  615. *
  616. * Uses the priv->rx_handlers callback function array to invoke
  617. * the appropriate handlers, including command responses,
  618. * frame-received notifications, and other notifications.
  619. */
  620. void iwl_rx_handle(struct iwl_priv *priv)
  621. {
  622. struct iwl_rx_mem_buffer *rxb;
  623. struct iwl_rx_packet *pkt;
  624. struct iwl_rx_queue *rxq = &priv->rxq;
  625. u32 r, i;
  626. int reclaim;
  627. unsigned long flags;
  628. u8 fill_rx = 0;
  629. u32 count = 8;
  630. int total_empty;
  631. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  632. * buffer that the driver may process (last buffer filled by ucode). */
  633. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  634. i = rxq->read;
  635. /* Rx interrupt, but nothing sent from uCode */
  636. if (i == r)
  637. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  638. /* calculate total frames need to be restock after handling RX */
  639. total_empty = r - rxq->write_actual;
  640. if (total_empty < 0)
  641. total_empty += RX_QUEUE_SIZE;
  642. if (total_empty > (RX_QUEUE_SIZE / 2))
  643. fill_rx = 1;
  644. while (i != r) {
  645. rxb = rxq->queue[i];
  646. /* If an RXB doesn't have a Rx queue slot associated with it,
  647. * then a bug has been introduced in the queue refilling
  648. * routines -- catch it here */
  649. BUG_ON(rxb == NULL);
  650. rxq->queue[i] = NULL;
  651. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  652. PAGE_SIZE << priv->hw_params.rx_page_order,
  653. PCI_DMA_FROMDEVICE);
  654. pkt = rxb_addr(rxb);
  655. trace_iwlwifi_dev_rx(priv, pkt,
  656. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  657. /* Reclaim a command buffer only if this packet is a response
  658. * to a (driver-originated) command.
  659. * If the packet (e.g. Rx frame) originated from uCode,
  660. * there is no command buffer to reclaim.
  661. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  662. * but apparently a few don't get set; catch them here. */
  663. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  664. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  665. (pkt->hdr.cmd != REPLY_RX) &&
  666. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  667. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  668. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  669. (pkt->hdr.cmd != REPLY_TX);
  670. /* Based on type of command response or notification,
  671. * handle those that need handling via function in
  672. * rx_handlers table. See iwl_setup_rx_handlers() */
  673. if (priv->rx_handlers[pkt->hdr.cmd]) {
  674. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  675. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  676. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  677. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  678. } else {
  679. /* No handling needed */
  680. IWL_DEBUG_RX(priv,
  681. "r %d i %d No handler needed for %s, 0x%02x\n",
  682. r, i, get_cmd_string(pkt->hdr.cmd),
  683. pkt->hdr.cmd);
  684. }
  685. /*
  686. * XXX: After here, we should always check rxb->page
  687. * against NULL before touching it or its virtual
  688. * memory (pkt). Because some rx_handler might have
  689. * already taken or freed the pages.
  690. */
  691. if (reclaim) {
  692. /* Invoke any callbacks, transfer the buffer to caller,
  693. * and fire off the (possibly) blocking iwl_send_cmd()
  694. * as we reclaim the driver command queue */
  695. if (rxb->page)
  696. iwl_tx_cmd_complete(priv, rxb);
  697. else
  698. IWL_WARN(priv, "Claim null rxb?\n");
  699. }
  700. /* Reuse the page if possible. For notification packets and
  701. * SKBs that fail to Rx correctly, add them back into the
  702. * rx_free list for reuse later. */
  703. spin_lock_irqsave(&rxq->lock, flags);
  704. if (rxb->page != NULL) {
  705. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  706. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  707. PCI_DMA_FROMDEVICE);
  708. list_add_tail(&rxb->list, &rxq->rx_free);
  709. rxq->free_count++;
  710. } else
  711. list_add_tail(&rxb->list, &rxq->rx_used);
  712. spin_unlock_irqrestore(&rxq->lock, flags);
  713. i = (i + 1) & RX_QUEUE_MASK;
  714. /* If there are a lot of unused frames,
  715. * restock the Rx queue so ucode wont assert. */
  716. if (fill_rx) {
  717. count++;
  718. if (count >= 8) {
  719. rxq->read = i;
  720. iwl_rx_replenish_now(priv);
  721. count = 0;
  722. }
  723. }
  724. }
  725. /* Backtrack one entry */
  726. rxq->read = i;
  727. if (fill_rx)
  728. iwl_rx_replenish_now(priv);
  729. else
  730. iwl_rx_queue_restock(priv);
  731. }
  732. /* call this function to flush any scheduled tasklet */
  733. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  734. {
  735. /* wait to make sure we flush pending tasklet*/
  736. synchronize_irq(priv->pci_dev->irq);
  737. tasklet_kill(&priv->irq_tasklet);
  738. }
  739. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  740. {
  741. u32 inta, handled = 0;
  742. u32 inta_fh;
  743. unsigned long flags;
  744. #ifdef CONFIG_IWLWIFI_DEBUG
  745. u32 inta_mask;
  746. #endif
  747. spin_lock_irqsave(&priv->lock, flags);
  748. /* Ack/clear/reset pending uCode interrupts.
  749. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  750. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  751. inta = iwl_read32(priv, CSR_INT);
  752. iwl_write32(priv, CSR_INT, inta);
  753. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  754. * Any new interrupts that happen after this, either while we're
  755. * in this tasklet, or later, will show up in next ISR/tasklet. */
  756. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  757. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  758. #ifdef CONFIG_IWLWIFI_DEBUG
  759. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  760. /* just for debug */
  761. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  762. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  763. inta, inta_mask, inta_fh);
  764. }
  765. #endif
  766. spin_unlock_irqrestore(&priv->lock, flags);
  767. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  768. * atomic, make sure that inta covers all the interrupts that
  769. * we've discovered, even if FH interrupt came in just after
  770. * reading CSR_INT. */
  771. if (inta_fh & CSR49_FH_INT_RX_MASK)
  772. inta |= CSR_INT_BIT_FH_RX;
  773. if (inta_fh & CSR49_FH_INT_TX_MASK)
  774. inta |= CSR_INT_BIT_FH_TX;
  775. /* Now service all interrupt bits discovered above. */
  776. if (inta & CSR_INT_BIT_HW_ERR) {
  777. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  778. /* Tell the device to stop sending interrupts */
  779. iwl_disable_interrupts(priv);
  780. priv->isr_stats.hw++;
  781. iwl_irq_handle_error(priv);
  782. handled |= CSR_INT_BIT_HW_ERR;
  783. return;
  784. }
  785. #ifdef CONFIG_IWLWIFI_DEBUG
  786. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  787. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  788. if (inta & CSR_INT_BIT_SCD) {
  789. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  790. "the frame/frames.\n");
  791. priv->isr_stats.sch++;
  792. }
  793. /* Alive notification via Rx interrupt will do the real work */
  794. if (inta & CSR_INT_BIT_ALIVE) {
  795. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  796. priv->isr_stats.alive++;
  797. }
  798. }
  799. #endif
  800. /* Safely ignore these bits for debug checks below */
  801. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  802. /* HW RF KILL switch toggled */
  803. if (inta & CSR_INT_BIT_RF_KILL) {
  804. int hw_rf_kill = 0;
  805. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  806. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  807. hw_rf_kill = 1;
  808. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  809. hw_rf_kill ? "disable radio" : "enable radio");
  810. priv->isr_stats.rfkill++;
  811. /* driver only loads ucode once setting the interface up.
  812. * the driver allows loading the ucode even if the radio
  813. * is killed. Hence update the killswitch state here. The
  814. * rfkill handler will care about restarting if needed.
  815. */
  816. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  817. if (hw_rf_kill)
  818. set_bit(STATUS_RF_KILL_HW, &priv->status);
  819. else
  820. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  821. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  822. }
  823. handled |= CSR_INT_BIT_RF_KILL;
  824. }
  825. /* Chip got too hot and stopped itself */
  826. if (inta & CSR_INT_BIT_CT_KILL) {
  827. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  828. priv->isr_stats.ctkill++;
  829. handled |= CSR_INT_BIT_CT_KILL;
  830. }
  831. /* Error detected by uCode */
  832. if (inta & CSR_INT_BIT_SW_ERR) {
  833. IWL_ERR(priv, "Microcode SW error detected. "
  834. " Restarting 0x%X.\n", inta);
  835. priv->isr_stats.sw++;
  836. priv->isr_stats.sw_err = inta;
  837. iwl_irq_handle_error(priv);
  838. handled |= CSR_INT_BIT_SW_ERR;
  839. }
  840. /* uCode wakes up after power-down sleep */
  841. if (inta & CSR_INT_BIT_WAKEUP) {
  842. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  843. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  844. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  845. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  846. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  847. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  848. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  849. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  850. priv->isr_stats.wakeup++;
  851. handled |= CSR_INT_BIT_WAKEUP;
  852. }
  853. /* All uCode command responses, including Tx command responses,
  854. * Rx "responses" (frame-received notification), and other
  855. * notifications from uCode come through here*/
  856. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  857. iwl_rx_handle(priv);
  858. priv->isr_stats.rx++;
  859. iwl_leds_background(priv);
  860. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  861. }
  862. /* This "Tx" DMA channel is used only for loading uCode */
  863. if (inta & CSR_INT_BIT_FH_TX) {
  864. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  865. priv->isr_stats.tx++;
  866. handled |= CSR_INT_BIT_FH_TX;
  867. /* Wake up uCode load routine, now that load is complete */
  868. priv->ucode_write_complete = 1;
  869. wake_up_interruptible(&priv->wait_command_queue);
  870. }
  871. if (inta & ~handled) {
  872. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  873. priv->isr_stats.unhandled++;
  874. }
  875. if (inta & ~(priv->inta_mask)) {
  876. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  877. inta & ~priv->inta_mask);
  878. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  879. }
  880. /* Re-enable all interrupts */
  881. /* only Re-enable if diabled by irq */
  882. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  883. iwl_enable_interrupts(priv);
  884. #ifdef CONFIG_IWLWIFI_DEBUG
  885. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  886. inta = iwl_read32(priv, CSR_INT);
  887. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  888. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  889. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  890. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  891. }
  892. #endif
  893. }
  894. /* tasklet for iwlagn interrupt */
  895. static void iwl_irq_tasklet(struct iwl_priv *priv)
  896. {
  897. u32 inta = 0;
  898. u32 handled = 0;
  899. unsigned long flags;
  900. #ifdef CONFIG_IWLWIFI_DEBUG
  901. u32 inta_mask;
  902. #endif
  903. spin_lock_irqsave(&priv->lock, flags);
  904. /* Ack/clear/reset pending uCode interrupts.
  905. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  906. */
  907. iwl_write32(priv, CSR_INT, priv->inta);
  908. inta = priv->inta;
  909. #ifdef CONFIG_IWLWIFI_DEBUG
  910. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  911. /* just for debug */
  912. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  913. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  914. inta, inta_mask);
  915. }
  916. #endif
  917. spin_unlock_irqrestore(&priv->lock, flags);
  918. /* saved interrupt in inta variable now we can reset priv->inta */
  919. priv->inta = 0;
  920. /* Now service all interrupt bits discovered above. */
  921. if (inta & CSR_INT_BIT_HW_ERR) {
  922. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  923. /* Tell the device to stop sending interrupts */
  924. iwl_disable_interrupts(priv);
  925. priv->isr_stats.hw++;
  926. iwl_irq_handle_error(priv);
  927. handled |= CSR_INT_BIT_HW_ERR;
  928. return;
  929. }
  930. #ifdef CONFIG_IWLWIFI_DEBUG
  931. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  932. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  933. if (inta & CSR_INT_BIT_SCD) {
  934. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  935. "the frame/frames.\n");
  936. priv->isr_stats.sch++;
  937. }
  938. /* Alive notification via Rx interrupt will do the real work */
  939. if (inta & CSR_INT_BIT_ALIVE) {
  940. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  941. priv->isr_stats.alive++;
  942. }
  943. }
  944. #endif
  945. /* Safely ignore these bits for debug checks below */
  946. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  947. /* HW RF KILL switch toggled */
  948. if (inta & CSR_INT_BIT_RF_KILL) {
  949. int hw_rf_kill = 0;
  950. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  951. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  952. hw_rf_kill = 1;
  953. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  954. hw_rf_kill ? "disable radio" : "enable radio");
  955. priv->isr_stats.rfkill++;
  956. /* driver only loads ucode once setting the interface up.
  957. * the driver allows loading the ucode even if the radio
  958. * is killed. Hence update the killswitch state here. The
  959. * rfkill handler will care about restarting if needed.
  960. */
  961. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  962. if (hw_rf_kill)
  963. set_bit(STATUS_RF_KILL_HW, &priv->status);
  964. else
  965. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  966. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  967. }
  968. handled |= CSR_INT_BIT_RF_KILL;
  969. }
  970. /* Chip got too hot and stopped itself */
  971. if (inta & CSR_INT_BIT_CT_KILL) {
  972. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  973. priv->isr_stats.ctkill++;
  974. handled |= CSR_INT_BIT_CT_KILL;
  975. }
  976. /* Error detected by uCode */
  977. if (inta & CSR_INT_BIT_SW_ERR) {
  978. IWL_ERR(priv, "Microcode SW error detected. "
  979. " Restarting 0x%X.\n", inta);
  980. priv->isr_stats.sw++;
  981. priv->isr_stats.sw_err = inta;
  982. iwl_irq_handle_error(priv);
  983. handled |= CSR_INT_BIT_SW_ERR;
  984. }
  985. /* uCode wakes up after power-down sleep */
  986. if (inta & CSR_INT_BIT_WAKEUP) {
  987. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  988. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  989. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  990. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  991. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  992. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  993. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  994. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  995. priv->isr_stats.wakeup++;
  996. handled |= CSR_INT_BIT_WAKEUP;
  997. }
  998. /* All uCode command responses, including Tx command responses,
  999. * Rx "responses" (frame-received notification), and other
  1000. * notifications from uCode come through here*/
  1001. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1002. CSR_INT_BIT_RX_PERIODIC)) {
  1003. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1004. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1005. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1006. iwl_write32(priv, CSR_FH_INT_STATUS,
  1007. CSR49_FH_INT_RX_MASK);
  1008. }
  1009. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1010. handled |= CSR_INT_BIT_RX_PERIODIC;
  1011. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1012. }
  1013. /* Sending RX interrupt require many steps to be done in the
  1014. * the device:
  1015. * 1- write interrupt to current index in ICT table.
  1016. * 2- dma RX frame.
  1017. * 3- update RX shared data to indicate last write index.
  1018. * 4- send interrupt.
  1019. * This could lead to RX race, driver could receive RX interrupt
  1020. * but the shared data changes does not reflect this.
  1021. * this could lead to RX race, RX periodic will solve this race
  1022. */
  1023. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1024. CSR_INT_PERIODIC_DIS);
  1025. iwl_rx_handle(priv);
  1026. /* Only set RX periodic if real RX is received. */
  1027. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1028. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1029. CSR_INT_PERIODIC_ENA);
  1030. priv->isr_stats.rx++;
  1031. iwl_leds_background(priv);
  1032. }
  1033. /* This "Tx" DMA channel is used only for loading uCode */
  1034. if (inta & CSR_INT_BIT_FH_TX) {
  1035. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1036. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1037. priv->isr_stats.tx++;
  1038. handled |= CSR_INT_BIT_FH_TX;
  1039. /* Wake up uCode load routine, now that load is complete */
  1040. priv->ucode_write_complete = 1;
  1041. wake_up_interruptible(&priv->wait_command_queue);
  1042. }
  1043. if (inta & ~handled) {
  1044. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1045. priv->isr_stats.unhandled++;
  1046. }
  1047. if (inta & ~(priv->inta_mask)) {
  1048. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1049. inta & ~priv->inta_mask);
  1050. }
  1051. /* Re-enable all interrupts */
  1052. /* only Re-enable if diabled by irq */
  1053. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1054. iwl_enable_interrupts(priv);
  1055. }
  1056. /******************************************************************************
  1057. *
  1058. * uCode download functions
  1059. *
  1060. ******************************************************************************/
  1061. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1062. {
  1063. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1064. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1065. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1066. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1067. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1068. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1069. }
  1070. static void iwl_nic_start(struct iwl_priv *priv)
  1071. {
  1072. /* Remove all resets to allow NIC to operate */
  1073. iwl_write32(priv, CSR_RESET, 0);
  1074. }
  1075. /**
  1076. * iwl_read_ucode - Read uCode images from disk file.
  1077. *
  1078. * Copy into buffers for card to fetch via bus-mastering
  1079. */
  1080. static int iwl_read_ucode(struct iwl_priv *priv)
  1081. {
  1082. struct iwl_ucode_header *ucode;
  1083. int ret = -EINVAL, index;
  1084. const struct firmware *ucode_raw;
  1085. const char *name_pre = priv->cfg->fw_name_pre;
  1086. const unsigned int api_max = priv->cfg->ucode_api_max;
  1087. const unsigned int api_min = priv->cfg->ucode_api_min;
  1088. char buf[25];
  1089. u8 *src;
  1090. size_t len;
  1091. u32 api_ver, build;
  1092. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1093. u16 eeprom_ver;
  1094. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1095. * request_firmware() is synchronous, file is in memory on return. */
  1096. for (index = api_max; index >= api_min; index--) {
  1097. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1098. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1099. if (ret < 0) {
  1100. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1101. buf, ret);
  1102. if (ret == -ENOENT)
  1103. continue;
  1104. else
  1105. goto error;
  1106. } else {
  1107. if (index < api_max)
  1108. IWL_ERR(priv, "Loaded firmware %s, "
  1109. "which is deprecated. "
  1110. "Please use API v%u instead.\n",
  1111. buf, api_max);
  1112. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1113. buf, ucode_raw->size);
  1114. break;
  1115. }
  1116. }
  1117. if (ret < 0)
  1118. goto error;
  1119. /* Make sure that we got at least the v1 header! */
  1120. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1121. IWL_ERR(priv, "File size way too small!\n");
  1122. ret = -EINVAL;
  1123. goto err_release;
  1124. }
  1125. /* Data from ucode file: header followed by uCode images */
  1126. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1127. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1128. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1129. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1130. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1131. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1132. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1133. init_data_size =
  1134. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1135. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1136. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1137. /* api_ver should match the api version forming part of the
  1138. * firmware filename ... but we don't check for that and only rely
  1139. * on the API version read from firmware header from here on forward */
  1140. if (api_ver < api_min || api_ver > api_max) {
  1141. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1142. "Driver supports v%u, firmware is v%u.\n",
  1143. api_max, api_ver);
  1144. priv->ucode_ver = 0;
  1145. ret = -EINVAL;
  1146. goto err_release;
  1147. }
  1148. if (api_ver != api_max)
  1149. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1150. "got v%u. New firmware can be obtained "
  1151. "from http://www.intellinuxwireless.org.\n",
  1152. api_max, api_ver);
  1153. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1154. IWL_UCODE_MAJOR(priv->ucode_ver),
  1155. IWL_UCODE_MINOR(priv->ucode_ver),
  1156. IWL_UCODE_API(priv->ucode_ver),
  1157. IWL_UCODE_SERIAL(priv->ucode_ver));
  1158. snprintf(priv->hw->wiphy->fw_version,
  1159. sizeof(priv->hw->wiphy->fw_version),
  1160. "%u.%u.%u.%u",
  1161. IWL_UCODE_MAJOR(priv->ucode_ver),
  1162. IWL_UCODE_MINOR(priv->ucode_ver),
  1163. IWL_UCODE_API(priv->ucode_ver),
  1164. IWL_UCODE_SERIAL(priv->ucode_ver));
  1165. if (build)
  1166. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1167. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1168. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1169. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1170. ? "OTP" : "EEPROM", eeprom_ver);
  1171. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1172. priv->ucode_ver);
  1173. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1174. inst_size);
  1175. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1176. data_size);
  1177. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1178. init_size);
  1179. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1180. init_data_size);
  1181. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1182. boot_size);
  1183. /* Verify size of file vs. image size info in file's header */
  1184. if (ucode_raw->size !=
  1185. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1186. inst_size + data_size + init_size +
  1187. init_data_size + boot_size) {
  1188. IWL_DEBUG_INFO(priv,
  1189. "uCode file size %d does not match expected size\n",
  1190. (int)ucode_raw->size);
  1191. ret = -EINVAL;
  1192. goto err_release;
  1193. }
  1194. /* Verify that uCode images will fit in card's SRAM */
  1195. if (inst_size > priv->hw_params.max_inst_size) {
  1196. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1197. inst_size);
  1198. ret = -EINVAL;
  1199. goto err_release;
  1200. }
  1201. if (data_size > priv->hw_params.max_data_size) {
  1202. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1203. data_size);
  1204. ret = -EINVAL;
  1205. goto err_release;
  1206. }
  1207. if (init_size > priv->hw_params.max_inst_size) {
  1208. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1209. init_size);
  1210. ret = -EINVAL;
  1211. goto err_release;
  1212. }
  1213. if (init_data_size > priv->hw_params.max_data_size) {
  1214. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1215. init_data_size);
  1216. ret = -EINVAL;
  1217. goto err_release;
  1218. }
  1219. if (boot_size > priv->hw_params.max_bsm_size) {
  1220. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1221. boot_size);
  1222. ret = -EINVAL;
  1223. goto err_release;
  1224. }
  1225. /* Allocate ucode buffers for card's bus-master loading ... */
  1226. /* Runtime instructions and 2 copies of data:
  1227. * 1) unmodified from disk
  1228. * 2) backup cache for save/restore during power-downs */
  1229. priv->ucode_code.len = inst_size;
  1230. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1231. priv->ucode_data.len = data_size;
  1232. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1233. priv->ucode_data_backup.len = data_size;
  1234. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1235. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1236. !priv->ucode_data_backup.v_addr)
  1237. goto err_pci_alloc;
  1238. /* Initialization instructions and data */
  1239. if (init_size && init_data_size) {
  1240. priv->ucode_init.len = init_size;
  1241. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1242. priv->ucode_init_data.len = init_data_size;
  1243. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1244. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1245. goto err_pci_alloc;
  1246. }
  1247. /* Bootstrap (instructions only, no data) */
  1248. if (boot_size) {
  1249. priv->ucode_boot.len = boot_size;
  1250. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1251. if (!priv->ucode_boot.v_addr)
  1252. goto err_pci_alloc;
  1253. }
  1254. /* Copy images into buffers for card's bus-master reads ... */
  1255. /* Runtime instructions (first block of data in file) */
  1256. len = inst_size;
  1257. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1258. memcpy(priv->ucode_code.v_addr, src, len);
  1259. src += len;
  1260. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1261. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1262. /* Runtime data (2nd block)
  1263. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1264. len = data_size;
  1265. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1266. memcpy(priv->ucode_data.v_addr, src, len);
  1267. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1268. src += len;
  1269. /* Initialization instructions (3rd block) */
  1270. if (init_size) {
  1271. len = init_size;
  1272. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1273. len);
  1274. memcpy(priv->ucode_init.v_addr, src, len);
  1275. src += len;
  1276. }
  1277. /* Initialization data (4th block) */
  1278. if (init_data_size) {
  1279. len = init_data_size;
  1280. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1281. len);
  1282. memcpy(priv->ucode_init_data.v_addr, src, len);
  1283. src += len;
  1284. }
  1285. /* Bootstrap instructions (5th block) */
  1286. len = boot_size;
  1287. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1288. memcpy(priv->ucode_boot.v_addr, src, len);
  1289. /* We have our copies now, allow OS release its copies */
  1290. release_firmware(ucode_raw);
  1291. return 0;
  1292. err_pci_alloc:
  1293. IWL_ERR(priv, "failed to allocate pci memory\n");
  1294. ret = -ENOMEM;
  1295. iwl_dealloc_ucode_pci(priv);
  1296. err_release:
  1297. release_firmware(ucode_raw);
  1298. error:
  1299. return ret;
  1300. }
  1301. #ifdef CONFIG_IWLWIFI_DEBUG
  1302. static const char *desc_lookup_text[] = {
  1303. "OK",
  1304. "FAIL",
  1305. "BAD_PARAM",
  1306. "BAD_CHECKSUM",
  1307. "NMI_INTERRUPT_WDG",
  1308. "SYSASSERT",
  1309. "FATAL_ERROR",
  1310. "BAD_COMMAND",
  1311. "HW_ERROR_TUNE_LOCK",
  1312. "HW_ERROR_TEMPERATURE",
  1313. "ILLEGAL_CHAN_FREQ",
  1314. "VCC_NOT_STABLE",
  1315. "FH_ERROR",
  1316. "NMI_INTERRUPT_HOST",
  1317. "NMI_INTERRUPT_ACTION_PT",
  1318. "NMI_INTERRUPT_UNKNOWN",
  1319. "UCODE_VERSION_MISMATCH",
  1320. "HW_ERROR_ABS_LOCK",
  1321. "HW_ERROR_CAL_LOCK_FAIL",
  1322. "NMI_INTERRUPT_INST_ACTION_PT",
  1323. "NMI_INTERRUPT_DATA_ACTION_PT",
  1324. "NMI_TRM_HW_ER",
  1325. "NMI_INTERRUPT_TRM",
  1326. "NMI_INTERRUPT_BREAK_POINT"
  1327. "DEBUG_0",
  1328. "DEBUG_1",
  1329. "DEBUG_2",
  1330. "DEBUG_3",
  1331. "UNKNOWN"
  1332. };
  1333. static const char *desc_lookup(int i)
  1334. {
  1335. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1336. if (i < 0 || i > max)
  1337. i = max;
  1338. return desc_lookup_text[i];
  1339. }
  1340. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1341. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1342. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1343. {
  1344. u32 data2, line;
  1345. u32 desc, time, count, base, data1;
  1346. u32 blink1, blink2, ilink1, ilink2;
  1347. if (priv->ucode_type == UCODE_INIT)
  1348. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1349. else
  1350. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1351. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1352. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1353. return;
  1354. }
  1355. count = iwl_read_targ_mem(priv, base);
  1356. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1357. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1358. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1359. priv->status, count);
  1360. }
  1361. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1362. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1363. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1364. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1365. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1366. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1367. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1368. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1369. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1370. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1371. blink1, blink2, ilink1, ilink2);
  1372. IWL_ERR(priv, "Desc Time "
  1373. "data1 data2 line\n");
  1374. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1375. desc_lookup(desc), desc, time, data1, data2, line);
  1376. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1377. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1378. ilink1, ilink2);
  1379. }
  1380. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1381. /**
  1382. * iwl_print_event_log - Dump error event log to syslog
  1383. *
  1384. */
  1385. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1386. u32 num_events, u32 mode)
  1387. {
  1388. u32 i;
  1389. u32 base; /* SRAM byte address of event log header */
  1390. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1391. u32 ptr; /* SRAM byte address of log data */
  1392. u32 ev, time, data; /* event log data */
  1393. if (num_events == 0)
  1394. return;
  1395. if (priv->ucode_type == UCODE_INIT)
  1396. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1397. else
  1398. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1399. if (mode == 0)
  1400. event_size = 2 * sizeof(u32);
  1401. else
  1402. event_size = 3 * sizeof(u32);
  1403. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1404. /* "time" is actually "data" for mode 0 (no timestamp).
  1405. * place event id # at far right for easier visual parsing. */
  1406. for (i = 0; i < num_events; i++) {
  1407. ev = iwl_read_targ_mem(priv, ptr);
  1408. ptr += sizeof(u32);
  1409. time = iwl_read_targ_mem(priv, ptr);
  1410. ptr += sizeof(u32);
  1411. if (mode == 0) {
  1412. /* data, ev */
  1413. trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
  1414. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1415. } else {
  1416. data = iwl_read_targ_mem(priv, ptr);
  1417. ptr += sizeof(u32);
  1418. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1419. time, data, ev);
  1420. trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
  1421. }
  1422. }
  1423. }
  1424. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1425. {
  1426. u32 base; /* SRAM byte address of event log header */
  1427. u32 capacity; /* event log capacity in # entries */
  1428. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1429. u32 num_wraps; /* # times uCode wrapped to top of log */
  1430. u32 next_entry; /* index of next entry to be written by uCode */
  1431. u32 size; /* # entries that we'll print */
  1432. if (priv->ucode_type == UCODE_INIT)
  1433. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1434. else
  1435. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1436. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1437. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1438. return;
  1439. }
  1440. /* event log header */
  1441. capacity = iwl_read_targ_mem(priv, base);
  1442. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1443. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1444. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1445. size = num_wraps ? capacity : next_entry;
  1446. /* bail out if nothing in log */
  1447. if (size == 0) {
  1448. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1449. return;
  1450. }
  1451. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1452. size, num_wraps);
  1453. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1454. * i.e the next one that uCode would fill. */
  1455. if (num_wraps)
  1456. iwl_print_event_log(priv, next_entry,
  1457. capacity - next_entry, mode);
  1458. /* (then/else) start at top of log */
  1459. iwl_print_event_log(priv, 0, next_entry, mode);
  1460. }
  1461. #endif
  1462. /**
  1463. * iwl_alive_start - called after REPLY_ALIVE notification received
  1464. * from protocol/runtime uCode (initialization uCode's
  1465. * Alive gets handled by iwl_init_alive_start()).
  1466. */
  1467. static void iwl_alive_start(struct iwl_priv *priv)
  1468. {
  1469. int ret = 0;
  1470. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1471. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1472. /* We had an error bringing up the hardware, so take it
  1473. * all the way back down so we can try again */
  1474. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1475. goto restart;
  1476. }
  1477. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1478. * This is a paranoid check, because we would not have gotten the
  1479. * "runtime" alive if code weren't properly loaded. */
  1480. if (iwl_verify_ucode(priv)) {
  1481. /* Runtime instruction load was bad;
  1482. * take it all the way back down so we can try again */
  1483. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1484. goto restart;
  1485. }
  1486. iwl_clear_stations_table(priv);
  1487. ret = priv->cfg->ops->lib->alive_notify(priv);
  1488. if (ret) {
  1489. IWL_WARN(priv,
  1490. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1491. goto restart;
  1492. }
  1493. /* After the ALIVE response, we can send host commands to the uCode */
  1494. set_bit(STATUS_ALIVE, &priv->status);
  1495. if (iwl_is_rfkill(priv))
  1496. return;
  1497. ieee80211_wake_queues(priv->hw);
  1498. priv->active_rate = priv->rates_mask;
  1499. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1500. /* Configure Tx antenna selection based on H/W config */
  1501. if (priv->cfg->ops->hcmd->set_tx_ant)
  1502. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1503. if (iwl_is_associated(priv)) {
  1504. struct iwl_rxon_cmd *active_rxon =
  1505. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1506. /* apply any changes in staging */
  1507. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1508. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1509. } else {
  1510. /* Initialize our rx_config data */
  1511. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1512. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1513. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1514. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1515. }
  1516. /* Configure Bluetooth device coexistence support */
  1517. iwl_send_bt_config(priv);
  1518. iwl_reset_run_time_calib(priv);
  1519. /* Configure the adapter for unassociated operation */
  1520. iwlcore_commit_rxon(priv);
  1521. /* At this point, the NIC is initialized and operational */
  1522. iwl_rf_kill_ct_config(priv);
  1523. iwl_leds_init(priv);
  1524. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1525. set_bit(STATUS_READY, &priv->status);
  1526. wake_up_interruptible(&priv->wait_command_queue);
  1527. iwl_power_update_mode(priv, true);
  1528. /* reassociate for ADHOC mode */
  1529. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1530. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1531. priv->vif);
  1532. if (beacon)
  1533. iwl_mac_beacon_update(priv->hw, beacon);
  1534. }
  1535. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1536. iwl_set_mode(priv, priv->iw_mode);
  1537. return;
  1538. restart:
  1539. queue_work(priv->workqueue, &priv->restart);
  1540. }
  1541. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1542. static void __iwl_down(struct iwl_priv *priv)
  1543. {
  1544. unsigned long flags;
  1545. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1546. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1547. if (!exit_pending)
  1548. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1549. iwl_clear_stations_table(priv);
  1550. /* Unblock any waiting calls */
  1551. wake_up_interruptible_all(&priv->wait_command_queue);
  1552. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1553. * exiting the module */
  1554. if (!exit_pending)
  1555. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1556. /* stop and reset the on-board processor */
  1557. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1558. /* tell the device to stop sending interrupts */
  1559. spin_lock_irqsave(&priv->lock, flags);
  1560. iwl_disable_interrupts(priv);
  1561. spin_unlock_irqrestore(&priv->lock, flags);
  1562. iwl_synchronize_irq(priv);
  1563. if (priv->mac80211_registered)
  1564. ieee80211_stop_queues(priv->hw);
  1565. /* If we have not previously called iwl_init() then
  1566. * clear all bits but the RF Kill bit and return */
  1567. if (!iwl_is_init(priv)) {
  1568. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1569. STATUS_RF_KILL_HW |
  1570. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1571. STATUS_GEO_CONFIGURED |
  1572. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1573. STATUS_EXIT_PENDING;
  1574. goto exit;
  1575. }
  1576. /* ...otherwise clear out all the status bits but the RF Kill
  1577. * bit and continue taking the NIC down. */
  1578. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1579. STATUS_RF_KILL_HW |
  1580. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1581. STATUS_GEO_CONFIGURED |
  1582. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1583. STATUS_FW_ERROR |
  1584. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1585. STATUS_EXIT_PENDING;
  1586. /* device going down, Stop using ICT table */
  1587. iwl_disable_ict(priv);
  1588. spin_lock_irqsave(&priv->lock, flags);
  1589. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1590. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1591. spin_unlock_irqrestore(&priv->lock, flags);
  1592. iwl_txq_ctx_stop(priv);
  1593. iwl_rxq_stop(priv);
  1594. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1595. APMG_CLK_VAL_DMA_CLK_RQT);
  1596. udelay(5);
  1597. /* Stop the device, and put it in low power state */
  1598. priv->cfg->ops->lib->apm_ops.stop(priv);
  1599. exit:
  1600. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1601. if (priv->ibss_beacon)
  1602. dev_kfree_skb(priv->ibss_beacon);
  1603. priv->ibss_beacon = NULL;
  1604. /* clear out any free frames */
  1605. iwl_clear_free_frames(priv);
  1606. }
  1607. static void iwl_down(struct iwl_priv *priv)
  1608. {
  1609. mutex_lock(&priv->mutex);
  1610. __iwl_down(priv);
  1611. mutex_unlock(&priv->mutex);
  1612. iwl_cancel_deferred_work(priv);
  1613. }
  1614. #define HW_READY_TIMEOUT (50)
  1615. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1616. {
  1617. int ret = 0;
  1618. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1619. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1620. /* See if we got it */
  1621. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1622. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1623. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1624. HW_READY_TIMEOUT);
  1625. if (ret != -ETIMEDOUT)
  1626. priv->hw_ready = true;
  1627. else
  1628. priv->hw_ready = false;
  1629. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1630. (priv->hw_ready == 1) ? "ready" : "not ready");
  1631. return ret;
  1632. }
  1633. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1634. {
  1635. int ret = 0;
  1636. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1637. ret = iwl_set_hw_ready(priv);
  1638. if (priv->hw_ready)
  1639. return ret;
  1640. /* If HW is not ready, prepare the conditions to check again */
  1641. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1642. CSR_HW_IF_CONFIG_REG_PREPARE);
  1643. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1644. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1645. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1646. /* HW should be ready by now, check again. */
  1647. if (ret != -ETIMEDOUT)
  1648. iwl_set_hw_ready(priv);
  1649. return ret;
  1650. }
  1651. #define MAX_HW_RESTARTS 5
  1652. static int __iwl_up(struct iwl_priv *priv)
  1653. {
  1654. int i;
  1655. int ret;
  1656. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1657. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1658. return -EIO;
  1659. }
  1660. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1661. IWL_ERR(priv, "ucode not available for device bringup\n");
  1662. return -EIO;
  1663. }
  1664. iwl_prepare_card_hw(priv);
  1665. if (!priv->hw_ready) {
  1666. IWL_WARN(priv, "Exit HW not ready\n");
  1667. return -EIO;
  1668. }
  1669. /* If platform's RF_KILL switch is NOT set to KILL */
  1670. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1671. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1672. else
  1673. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1674. if (iwl_is_rfkill(priv)) {
  1675. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1676. iwl_enable_interrupts(priv);
  1677. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1678. return 0;
  1679. }
  1680. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1681. ret = iwl_hw_nic_init(priv);
  1682. if (ret) {
  1683. IWL_ERR(priv, "Unable to init nic\n");
  1684. return ret;
  1685. }
  1686. /* make sure rfkill handshake bits are cleared */
  1687. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1688. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1689. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1690. /* clear (again), then enable host interrupts */
  1691. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1692. iwl_enable_interrupts(priv);
  1693. /* really make sure rfkill handshake bits are cleared */
  1694. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1695. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1696. /* Copy original ucode data image from disk into backup cache.
  1697. * This will be used to initialize the on-board processor's
  1698. * data SRAM for a clean start when the runtime program first loads. */
  1699. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1700. priv->ucode_data.len);
  1701. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1702. iwl_clear_stations_table(priv);
  1703. /* load bootstrap state machine,
  1704. * load bootstrap program into processor's memory,
  1705. * prepare to load the "initialize" uCode */
  1706. ret = priv->cfg->ops->lib->load_ucode(priv);
  1707. if (ret) {
  1708. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1709. ret);
  1710. continue;
  1711. }
  1712. /* start card; "initialize" will load runtime ucode */
  1713. iwl_nic_start(priv);
  1714. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1715. return 0;
  1716. }
  1717. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1718. __iwl_down(priv);
  1719. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1720. /* tried to restart and config the device for as long as our
  1721. * patience could withstand */
  1722. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1723. return -EIO;
  1724. }
  1725. /*****************************************************************************
  1726. *
  1727. * Workqueue callbacks
  1728. *
  1729. *****************************************************************************/
  1730. static void iwl_bg_init_alive_start(struct work_struct *data)
  1731. {
  1732. struct iwl_priv *priv =
  1733. container_of(data, struct iwl_priv, init_alive_start.work);
  1734. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1735. return;
  1736. mutex_lock(&priv->mutex);
  1737. priv->cfg->ops->lib->init_alive_start(priv);
  1738. mutex_unlock(&priv->mutex);
  1739. }
  1740. static void iwl_bg_alive_start(struct work_struct *data)
  1741. {
  1742. struct iwl_priv *priv =
  1743. container_of(data, struct iwl_priv, alive_start.work);
  1744. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1745. return;
  1746. /* enable dram interrupt */
  1747. iwl_reset_ict(priv);
  1748. mutex_lock(&priv->mutex);
  1749. iwl_alive_start(priv);
  1750. mutex_unlock(&priv->mutex);
  1751. }
  1752. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1753. {
  1754. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1755. run_time_calib_work);
  1756. mutex_lock(&priv->mutex);
  1757. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1758. test_bit(STATUS_SCANNING, &priv->status)) {
  1759. mutex_unlock(&priv->mutex);
  1760. return;
  1761. }
  1762. if (priv->start_calib) {
  1763. iwl_chain_noise_calibration(priv, &priv->statistics);
  1764. iwl_sensitivity_calibration(priv, &priv->statistics);
  1765. }
  1766. mutex_unlock(&priv->mutex);
  1767. return;
  1768. }
  1769. static void iwl_bg_up(struct work_struct *data)
  1770. {
  1771. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1772. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1773. return;
  1774. mutex_lock(&priv->mutex);
  1775. __iwl_up(priv);
  1776. mutex_unlock(&priv->mutex);
  1777. }
  1778. static void iwl_bg_restart(struct work_struct *data)
  1779. {
  1780. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1781. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1782. return;
  1783. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1784. mutex_lock(&priv->mutex);
  1785. priv->vif = NULL;
  1786. priv->is_open = 0;
  1787. mutex_unlock(&priv->mutex);
  1788. iwl_down(priv);
  1789. ieee80211_restart_hw(priv->hw);
  1790. } else {
  1791. iwl_down(priv);
  1792. queue_work(priv->workqueue, &priv->up);
  1793. }
  1794. }
  1795. static void iwl_bg_rx_replenish(struct work_struct *data)
  1796. {
  1797. struct iwl_priv *priv =
  1798. container_of(data, struct iwl_priv, rx_replenish);
  1799. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1800. return;
  1801. mutex_lock(&priv->mutex);
  1802. iwl_rx_replenish(priv);
  1803. mutex_unlock(&priv->mutex);
  1804. }
  1805. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1806. void iwl_post_associate(struct iwl_priv *priv)
  1807. {
  1808. struct ieee80211_conf *conf = NULL;
  1809. int ret = 0;
  1810. unsigned long flags;
  1811. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1812. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1813. return;
  1814. }
  1815. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1816. priv->assoc_id, priv->active_rxon.bssid_addr);
  1817. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1818. return;
  1819. if (!priv->vif || !priv->is_open)
  1820. return;
  1821. iwl_scan_cancel_timeout(priv, 200);
  1822. conf = ieee80211_get_hw_conf(priv->hw);
  1823. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1824. iwlcore_commit_rxon(priv);
  1825. iwl_setup_rxon_timing(priv);
  1826. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1827. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1828. if (ret)
  1829. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1830. "Attempting to continue.\n");
  1831. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1832. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1833. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1834. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1835. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1836. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1837. priv->assoc_id, priv->beacon_int);
  1838. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1839. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1840. else
  1841. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1842. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1843. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1844. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1845. else
  1846. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1847. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1848. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1849. }
  1850. iwlcore_commit_rxon(priv);
  1851. switch (priv->iw_mode) {
  1852. case NL80211_IFTYPE_STATION:
  1853. break;
  1854. case NL80211_IFTYPE_ADHOC:
  1855. /* assume default assoc id */
  1856. priv->assoc_id = 1;
  1857. iwl_rxon_add_station(priv, priv->bssid, 0);
  1858. iwl_send_beacon_cmd(priv);
  1859. break;
  1860. default:
  1861. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1862. __func__, priv->iw_mode);
  1863. break;
  1864. }
  1865. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1866. priv->assoc_station_added = 1;
  1867. spin_lock_irqsave(&priv->lock, flags);
  1868. iwl_activate_qos(priv, 0);
  1869. spin_unlock_irqrestore(&priv->lock, flags);
  1870. /* the chain noise calibration will enabled PM upon completion
  1871. * If chain noise has already been run, then we need to enable
  1872. * power management here */
  1873. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1874. iwl_power_update_mode(priv, false);
  1875. /* Enable Rx differential gain and sensitivity calibrations */
  1876. iwl_chain_noise_reset(priv);
  1877. priv->start_calib = 1;
  1878. }
  1879. /*****************************************************************************
  1880. *
  1881. * mac80211 entry point functions
  1882. *
  1883. *****************************************************************************/
  1884. #define UCODE_READY_TIMEOUT (4 * HZ)
  1885. /*
  1886. * Not a mac80211 entry point function, but it fits in with all the
  1887. * other mac80211 functions grouped here.
  1888. */
  1889. static int iwl_setup_mac(struct iwl_priv *priv)
  1890. {
  1891. int ret;
  1892. struct ieee80211_hw *hw = priv->hw;
  1893. hw->rate_control_algorithm = "iwl-agn-rs";
  1894. /* Tell mac80211 our characteristics */
  1895. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1896. IEEE80211_HW_NOISE_DBM |
  1897. IEEE80211_HW_AMPDU_AGGREGATION |
  1898. IEEE80211_HW_SPECTRUM_MGMT;
  1899. if (!priv->cfg->broken_powersave)
  1900. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  1901. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  1902. hw->sta_data_size = sizeof(struct iwl_station_priv);
  1903. hw->wiphy->interface_modes =
  1904. BIT(NL80211_IFTYPE_STATION) |
  1905. BIT(NL80211_IFTYPE_ADHOC);
  1906. hw->wiphy->custom_regulatory = true;
  1907. /* Firmware does not support this */
  1908. hw->wiphy->disable_beacon_hints = true;
  1909. /*
  1910. * For now, disable PS by default because it affects
  1911. * RX performance significantly.
  1912. */
  1913. hw->wiphy->ps_default = false;
  1914. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  1915. /* we create the 802.11 header and a zero-length SSID element */
  1916. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  1917. /* Default value; 4 EDCA QOS priorities */
  1918. hw->queues = 4;
  1919. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  1920. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  1921. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1922. &priv->bands[IEEE80211_BAND_2GHZ];
  1923. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  1924. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1925. &priv->bands[IEEE80211_BAND_5GHZ];
  1926. ret = ieee80211_register_hw(priv->hw);
  1927. if (ret) {
  1928. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  1929. return ret;
  1930. }
  1931. priv->mac80211_registered = 1;
  1932. return 0;
  1933. }
  1934. static int iwl_mac_start(struct ieee80211_hw *hw)
  1935. {
  1936. struct iwl_priv *priv = hw->priv;
  1937. int ret;
  1938. IWL_DEBUG_MAC80211(priv, "enter\n");
  1939. /* we should be verifying the device is ready to be opened */
  1940. mutex_lock(&priv->mutex);
  1941. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1942. * ucode filename and max sizes are card-specific. */
  1943. if (!priv->ucode_code.len) {
  1944. ret = iwl_read_ucode(priv);
  1945. if (ret) {
  1946. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1947. mutex_unlock(&priv->mutex);
  1948. return ret;
  1949. }
  1950. }
  1951. ret = __iwl_up(priv);
  1952. mutex_unlock(&priv->mutex);
  1953. if (ret)
  1954. return ret;
  1955. if (iwl_is_rfkill(priv))
  1956. goto out;
  1957. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1958. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1959. * mac80211 will not be run successfully. */
  1960. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1961. test_bit(STATUS_READY, &priv->status),
  1962. UCODE_READY_TIMEOUT);
  1963. if (!ret) {
  1964. if (!test_bit(STATUS_READY, &priv->status)) {
  1965. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1966. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1967. return -ETIMEDOUT;
  1968. }
  1969. }
  1970. iwl_led_start(priv);
  1971. out:
  1972. priv->is_open = 1;
  1973. IWL_DEBUG_MAC80211(priv, "leave\n");
  1974. return 0;
  1975. }
  1976. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1977. {
  1978. struct iwl_priv *priv = hw->priv;
  1979. IWL_DEBUG_MAC80211(priv, "enter\n");
  1980. if (!priv->is_open)
  1981. return;
  1982. priv->is_open = 0;
  1983. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  1984. /* stop mac, cancel any scan request and clear
  1985. * RXON_FILTER_ASSOC_MSK BIT
  1986. */
  1987. mutex_lock(&priv->mutex);
  1988. iwl_scan_cancel_timeout(priv, 100);
  1989. mutex_unlock(&priv->mutex);
  1990. }
  1991. iwl_down(priv);
  1992. flush_workqueue(priv->workqueue);
  1993. /* enable interrupts again in order to receive rfkill changes */
  1994. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1995. iwl_enable_interrupts(priv);
  1996. IWL_DEBUG_MAC80211(priv, "leave\n");
  1997. }
  1998. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1999. {
  2000. struct iwl_priv *priv = hw->priv;
  2001. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2002. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2003. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2004. if (iwl_tx_skb(priv, skb))
  2005. dev_kfree_skb_any(skb);
  2006. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2007. return NETDEV_TX_OK;
  2008. }
  2009. void iwl_config_ap(struct iwl_priv *priv)
  2010. {
  2011. int ret = 0;
  2012. unsigned long flags;
  2013. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2014. return;
  2015. /* The following should be done only at AP bring up */
  2016. if (!iwl_is_associated(priv)) {
  2017. /* RXON - unassoc (to set timing command) */
  2018. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2019. iwlcore_commit_rxon(priv);
  2020. /* RXON Timing */
  2021. iwl_setup_rxon_timing(priv);
  2022. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2023. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2024. if (ret)
  2025. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2026. "Attempting to continue.\n");
  2027. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2028. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2029. /* FIXME: what should be the assoc_id for AP? */
  2030. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2031. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2032. priv->staging_rxon.flags |=
  2033. RXON_FLG_SHORT_PREAMBLE_MSK;
  2034. else
  2035. priv->staging_rxon.flags &=
  2036. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2037. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2038. if (priv->assoc_capability &
  2039. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2040. priv->staging_rxon.flags |=
  2041. RXON_FLG_SHORT_SLOT_MSK;
  2042. else
  2043. priv->staging_rxon.flags &=
  2044. ~RXON_FLG_SHORT_SLOT_MSK;
  2045. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2046. priv->staging_rxon.flags &=
  2047. ~RXON_FLG_SHORT_SLOT_MSK;
  2048. }
  2049. /* restore RXON assoc */
  2050. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2051. iwlcore_commit_rxon(priv);
  2052. spin_lock_irqsave(&priv->lock, flags);
  2053. iwl_activate_qos(priv, 1);
  2054. spin_unlock_irqrestore(&priv->lock, flags);
  2055. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  2056. }
  2057. iwl_send_beacon_cmd(priv);
  2058. /* FIXME - we need to add code here to detect a totally new
  2059. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2060. * clear sta table, add BCAST sta... */
  2061. }
  2062. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2063. struct ieee80211_key_conf *keyconf, const u8 *addr,
  2064. u32 iv32, u16 *phase1key)
  2065. {
  2066. struct iwl_priv *priv = hw->priv;
  2067. IWL_DEBUG_MAC80211(priv, "enter\n");
  2068. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  2069. IWL_DEBUG_MAC80211(priv, "leave\n");
  2070. }
  2071. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2072. struct ieee80211_vif *vif,
  2073. struct ieee80211_sta *sta,
  2074. struct ieee80211_key_conf *key)
  2075. {
  2076. struct iwl_priv *priv = hw->priv;
  2077. const u8 *addr;
  2078. int ret;
  2079. u8 sta_id;
  2080. bool is_default_wep_key = false;
  2081. IWL_DEBUG_MAC80211(priv, "enter\n");
  2082. if (priv->cfg->mod_params->sw_crypto) {
  2083. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2084. return -EOPNOTSUPP;
  2085. }
  2086. addr = sta ? sta->addr : iwl_bcast_addr;
  2087. sta_id = iwl_find_station(priv, addr);
  2088. if (sta_id == IWL_INVALID_STATION) {
  2089. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2090. addr);
  2091. return -EINVAL;
  2092. }
  2093. mutex_lock(&priv->mutex);
  2094. iwl_scan_cancel_timeout(priv, 100);
  2095. mutex_unlock(&priv->mutex);
  2096. /* If we are getting WEP group key and we didn't receive any key mapping
  2097. * so far, we are in legacy wep mode (group key only), otherwise we are
  2098. * in 1X mode.
  2099. * In legacy wep mode, we use another host command to the uCode */
  2100. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2101. priv->iw_mode != NL80211_IFTYPE_AP) {
  2102. if (cmd == SET_KEY)
  2103. is_default_wep_key = !priv->key_mapping_key;
  2104. else
  2105. is_default_wep_key =
  2106. (key->hw_key_idx == HW_KEY_DEFAULT);
  2107. }
  2108. switch (cmd) {
  2109. case SET_KEY:
  2110. if (is_default_wep_key)
  2111. ret = iwl_set_default_wep_key(priv, key);
  2112. else
  2113. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2114. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2115. break;
  2116. case DISABLE_KEY:
  2117. if (is_default_wep_key)
  2118. ret = iwl_remove_default_wep_key(priv, key);
  2119. else
  2120. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2121. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2122. break;
  2123. default:
  2124. ret = -EINVAL;
  2125. }
  2126. IWL_DEBUG_MAC80211(priv, "leave\n");
  2127. return ret;
  2128. }
  2129. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2130. enum ieee80211_ampdu_mlme_action action,
  2131. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2132. {
  2133. struct iwl_priv *priv = hw->priv;
  2134. int ret;
  2135. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2136. sta->addr, tid);
  2137. if (!(priv->cfg->sku & IWL_SKU_N))
  2138. return -EACCES;
  2139. switch (action) {
  2140. case IEEE80211_AMPDU_RX_START:
  2141. IWL_DEBUG_HT(priv, "start Rx\n");
  2142. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2143. case IEEE80211_AMPDU_RX_STOP:
  2144. IWL_DEBUG_HT(priv, "stop Rx\n");
  2145. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2146. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2147. return 0;
  2148. else
  2149. return ret;
  2150. case IEEE80211_AMPDU_TX_START:
  2151. IWL_DEBUG_HT(priv, "start Tx\n");
  2152. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2153. case IEEE80211_AMPDU_TX_STOP:
  2154. IWL_DEBUG_HT(priv, "stop Tx\n");
  2155. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2156. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2157. return 0;
  2158. else
  2159. return ret;
  2160. default:
  2161. IWL_DEBUG_HT(priv, "unknown\n");
  2162. return -EINVAL;
  2163. break;
  2164. }
  2165. return 0;
  2166. }
  2167. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2168. struct ieee80211_low_level_stats *stats)
  2169. {
  2170. struct iwl_priv *priv = hw->priv;
  2171. priv = hw->priv;
  2172. IWL_DEBUG_MAC80211(priv, "enter\n");
  2173. IWL_DEBUG_MAC80211(priv, "leave\n");
  2174. return 0;
  2175. }
  2176. /*****************************************************************************
  2177. *
  2178. * sysfs attributes
  2179. *
  2180. *****************************************************************************/
  2181. #ifdef CONFIG_IWLWIFI_DEBUG
  2182. /*
  2183. * The following adds a new attribute to the sysfs representation
  2184. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2185. * used for controlling the debug level.
  2186. *
  2187. * See the level definitions in iwl for details.
  2188. *
  2189. * The debug_level being managed using sysfs below is a per device debug
  2190. * level that is used instead of the global debug level if it (the per
  2191. * device debug level) is set.
  2192. */
  2193. static ssize_t show_debug_level(struct device *d,
  2194. struct device_attribute *attr, char *buf)
  2195. {
  2196. struct iwl_priv *priv = dev_get_drvdata(d);
  2197. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2198. }
  2199. static ssize_t store_debug_level(struct device *d,
  2200. struct device_attribute *attr,
  2201. const char *buf, size_t count)
  2202. {
  2203. struct iwl_priv *priv = dev_get_drvdata(d);
  2204. unsigned long val;
  2205. int ret;
  2206. ret = strict_strtoul(buf, 0, &val);
  2207. if (ret)
  2208. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2209. else {
  2210. priv->debug_level = val;
  2211. if (iwl_alloc_traffic_mem(priv))
  2212. IWL_ERR(priv,
  2213. "Not enough memory to generate traffic log\n");
  2214. }
  2215. return strnlen(buf, count);
  2216. }
  2217. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2218. show_debug_level, store_debug_level);
  2219. #endif /* CONFIG_IWLWIFI_DEBUG */
  2220. static ssize_t show_temperature(struct device *d,
  2221. struct device_attribute *attr, char *buf)
  2222. {
  2223. struct iwl_priv *priv = dev_get_drvdata(d);
  2224. if (!iwl_is_alive(priv))
  2225. return -EAGAIN;
  2226. return sprintf(buf, "%d\n", priv->temperature);
  2227. }
  2228. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2229. static ssize_t show_tx_power(struct device *d,
  2230. struct device_attribute *attr, char *buf)
  2231. {
  2232. struct iwl_priv *priv = dev_get_drvdata(d);
  2233. if (!iwl_is_ready_rf(priv))
  2234. return sprintf(buf, "off\n");
  2235. else
  2236. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2237. }
  2238. static ssize_t store_tx_power(struct device *d,
  2239. struct device_attribute *attr,
  2240. const char *buf, size_t count)
  2241. {
  2242. struct iwl_priv *priv = dev_get_drvdata(d);
  2243. unsigned long val;
  2244. int ret;
  2245. ret = strict_strtoul(buf, 10, &val);
  2246. if (ret)
  2247. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2248. else {
  2249. ret = iwl_set_tx_power(priv, val, false);
  2250. if (ret)
  2251. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2252. ret);
  2253. else
  2254. ret = count;
  2255. }
  2256. return ret;
  2257. }
  2258. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2259. static ssize_t show_flags(struct device *d,
  2260. struct device_attribute *attr, char *buf)
  2261. {
  2262. struct iwl_priv *priv = dev_get_drvdata(d);
  2263. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2264. }
  2265. static ssize_t store_flags(struct device *d,
  2266. struct device_attribute *attr,
  2267. const char *buf, size_t count)
  2268. {
  2269. struct iwl_priv *priv = dev_get_drvdata(d);
  2270. unsigned long val;
  2271. u32 flags;
  2272. int ret = strict_strtoul(buf, 0, &val);
  2273. if (ret)
  2274. return ret;
  2275. flags = (u32)val;
  2276. mutex_lock(&priv->mutex);
  2277. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2278. /* Cancel any currently running scans... */
  2279. if (iwl_scan_cancel_timeout(priv, 100))
  2280. IWL_WARN(priv, "Could not cancel scan.\n");
  2281. else {
  2282. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2283. priv->staging_rxon.flags = cpu_to_le32(flags);
  2284. iwlcore_commit_rxon(priv);
  2285. }
  2286. }
  2287. mutex_unlock(&priv->mutex);
  2288. return count;
  2289. }
  2290. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2291. static ssize_t show_filter_flags(struct device *d,
  2292. struct device_attribute *attr, char *buf)
  2293. {
  2294. struct iwl_priv *priv = dev_get_drvdata(d);
  2295. return sprintf(buf, "0x%04X\n",
  2296. le32_to_cpu(priv->active_rxon.filter_flags));
  2297. }
  2298. static ssize_t store_filter_flags(struct device *d,
  2299. struct device_attribute *attr,
  2300. const char *buf, size_t count)
  2301. {
  2302. struct iwl_priv *priv = dev_get_drvdata(d);
  2303. unsigned long val;
  2304. u32 filter_flags;
  2305. int ret = strict_strtoul(buf, 0, &val);
  2306. if (ret)
  2307. return ret;
  2308. filter_flags = (u32)val;
  2309. mutex_lock(&priv->mutex);
  2310. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2311. /* Cancel any currently running scans... */
  2312. if (iwl_scan_cancel_timeout(priv, 100))
  2313. IWL_WARN(priv, "Could not cancel scan.\n");
  2314. else {
  2315. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2316. "0x%04X\n", filter_flags);
  2317. priv->staging_rxon.filter_flags =
  2318. cpu_to_le32(filter_flags);
  2319. iwlcore_commit_rxon(priv);
  2320. }
  2321. }
  2322. mutex_unlock(&priv->mutex);
  2323. return count;
  2324. }
  2325. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2326. store_filter_flags);
  2327. static ssize_t show_statistics(struct device *d,
  2328. struct device_attribute *attr, char *buf)
  2329. {
  2330. struct iwl_priv *priv = dev_get_drvdata(d);
  2331. u32 size = sizeof(struct iwl_notif_statistics);
  2332. u32 len = 0, ofs = 0;
  2333. u8 *data = (u8 *)&priv->statistics;
  2334. int rc = 0;
  2335. if (!iwl_is_alive(priv))
  2336. return -EAGAIN;
  2337. mutex_lock(&priv->mutex);
  2338. rc = iwl_send_statistics_request(priv, 0);
  2339. mutex_unlock(&priv->mutex);
  2340. if (rc) {
  2341. len = sprintf(buf,
  2342. "Error sending statistics request: 0x%08X\n", rc);
  2343. return len;
  2344. }
  2345. while (size && (PAGE_SIZE - len)) {
  2346. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2347. PAGE_SIZE - len, 1);
  2348. len = strlen(buf);
  2349. if (PAGE_SIZE - len)
  2350. buf[len++] = '\n';
  2351. ofs += 16;
  2352. size -= min(size, 16U);
  2353. }
  2354. return len;
  2355. }
  2356. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2357. static ssize_t show_rts_ht_protection(struct device *d,
  2358. struct device_attribute *attr, char *buf)
  2359. {
  2360. struct iwl_priv *priv = dev_get_drvdata(d);
  2361. return sprintf(buf, "%s\n",
  2362. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2363. }
  2364. static ssize_t store_rts_ht_protection(struct device *d,
  2365. struct device_attribute *attr,
  2366. const char *buf, size_t count)
  2367. {
  2368. struct iwl_priv *priv = dev_get_drvdata(d);
  2369. unsigned long val;
  2370. int ret;
  2371. ret = strict_strtoul(buf, 10, &val);
  2372. if (ret)
  2373. IWL_INFO(priv, "Input is not in decimal form.\n");
  2374. else {
  2375. if (!iwl_is_associated(priv))
  2376. priv->cfg->use_rts_for_ht = val ? true : false;
  2377. else
  2378. IWL_ERR(priv, "Sta associated with AP - "
  2379. "Change protection mechanism is not allowed\n");
  2380. ret = count;
  2381. }
  2382. return ret;
  2383. }
  2384. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2385. show_rts_ht_protection, store_rts_ht_protection);
  2386. /*****************************************************************************
  2387. *
  2388. * driver setup and teardown
  2389. *
  2390. *****************************************************************************/
  2391. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2392. {
  2393. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2394. init_waitqueue_head(&priv->wait_command_queue);
  2395. INIT_WORK(&priv->up, iwl_bg_up);
  2396. INIT_WORK(&priv->restart, iwl_bg_restart);
  2397. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2398. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2399. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2400. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2401. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2402. iwl_setup_scan_deferred_work(priv);
  2403. if (priv->cfg->ops->lib->setup_deferred_work)
  2404. priv->cfg->ops->lib->setup_deferred_work(priv);
  2405. init_timer(&priv->statistics_periodic);
  2406. priv->statistics_periodic.data = (unsigned long)priv;
  2407. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2408. if (!priv->cfg->use_isr_legacy)
  2409. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2410. iwl_irq_tasklet, (unsigned long)priv);
  2411. else
  2412. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2413. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2414. }
  2415. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2416. {
  2417. if (priv->cfg->ops->lib->cancel_deferred_work)
  2418. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2419. cancel_delayed_work_sync(&priv->init_alive_start);
  2420. cancel_delayed_work(&priv->scan_check);
  2421. cancel_delayed_work(&priv->alive_start);
  2422. cancel_work_sync(&priv->beacon_update);
  2423. del_timer_sync(&priv->statistics_periodic);
  2424. }
  2425. static struct attribute *iwl_sysfs_entries[] = {
  2426. &dev_attr_flags.attr,
  2427. &dev_attr_filter_flags.attr,
  2428. &dev_attr_statistics.attr,
  2429. &dev_attr_temperature.attr,
  2430. &dev_attr_tx_power.attr,
  2431. &dev_attr_rts_ht_protection.attr,
  2432. #ifdef CONFIG_IWLWIFI_DEBUG
  2433. &dev_attr_debug_level.attr,
  2434. #endif
  2435. NULL
  2436. };
  2437. static struct attribute_group iwl_attribute_group = {
  2438. .name = NULL, /* put in device directory */
  2439. .attrs = iwl_sysfs_entries,
  2440. };
  2441. static struct ieee80211_ops iwl_hw_ops = {
  2442. .tx = iwl_mac_tx,
  2443. .start = iwl_mac_start,
  2444. .stop = iwl_mac_stop,
  2445. .add_interface = iwl_mac_add_interface,
  2446. .remove_interface = iwl_mac_remove_interface,
  2447. .config = iwl_mac_config,
  2448. .configure_filter = iwl_configure_filter,
  2449. .set_key = iwl_mac_set_key,
  2450. .update_tkip_key = iwl_mac_update_tkip_key,
  2451. .get_stats = iwl_mac_get_stats,
  2452. .get_tx_stats = iwl_mac_get_tx_stats,
  2453. .conf_tx = iwl_mac_conf_tx,
  2454. .reset_tsf = iwl_mac_reset_tsf,
  2455. .bss_info_changed = iwl_bss_info_changed,
  2456. .ampdu_action = iwl_mac_ampdu_action,
  2457. .hw_scan = iwl_mac_hw_scan
  2458. };
  2459. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2460. {
  2461. int err = 0;
  2462. struct iwl_priv *priv;
  2463. struct ieee80211_hw *hw;
  2464. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2465. unsigned long flags;
  2466. u16 pci_cmd;
  2467. /************************
  2468. * 1. Allocating HW data
  2469. ************************/
  2470. /* Disabling hardware scan means that mac80211 will perform scans
  2471. * "the hard way", rather than using device's scan. */
  2472. if (cfg->mod_params->disable_hw_scan) {
  2473. if (iwl_debug_level & IWL_DL_INFO)
  2474. dev_printk(KERN_DEBUG, &(pdev->dev),
  2475. "Disabling hw_scan\n");
  2476. iwl_hw_ops.hw_scan = NULL;
  2477. }
  2478. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2479. if (!hw) {
  2480. err = -ENOMEM;
  2481. goto out;
  2482. }
  2483. priv = hw->priv;
  2484. /* At this point both hw and priv are allocated. */
  2485. SET_IEEE80211_DEV(hw, &pdev->dev);
  2486. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2487. priv->cfg = cfg;
  2488. priv->pci_dev = pdev;
  2489. priv->inta_mask = CSR_INI_SET_MASK;
  2490. #ifdef CONFIG_IWLWIFI_DEBUG
  2491. atomic_set(&priv->restrict_refcnt, 0);
  2492. #endif
  2493. if (iwl_alloc_traffic_mem(priv))
  2494. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2495. /**************************
  2496. * 2. Initializing PCI bus
  2497. **************************/
  2498. if (pci_enable_device(pdev)) {
  2499. err = -ENODEV;
  2500. goto out_ieee80211_free_hw;
  2501. }
  2502. pci_set_master(pdev);
  2503. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2504. if (!err)
  2505. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2506. if (err) {
  2507. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2508. if (!err)
  2509. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2510. /* both attempts failed: */
  2511. if (err) {
  2512. IWL_WARN(priv, "No suitable DMA available.\n");
  2513. goto out_pci_disable_device;
  2514. }
  2515. }
  2516. err = pci_request_regions(pdev, DRV_NAME);
  2517. if (err)
  2518. goto out_pci_disable_device;
  2519. pci_set_drvdata(pdev, priv);
  2520. /***********************
  2521. * 3. Read REV register
  2522. ***********************/
  2523. priv->hw_base = pci_iomap(pdev, 0, 0);
  2524. if (!priv->hw_base) {
  2525. err = -ENODEV;
  2526. goto out_pci_release_regions;
  2527. }
  2528. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2529. (unsigned long long) pci_resource_len(pdev, 0));
  2530. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2531. /* this spin lock will be used in apm_ops.init and EEPROM access
  2532. * we should init now
  2533. */
  2534. spin_lock_init(&priv->reg_lock);
  2535. iwl_hw_detect(priv);
  2536. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2537. priv->cfg->name, priv->hw_rev);
  2538. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2539. * PCI Tx retries from interfering with C3 CPU state */
  2540. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2541. iwl_prepare_card_hw(priv);
  2542. if (!priv->hw_ready) {
  2543. IWL_WARN(priv, "Failed, HW not ready\n");
  2544. goto out_iounmap;
  2545. }
  2546. /*****************
  2547. * 4. Read EEPROM
  2548. *****************/
  2549. /* Read the EEPROM */
  2550. err = iwl_eeprom_init(priv);
  2551. if (err) {
  2552. IWL_ERR(priv, "Unable to init EEPROM\n");
  2553. goto out_iounmap;
  2554. }
  2555. err = iwl_eeprom_check_version(priv);
  2556. if (err)
  2557. goto out_free_eeprom;
  2558. /* extract MAC Address */
  2559. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2560. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2561. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2562. /************************
  2563. * 5. Setup HW constants
  2564. ************************/
  2565. if (iwl_set_hw_params(priv)) {
  2566. IWL_ERR(priv, "failed to set hw parameters\n");
  2567. goto out_free_eeprom;
  2568. }
  2569. /*******************
  2570. * 6. Setup priv
  2571. *******************/
  2572. err = iwl_init_drv(priv);
  2573. if (err)
  2574. goto out_free_eeprom;
  2575. /* At this point both hw and priv are initialized. */
  2576. /********************
  2577. * 7. Setup services
  2578. ********************/
  2579. spin_lock_irqsave(&priv->lock, flags);
  2580. iwl_disable_interrupts(priv);
  2581. spin_unlock_irqrestore(&priv->lock, flags);
  2582. pci_enable_msi(priv->pci_dev);
  2583. iwl_alloc_isr_ict(priv);
  2584. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2585. IRQF_SHARED, DRV_NAME, priv);
  2586. if (err) {
  2587. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2588. goto out_disable_msi;
  2589. }
  2590. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2591. if (err) {
  2592. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2593. goto out_free_irq;
  2594. }
  2595. iwl_setup_deferred_work(priv);
  2596. iwl_setup_rx_handlers(priv);
  2597. /**********************************
  2598. * 8. Setup and register mac80211
  2599. **********************************/
  2600. /* enable interrupts if needed: hw bug w/a */
  2601. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2602. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2603. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2604. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2605. }
  2606. iwl_enable_interrupts(priv);
  2607. err = iwl_setup_mac(priv);
  2608. if (err)
  2609. goto out_remove_sysfs;
  2610. err = iwl_dbgfs_register(priv, DRV_NAME);
  2611. if (err)
  2612. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2613. /* If platform's RF_KILL switch is NOT set to KILL */
  2614. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2615. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2616. else
  2617. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2618. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2619. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2620. iwl_power_initialize(priv);
  2621. iwl_tt_initialize(priv);
  2622. return 0;
  2623. out_remove_sysfs:
  2624. destroy_workqueue(priv->workqueue);
  2625. priv->workqueue = NULL;
  2626. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2627. out_free_irq:
  2628. free_irq(priv->pci_dev->irq, priv);
  2629. iwl_free_isr_ict(priv);
  2630. out_disable_msi:
  2631. pci_disable_msi(priv->pci_dev);
  2632. iwl_uninit_drv(priv);
  2633. out_free_eeprom:
  2634. iwl_eeprom_free(priv);
  2635. out_iounmap:
  2636. pci_iounmap(pdev, priv->hw_base);
  2637. out_pci_release_regions:
  2638. pci_set_drvdata(pdev, NULL);
  2639. pci_release_regions(pdev);
  2640. out_pci_disable_device:
  2641. pci_disable_device(pdev);
  2642. out_ieee80211_free_hw:
  2643. iwl_free_traffic_mem(priv);
  2644. ieee80211_free_hw(priv->hw);
  2645. out:
  2646. return err;
  2647. }
  2648. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2649. {
  2650. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2651. unsigned long flags;
  2652. if (!priv)
  2653. return;
  2654. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2655. iwl_dbgfs_unregister(priv);
  2656. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2657. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2658. * to be called and iwl_down since we are removing the device
  2659. * we need to set STATUS_EXIT_PENDING bit.
  2660. */
  2661. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2662. if (priv->mac80211_registered) {
  2663. ieee80211_unregister_hw(priv->hw);
  2664. priv->mac80211_registered = 0;
  2665. } else {
  2666. iwl_down(priv);
  2667. }
  2668. /*
  2669. * Make sure device is reset to low power before unloading driver.
  2670. * This may be redundant with iwl_down(), but there are paths to
  2671. * run iwl_down() without calling apm_ops.stop(), and there are
  2672. * paths to avoid running iwl_down() at all before leaving driver.
  2673. * This (inexpensive) call *makes sure* device is reset.
  2674. */
  2675. priv->cfg->ops->lib->apm_ops.stop(priv);
  2676. iwl_tt_exit(priv);
  2677. /* make sure we flush any pending irq or
  2678. * tasklet for the driver
  2679. */
  2680. spin_lock_irqsave(&priv->lock, flags);
  2681. iwl_disable_interrupts(priv);
  2682. spin_unlock_irqrestore(&priv->lock, flags);
  2683. iwl_synchronize_irq(priv);
  2684. iwl_dealloc_ucode_pci(priv);
  2685. if (priv->rxq.bd)
  2686. iwl_rx_queue_free(priv, &priv->rxq);
  2687. iwl_hw_txq_ctx_free(priv);
  2688. iwl_clear_stations_table(priv);
  2689. iwl_eeprom_free(priv);
  2690. /*netif_stop_queue(dev); */
  2691. flush_workqueue(priv->workqueue);
  2692. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2693. * priv->workqueue... so we can't take down the workqueue
  2694. * until now... */
  2695. destroy_workqueue(priv->workqueue);
  2696. priv->workqueue = NULL;
  2697. iwl_free_traffic_mem(priv);
  2698. free_irq(priv->pci_dev->irq, priv);
  2699. pci_disable_msi(priv->pci_dev);
  2700. pci_iounmap(pdev, priv->hw_base);
  2701. pci_release_regions(pdev);
  2702. pci_disable_device(pdev);
  2703. pci_set_drvdata(pdev, NULL);
  2704. iwl_uninit_drv(priv);
  2705. iwl_free_isr_ict(priv);
  2706. if (priv->ibss_beacon)
  2707. dev_kfree_skb(priv->ibss_beacon);
  2708. ieee80211_free_hw(priv->hw);
  2709. }
  2710. /*****************************************************************************
  2711. *
  2712. * driver and module entry point
  2713. *
  2714. *****************************************************************************/
  2715. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2716. static struct pci_device_id iwl_hw_card_ids[] = {
  2717. #ifdef CONFIG_IWL4965
  2718. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2719. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2720. #endif /* CONFIG_IWL4965 */
  2721. #ifdef CONFIG_IWL5000
  2722. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2723. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2724. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2725. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2726. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2727. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2728. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2729. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2730. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2731. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2732. /* 5350 WiFi/WiMax */
  2733. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2734. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2735. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2736. /* 5150 Wifi/WiMax */
  2737. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2738. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2739. /* 6x00 Series */
  2740. {IWL_PCI_DEVICE(0x008D, 0x1301, iwl6000h_2agn_cfg)},
  2741. {IWL_PCI_DEVICE(0x008D, 0x1321, iwl6000h_2agn_cfg)},
  2742. {IWL_PCI_DEVICE(0x008D, 0x1326, iwl6000h_2abg_cfg)},
  2743. {IWL_PCI_DEVICE(0x008D, 0x1306, iwl6000h_2abg_cfg)},
  2744. {IWL_PCI_DEVICE(0x008D, 0x1307, iwl6000h_2bg_cfg)},
  2745. {IWL_PCI_DEVICE(0x008E, 0x1311, iwl6000h_2agn_cfg)},
  2746. {IWL_PCI_DEVICE(0x008E, 0x1316, iwl6000h_2abg_cfg)},
  2747. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  2748. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  2749. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  2750. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  2751. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  2752. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  2753. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  2754. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  2755. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  2756. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  2757. /* 6x50 WiFi/WiMax Series */
  2758. {IWL_PCI_DEVICE(0x0086, 0x1101, iwl6050_3agn_cfg)},
  2759. {IWL_PCI_DEVICE(0x0086, 0x1121, iwl6050_3agn_cfg)},
  2760. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  2761. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  2762. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  2763. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  2764. {IWL_PCI_DEVICE(0x0088, 0x1111, iwl6050_3agn_cfg)},
  2765. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  2766. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  2767. /* 1000 Series WiFi */
  2768. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  2769. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  2770. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  2771. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  2772. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  2773. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  2774. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  2775. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  2776. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  2777. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  2778. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  2779. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  2780. #endif /* CONFIG_IWL5000 */
  2781. {0}
  2782. };
  2783. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2784. static struct pci_driver iwl_driver = {
  2785. .name = DRV_NAME,
  2786. .id_table = iwl_hw_card_ids,
  2787. .probe = iwl_pci_probe,
  2788. .remove = __devexit_p(iwl_pci_remove),
  2789. #ifdef CONFIG_PM
  2790. .suspend = iwl_pci_suspend,
  2791. .resume = iwl_pci_resume,
  2792. #endif
  2793. };
  2794. static int __init iwl_init(void)
  2795. {
  2796. int ret;
  2797. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2798. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2799. ret = iwlagn_rate_control_register();
  2800. if (ret) {
  2801. printk(KERN_ERR DRV_NAME
  2802. "Unable to register rate control algorithm: %d\n", ret);
  2803. return ret;
  2804. }
  2805. ret = pci_register_driver(&iwl_driver);
  2806. if (ret) {
  2807. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2808. goto error_register;
  2809. }
  2810. return ret;
  2811. error_register:
  2812. iwlagn_rate_control_unregister();
  2813. return ret;
  2814. }
  2815. static void __exit iwl_exit(void)
  2816. {
  2817. pci_unregister_driver(&iwl_driver);
  2818. iwlagn_rate_control_unregister();
  2819. }
  2820. module_exit(iwl_exit);
  2821. module_init(iwl_init);
  2822. #ifdef CONFIG_IWLWIFI_DEBUG
  2823. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  2824. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  2825. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  2826. MODULE_PARM_DESC(debug, "debug output mask");
  2827. #endif