qla_mbx.c 116 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/gfp.h>
  10. /*
  11. * qla2x00_mailbox_command
  12. * Issue mailbox command and waits for completion.
  13. *
  14. * Input:
  15. * ha = adapter block pointer.
  16. * mcp = driver internal mbx struct pointer.
  17. *
  18. * Output:
  19. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  20. *
  21. * Returns:
  22. * 0 : QLA_SUCCESS = cmd performed success
  23. * 1 : QLA_FUNCTION_FAILED (error encountered)
  24. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  25. *
  26. * Context:
  27. * Kernel context.
  28. */
  29. static int
  30. qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
  31. {
  32. int rval;
  33. unsigned long flags = 0;
  34. device_reg_t __iomem *reg;
  35. uint8_t abort_active;
  36. uint8_t io_lock_on;
  37. uint16_t command = 0;
  38. uint16_t *iptr;
  39. uint16_t __iomem *optr;
  40. uint32_t cnt;
  41. uint32_t mboxes;
  42. unsigned long wait_time;
  43. struct qla_hw_data *ha = vha->hw;
  44. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  45. ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
  46. if (ha->pdev->error_state > pci_channel_io_frozen) {
  47. ql_log(ql_log_warn, vha, 0x1001,
  48. "error_state is greater than pci_channel_io_frozen, "
  49. "exiting.\n");
  50. return QLA_FUNCTION_TIMEOUT;
  51. }
  52. if (vha->device_flags & DFLG_DEV_FAILED) {
  53. ql_log(ql_log_warn, vha, 0x1002,
  54. "Device in failed state, exiting.\n");
  55. return QLA_FUNCTION_TIMEOUT;
  56. }
  57. reg = ha->iobase;
  58. io_lock_on = base_vha->flags.init_done;
  59. rval = QLA_SUCCESS;
  60. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  61. if (ha->flags.pci_channel_io_perm_failure) {
  62. ql_log(ql_log_warn, vha, 0x1003,
  63. "Perm failure on EEH timeout MBX, exiting.\n");
  64. return QLA_FUNCTION_TIMEOUT;
  65. }
  66. if (ha->flags.isp82xx_fw_hung) {
  67. /* Setting Link-Down error */
  68. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  69. ql_log(ql_log_warn, vha, 0x1004,
  70. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  71. return QLA_FUNCTION_TIMEOUT;
  72. }
  73. /*
  74. * Wait for active mailbox commands to finish by waiting at most tov
  75. * seconds. This is to serialize actual issuing of mailbox cmds during
  76. * non ISP abort time.
  77. */
  78. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  79. /* Timeout occurred. Return error. */
  80. ql_log(ql_log_warn, vha, 0x1005,
  81. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  82. mcp->mb[0]);
  83. return QLA_FUNCTION_TIMEOUT;
  84. }
  85. ha->flags.mbox_busy = 1;
  86. /* Save mailbox command for debug */
  87. ha->mcp = mcp;
  88. ql_dbg(ql_dbg_mbx, vha, 0x1006,
  89. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  90. spin_lock_irqsave(&ha->hardware_lock, flags);
  91. /* Load mailbox registers. */
  92. if (IS_QLA82XX(ha))
  93. optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
  94. else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha))
  95. optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
  96. else
  97. optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
  98. iptr = mcp->mb;
  99. command = mcp->mb[0];
  100. mboxes = mcp->out_mb;
  101. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  102. if (IS_QLA2200(ha) && cnt == 8)
  103. optr =
  104. (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
  105. if (mboxes & BIT_0)
  106. WRT_REG_WORD(optr, *iptr);
  107. mboxes >>= 1;
  108. optr++;
  109. iptr++;
  110. }
  111. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111,
  112. "Loaded MBX registers (displayed in bytes) =.\n");
  113. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1112,
  114. (uint8_t *)mcp->mb, 16);
  115. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1113,
  116. ".\n");
  117. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1114,
  118. ((uint8_t *)mcp->mb + 0x10), 16);
  119. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1115,
  120. ".\n");
  121. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1116,
  122. ((uint8_t *)mcp->mb + 0x20), 8);
  123. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
  124. "I/O Address = %p.\n", optr);
  125. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x100e);
  126. /* Issue set host interrupt command to send cmd out. */
  127. ha->flags.mbox_int = 0;
  128. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  129. /* Unlock mbx registers and wait for interrupt */
  130. ql_dbg(ql_dbg_mbx, vha, 0x100f,
  131. "Going to unlock irq & waiting for interrupts. "
  132. "jiffies=%lx.\n", jiffies);
  133. /* Wait for mbx cmd completion until timeout */
  134. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  135. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  136. if (IS_QLA82XX(ha)) {
  137. if (RD_REG_DWORD(&reg->isp82.hint) &
  138. HINT_MBX_INT_PENDING) {
  139. spin_unlock_irqrestore(&ha->hardware_lock,
  140. flags);
  141. ha->flags.mbox_busy = 0;
  142. ql_dbg(ql_dbg_mbx, vha, 0x1010,
  143. "Pending mailbox timeout, exiting.\n");
  144. rval = QLA_FUNCTION_TIMEOUT;
  145. goto premature_exit;
  146. }
  147. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  148. } else if (IS_FWI2_CAPABLE(ha))
  149. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  150. else
  151. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  152. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  153. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  154. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  155. } else {
  156. ql_dbg(ql_dbg_mbx, vha, 0x1011,
  157. "Cmd=%x Polling Mode.\n", command);
  158. if (IS_QLA82XX(ha)) {
  159. if (RD_REG_DWORD(&reg->isp82.hint) &
  160. HINT_MBX_INT_PENDING) {
  161. spin_unlock_irqrestore(&ha->hardware_lock,
  162. flags);
  163. ha->flags.mbox_busy = 0;
  164. ql_dbg(ql_dbg_mbx, vha, 0x1012,
  165. "Pending mailbox timeout, exiting.\n");
  166. rval = QLA_FUNCTION_TIMEOUT;
  167. goto premature_exit;
  168. }
  169. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  170. } else if (IS_FWI2_CAPABLE(ha))
  171. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  172. else
  173. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  174. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  175. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  176. while (!ha->flags.mbox_int) {
  177. if (time_after(jiffies, wait_time))
  178. break;
  179. /* Check for pending interrupts. */
  180. qla2x00_poll(ha->rsp_q_map[0]);
  181. if (!ha->flags.mbox_int &&
  182. !(IS_QLA2200(ha) &&
  183. command == MBC_LOAD_RISC_RAM_EXTENDED))
  184. msleep(10);
  185. } /* while */
  186. ql_dbg(ql_dbg_mbx, vha, 0x1013,
  187. "Waited %d sec.\n",
  188. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  189. }
  190. /* Check whether we timed out */
  191. if (ha->flags.mbox_int) {
  192. uint16_t *iptr2;
  193. ql_dbg(ql_dbg_mbx, vha, 0x1014,
  194. "Cmd=%x completed.\n", command);
  195. /* Got interrupt. Clear the flag. */
  196. ha->flags.mbox_int = 0;
  197. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  198. if (ha->flags.isp82xx_fw_hung) {
  199. ha->flags.mbox_busy = 0;
  200. /* Setting Link-Down error */
  201. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  202. ha->mcp = NULL;
  203. rval = QLA_FUNCTION_FAILED;
  204. ql_log(ql_log_warn, vha, 0x1015,
  205. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  206. goto premature_exit;
  207. }
  208. if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
  209. rval = QLA_FUNCTION_FAILED;
  210. /* Load return mailbox registers. */
  211. iptr2 = mcp->mb;
  212. iptr = (uint16_t *)&ha->mailbox_out[0];
  213. mboxes = mcp->in_mb;
  214. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  215. if (mboxes & BIT_0)
  216. *iptr2 = *iptr;
  217. mboxes >>= 1;
  218. iptr2++;
  219. iptr++;
  220. }
  221. } else {
  222. uint16_t mb0;
  223. uint32_t ictrl;
  224. if (IS_FWI2_CAPABLE(ha)) {
  225. mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
  226. ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
  227. } else {
  228. mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
  229. ictrl = RD_REG_WORD(&reg->isp.ictrl);
  230. }
  231. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
  232. "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
  233. "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
  234. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
  235. /*
  236. * Attempt to capture a firmware dump for further analysis
  237. * of the current firmware state
  238. */
  239. ha->isp_ops->fw_dump(vha, 0);
  240. rval = QLA_FUNCTION_TIMEOUT;
  241. }
  242. ha->flags.mbox_busy = 0;
  243. /* Clean up */
  244. ha->mcp = NULL;
  245. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  246. ql_dbg(ql_dbg_mbx, vha, 0x101a,
  247. "Checking for additional resp interrupt.\n");
  248. /* polling mode for non isp_abort commands. */
  249. qla2x00_poll(ha->rsp_q_map[0]);
  250. }
  251. if (rval == QLA_FUNCTION_TIMEOUT &&
  252. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  253. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  254. ha->flags.eeh_busy) {
  255. /* not in dpc. schedule it for dpc to take over. */
  256. ql_dbg(ql_dbg_mbx, vha, 0x101b,
  257. "Timeout, schedule isp_abort_needed.\n");
  258. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  259. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  260. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  261. if (IS_QLA82XX(ha)) {
  262. ql_dbg(ql_dbg_mbx, vha, 0x112a,
  263. "disabling pause transmit on port "
  264. "0 & 1.\n");
  265. qla82xx_wr_32(ha,
  266. QLA82XX_CRB_NIU + 0x98,
  267. CRB_NIU_XG_PAUSE_CTL_P0|
  268. CRB_NIU_XG_PAUSE_CTL_P1);
  269. }
  270. ql_log(ql_log_info, base_vha, 0x101c,
  271. "Mailbox cmd timeout occurred, cmd=0x%x, "
  272. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  273. "abort.\n", command, mcp->mb[0],
  274. ha->flags.eeh_busy);
  275. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  276. qla2xxx_wake_dpc(vha);
  277. }
  278. } else if (!abort_active) {
  279. /* call abort directly since we are in the DPC thread */
  280. ql_dbg(ql_dbg_mbx, vha, 0x101d,
  281. "Timeout, calling abort_isp.\n");
  282. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  283. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  284. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  285. if (IS_QLA82XX(ha)) {
  286. ql_dbg(ql_dbg_mbx, vha, 0x112b,
  287. "disabling pause transmit on port "
  288. "0 & 1.\n");
  289. qla82xx_wr_32(ha,
  290. QLA82XX_CRB_NIU + 0x98,
  291. CRB_NIU_XG_PAUSE_CTL_P0|
  292. CRB_NIU_XG_PAUSE_CTL_P1);
  293. }
  294. ql_log(ql_log_info, base_vha, 0x101e,
  295. "Mailbox cmd timeout occurred, cmd=0x%x, "
  296. "mb[0]=0x%x. Scheduling ISP abort ",
  297. command, mcp->mb[0]);
  298. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  299. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  300. /* Allow next mbx cmd to come in. */
  301. complete(&ha->mbx_cmd_comp);
  302. if (ha->isp_ops->abort_isp(vha)) {
  303. /* Failed. retry later. */
  304. set_bit(ISP_ABORT_NEEDED,
  305. &vha->dpc_flags);
  306. }
  307. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  308. ql_dbg(ql_dbg_mbx, vha, 0x101f,
  309. "Finished abort_isp.\n");
  310. goto mbx_done;
  311. }
  312. }
  313. }
  314. premature_exit:
  315. /* Allow next mbx cmd to come in. */
  316. complete(&ha->mbx_cmd_comp);
  317. mbx_done:
  318. if (rval) {
  319. ql_dbg(ql_dbg_mbx, base_vha, 0x1020,
  320. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
  321. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  322. } else {
  323. ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
  324. }
  325. return rval;
  326. }
  327. int
  328. qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
  329. uint32_t risc_code_size)
  330. {
  331. int rval;
  332. struct qla_hw_data *ha = vha->hw;
  333. mbx_cmd_t mc;
  334. mbx_cmd_t *mcp = &mc;
  335. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
  336. "Entered %s.\n", __func__);
  337. if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
  338. mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
  339. mcp->mb[8] = MSW(risc_addr);
  340. mcp->out_mb = MBX_8|MBX_0;
  341. } else {
  342. mcp->mb[0] = MBC_LOAD_RISC_RAM;
  343. mcp->out_mb = MBX_0;
  344. }
  345. mcp->mb[1] = LSW(risc_addr);
  346. mcp->mb[2] = MSW(req_dma);
  347. mcp->mb[3] = LSW(req_dma);
  348. mcp->mb[6] = MSW(MSD(req_dma));
  349. mcp->mb[7] = LSW(MSD(req_dma));
  350. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  351. if (IS_FWI2_CAPABLE(ha)) {
  352. mcp->mb[4] = MSW(risc_code_size);
  353. mcp->mb[5] = LSW(risc_code_size);
  354. mcp->out_mb |= MBX_5|MBX_4;
  355. } else {
  356. mcp->mb[4] = LSW(risc_code_size);
  357. mcp->out_mb |= MBX_4;
  358. }
  359. mcp->in_mb = MBX_0;
  360. mcp->tov = MBX_TOV_SECONDS;
  361. mcp->flags = 0;
  362. rval = qla2x00_mailbox_command(vha, mcp);
  363. if (rval != QLA_SUCCESS) {
  364. ql_dbg(ql_dbg_mbx, vha, 0x1023,
  365. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  366. } else {
  367. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
  368. "Done %s.\n", __func__);
  369. }
  370. return rval;
  371. }
  372. #define EXTENDED_BB_CREDITS BIT_0
  373. /*
  374. * qla2x00_execute_fw
  375. * Start adapter firmware.
  376. *
  377. * Input:
  378. * ha = adapter block pointer.
  379. * TARGET_QUEUE_LOCK must be released.
  380. * ADAPTER_STATE_LOCK must be released.
  381. *
  382. * Returns:
  383. * qla2x00 local function return status code.
  384. *
  385. * Context:
  386. * Kernel context.
  387. */
  388. int
  389. qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
  390. {
  391. int rval;
  392. struct qla_hw_data *ha = vha->hw;
  393. mbx_cmd_t mc;
  394. mbx_cmd_t *mcp = &mc;
  395. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
  396. "Entered %s.\n", __func__);
  397. mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
  398. mcp->out_mb = MBX_0;
  399. mcp->in_mb = MBX_0;
  400. if (IS_FWI2_CAPABLE(ha)) {
  401. mcp->mb[1] = MSW(risc_addr);
  402. mcp->mb[2] = LSW(risc_addr);
  403. mcp->mb[3] = 0;
  404. if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) {
  405. struct nvram_81xx *nv = ha->nvram;
  406. mcp->mb[4] = (nv->enhanced_features &
  407. EXTENDED_BB_CREDITS);
  408. } else
  409. mcp->mb[4] = 0;
  410. mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
  411. mcp->in_mb |= MBX_1;
  412. } else {
  413. mcp->mb[1] = LSW(risc_addr);
  414. mcp->out_mb |= MBX_1;
  415. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  416. mcp->mb[2] = 0;
  417. mcp->out_mb |= MBX_2;
  418. }
  419. }
  420. mcp->tov = MBX_TOV_SECONDS;
  421. mcp->flags = 0;
  422. rval = qla2x00_mailbox_command(vha, mcp);
  423. if (rval != QLA_SUCCESS) {
  424. ql_dbg(ql_dbg_mbx, vha, 0x1026,
  425. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  426. } else {
  427. if (IS_FWI2_CAPABLE(ha)) {
  428. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
  429. "Done exchanges=%x.\n", mcp->mb[1]);
  430. } else {
  431. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
  432. "Done %s.\n", __func__);
  433. }
  434. }
  435. return rval;
  436. }
  437. /*
  438. * qla2x00_get_fw_version
  439. * Get firmware version.
  440. *
  441. * Input:
  442. * ha: adapter state pointer.
  443. * major: pointer for major number.
  444. * minor: pointer for minor number.
  445. * subminor: pointer for subminor number.
  446. *
  447. * Returns:
  448. * qla2x00 local function return status code.
  449. *
  450. * Context:
  451. * Kernel context.
  452. */
  453. int
  454. qla2x00_get_fw_version(scsi_qla_host_t *vha)
  455. {
  456. int rval;
  457. mbx_cmd_t mc;
  458. mbx_cmd_t *mcp = &mc;
  459. struct qla_hw_data *ha = vha->hw;
  460. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
  461. "Entered %s.\n", __func__);
  462. mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
  463. mcp->out_mb = MBX_0;
  464. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  465. if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha))
  466. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
  467. if (IS_QLA83XX(vha->hw))
  468. mcp->in_mb |= MBX_17|MBX_16|MBX_15;
  469. mcp->flags = 0;
  470. mcp->tov = MBX_TOV_SECONDS;
  471. rval = qla2x00_mailbox_command(vha, mcp);
  472. if (rval != QLA_SUCCESS)
  473. goto failed;
  474. /* Return mailbox data. */
  475. ha->fw_major_version = mcp->mb[1];
  476. ha->fw_minor_version = mcp->mb[2];
  477. ha->fw_subminor_version = mcp->mb[3];
  478. ha->fw_attributes = mcp->mb[6];
  479. if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
  480. ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
  481. else
  482. ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
  483. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw)) {
  484. ha->mpi_version[0] = mcp->mb[10] & 0xff;
  485. ha->mpi_version[1] = mcp->mb[11] >> 8;
  486. ha->mpi_version[2] = mcp->mb[11] & 0xff;
  487. ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
  488. ha->phy_version[0] = mcp->mb[8] & 0xff;
  489. ha->phy_version[1] = mcp->mb[9] >> 8;
  490. ha->phy_version[2] = mcp->mb[9] & 0xff;
  491. }
  492. if (IS_QLA83XX(ha)) {
  493. if (mcp->mb[6] & BIT_15) {
  494. ha->fw_attributes_h = mcp->mb[15];
  495. ha->fw_attributes_ext[0] = mcp->mb[16];
  496. ha->fw_attributes_ext[1] = mcp->mb[17];
  497. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
  498. "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
  499. __func__, mcp->mb[15], mcp->mb[6]);
  500. } else
  501. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
  502. "%s: FwAttributes [Upper] invalid, MB6:%04x\n",
  503. __func__, mcp->mb[6]);
  504. }
  505. failed:
  506. if (rval != QLA_SUCCESS) {
  507. /*EMPTY*/
  508. ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
  509. } else {
  510. /*EMPTY*/
  511. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
  512. "Done %s.\n", __func__);
  513. }
  514. return rval;
  515. }
  516. /*
  517. * qla2x00_get_fw_options
  518. * Set firmware options.
  519. *
  520. * Input:
  521. * ha = adapter block pointer.
  522. * fwopt = pointer for firmware options.
  523. *
  524. * Returns:
  525. * qla2x00 local function return status code.
  526. *
  527. * Context:
  528. * Kernel context.
  529. */
  530. int
  531. qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  532. {
  533. int rval;
  534. mbx_cmd_t mc;
  535. mbx_cmd_t *mcp = &mc;
  536. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
  537. "Entered %s.\n", __func__);
  538. mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
  539. mcp->out_mb = MBX_0;
  540. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  541. mcp->tov = MBX_TOV_SECONDS;
  542. mcp->flags = 0;
  543. rval = qla2x00_mailbox_command(vha, mcp);
  544. if (rval != QLA_SUCCESS) {
  545. /*EMPTY*/
  546. ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
  547. } else {
  548. fwopts[0] = mcp->mb[0];
  549. fwopts[1] = mcp->mb[1];
  550. fwopts[2] = mcp->mb[2];
  551. fwopts[3] = mcp->mb[3];
  552. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
  553. "Done %s.\n", __func__);
  554. }
  555. return rval;
  556. }
  557. /*
  558. * qla2x00_set_fw_options
  559. * Set firmware options.
  560. *
  561. * Input:
  562. * ha = adapter block pointer.
  563. * fwopt = pointer for firmware options.
  564. *
  565. * Returns:
  566. * qla2x00 local function return status code.
  567. *
  568. * Context:
  569. * Kernel context.
  570. */
  571. int
  572. qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  573. {
  574. int rval;
  575. mbx_cmd_t mc;
  576. mbx_cmd_t *mcp = &mc;
  577. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
  578. "Entered %s.\n", __func__);
  579. mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
  580. mcp->mb[1] = fwopts[1];
  581. mcp->mb[2] = fwopts[2];
  582. mcp->mb[3] = fwopts[3];
  583. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  584. mcp->in_mb = MBX_0;
  585. if (IS_FWI2_CAPABLE(vha->hw)) {
  586. mcp->in_mb |= MBX_1;
  587. } else {
  588. mcp->mb[10] = fwopts[10];
  589. mcp->mb[11] = fwopts[11];
  590. mcp->mb[12] = 0; /* Undocumented, but used */
  591. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  592. }
  593. mcp->tov = MBX_TOV_SECONDS;
  594. mcp->flags = 0;
  595. rval = qla2x00_mailbox_command(vha, mcp);
  596. fwopts[0] = mcp->mb[0];
  597. if (rval != QLA_SUCCESS) {
  598. /*EMPTY*/
  599. ql_dbg(ql_dbg_mbx, vha, 0x1030,
  600. "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
  601. } else {
  602. /*EMPTY*/
  603. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
  604. "Done %s.\n", __func__);
  605. }
  606. return rval;
  607. }
  608. /*
  609. * qla2x00_mbx_reg_test
  610. * Mailbox register wrap test.
  611. *
  612. * Input:
  613. * ha = adapter block pointer.
  614. * TARGET_QUEUE_LOCK must be released.
  615. * ADAPTER_STATE_LOCK must be released.
  616. *
  617. * Returns:
  618. * qla2x00 local function return status code.
  619. *
  620. * Context:
  621. * Kernel context.
  622. */
  623. int
  624. qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
  625. {
  626. int rval;
  627. mbx_cmd_t mc;
  628. mbx_cmd_t *mcp = &mc;
  629. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
  630. "Entered %s.\n", __func__);
  631. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  632. mcp->mb[1] = 0xAAAA;
  633. mcp->mb[2] = 0x5555;
  634. mcp->mb[3] = 0xAA55;
  635. mcp->mb[4] = 0x55AA;
  636. mcp->mb[5] = 0xA5A5;
  637. mcp->mb[6] = 0x5A5A;
  638. mcp->mb[7] = 0x2525;
  639. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  640. mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  641. mcp->tov = MBX_TOV_SECONDS;
  642. mcp->flags = 0;
  643. rval = qla2x00_mailbox_command(vha, mcp);
  644. if (rval == QLA_SUCCESS) {
  645. if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
  646. mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
  647. rval = QLA_FUNCTION_FAILED;
  648. if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
  649. mcp->mb[7] != 0x2525)
  650. rval = QLA_FUNCTION_FAILED;
  651. }
  652. if (rval != QLA_SUCCESS) {
  653. /*EMPTY*/
  654. ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
  655. } else {
  656. /*EMPTY*/
  657. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
  658. "Done %s.\n", __func__);
  659. }
  660. return rval;
  661. }
  662. /*
  663. * qla2x00_verify_checksum
  664. * Verify firmware checksum.
  665. *
  666. * Input:
  667. * ha = adapter block pointer.
  668. * TARGET_QUEUE_LOCK must be released.
  669. * ADAPTER_STATE_LOCK must be released.
  670. *
  671. * Returns:
  672. * qla2x00 local function return status code.
  673. *
  674. * Context:
  675. * Kernel context.
  676. */
  677. int
  678. qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
  679. {
  680. int rval;
  681. mbx_cmd_t mc;
  682. mbx_cmd_t *mcp = &mc;
  683. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
  684. "Entered %s.\n", __func__);
  685. mcp->mb[0] = MBC_VERIFY_CHECKSUM;
  686. mcp->out_mb = MBX_0;
  687. mcp->in_mb = MBX_0;
  688. if (IS_FWI2_CAPABLE(vha->hw)) {
  689. mcp->mb[1] = MSW(risc_addr);
  690. mcp->mb[2] = LSW(risc_addr);
  691. mcp->out_mb |= MBX_2|MBX_1;
  692. mcp->in_mb |= MBX_2|MBX_1;
  693. } else {
  694. mcp->mb[1] = LSW(risc_addr);
  695. mcp->out_mb |= MBX_1;
  696. mcp->in_mb |= MBX_1;
  697. }
  698. mcp->tov = MBX_TOV_SECONDS;
  699. mcp->flags = 0;
  700. rval = qla2x00_mailbox_command(vha, mcp);
  701. if (rval != QLA_SUCCESS) {
  702. ql_dbg(ql_dbg_mbx, vha, 0x1036,
  703. "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
  704. (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
  705. } else {
  706. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
  707. "Done %s.\n", __func__);
  708. }
  709. return rval;
  710. }
  711. /*
  712. * qla2x00_issue_iocb
  713. * Issue IOCB using mailbox command
  714. *
  715. * Input:
  716. * ha = adapter state pointer.
  717. * buffer = buffer pointer.
  718. * phys_addr = physical address of buffer.
  719. * size = size of buffer.
  720. * TARGET_QUEUE_LOCK must be released.
  721. * ADAPTER_STATE_LOCK must be released.
  722. *
  723. * Returns:
  724. * qla2x00 local function return status code.
  725. *
  726. * Context:
  727. * Kernel context.
  728. */
  729. int
  730. qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
  731. dma_addr_t phys_addr, size_t size, uint32_t tov)
  732. {
  733. int rval;
  734. mbx_cmd_t mc;
  735. mbx_cmd_t *mcp = &mc;
  736. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
  737. "Entered %s.\n", __func__);
  738. mcp->mb[0] = MBC_IOCB_COMMAND_A64;
  739. mcp->mb[1] = 0;
  740. mcp->mb[2] = MSW(phys_addr);
  741. mcp->mb[3] = LSW(phys_addr);
  742. mcp->mb[6] = MSW(MSD(phys_addr));
  743. mcp->mb[7] = LSW(MSD(phys_addr));
  744. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  745. mcp->in_mb = MBX_2|MBX_0;
  746. mcp->tov = tov;
  747. mcp->flags = 0;
  748. rval = qla2x00_mailbox_command(vha, mcp);
  749. if (rval != QLA_SUCCESS) {
  750. /*EMPTY*/
  751. ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
  752. } else {
  753. sts_entry_t *sts_entry = (sts_entry_t *) buffer;
  754. /* Mask reserved bits. */
  755. sts_entry->entry_status &=
  756. IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
  757. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
  758. "Done %s.\n", __func__);
  759. }
  760. return rval;
  761. }
  762. int
  763. qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
  764. size_t size)
  765. {
  766. return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
  767. MBX_TOV_SECONDS);
  768. }
  769. /*
  770. * qla2x00_abort_command
  771. * Abort command aborts a specified IOCB.
  772. *
  773. * Input:
  774. * ha = adapter block pointer.
  775. * sp = SB structure pointer.
  776. *
  777. * Returns:
  778. * qla2x00 local function return status code.
  779. *
  780. * Context:
  781. * Kernel context.
  782. */
  783. int
  784. qla2x00_abort_command(srb_t *sp)
  785. {
  786. unsigned long flags = 0;
  787. int rval;
  788. uint32_t handle = 0;
  789. mbx_cmd_t mc;
  790. mbx_cmd_t *mcp = &mc;
  791. fc_port_t *fcport = sp->fcport;
  792. scsi_qla_host_t *vha = fcport->vha;
  793. struct qla_hw_data *ha = vha->hw;
  794. struct req_que *req = vha->req;
  795. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  796. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
  797. "Entered %s.\n", __func__);
  798. spin_lock_irqsave(&ha->hardware_lock, flags);
  799. for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
  800. if (req->outstanding_cmds[handle] == sp)
  801. break;
  802. }
  803. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  804. if (handle == MAX_OUTSTANDING_COMMANDS) {
  805. /* command not found */
  806. return QLA_FUNCTION_FAILED;
  807. }
  808. mcp->mb[0] = MBC_ABORT_COMMAND;
  809. if (HAS_EXTENDED_IDS(ha))
  810. mcp->mb[1] = fcport->loop_id;
  811. else
  812. mcp->mb[1] = fcport->loop_id << 8;
  813. mcp->mb[2] = (uint16_t)handle;
  814. mcp->mb[3] = (uint16_t)(handle >> 16);
  815. mcp->mb[6] = (uint16_t)cmd->device->lun;
  816. mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  817. mcp->in_mb = MBX_0;
  818. mcp->tov = MBX_TOV_SECONDS;
  819. mcp->flags = 0;
  820. rval = qla2x00_mailbox_command(vha, mcp);
  821. if (rval != QLA_SUCCESS) {
  822. ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
  823. } else {
  824. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
  825. "Done %s.\n", __func__);
  826. }
  827. return rval;
  828. }
  829. int
  830. qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  831. {
  832. int rval, rval2;
  833. mbx_cmd_t mc;
  834. mbx_cmd_t *mcp = &mc;
  835. scsi_qla_host_t *vha;
  836. struct req_que *req;
  837. struct rsp_que *rsp;
  838. l = l;
  839. vha = fcport->vha;
  840. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
  841. "Entered %s.\n", __func__);
  842. req = vha->hw->req_q_map[0];
  843. rsp = req->rsp;
  844. mcp->mb[0] = MBC_ABORT_TARGET;
  845. mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
  846. if (HAS_EXTENDED_IDS(vha->hw)) {
  847. mcp->mb[1] = fcport->loop_id;
  848. mcp->mb[10] = 0;
  849. mcp->out_mb |= MBX_10;
  850. } else {
  851. mcp->mb[1] = fcport->loop_id << 8;
  852. }
  853. mcp->mb[2] = vha->hw->loop_reset_delay;
  854. mcp->mb[9] = vha->vp_idx;
  855. mcp->in_mb = MBX_0;
  856. mcp->tov = MBX_TOV_SECONDS;
  857. mcp->flags = 0;
  858. rval = qla2x00_mailbox_command(vha, mcp);
  859. if (rval != QLA_SUCCESS) {
  860. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
  861. "Failed=%x.\n", rval);
  862. }
  863. /* Issue marker IOCB. */
  864. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
  865. MK_SYNC_ID);
  866. if (rval2 != QLA_SUCCESS) {
  867. ql_dbg(ql_dbg_mbx, vha, 0x1040,
  868. "Failed to issue marker IOCB (%x).\n", rval2);
  869. } else {
  870. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
  871. "Done %s.\n", __func__);
  872. }
  873. return rval;
  874. }
  875. int
  876. qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  877. {
  878. int rval, rval2;
  879. mbx_cmd_t mc;
  880. mbx_cmd_t *mcp = &mc;
  881. scsi_qla_host_t *vha;
  882. struct req_que *req;
  883. struct rsp_que *rsp;
  884. vha = fcport->vha;
  885. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
  886. "Entered %s.\n", __func__);
  887. req = vha->hw->req_q_map[0];
  888. rsp = req->rsp;
  889. mcp->mb[0] = MBC_LUN_RESET;
  890. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  891. if (HAS_EXTENDED_IDS(vha->hw))
  892. mcp->mb[1] = fcport->loop_id;
  893. else
  894. mcp->mb[1] = fcport->loop_id << 8;
  895. mcp->mb[2] = l;
  896. mcp->mb[3] = 0;
  897. mcp->mb[9] = vha->vp_idx;
  898. mcp->in_mb = MBX_0;
  899. mcp->tov = MBX_TOV_SECONDS;
  900. mcp->flags = 0;
  901. rval = qla2x00_mailbox_command(vha, mcp);
  902. if (rval != QLA_SUCCESS) {
  903. ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
  904. }
  905. /* Issue marker IOCB. */
  906. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  907. MK_SYNC_ID_LUN);
  908. if (rval2 != QLA_SUCCESS) {
  909. ql_dbg(ql_dbg_mbx, vha, 0x1044,
  910. "Failed to issue marker IOCB (%x).\n", rval2);
  911. } else {
  912. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
  913. "Done %s.\n", __func__);
  914. }
  915. return rval;
  916. }
  917. /*
  918. * qla2x00_get_adapter_id
  919. * Get adapter ID and topology.
  920. *
  921. * Input:
  922. * ha = adapter block pointer.
  923. * id = pointer for loop ID.
  924. * al_pa = pointer for AL_PA.
  925. * area = pointer for area.
  926. * domain = pointer for domain.
  927. * top = pointer for topology.
  928. * TARGET_QUEUE_LOCK must be released.
  929. * ADAPTER_STATE_LOCK must be released.
  930. *
  931. * Returns:
  932. * qla2x00 local function return status code.
  933. *
  934. * Context:
  935. * Kernel context.
  936. */
  937. int
  938. qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
  939. uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
  940. {
  941. int rval;
  942. mbx_cmd_t mc;
  943. mbx_cmd_t *mcp = &mc;
  944. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
  945. "Entered %s.\n", __func__);
  946. mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
  947. mcp->mb[9] = vha->vp_idx;
  948. mcp->out_mb = MBX_9|MBX_0;
  949. mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  950. if (IS_CNA_CAPABLE(vha->hw))
  951. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
  952. mcp->tov = MBX_TOV_SECONDS;
  953. mcp->flags = 0;
  954. rval = qla2x00_mailbox_command(vha, mcp);
  955. if (mcp->mb[0] == MBS_COMMAND_ERROR)
  956. rval = QLA_COMMAND_ERROR;
  957. else if (mcp->mb[0] == MBS_INVALID_COMMAND)
  958. rval = QLA_INVALID_COMMAND;
  959. /* Return data. */
  960. *id = mcp->mb[1];
  961. *al_pa = LSB(mcp->mb[2]);
  962. *area = MSB(mcp->mb[2]);
  963. *domain = LSB(mcp->mb[3]);
  964. *top = mcp->mb[6];
  965. *sw_cap = mcp->mb[7];
  966. if (rval != QLA_SUCCESS) {
  967. /*EMPTY*/
  968. ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
  969. } else {
  970. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
  971. "Done %s.\n", __func__);
  972. if (IS_CNA_CAPABLE(vha->hw)) {
  973. vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
  974. vha->fcoe_fcf_idx = mcp->mb[10];
  975. vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
  976. vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
  977. vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
  978. vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
  979. vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
  980. vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
  981. }
  982. }
  983. return rval;
  984. }
  985. /*
  986. * qla2x00_get_retry_cnt
  987. * Get current firmware login retry count and delay.
  988. *
  989. * Input:
  990. * ha = adapter block pointer.
  991. * retry_cnt = pointer to login retry count.
  992. * tov = pointer to login timeout value.
  993. *
  994. * Returns:
  995. * qla2x00 local function return status code.
  996. *
  997. * Context:
  998. * Kernel context.
  999. */
  1000. int
  1001. qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
  1002. uint16_t *r_a_tov)
  1003. {
  1004. int rval;
  1005. uint16_t ratov;
  1006. mbx_cmd_t mc;
  1007. mbx_cmd_t *mcp = &mc;
  1008. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
  1009. "Entered %s.\n", __func__);
  1010. mcp->mb[0] = MBC_GET_RETRY_COUNT;
  1011. mcp->out_mb = MBX_0;
  1012. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1013. mcp->tov = MBX_TOV_SECONDS;
  1014. mcp->flags = 0;
  1015. rval = qla2x00_mailbox_command(vha, mcp);
  1016. if (rval != QLA_SUCCESS) {
  1017. /*EMPTY*/
  1018. ql_dbg(ql_dbg_mbx, vha, 0x104a,
  1019. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1020. } else {
  1021. /* Convert returned data and check our values. */
  1022. *r_a_tov = mcp->mb[3] / 2;
  1023. ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
  1024. if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
  1025. /* Update to the larger values */
  1026. *retry_cnt = (uint8_t)mcp->mb[1];
  1027. *tov = ratov;
  1028. }
  1029. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
  1030. "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
  1031. }
  1032. return rval;
  1033. }
  1034. /*
  1035. * qla2x00_init_firmware
  1036. * Initialize adapter firmware.
  1037. *
  1038. * Input:
  1039. * ha = adapter block pointer.
  1040. * dptr = Initialization control block pointer.
  1041. * size = size of initialization control block.
  1042. * TARGET_QUEUE_LOCK must be released.
  1043. * ADAPTER_STATE_LOCK must be released.
  1044. *
  1045. * Returns:
  1046. * qla2x00 local function return status code.
  1047. *
  1048. * Context:
  1049. * Kernel context.
  1050. */
  1051. int
  1052. qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  1053. {
  1054. int rval;
  1055. mbx_cmd_t mc;
  1056. mbx_cmd_t *mcp = &mc;
  1057. struct qla_hw_data *ha = vha->hw;
  1058. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
  1059. "Entered %s.\n", __func__);
  1060. if (IS_QLA82XX(ha) && ql2xdbwr)
  1061. qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
  1062. (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
  1063. if (ha->flags.npiv_supported)
  1064. mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
  1065. else
  1066. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  1067. mcp->mb[1] = 0;
  1068. mcp->mb[2] = MSW(ha->init_cb_dma);
  1069. mcp->mb[3] = LSW(ha->init_cb_dma);
  1070. mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
  1071. mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
  1072. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1073. if ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) && ha->ex_init_cb->ex_version) {
  1074. mcp->mb[1] = BIT_0;
  1075. mcp->mb[10] = MSW(ha->ex_init_cb_dma);
  1076. mcp->mb[11] = LSW(ha->ex_init_cb_dma);
  1077. mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
  1078. mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
  1079. mcp->mb[14] = sizeof(*ha->ex_init_cb);
  1080. mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
  1081. }
  1082. /* 1 and 2 should normally be captured. */
  1083. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  1084. if (IS_QLA83XX(ha))
  1085. /* mb3 is additional info about the installed SFP. */
  1086. mcp->in_mb |= MBX_3;
  1087. mcp->buf_size = size;
  1088. mcp->flags = MBX_DMA_OUT;
  1089. mcp->tov = MBX_TOV_SECONDS;
  1090. rval = qla2x00_mailbox_command(vha, mcp);
  1091. if (rval != QLA_SUCCESS) {
  1092. /*EMPTY*/
  1093. ql_dbg(ql_dbg_mbx, vha, 0x104d,
  1094. "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
  1095. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
  1096. } else {
  1097. /*EMPTY*/
  1098. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
  1099. "Done %s.\n", __func__);
  1100. }
  1101. return rval;
  1102. }
  1103. /*
  1104. * qla2x00_get_port_database
  1105. * Issue normal/enhanced get port database mailbox command
  1106. * and copy device name as necessary.
  1107. *
  1108. * Input:
  1109. * ha = adapter state pointer.
  1110. * dev = structure pointer.
  1111. * opt = enhanced cmd option byte.
  1112. *
  1113. * Returns:
  1114. * qla2x00 local function return status code.
  1115. *
  1116. * Context:
  1117. * Kernel context.
  1118. */
  1119. int
  1120. qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
  1121. {
  1122. int rval;
  1123. mbx_cmd_t mc;
  1124. mbx_cmd_t *mcp = &mc;
  1125. port_database_t *pd;
  1126. struct port_database_24xx *pd24;
  1127. dma_addr_t pd_dma;
  1128. struct qla_hw_data *ha = vha->hw;
  1129. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
  1130. "Entered %s.\n", __func__);
  1131. pd24 = NULL;
  1132. pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
  1133. if (pd == NULL) {
  1134. ql_log(ql_log_warn, vha, 0x1050,
  1135. "Failed to allocate port database structure.\n");
  1136. return QLA_MEMORY_ALLOC_FAILED;
  1137. }
  1138. memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
  1139. mcp->mb[0] = MBC_GET_PORT_DATABASE;
  1140. if (opt != 0 && !IS_FWI2_CAPABLE(ha))
  1141. mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
  1142. mcp->mb[2] = MSW(pd_dma);
  1143. mcp->mb[3] = LSW(pd_dma);
  1144. mcp->mb[6] = MSW(MSD(pd_dma));
  1145. mcp->mb[7] = LSW(MSD(pd_dma));
  1146. mcp->mb[9] = vha->vp_idx;
  1147. mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1148. mcp->in_mb = MBX_0;
  1149. if (IS_FWI2_CAPABLE(ha)) {
  1150. mcp->mb[1] = fcport->loop_id;
  1151. mcp->mb[10] = opt;
  1152. mcp->out_mb |= MBX_10|MBX_1;
  1153. mcp->in_mb |= MBX_1;
  1154. } else if (HAS_EXTENDED_IDS(ha)) {
  1155. mcp->mb[1] = fcport->loop_id;
  1156. mcp->mb[10] = opt;
  1157. mcp->out_mb |= MBX_10|MBX_1;
  1158. } else {
  1159. mcp->mb[1] = fcport->loop_id << 8 | opt;
  1160. mcp->out_mb |= MBX_1;
  1161. }
  1162. mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
  1163. PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
  1164. mcp->flags = MBX_DMA_IN;
  1165. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1166. rval = qla2x00_mailbox_command(vha, mcp);
  1167. if (rval != QLA_SUCCESS)
  1168. goto gpd_error_out;
  1169. if (IS_FWI2_CAPABLE(ha)) {
  1170. uint64_t zero = 0;
  1171. pd24 = (struct port_database_24xx *) pd;
  1172. /* Check for logged in state. */
  1173. if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
  1174. pd24->last_login_state != PDS_PRLI_COMPLETE) {
  1175. ql_dbg(ql_dbg_mbx, vha, 0x1051,
  1176. "Unable to verify login-state (%x/%x) for "
  1177. "loop_id %x.\n", pd24->current_login_state,
  1178. pd24->last_login_state, fcport->loop_id);
  1179. rval = QLA_FUNCTION_FAILED;
  1180. goto gpd_error_out;
  1181. }
  1182. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1183. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1184. memcmp(fcport->port_name, pd24->port_name, 8))) {
  1185. /* We lost the device mid way. */
  1186. rval = QLA_NOT_LOGGED_IN;
  1187. goto gpd_error_out;
  1188. }
  1189. /* Names are little-endian. */
  1190. memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
  1191. memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
  1192. /* Get port_id of device. */
  1193. fcport->d_id.b.domain = pd24->port_id[0];
  1194. fcport->d_id.b.area = pd24->port_id[1];
  1195. fcport->d_id.b.al_pa = pd24->port_id[2];
  1196. fcport->d_id.b.rsvd_1 = 0;
  1197. /* If not target must be initiator or unknown type. */
  1198. if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
  1199. fcport->port_type = FCT_INITIATOR;
  1200. else
  1201. fcport->port_type = FCT_TARGET;
  1202. } else {
  1203. uint64_t zero = 0;
  1204. /* Check for logged in state. */
  1205. if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
  1206. pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
  1207. ql_dbg(ql_dbg_mbx, vha, 0x100a,
  1208. "Unable to verify login-state (%x/%x) - "
  1209. "portid=%02x%02x%02x.\n", pd->master_state,
  1210. pd->slave_state, fcport->d_id.b.domain,
  1211. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  1212. rval = QLA_FUNCTION_FAILED;
  1213. goto gpd_error_out;
  1214. }
  1215. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1216. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1217. memcmp(fcport->port_name, pd->port_name, 8))) {
  1218. /* We lost the device mid way. */
  1219. rval = QLA_NOT_LOGGED_IN;
  1220. goto gpd_error_out;
  1221. }
  1222. /* Names are little-endian. */
  1223. memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
  1224. memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
  1225. /* Get port_id of device. */
  1226. fcport->d_id.b.domain = pd->port_id[0];
  1227. fcport->d_id.b.area = pd->port_id[3];
  1228. fcport->d_id.b.al_pa = pd->port_id[2];
  1229. fcport->d_id.b.rsvd_1 = 0;
  1230. /* If not target must be initiator or unknown type. */
  1231. if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
  1232. fcport->port_type = FCT_INITIATOR;
  1233. else
  1234. fcport->port_type = FCT_TARGET;
  1235. /* Passback COS information. */
  1236. fcport->supported_classes = (pd->options & BIT_4) ?
  1237. FC_COS_CLASS2: FC_COS_CLASS3;
  1238. }
  1239. gpd_error_out:
  1240. dma_pool_free(ha->s_dma_pool, pd, pd_dma);
  1241. if (rval != QLA_SUCCESS) {
  1242. ql_dbg(ql_dbg_mbx, vha, 0x1052,
  1243. "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
  1244. mcp->mb[0], mcp->mb[1]);
  1245. } else {
  1246. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
  1247. "Done %s.\n", __func__);
  1248. }
  1249. return rval;
  1250. }
  1251. /*
  1252. * qla2x00_get_firmware_state
  1253. * Get adapter firmware state.
  1254. *
  1255. * Input:
  1256. * ha = adapter block pointer.
  1257. * dptr = pointer for firmware state.
  1258. * TARGET_QUEUE_LOCK must be released.
  1259. * ADAPTER_STATE_LOCK must be released.
  1260. *
  1261. * Returns:
  1262. * qla2x00 local function return status code.
  1263. *
  1264. * Context:
  1265. * Kernel context.
  1266. */
  1267. int
  1268. qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
  1269. {
  1270. int rval;
  1271. mbx_cmd_t mc;
  1272. mbx_cmd_t *mcp = &mc;
  1273. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
  1274. "Entered %s.\n", __func__);
  1275. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  1276. mcp->out_mb = MBX_0;
  1277. if (IS_FWI2_CAPABLE(vha->hw))
  1278. mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  1279. else
  1280. mcp->in_mb = MBX_1|MBX_0;
  1281. mcp->tov = MBX_TOV_SECONDS;
  1282. mcp->flags = 0;
  1283. rval = qla2x00_mailbox_command(vha, mcp);
  1284. /* Return firmware states. */
  1285. states[0] = mcp->mb[1];
  1286. if (IS_FWI2_CAPABLE(vha->hw)) {
  1287. states[1] = mcp->mb[2];
  1288. states[2] = mcp->mb[3];
  1289. states[3] = mcp->mb[4];
  1290. states[4] = mcp->mb[5];
  1291. }
  1292. if (rval != QLA_SUCCESS) {
  1293. /*EMPTY*/
  1294. ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
  1295. } else {
  1296. /*EMPTY*/
  1297. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
  1298. "Done %s.\n", __func__);
  1299. }
  1300. return rval;
  1301. }
  1302. /*
  1303. * qla2x00_get_port_name
  1304. * Issue get port name mailbox command.
  1305. * Returned name is in big endian format.
  1306. *
  1307. * Input:
  1308. * ha = adapter block pointer.
  1309. * loop_id = loop ID of device.
  1310. * name = pointer for name.
  1311. * TARGET_QUEUE_LOCK must be released.
  1312. * ADAPTER_STATE_LOCK must be released.
  1313. *
  1314. * Returns:
  1315. * qla2x00 local function return status code.
  1316. *
  1317. * Context:
  1318. * Kernel context.
  1319. */
  1320. int
  1321. qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
  1322. uint8_t opt)
  1323. {
  1324. int rval;
  1325. mbx_cmd_t mc;
  1326. mbx_cmd_t *mcp = &mc;
  1327. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
  1328. "Entered %s.\n", __func__);
  1329. mcp->mb[0] = MBC_GET_PORT_NAME;
  1330. mcp->mb[9] = vha->vp_idx;
  1331. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  1332. if (HAS_EXTENDED_IDS(vha->hw)) {
  1333. mcp->mb[1] = loop_id;
  1334. mcp->mb[10] = opt;
  1335. mcp->out_mb |= MBX_10;
  1336. } else {
  1337. mcp->mb[1] = loop_id << 8 | opt;
  1338. }
  1339. mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1340. mcp->tov = MBX_TOV_SECONDS;
  1341. mcp->flags = 0;
  1342. rval = qla2x00_mailbox_command(vha, mcp);
  1343. if (rval != QLA_SUCCESS) {
  1344. /*EMPTY*/
  1345. ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
  1346. } else {
  1347. if (name != NULL) {
  1348. /* This function returns name in big endian. */
  1349. name[0] = MSB(mcp->mb[2]);
  1350. name[1] = LSB(mcp->mb[2]);
  1351. name[2] = MSB(mcp->mb[3]);
  1352. name[3] = LSB(mcp->mb[3]);
  1353. name[4] = MSB(mcp->mb[6]);
  1354. name[5] = LSB(mcp->mb[6]);
  1355. name[6] = MSB(mcp->mb[7]);
  1356. name[7] = LSB(mcp->mb[7]);
  1357. }
  1358. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
  1359. "Done %s.\n", __func__);
  1360. }
  1361. return rval;
  1362. }
  1363. /*
  1364. * qla2x00_lip_reset
  1365. * Issue LIP reset mailbox command.
  1366. *
  1367. * Input:
  1368. * ha = adapter block pointer.
  1369. * TARGET_QUEUE_LOCK must be released.
  1370. * ADAPTER_STATE_LOCK must be released.
  1371. *
  1372. * Returns:
  1373. * qla2x00 local function return status code.
  1374. *
  1375. * Context:
  1376. * Kernel context.
  1377. */
  1378. int
  1379. qla2x00_lip_reset(scsi_qla_host_t *vha)
  1380. {
  1381. int rval;
  1382. mbx_cmd_t mc;
  1383. mbx_cmd_t *mcp = &mc;
  1384. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
  1385. "Entered %s.\n", __func__);
  1386. if (IS_CNA_CAPABLE(vha->hw)) {
  1387. /* Logout across all FCFs. */
  1388. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1389. mcp->mb[1] = BIT_1;
  1390. mcp->mb[2] = 0;
  1391. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1392. } else if (IS_FWI2_CAPABLE(vha->hw)) {
  1393. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1394. mcp->mb[1] = BIT_6;
  1395. mcp->mb[2] = 0;
  1396. mcp->mb[3] = vha->hw->loop_reset_delay;
  1397. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1398. } else {
  1399. mcp->mb[0] = MBC_LIP_RESET;
  1400. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1401. if (HAS_EXTENDED_IDS(vha->hw)) {
  1402. mcp->mb[1] = 0x00ff;
  1403. mcp->mb[10] = 0;
  1404. mcp->out_mb |= MBX_10;
  1405. } else {
  1406. mcp->mb[1] = 0xff00;
  1407. }
  1408. mcp->mb[2] = vha->hw->loop_reset_delay;
  1409. mcp->mb[3] = 0;
  1410. }
  1411. mcp->in_mb = MBX_0;
  1412. mcp->tov = MBX_TOV_SECONDS;
  1413. mcp->flags = 0;
  1414. rval = qla2x00_mailbox_command(vha, mcp);
  1415. if (rval != QLA_SUCCESS) {
  1416. /*EMPTY*/
  1417. ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
  1418. } else {
  1419. /*EMPTY*/
  1420. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
  1421. "Done %s.\n", __func__);
  1422. }
  1423. return rval;
  1424. }
  1425. /*
  1426. * qla2x00_send_sns
  1427. * Send SNS command.
  1428. *
  1429. * Input:
  1430. * ha = adapter block pointer.
  1431. * sns = pointer for command.
  1432. * cmd_size = command size.
  1433. * buf_size = response/command size.
  1434. * TARGET_QUEUE_LOCK must be released.
  1435. * ADAPTER_STATE_LOCK must be released.
  1436. *
  1437. * Returns:
  1438. * qla2x00 local function return status code.
  1439. *
  1440. * Context:
  1441. * Kernel context.
  1442. */
  1443. int
  1444. qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
  1445. uint16_t cmd_size, size_t buf_size)
  1446. {
  1447. int rval;
  1448. mbx_cmd_t mc;
  1449. mbx_cmd_t *mcp = &mc;
  1450. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
  1451. "Entered %s.\n", __func__);
  1452. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
  1453. "Retry cnt=%d ratov=%d total tov=%d.\n",
  1454. vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
  1455. mcp->mb[0] = MBC_SEND_SNS_COMMAND;
  1456. mcp->mb[1] = cmd_size;
  1457. mcp->mb[2] = MSW(sns_phys_address);
  1458. mcp->mb[3] = LSW(sns_phys_address);
  1459. mcp->mb[6] = MSW(MSD(sns_phys_address));
  1460. mcp->mb[7] = LSW(MSD(sns_phys_address));
  1461. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1462. mcp->in_mb = MBX_0|MBX_1;
  1463. mcp->buf_size = buf_size;
  1464. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
  1465. mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
  1466. rval = qla2x00_mailbox_command(vha, mcp);
  1467. if (rval != QLA_SUCCESS) {
  1468. /*EMPTY*/
  1469. ql_dbg(ql_dbg_mbx, vha, 0x105f,
  1470. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  1471. rval, mcp->mb[0], mcp->mb[1]);
  1472. } else {
  1473. /*EMPTY*/
  1474. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
  1475. "Done %s.\n", __func__);
  1476. }
  1477. return rval;
  1478. }
  1479. int
  1480. qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1481. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1482. {
  1483. int rval;
  1484. struct logio_entry_24xx *lg;
  1485. dma_addr_t lg_dma;
  1486. uint32_t iop[2];
  1487. struct qla_hw_data *ha = vha->hw;
  1488. struct req_que *req;
  1489. struct rsp_que *rsp;
  1490. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
  1491. "Entered %s.\n", __func__);
  1492. if (ha->flags.cpu_affinity_enabled)
  1493. req = ha->req_q_map[0];
  1494. else
  1495. req = vha->req;
  1496. rsp = req->rsp;
  1497. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1498. if (lg == NULL) {
  1499. ql_log(ql_log_warn, vha, 0x1062,
  1500. "Failed to allocate login IOCB.\n");
  1501. return QLA_MEMORY_ALLOC_FAILED;
  1502. }
  1503. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1504. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1505. lg->entry_count = 1;
  1506. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1507. lg->nport_handle = cpu_to_le16(loop_id);
  1508. lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
  1509. if (opt & BIT_0)
  1510. lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
  1511. if (opt & BIT_1)
  1512. lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
  1513. lg->port_id[0] = al_pa;
  1514. lg->port_id[1] = area;
  1515. lg->port_id[2] = domain;
  1516. lg->vp_index = vha->vp_idx;
  1517. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1518. (ha->r_a_tov / 10 * 2) + 2);
  1519. if (rval != QLA_SUCCESS) {
  1520. ql_dbg(ql_dbg_mbx, vha, 0x1063,
  1521. "Failed to issue login IOCB (%x).\n", rval);
  1522. } else if (lg->entry_status != 0) {
  1523. ql_dbg(ql_dbg_mbx, vha, 0x1064,
  1524. "Failed to complete IOCB -- error status (%x).\n",
  1525. lg->entry_status);
  1526. rval = QLA_FUNCTION_FAILED;
  1527. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1528. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1529. iop[1] = le32_to_cpu(lg->io_parameter[1]);
  1530. ql_dbg(ql_dbg_mbx, vha, 0x1065,
  1531. "Failed to complete IOCB -- completion status (%x) "
  1532. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1533. iop[0], iop[1]);
  1534. switch (iop[0]) {
  1535. case LSC_SCODE_PORTID_USED:
  1536. mb[0] = MBS_PORT_ID_USED;
  1537. mb[1] = LSW(iop[1]);
  1538. break;
  1539. case LSC_SCODE_NPORT_USED:
  1540. mb[0] = MBS_LOOP_ID_USED;
  1541. break;
  1542. case LSC_SCODE_NOLINK:
  1543. case LSC_SCODE_NOIOCB:
  1544. case LSC_SCODE_NOXCB:
  1545. case LSC_SCODE_CMD_FAILED:
  1546. case LSC_SCODE_NOFABRIC:
  1547. case LSC_SCODE_FW_NOT_READY:
  1548. case LSC_SCODE_NOT_LOGGED_IN:
  1549. case LSC_SCODE_NOPCB:
  1550. case LSC_SCODE_ELS_REJECT:
  1551. case LSC_SCODE_CMD_PARAM_ERR:
  1552. case LSC_SCODE_NONPORT:
  1553. case LSC_SCODE_LOGGED_IN:
  1554. case LSC_SCODE_NOFLOGI_ACC:
  1555. default:
  1556. mb[0] = MBS_COMMAND_ERROR;
  1557. break;
  1558. }
  1559. } else {
  1560. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
  1561. "Done %s.\n", __func__);
  1562. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1563. mb[0] = MBS_COMMAND_COMPLETE;
  1564. mb[1] = 0;
  1565. if (iop[0] & BIT_4) {
  1566. if (iop[0] & BIT_8)
  1567. mb[1] |= BIT_1;
  1568. } else
  1569. mb[1] = BIT_0;
  1570. /* Passback COS information. */
  1571. mb[10] = 0;
  1572. if (lg->io_parameter[7] || lg->io_parameter[8])
  1573. mb[10] |= BIT_0; /* Class 2. */
  1574. if (lg->io_parameter[9] || lg->io_parameter[10])
  1575. mb[10] |= BIT_1; /* Class 3. */
  1576. }
  1577. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1578. return rval;
  1579. }
  1580. /*
  1581. * qla2x00_login_fabric
  1582. * Issue login fabric port mailbox command.
  1583. *
  1584. * Input:
  1585. * ha = adapter block pointer.
  1586. * loop_id = device loop ID.
  1587. * domain = device domain.
  1588. * area = device area.
  1589. * al_pa = device AL_PA.
  1590. * status = pointer for return status.
  1591. * opt = command options.
  1592. * TARGET_QUEUE_LOCK must be released.
  1593. * ADAPTER_STATE_LOCK must be released.
  1594. *
  1595. * Returns:
  1596. * qla2x00 local function return status code.
  1597. *
  1598. * Context:
  1599. * Kernel context.
  1600. */
  1601. int
  1602. qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1603. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1604. {
  1605. int rval;
  1606. mbx_cmd_t mc;
  1607. mbx_cmd_t *mcp = &mc;
  1608. struct qla_hw_data *ha = vha->hw;
  1609. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
  1610. "Entered %s.\n", __func__);
  1611. mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
  1612. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1613. if (HAS_EXTENDED_IDS(ha)) {
  1614. mcp->mb[1] = loop_id;
  1615. mcp->mb[10] = opt;
  1616. mcp->out_mb |= MBX_10;
  1617. } else {
  1618. mcp->mb[1] = (loop_id << 8) | opt;
  1619. }
  1620. mcp->mb[2] = domain;
  1621. mcp->mb[3] = area << 8 | al_pa;
  1622. mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
  1623. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1624. mcp->flags = 0;
  1625. rval = qla2x00_mailbox_command(vha, mcp);
  1626. /* Return mailbox statuses. */
  1627. if (mb != NULL) {
  1628. mb[0] = mcp->mb[0];
  1629. mb[1] = mcp->mb[1];
  1630. mb[2] = mcp->mb[2];
  1631. mb[6] = mcp->mb[6];
  1632. mb[7] = mcp->mb[7];
  1633. /* COS retrieved from Get-Port-Database mailbox command. */
  1634. mb[10] = 0;
  1635. }
  1636. if (rval != QLA_SUCCESS) {
  1637. /* RLU tmp code: need to change main mailbox_command function to
  1638. * return ok even when the mailbox completion value is not
  1639. * SUCCESS. The caller needs to be responsible to interpret
  1640. * the return values of this mailbox command if we're not
  1641. * to change too much of the existing code.
  1642. */
  1643. if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
  1644. mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
  1645. mcp->mb[0] == 0x4006)
  1646. rval = QLA_SUCCESS;
  1647. /*EMPTY*/
  1648. ql_dbg(ql_dbg_mbx, vha, 0x1068,
  1649. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  1650. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  1651. } else {
  1652. /*EMPTY*/
  1653. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
  1654. "Done %s.\n", __func__);
  1655. }
  1656. return rval;
  1657. }
  1658. /*
  1659. * qla2x00_login_local_device
  1660. * Issue login loop port mailbox command.
  1661. *
  1662. * Input:
  1663. * ha = adapter block pointer.
  1664. * loop_id = device loop ID.
  1665. * opt = command options.
  1666. *
  1667. * Returns:
  1668. * Return status code.
  1669. *
  1670. * Context:
  1671. * Kernel context.
  1672. *
  1673. */
  1674. int
  1675. qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
  1676. uint16_t *mb_ret, uint8_t opt)
  1677. {
  1678. int rval;
  1679. mbx_cmd_t mc;
  1680. mbx_cmd_t *mcp = &mc;
  1681. struct qla_hw_data *ha = vha->hw;
  1682. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
  1683. "Entered %s.\n", __func__);
  1684. if (IS_FWI2_CAPABLE(ha))
  1685. return qla24xx_login_fabric(vha, fcport->loop_id,
  1686. fcport->d_id.b.domain, fcport->d_id.b.area,
  1687. fcport->d_id.b.al_pa, mb_ret, opt);
  1688. mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
  1689. if (HAS_EXTENDED_IDS(ha))
  1690. mcp->mb[1] = fcport->loop_id;
  1691. else
  1692. mcp->mb[1] = fcport->loop_id << 8;
  1693. mcp->mb[2] = opt;
  1694. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1695. mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
  1696. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1697. mcp->flags = 0;
  1698. rval = qla2x00_mailbox_command(vha, mcp);
  1699. /* Return mailbox statuses. */
  1700. if (mb_ret != NULL) {
  1701. mb_ret[0] = mcp->mb[0];
  1702. mb_ret[1] = mcp->mb[1];
  1703. mb_ret[6] = mcp->mb[6];
  1704. mb_ret[7] = mcp->mb[7];
  1705. }
  1706. if (rval != QLA_SUCCESS) {
  1707. /* AV tmp code: need to change main mailbox_command function to
  1708. * return ok even when the mailbox completion value is not
  1709. * SUCCESS. The caller needs to be responsible to interpret
  1710. * the return values of this mailbox command if we're not
  1711. * to change too much of the existing code.
  1712. */
  1713. if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
  1714. rval = QLA_SUCCESS;
  1715. ql_dbg(ql_dbg_mbx, vha, 0x106b,
  1716. "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
  1717. rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
  1718. } else {
  1719. /*EMPTY*/
  1720. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
  1721. "Done %s.\n", __func__);
  1722. }
  1723. return (rval);
  1724. }
  1725. int
  1726. qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1727. uint8_t area, uint8_t al_pa)
  1728. {
  1729. int rval;
  1730. struct logio_entry_24xx *lg;
  1731. dma_addr_t lg_dma;
  1732. struct qla_hw_data *ha = vha->hw;
  1733. struct req_que *req;
  1734. struct rsp_que *rsp;
  1735. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
  1736. "Entered %s.\n", __func__);
  1737. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1738. if (lg == NULL) {
  1739. ql_log(ql_log_warn, vha, 0x106e,
  1740. "Failed to allocate logout IOCB.\n");
  1741. return QLA_MEMORY_ALLOC_FAILED;
  1742. }
  1743. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1744. if (ql2xmaxqueues > 1)
  1745. req = ha->req_q_map[0];
  1746. else
  1747. req = vha->req;
  1748. rsp = req->rsp;
  1749. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1750. lg->entry_count = 1;
  1751. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1752. lg->nport_handle = cpu_to_le16(loop_id);
  1753. lg->control_flags =
  1754. __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
  1755. LCF_FREE_NPORT);
  1756. lg->port_id[0] = al_pa;
  1757. lg->port_id[1] = area;
  1758. lg->port_id[2] = domain;
  1759. lg->vp_index = vha->vp_idx;
  1760. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1761. (ha->r_a_tov / 10 * 2) + 2);
  1762. if (rval != QLA_SUCCESS) {
  1763. ql_dbg(ql_dbg_mbx, vha, 0x106f,
  1764. "Failed to issue logout IOCB (%x).\n", rval);
  1765. } else if (lg->entry_status != 0) {
  1766. ql_dbg(ql_dbg_mbx, vha, 0x1070,
  1767. "Failed to complete IOCB -- error status (%x).\n",
  1768. lg->entry_status);
  1769. rval = QLA_FUNCTION_FAILED;
  1770. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1771. ql_dbg(ql_dbg_mbx, vha, 0x1071,
  1772. "Failed to complete IOCB -- completion status (%x) "
  1773. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1774. le32_to_cpu(lg->io_parameter[0]),
  1775. le32_to_cpu(lg->io_parameter[1]));
  1776. } else {
  1777. /*EMPTY*/
  1778. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
  1779. "Done %s.\n", __func__);
  1780. }
  1781. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1782. return rval;
  1783. }
  1784. /*
  1785. * qla2x00_fabric_logout
  1786. * Issue logout fabric port mailbox command.
  1787. *
  1788. * Input:
  1789. * ha = adapter block pointer.
  1790. * loop_id = device loop ID.
  1791. * TARGET_QUEUE_LOCK must be released.
  1792. * ADAPTER_STATE_LOCK must be released.
  1793. *
  1794. * Returns:
  1795. * qla2x00 local function return status code.
  1796. *
  1797. * Context:
  1798. * Kernel context.
  1799. */
  1800. int
  1801. qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1802. uint8_t area, uint8_t al_pa)
  1803. {
  1804. int rval;
  1805. mbx_cmd_t mc;
  1806. mbx_cmd_t *mcp = &mc;
  1807. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
  1808. "Entered %s.\n", __func__);
  1809. mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
  1810. mcp->out_mb = MBX_1|MBX_0;
  1811. if (HAS_EXTENDED_IDS(vha->hw)) {
  1812. mcp->mb[1] = loop_id;
  1813. mcp->mb[10] = 0;
  1814. mcp->out_mb |= MBX_10;
  1815. } else {
  1816. mcp->mb[1] = loop_id << 8;
  1817. }
  1818. mcp->in_mb = MBX_1|MBX_0;
  1819. mcp->tov = MBX_TOV_SECONDS;
  1820. mcp->flags = 0;
  1821. rval = qla2x00_mailbox_command(vha, mcp);
  1822. if (rval != QLA_SUCCESS) {
  1823. /*EMPTY*/
  1824. ql_dbg(ql_dbg_mbx, vha, 0x1074,
  1825. "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
  1826. } else {
  1827. /*EMPTY*/
  1828. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
  1829. "Done %s.\n", __func__);
  1830. }
  1831. return rval;
  1832. }
  1833. /*
  1834. * qla2x00_full_login_lip
  1835. * Issue full login LIP mailbox command.
  1836. *
  1837. * Input:
  1838. * ha = adapter block pointer.
  1839. * TARGET_QUEUE_LOCK must be released.
  1840. * ADAPTER_STATE_LOCK must be released.
  1841. *
  1842. * Returns:
  1843. * qla2x00 local function return status code.
  1844. *
  1845. * Context:
  1846. * Kernel context.
  1847. */
  1848. int
  1849. qla2x00_full_login_lip(scsi_qla_host_t *vha)
  1850. {
  1851. int rval;
  1852. mbx_cmd_t mc;
  1853. mbx_cmd_t *mcp = &mc;
  1854. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
  1855. "Entered %s.\n", __func__);
  1856. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1857. mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
  1858. mcp->mb[2] = 0;
  1859. mcp->mb[3] = 0;
  1860. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1861. mcp->in_mb = MBX_0;
  1862. mcp->tov = MBX_TOV_SECONDS;
  1863. mcp->flags = 0;
  1864. rval = qla2x00_mailbox_command(vha, mcp);
  1865. if (rval != QLA_SUCCESS) {
  1866. /*EMPTY*/
  1867. ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
  1868. } else {
  1869. /*EMPTY*/
  1870. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
  1871. "Done %s.\n", __func__);
  1872. }
  1873. return rval;
  1874. }
  1875. /*
  1876. * qla2x00_get_id_list
  1877. *
  1878. * Input:
  1879. * ha = adapter block pointer.
  1880. *
  1881. * Returns:
  1882. * qla2x00 local function return status code.
  1883. *
  1884. * Context:
  1885. * Kernel context.
  1886. */
  1887. int
  1888. qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
  1889. uint16_t *entries)
  1890. {
  1891. int rval;
  1892. mbx_cmd_t mc;
  1893. mbx_cmd_t *mcp = &mc;
  1894. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
  1895. "Entered %s.\n", __func__);
  1896. if (id_list == NULL)
  1897. return QLA_FUNCTION_FAILED;
  1898. mcp->mb[0] = MBC_GET_ID_LIST;
  1899. mcp->out_mb = MBX_0;
  1900. if (IS_FWI2_CAPABLE(vha->hw)) {
  1901. mcp->mb[2] = MSW(id_list_dma);
  1902. mcp->mb[3] = LSW(id_list_dma);
  1903. mcp->mb[6] = MSW(MSD(id_list_dma));
  1904. mcp->mb[7] = LSW(MSD(id_list_dma));
  1905. mcp->mb[8] = 0;
  1906. mcp->mb[9] = vha->vp_idx;
  1907. mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
  1908. } else {
  1909. mcp->mb[1] = MSW(id_list_dma);
  1910. mcp->mb[2] = LSW(id_list_dma);
  1911. mcp->mb[3] = MSW(MSD(id_list_dma));
  1912. mcp->mb[6] = LSW(MSD(id_list_dma));
  1913. mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
  1914. }
  1915. mcp->in_mb = MBX_1|MBX_0;
  1916. mcp->tov = MBX_TOV_SECONDS;
  1917. mcp->flags = 0;
  1918. rval = qla2x00_mailbox_command(vha, mcp);
  1919. if (rval != QLA_SUCCESS) {
  1920. /*EMPTY*/
  1921. ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
  1922. } else {
  1923. *entries = mcp->mb[1];
  1924. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
  1925. "Done %s.\n", __func__);
  1926. }
  1927. return rval;
  1928. }
  1929. /*
  1930. * qla2x00_get_resource_cnts
  1931. * Get current firmware resource counts.
  1932. *
  1933. * Input:
  1934. * ha = adapter block pointer.
  1935. *
  1936. * Returns:
  1937. * qla2x00 local function return status code.
  1938. *
  1939. * Context:
  1940. * Kernel context.
  1941. */
  1942. int
  1943. qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
  1944. uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
  1945. uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
  1946. {
  1947. int rval;
  1948. mbx_cmd_t mc;
  1949. mbx_cmd_t *mcp = &mc;
  1950. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
  1951. "Entered %s.\n", __func__);
  1952. mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
  1953. mcp->out_mb = MBX_0;
  1954. mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1955. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
  1956. mcp->in_mb |= MBX_12;
  1957. mcp->tov = MBX_TOV_SECONDS;
  1958. mcp->flags = 0;
  1959. rval = qla2x00_mailbox_command(vha, mcp);
  1960. if (rval != QLA_SUCCESS) {
  1961. /*EMPTY*/
  1962. ql_dbg(ql_dbg_mbx, vha, 0x107d,
  1963. "Failed mb[0]=%x.\n", mcp->mb[0]);
  1964. } else {
  1965. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
  1966. "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
  1967. "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
  1968. mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
  1969. mcp->mb[11], mcp->mb[12]);
  1970. if (cur_xchg_cnt)
  1971. *cur_xchg_cnt = mcp->mb[3];
  1972. if (orig_xchg_cnt)
  1973. *orig_xchg_cnt = mcp->mb[6];
  1974. if (cur_iocb_cnt)
  1975. *cur_iocb_cnt = mcp->mb[7];
  1976. if (orig_iocb_cnt)
  1977. *orig_iocb_cnt = mcp->mb[10];
  1978. if (vha->hw->flags.npiv_supported && max_npiv_vports)
  1979. *max_npiv_vports = mcp->mb[11];
  1980. if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
  1981. *max_fcfs = mcp->mb[12];
  1982. }
  1983. return (rval);
  1984. }
  1985. /*
  1986. * qla2x00_get_fcal_position_map
  1987. * Get FCAL (LILP) position map using mailbox command
  1988. *
  1989. * Input:
  1990. * ha = adapter state pointer.
  1991. * pos_map = buffer pointer (can be NULL).
  1992. *
  1993. * Returns:
  1994. * qla2x00 local function return status code.
  1995. *
  1996. * Context:
  1997. * Kernel context.
  1998. */
  1999. int
  2000. qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
  2001. {
  2002. int rval;
  2003. mbx_cmd_t mc;
  2004. mbx_cmd_t *mcp = &mc;
  2005. char *pmap;
  2006. dma_addr_t pmap_dma;
  2007. struct qla_hw_data *ha = vha->hw;
  2008. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
  2009. "Entered %s.\n", __func__);
  2010. pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
  2011. if (pmap == NULL) {
  2012. ql_log(ql_log_warn, vha, 0x1080,
  2013. "Memory alloc failed.\n");
  2014. return QLA_MEMORY_ALLOC_FAILED;
  2015. }
  2016. memset(pmap, 0, FCAL_MAP_SIZE);
  2017. mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
  2018. mcp->mb[2] = MSW(pmap_dma);
  2019. mcp->mb[3] = LSW(pmap_dma);
  2020. mcp->mb[6] = MSW(MSD(pmap_dma));
  2021. mcp->mb[7] = LSW(MSD(pmap_dma));
  2022. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2023. mcp->in_mb = MBX_1|MBX_0;
  2024. mcp->buf_size = FCAL_MAP_SIZE;
  2025. mcp->flags = MBX_DMA_IN;
  2026. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  2027. rval = qla2x00_mailbox_command(vha, mcp);
  2028. if (rval == QLA_SUCCESS) {
  2029. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
  2030. "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
  2031. mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
  2032. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
  2033. pmap, pmap[0] + 1);
  2034. if (pos_map)
  2035. memcpy(pos_map, pmap, FCAL_MAP_SIZE);
  2036. }
  2037. dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
  2038. if (rval != QLA_SUCCESS) {
  2039. ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
  2040. } else {
  2041. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
  2042. "Done %s.\n", __func__);
  2043. }
  2044. return rval;
  2045. }
  2046. /*
  2047. * qla2x00_get_link_status
  2048. *
  2049. * Input:
  2050. * ha = adapter block pointer.
  2051. * loop_id = device loop ID.
  2052. * ret_buf = pointer to link status return buffer.
  2053. *
  2054. * Returns:
  2055. * 0 = success.
  2056. * BIT_0 = mem alloc error.
  2057. * BIT_1 = mailbox error.
  2058. */
  2059. int
  2060. qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
  2061. struct link_statistics *stats, dma_addr_t stats_dma)
  2062. {
  2063. int rval;
  2064. mbx_cmd_t mc;
  2065. mbx_cmd_t *mcp = &mc;
  2066. uint32_t *siter, *diter, dwords;
  2067. struct qla_hw_data *ha = vha->hw;
  2068. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
  2069. "Entered %s.\n", __func__);
  2070. mcp->mb[0] = MBC_GET_LINK_STATUS;
  2071. mcp->mb[2] = MSW(stats_dma);
  2072. mcp->mb[3] = LSW(stats_dma);
  2073. mcp->mb[6] = MSW(MSD(stats_dma));
  2074. mcp->mb[7] = LSW(MSD(stats_dma));
  2075. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2076. mcp->in_mb = MBX_0;
  2077. if (IS_FWI2_CAPABLE(ha)) {
  2078. mcp->mb[1] = loop_id;
  2079. mcp->mb[4] = 0;
  2080. mcp->mb[10] = 0;
  2081. mcp->out_mb |= MBX_10|MBX_4|MBX_1;
  2082. mcp->in_mb |= MBX_1;
  2083. } else if (HAS_EXTENDED_IDS(ha)) {
  2084. mcp->mb[1] = loop_id;
  2085. mcp->mb[10] = 0;
  2086. mcp->out_mb |= MBX_10|MBX_1;
  2087. } else {
  2088. mcp->mb[1] = loop_id << 8;
  2089. mcp->out_mb |= MBX_1;
  2090. }
  2091. mcp->tov = MBX_TOV_SECONDS;
  2092. mcp->flags = IOCTL_CMD;
  2093. rval = qla2x00_mailbox_command(vha, mcp);
  2094. if (rval == QLA_SUCCESS) {
  2095. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2096. ql_dbg(ql_dbg_mbx, vha, 0x1085,
  2097. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2098. rval = QLA_FUNCTION_FAILED;
  2099. } else {
  2100. /* Copy over data -- firmware data is LE. */
  2101. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
  2102. "Done %s.\n", __func__);
  2103. dwords = offsetof(struct link_statistics, unused1) / 4;
  2104. siter = diter = &stats->link_fail_cnt;
  2105. while (dwords--)
  2106. *diter++ = le32_to_cpu(*siter++);
  2107. }
  2108. } else {
  2109. /* Failed. */
  2110. ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
  2111. }
  2112. return rval;
  2113. }
  2114. int
  2115. qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
  2116. dma_addr_t stats_dma)
  2117. {
  2118. int rval;
  2119. mbx_cmd_t mc;
  2120. mbx_cmd_t *mcp = &mc;
  2121. uint32_t *siter, *diter, dwords;
  2122. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
  2123. "Entered %s.\n", __func__);
  2124. mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
  2125. mcp->mb[2] = MSW(stats_dma);
  2126. mcp->mb[3] = LSW(stats_dma);
  2127. mcp->mb[6] = MSW(MSD(stats_dma));
  2128. mcp->mb[7] = LSW(MSD(stats_dma));
  2129. mcp->mb[8] = sizeof(struct link_statistics) / 4;
  2130. mcp->mb[9] = vha->vp_idx;
  2131. mcp->mb[10] = 0;
  2132. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2133. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  2134. mcp->tov = MBX_TOV_SECONDS;
  2135. mcp->flags = IOCTL_CMD;
  2136. rval = qla2x00_mailbox_command(vha, mcp);
  2137. if (rval == QLA_SUCCESS) {
  2138. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2139. ql_dbg(ql_dbg_mbx, vha, 0x1089,
  2140. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2141. rval = QLA_FUNCTION_FAILED;
  2142. } else {
  2143. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
  2144. "Done %s.\n", __func__);
  2145. /* Copy over data -- firmware data is LE. */
  2146. dwords = sizeof(struct link_statistics) / 4;
  2147. siter = diter = &stats->link_fail_cnt;
  2148. while (dwords--)
  2149. *diter++ = le32_to_cpu(*siter++);
  2150. }
  2151. } else {
  2152. /* Failed. */
  2153. ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
  2154. }
  2155. return rval;
  2156. }
  2157. int
  2158. qla24xx_abort_command(srb_t *sp)
  2159. {
  2160. int rval;
  2161. unsigned long flags = 0;
  2162. struct abort_entry_24xx *abt;
  2163. dma_addr_t abt_dma;
  2164. uint32_t handle;
  2165. fc_port_t *fcport = sp->fcport;
  2166. struct scsi_qla_host *vha = fcport->vha;
  2167. struct qla_hw_data *ha = vha->hw;
  2168. struct req_que *req = vha->req;
  2169. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
  2170. "Entered %s.\n", __func__);
  2171. spin_lock_irqsave(&ha->hardware_lock, flags);
  2172. for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
  2173. if (req->outstanding_cmds[handle] == sp)
  2174. break;
  2175. }
  2176. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2177. if (handle == MAX_OUTSTANDING_COMMANDS) {
  2178. /* Command not found. */
  2179. return QLA_FUNCTION_FAILED;
  2180. }
  2181. abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
  2182. if (abt == NULL) {
  2183. ql_log(ql_log_warn, vha, 0x108d,
  2184. "Failed to allocate abort IOCB.\n");
  2185. return QLA_MEMORY_ALLOC_FAILED;
  2186. }
  2187. memset(abt, 0, sizeof(struct abort_entry_24xx));
  2188. abt->entry_type = ABORT_IOCB_TYPE;
  2189. abt->entry_count = 1;
  2190. abt->handle = MAKE_HANDLE(req->id, abt->handle);
  2191. abt->nport_handle = cpu_to_le16(fcport->loop_id);
  2192. abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
  2193. abt->port_id[0] = fcport->d_id.b.al_pa;
  2194. abt->port_id[1] = fcport->d_id.b.area;
  2195. abt->port_id[2] = fcport->d_id.b.domain;
  2196. abt->vp_index = fcport->vha->vp_idx;
  2197. abt->req_que_no = cpu_to_le16(req->id);
  2198. rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
  2199. if (rval != QLA_SUCCESS) {
  2200. ql_dbg(ql_dbg_mbx, vha, 0x108e,
  2201. "Failed to issue IOCB (%x).\n", rval);
  2202. } else if (abt->entry_status != 0) {
  2203. ql_dbg(ql_dbg_mbx, vha, 0x108f,
  2204. "Failed to complete IOCB -- error status (%x).\n",
  2205. abt->entry_status);
  2206. rval = QLA_FUNCTION_FAILED;
  2207. } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
  2208. ql_dbg(ql_dbg_mbx, vha, 0x1090,
  2209. "Failed to complete IOCB -- completion status (%x).\n",
  2210. le16_to_cpu(abt->nport_handle));
  2211. rval = QLA_FUNCTION_FAILED;
  2212. } else {
  2213. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
  2214. "Done %s.\n", __func__);
  2215. }
  2216. dma_pool_free(ha->s_dma_pool, abt, abt_dma);
  2217. return rval;
  2218. }
  2219. struct tsk_mgmt_cmd {
  2220. union {
  2221. struct tsk_mgmt_entry tsk;
  2222. struct sts_entry_24xx sts;
  2223. } p;
  2224. };
  2225. static int
  2226. __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
  2227. unsigned int l, int tag)
  2228. {
  2229. int rval, rval2;
  2230. struct tsk_mgmt_cmd *tsk;
  2231. struct sts_entry_24xx *sts;
  2232. dma_addr_t tsk_dma;
  2233. scsi_qla_host_t *vha;
  2234. struct qla_hw_data *ha;
  2235. struct req_que *req;
  2236. struct rsp_que *rsp;
  2237. vha = fcport->vha;
  2238. ha = vha->hw;
  2239. req = vha->req;
  2240. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
  2241. "Entered %s.\n", __func__);
  2242. if (ha->flags.cpu_affinity_enabled)
  2243. rsp = ha->rsp_q_map[tag + 1];
  2244. else
  2245. rsp = req->rsp;
  2246. tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
  2247. if (tsk == NULL) {
  2248. ql_log(ql_log_warn, vha, 0x1093,
  2249. "Failed to allocate task management IOCB.\n");
  2250. return QLA_MEMORY_ALLOC_FAILED;
  2251. }
  2252. memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
  2253. tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
  2254. tsk->p.tsk.entry_count = 1;
  2255. tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
  2256. tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
  2257. tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
  2258. tsk->p.tsk.control_flags = cpu_to_le32(type);
  2259. tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
  2260. tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
  2261. tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
  2262. tsk->p.tsk.vp_index = fcport->vha->vp_idx;
  2263. if (type == TCF_LUN_RESET) {
  2264. int_to_scsilun(l, &tsk->p.tsk.lun);
  2265. host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
  2266. sizeof(tsk->p.tsk.lun));
  2267. }
  2268. sts = &tsk->p.sts;
  2269. rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
  2270. if (rval != QLA_SUCCESS) {
  2271. ql_dbg(ql_dbg_mbx, vha, 0x1094,
  2272. "Failed to issue %s reset IOCB (%x).\n", name, rval);
  2273. } else if (sts->entry_status != 0) {
  2274. ql_dbg(ql_dbg_mbx, vha, 0x1095,
  2275. "Failed to complete IOCB -- error status (%x).\n",
  2276. sts->entry_status);
  2277. rval = QLA_FUNCTION_FAILED;
  2278. } else if (sts->comp_status !=
  2279. __constant_cpu_to_le16(CS_COMPLETE)) {
  2280. ql_dbg(ql_dbg_mbx, vha, 0x1096,
  2281. "Failed to complete IOCB -- completion status (%x).\n",
  2282. le16_to_cpu(sts->comp_status));
  2283. rval = QLA_FUNCTION_FAILED;
  2284. } else if (le16_to_cpu(sts->scsi_status) &
  2285. SS_RESPONSE_INFO_LEN_VALID) {
  2286. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  2287. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
  2288. "Ignoring inconsistent data length -- not enough "
  2289. "response info (%d).\n",
  2290. le32_to_cpu(sts->rsp_data_len));
  2291. } else if (sts->data[3]) {
  2292. ql_dbg(ql_dbg_mbx, vha, 0x1098,
  2293. "Failed to complete IOCB -- response (%x).\n",
  2294. sts->data[3]);
  2295. rval = QLA_FUNCTION_FAILED;
  2296. }
  2297. }
  2298. /* Issue marker IOCB. */
  2299. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  2300. type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
  2301. if (rval2 != QLA_SUCCESS) {
  2302. ql_dbg(ql_dbg_mbx, vha, 0x1099,
  2303. "Failed to issue marker IOCB (%x).\n", rval2);
  2304. } else {
  2305. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
  2306. "Done %s.\n", __func__);
  2307. }
  2308. dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
  2309. return rval;
  2310. }
  2311. int
  2312. qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  2313. {
  2314. struct qla_hw_data *ha = fcport->vha->hw;
  2315. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2316. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  2317. return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
  2318. }
  2319. int
  2320. qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  2321. {
  2322. struct qla_hw_data *ha = fcport->vha->hw;
  2323. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2324. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  2325. return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
  2326. }
  2327. int
  2328. qla2x00_system_error(scsi_qla_host_t *vha)
  2329. {
  2330. int rval;
  2331. mbx_cmd_t mc;
  2332. mbx_cmd_t *mcp = &mc;
  2333. struct qla_hw_data *ha = vha->hw;
  2334. if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
  2335. return QLA_FUNCTION_FAILED;
  2336. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
  2337. "Entered %s.\n", __func__);
  2338. mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
  2339. mcp->out_mb = MBX_0;
  2340. mcp->in_mb = MBX_0;
  2341. mcp->tov = 5;
  2342. mcp->flags = 0;
  2343. rval = qla2x00_mailbox_command(vha, mcp);
  2344. if (rval != QLA_SUCCESS) {
  2345. ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
  2346. } else {
  2347. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
  2348. "Done %s.\n", __func__);
  2349. }
  2350. return rval;
  2351. }
  2352. /**
  2353. * qla2x00_set_serdes_params() -
  2354. * @ha: HA context
  2355. *
  2356. * Returns
  2357. */
  2358. int
  2359. qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
  2360. uint16_t sw_em_2g, uint16_t sw_em_4g)
  2361. {
  2362. int rval;
  2363. mbx_cmd_t mc;
  2364. mbx_cmd_t *mcp = &mc;
  2365. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
  2366. "Entered %s.\n", __func__);
  2367. mcp->mb[0] = MBC_SERDES_PARAMS;
  2368. mcp->mb[1] = BIT_0;
  2369. mcp->mb[2] = sw_em_1g | BIT_15;
  2370. mcp->mb[3] = sw_em_2g | BIT_15;
  2371. mcp->mb[4] = sw_em_4g | BIT_15;
  2372. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2373. mcp->in_mb = MBX_0;
  2374. mcp->tov = MBX_TOV_SECONDS;
  2375. mcp->flags = 0;
  2376. rval = qla2x00_mailbox_command(vha, mcp);
  2377. if (rval != QLA_SUCCESS) {
  2378. /*EMPTY*/
  2379. ql_dbg(ql_dbg_mbx, vha, 0x109f,
  2380. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2381. } else {
  2382. /*EMPTY*/
  2383. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
  2384. "Done %s.\n", __func__);
  2385. }
  2386. return rval;
  2387. }
  2388. int
  2389. qla2x00_stop_firmware(scsi_qla_host_t *vha)
  2390. {
  2391. int rval;
  2392. mbx_cmd_t mc;
  2393. mbx_cmd_t *mcp = &mc;
  2394. if (!IS_FWI2_CAPABLE(vha->hw))
  2395. return QLA_FUNCTION_FAILED;
  2396. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
  2397. "Entered %s.\n", __func__);
  2398. mcp->mb[0] = MBC_STOP_FIRMWARE;
  2399. mcp->mb[1] = 0;
  2400. mcp->out_mb = MBX_1|MBX_0;
  2401. mcp->in_mb = MBX_0;
  2402. mcp->tov = 5;
  2403. mcp->flags = 0;
  2404. rval = qla2x00_mailbox_command(vha, mcp);
  2405. if (rval != QLA_SUCCESS) {
  2406. ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
  2407. if (mcp->mb[0] == MBS_INVALID_COMMAND)
  2408. rval = QLA_INVALID_COMMAND;
  2409. } else {
  2410. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
  2411. "Done %s.\n", __func__);
  2412. }
  2413. return rval;
  2414. }
  2415. int
  2416. qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
  2417. uint16_t buffers)
  2418. {
  2419. int rval;
  2420. mbx_cmd_t mc;
  2421. mbx_cmd_t *mcp = &mc;
  2422. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
  2423. "Entered %s.\n", __func__);
  2424. if (!IS_FWI2_CAPABLE(vha->hw))
  2425. return QLA_FUNCTION_FAILED;
  2426. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2427. return QLA_FUNCTION_FAILED;
  2428. mcp->mb[0] = MBC_TRACE_CONTROL;
  2429. mcp->mb[1] = TC_EFT_ENABLE;
  2430. mcp->mb[2] = LSW(eft_dma);
  2431. mcp->mb[3] = MSW(eft_dma);
  2432. mcp->mb[4] = LSW(MSD(eft_dma));
  2433. mcp->mb[5] = MSW(MSD(eft_dma));
  2434. mcp->mb[6] = buffers;
  2435. mcp->mb[7] = TC_AEN_DISABLE;
  2436. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2437. mcp->in_mb = MBX_1|MBX_0;
  2438. mcp->tov = MBX_TOV_SECONDS;
  2439. mcp->flags = 0;
  2440. rval = qla2x00_mailbox_command(vha, mcp);
  2441. if (rval != QLA_SUCCESS) {
  2442. ql_dbg(ql_dbg_mbx, vha, 0x10a5,
  2443. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2444. rval, mcp->mb[0], mcp->mb[1]);
  2445. } else {
  2446. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
  2447. "Done %s.\n", __func__);
  2448. }
  2449. return rval;
  2450. }
  2451. int
  2452. qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
  2453. {
  2454. int rval;
  2455. mbx_cmd_t mc;
  2456. mbx_cmd_t *mcp = &mc;
  2457. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
  2458. "Entered %s.\n", __func__);
  2459. if (!IS_FWI2_CAPABLE(vha->hw))
  2460. return QLA_FUNCTION_FAILED;
  2461. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2462. return QLA_FUNCTION_FAILED;
  2463. mcp->mb[0] = MBC_TRACE_CONTROL;
  2464. mcp->mb[1] = TC_EFT_DISABLE;
  2465. mcp->out_mb = MBX_1|MBX_0;
  2466. mcp->in_mb = MBX_1|MBX_0;
  2467. mcp->tov = MBX_TOV_SECONDS;
  2468. mcp->flags = 0;
  2469. rval = qla2x00_mailbox_command(vha, mcp);
  2470. if (rval != QLA_SUCCESS) {
  2471. ql_dbg(ql_dbg_mbx, vha, 0x10a8,
  2472. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2473. rval, mcp->mb[0], mcp->mb[1]);
  2474. } else {
  2475. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
  2476. "Done %s.\n", __func__);
  2477. }
  2478. return rval;
  2479. }
  2480. int
  2481. qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
  2482. uint16_t buffers, uint16_t *mb, uint32_t *dwords)
  2483. {
  2484. int rval;
  2485. mbx_cmd_t mc;
  2486. mbx_cmd_t *mcp = &mc;
  2487. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
  2488. "Entered %s.\n", __func__);
  2489. if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
  2490. !IS_QLA83XX(vha->hw))
  2491. return QLA_FUNCTION_FAILED;
  2492. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2493. return QLA_FUNCTION_FAILED;
  2494. mcp->mb[0] = MBC_TRACE_CONTROL;
  2495. mcp->mb[1] = TC_FCE_ENABLE;
  2496. mcp->mb[2] = LSW(fce_dma);
  2497. mcp->mb[3] = MSW(fce_dma);
  2498. mcp->mb[4] = LSW(MSD(fce_dma));
  2499. mcp->mb[5] = MSW(MSD(fce_dma));
  2500. mcp->mb[6] = buffers;
  2501. mcp->mb[7] = TC_AEN_DISABLE;
  2502. mcp->mb[8] = 0;
  2503. mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
  2504. mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
  2505. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2506. MBX_1|MBX_0;
  2507. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2508. mcp->tov = MBX_TOV_SECONDS;
  2509. mcp->flags = 0;
  2510. rval = qla2x00_mailbox_command(vha, mcp);
  2511. if (rval != QLA_SUCCESS) {
  2512. ql_dbg(ql_dbg_mbx, vha, 0x10ab,
  2513. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2514. rval, mcp->mb[0], mcp->mb[1]);
  2515. } else {
  2516. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
  2517. "Done %s.\n", __func__);
  2518. if (mb)
  2519. memcpy(mb, mcp->mb, 8 * sizeof(*mb));
  2520. if (dwords)
  2521. *dwords = buffers;
  2522. }
  2523. return rval;
  2524. }
  2525. int
  2526. qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
  2527. {
  2528. int rval;
  2529. mbx_cmd_t mc;
  2530. mbx_cmd_t *mcp = &mc;
  2531. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
  2532. "Entered %s.\n", __func__);
  2533. if (!IS_FWI2_CAPABLE(vha->hw))
  2534. return QLA_FUNCTION_FAILED;
  2535. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2536. return QLA_FUNCTION_FAILED;
  2537. mcp->mb[0] = MBC_TRACE_CONTROL;
  2538. mcp->mb[1] = TC_FCE_DISABLE;
  2539. mcp->mb[2] = TC_FCE_DISABLE_TRACE;
  2540. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  2541. mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2542. MBX_1|MBX_0;
  2543. mcp->tov = MBX_TOV_SECONDS;
  2544. mcp->flags = 0;
  2545. rval = qla2x00_mailbox_command(vha, mcp);
  2546. if (rval != QLA_SUCCESS) {
  2547. ql_dbg(ql_dbg_mbx, vha, 0x10ae,
  2548. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2549. rval, mcp->mb[0], mcp->mb[1]);
  2550. } else {
  2551. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
  2552. "Done %s.\n", __func__);
  2553. if (wr)
  2554. *wr = (uint64_t) mcp->mb[5] << 48 |
  2555. (uint64_t) mcp->mb[4] << 32 |
  2556. (uint64_t) mcp->mb[3] << 16 |
  2557. (uint64_t) mcp->mb[2];
  2558. if (rd)
  2559. *rd = (uint64_t) mcp->mb[9] << 48 |
  2560. (uint64_t) mcp->mb[8] << 32 |
  2561. (uint64_t) mcp->mb[7] << 16 |
  2562. (uint64_t) mcp->mb[6];
  2563. }
  2564. return rval;
  2565. }
  2566. int
  2567. qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2568. uint16_t *port_speed, uint16_t *mb)
  2569. {
  2570. int rval;
  2571. mbx_cmd_t mc;
  2572. mbx_cmd_t *mcp = &mc;
  2573. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
  2574. "Entered %s.\n", __func__);
  2575. if (!IS_IIDMA_CAPABLE(vha->hw))
  2576. return QLA_FUNCTION_FAILED;
  2577. mcp->mb[0] = MBC_PORT_PARAMS;
  2578. mcp->mb[1] = loop_id;
  2579. mcp->mb[2] = mcp->mb[3] = 0;
  2580. mcp->mb[9] = vha->vp_idx;
  2581. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2582. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2583. mcp->tov = MBX_TOV_SECONDS;
  2584. mcp->flags = 0;
  2585. rval = qla2x00_mailbox_command(vha, mcp);
  2586. /* Return mailbox statuses. */
  2587. if (mb != NULL) {
  2588. mb[0] = mcp->mb[0];
  2589. mb[1] = mcp->mb[1];
  2590. mb[3] = mcp->mb[3];
  2591. }
  2592. if (rval != QLA_SUCCESS) {
  2593. ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
  2594. } else {
  2595. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
  2596. "Done %s.\n", __func__);
  2597. if (port_speed)
  2598. *port_speed = mcp->mb[3];
  2599. }
  2600. return rval;
  2601. }
  2602. int
  2603. qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2604. uint16_t port_speed, uint16_t *mb)
  2605. {
  2606. int rval;
  2607. mbx_cmd_t mc;
  2608. mbx_cmd_t *mcp = &mc;
  2609. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
  2610. "Entered %s.\n", __func__);
  2611. if (!IS_IIDMA_CAPABLE(vha->hw))
  2612. return QLA_FUNCTION_FAILED;
  2613. mcp->mb[0] = MBC_PORT_PARAMS;
  2614. mcp->mb[1] = loop_id;
  2615. mcp->mb[2] = BIT_0;
  2616. if (IS_CNA_CAPABLE(vha->hw))
  2617. mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
  2618. else
  2619. mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
  2620. mcp->mb[9] = vha->vp_idx;
  2621. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2622. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2623. mcp->tov = MBX_TOV_SECONDS;
  2624. mcp->flags = 0;
  2625. rval = qla2x00_mailbox_command(vha, mcp);
  2626. /* Return mailbox statuses. */
  2627. if (mb != NULL) {
  2628. mb[0] = mcp->mb[0];
  2629. mb[1] = mcp->mb[1];
  2630. mb[3] = mcp->mb[3];
  2631. }
  2632. if (rval != QLA_SUCCESS) {
  2633. ql_dbg(ql_dbg_mbx, vha, 0x10b4,
  2634. "Failed=%x.\n", rval);
  2635. } else {
  2636. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
  2637. "Done %s.\n", __func__);
  2638. }
  2639. return rval;
  2640. }
  2641. void
  2642. qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
  2643. struct vp_rpt_id_entry_24xx *rptid_entry)
  2644. {
  2645. uint8_t vp_idx;
  2646. uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
  2647. struct qla_hw_data *ha = vha->hw;
  2648. scsi_qla_host_t *vp;
  2649. unsigned long flags;
  2650. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
  2651. "Entered %s.\n", __func__);
  2652. if (rptid_entry->entry_status != 0)
  2653. return;
  2654. if (rptid_entry->format == 0) {
  2655. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
  2656. "Format 0 : Number of VPs setup %d, number of "
  2657. "VPs acquired %d.\n",
  2658. MSB(le16_to_cpu(rptid_entry->vp_count)),
  2659. LSB(le16_to_cpu(rptid_entry->vp_count)));
  2660. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
  2661. "Primary port id %02x%02x%02x.\n",
  2662. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2663. rptid_entry->port_id[0]);
  2664. } else if (rptid_entry->format == 1) {
  2665. vp_idx = LSB(stat);
  2666. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
  2667. "Format 1: VP[%d] enabled - status %d - with "
  2668. "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
  2669. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2670. rptid_entry->port_id[0]);
  2671. vp = vha;
  2672. if (vp_idx == 0 && (MSB(stat) != 1))
  2673. goto reg_needed;
  2674. if (MSB(stat) != 0) {
  2675. ql_dbg(ql_dbg_mbx, vha, 0x10ba,
  2676. "Could not acquire ID for VP[%d].\n", vp_idx);
  2677. return;
  2678. }
  2679. spin_lock_irqsave(&ha->vport_slock, flags);
  2680. list_for_each_entry(vp, &ha->vp_list, list)
  2681. if (vp_idx == vp->vp_idx)
  2682. break;
  2683. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2684. if (!vp)
  2685. return;
  2686. vp->d_id.b.domain = rptid_entry->port_id[2];
  2687. vp->d_id.b.area = rptid_entry->port_id[1];
  2688. vp->d_id.b.al_pa = rptid_entry->port_id[0];
  2689. /*
  2690. * Cannot configure here as we are still sitting on the
  2691. * response queue. Handle it in dpc context.
  2692. */
  2693. set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
  2694. reg_needed:
  2695. set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
  2696. set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
  2697. set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
  2698. qla2xxx_wake_dpc(vha);
  2699. }
  2700. }
  2701. /*
  2702. * qla24xx_modify_vp_config
  2703. * Change VP configuration for vha
  2704. *
  2705. * Input:
  2706. * vha = adapter block pointer.
  2707. *
  2708. * Returns:
  2709. * qla2xxx local function return status code.
  2710. *
  2711. * Context:
  2712. * Kernel context.
  2713. */
  2714. int
  2715. qla24xx_modify_vp_config(scsi_qla_host_t *vha)
  2716. {
  2717. int rval;
  2718. struct vp_config_entry_24xx *vpmod;
  2719. dma_addr_t vpmod_dma;
  2720. struct qla_hw_data *ha = vha->hw;
  2721. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2722. /* This can be called by the parent */
  2723. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
  2724. "Entered %s.\n", __func__);
  2725. vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
  2726. if (!vpmod) {
  2727. ql_log(ql_log_warn, vha, 0x10bc,
  2728. "Failed to allocate modify VP IOCB.\n");
  2729. return QLA_MEMORY_ALLOC_FAILED;
  2730. }
  2731. memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
  2732. vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
  2733. vpmod->entry_count = 1;
  2734. vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
  2735. vpmod->vp_count = 1;
  2736. vpmod->vp_index1 = vha->vp_idx;
  2737. vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
  2738. memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
  2739. memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
  2740. vpmod->entry_count = 1;
  2741. rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
  2742. if (rval != QLA_SUCCESS) {
  2743. ql_dbg(ql_dbg_mbx, vha, 0x10bd,
  2744. "Failed to issue VP config IOCB (%x).\n", rval);
  2745. } else if (vpmod->comp_status != 0) {
  2746. ql_dbg(ql_dbg_mbx, vha, 0x10be,
  2747. "Failed to complete IOCB -- error status (%x).\n",
  2748. vpmod->comp_status);
  2749. rval = QLA_FUNCTION_FAILED;
  2750. } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2751. ql_dbg(ql_dbg_mbx, vha, 0x10bf,
  2752. "Failed to complete IOCB -- completion status (%x).\n",
  2753. le16_to_cpu(vpmod->comp_status));
  2754. rval = QLA_FUNCTION_FAILED;
  2755. } else {
  2756. /* EMPTY */
  2757. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
  2758. "Done %s.\n", __func__);
  2759. fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
  2760. }
  2761. dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
  2762. return rval;
  2763. }
  2764. /*
  2765. * qla24xx_control_vp
  2766. * Enable a virtual port for given host
  2767. *
  2768. * Input:
  2769. * ha = adapter block pointer.
  2770. * vhba = virtual adapter (unused)
  2771. * index = index number for enabled VP
  2772. *
  2773. * Returns:
  2774. * qla2xxx local function return status code.
  2775. *
  2776. * Context:
  2777. * Kernel context.
  2778. */
  2779. int
  2780. qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
  2781. {
  2782. int rval;
  2783. int map, pos;
  2784. struct vp_ctrl_entry_24xx *vce;
  2785. dma_addr_t vce_dma;
  2786. struct qla_hw_data *ha = vha->hw;
  2787. int vp_index = vha->vp_idx;
  2788. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2789. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
  2790. "Entered %s enabling index %d.\n", __func__, vp_index);
  2791. if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
  2792. return QLA_PARAMETER_ERROR;
  2793. vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
  2794. if (!vce) {
  2795. ql_log(ql_log_warn, vha, 0x10c2,
  2796. "Failed to allocate VP control IOCB.\n");
  2797. return QLA_MEMORY_ALLOC_FAILED;
  2798. }
  2799. memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
  2800. vce->entry_type = VP_CTRL_IOCB_TYPE;
  2801. vce->entry_count = 1;
  2802. vce->command = cpu_to_le16(cmd);
  2803. vce->vp_count = __constant_cpu_to_le16(1);
  2804. /* index map in firmware starts with 1; decrement index
  2805. * this is ok as we never use index 0
  2806. */
  2807. map = (vp_index - 1) / 8;
  2808. pos = (vp_index - 1) & 7;
  2809. mutex_lock(&ha->vport_lock);
  2810. vce->vp_idx_map[map] |= 1 << pos;
  2811. mutex_unlock(&ha->vport_lock);
  2812. rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
  2813. if (rval != QLA_SUCCESS) {
  2814. ql_dbg(ql_dbg_mbx, vha, 0x10c3,
  2815. "Failed to issue VP control IOCB (%x).\n", rval);
  2816. } else if (vce->entry_status != 0) {
  2817. ql_dbg(ql_dbg_mbx, vha, 0x10c4,
  2818. "Failed to complete IOCB -- error status (%x).\n",
  2819. vce->entry_status);
  2820. rval = QLA_FUNCTION_FAILED;
  2821. } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2822. ql_dbg(ql_dbg_mbx, vha, 0x10c5,
  2823. "Failed to complet IOCB -- completion status (%x).\n",
  2824. le16_to_cpu(vce->comp_status));
  2825. rval = QLA_FUNCTION_FAILED;
  2826. } else {
  2827. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
  2828. "Done %s.\n", __func__);
  2829. }
  2830. dma_pool_free(ha->s_dma_pool, vce, vce_dma);
  2831. return rval;
  2832. }
  2833. /*
  2834. * qla2x00_send_change_request
  2835. * Receive or disable RSCN request from fabric controller
  2836. *
  2837. * Input:
  2838. * ha = adapter block pointer
  2839. * format = registration format:
  2840. * 0 - Reserved
  2841. * 1 - Fabric detected registration
  2842. * 2 - N_port detected registration
  2843. * 3 - Full registration
  2844. * FF - clear registration
  2845. * vp_idx = Virtual port index
  2846. *
  2847. * Returns:
  2848. * qla2x00 local function return status code.
  2849. *
  2850. * Context:
  2851. * Kernel Context
  2852. */
  2853. int
  2854. qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
  2855. uint16_t vp_idx)
  2856. {
  2857. int rval;
  2858. mbx_cmd_t mc;
  2859. mbx_cmd_t *mcp = &mc;
  2860. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
  2861. "Entered %s.\n", __func__);
  2862. /*
  2863. * This command is implicitly executed by firmware during login for the
  2864. * physical hosts
  2865. */
  2866. if (vp_idx == 0)
  2867. return QLA_FUNCTION_FAILED;
  2868. mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
  2869. mcp->mb[1] = format;
  2870. mcp->mb[9] = vp_idx;
  2871. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  2872. mcp->in_mb = MBX_0|MBX_1;
  2873. mcp->tov = MBX_TOV_SECONDS;
  2874. mcp->flags = 0;
  2875. rval = qla2x00_mailbox_command(vha, mcp);
  2876. if (rval == QLA_SUCCESS) {
  2877. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2878. rval = BIT_1;
  2879. }
  2880. } else
  2881. rval = BIT_1;
  2882. return rval;
  2883. }
  2884. int
  2885. qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  2886. uint32_t size)
  2887. {
  2888. int rval;
  2889. mbx_cmd_t mc;
  2890. mbx_cmd_t *mcp = &mc;
  2891. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
  2892. "Entered %s.\n", __func__);
  2893. if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
  2894. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  2895. mcp->mb[8] = MSW(addr);
  2896. mcp->out_mb = MBX_8|MBX_0;
  2897. } else {
  2898. mcp->mb[0] = MBC_DUMP_RISC_RAM;
  2899. mcp->out_mb = MBX_0;
  2900. }
  2901. mcp->mb[1] = LSW(addr);
  2902. mcp->mb[2] = MSW(req_dma);
  2903. mcp->mb[3] = LSW(req_dma);
  2904. mcp->mb[6] = MSW(MSD(req_dma));
  2905. mcp->mb[7] = LSW(MSD(req_dma));
  2906. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  2907. if (IS_FWI2_CAPABLE(vha->hw)) {
  2908. mcp->mb[4] = MSW(size);
  2909. mcp->mb[5] = LSW(size);
  2910. mcp->out_mb |= MBX_5|MBX_4;
  2911. } else {
  2912. mcp->mb[4] = LSW(size);
  2913. mcp->out_mb |= MBX_4;
  2914. }
  2915. mcp->in_mb = MBX_0;
  2916. mcp->tov = MBX_TOV_SECONDS;
  2917. mcp->flags = 0;
  2918. rval = qla2x00_mailbox_command(vha, mcp);
  2919. if (rval != QLA_SUCCESS) {
  2920. ql_dbg(ql_dbg_mbx, vha, 0x1008,
  2921. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2922. } else {
  2923. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
  2924. "Done %s.\n", __func__);
  2925. }
  2926. return rval;
  2927. }
  2928. /* 84XX Support **************************************************************/
  2929. struct cs84xx_mgmt_cmd {
  2930. union {
  2931. struct verify_chip_entry_84xx req;
  2932. struct verify_chip_rsp_84xx rsp;
  2933. } p;
  2934. };
  2935. int
  2936. qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
  2937. {
  2938. int rval, retry;
  2939. struct cs84xx_mgmt_cmd *mn;
  2940. dma_addr_t mn_dma;
  2941. uint16_t options;
  2942. unsigned long flags;
  2943. struct qla_hw_data *ha = vha->hw;
  2944. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
  2945. "Entered %s.\n", __func__);
  2946. mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
  2947. if (mn == NULL) {
  2948. return QLA_MEMORY_ALLOC_FAILED;
  2949. }
  2950. /* Force Update? */
  2951. options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
  2952. /* Diagnostic firmware? */
  2953. /* options |= MENLO_DIAG_FW; */
  2954. /* We update the firmware with only one data sequence. */
  2955. options |= VCO_END_OF_DATA;
  2956. do {
  2957. retry = 0;
  2958. memset(mn, 0, sizeof(*mn));
  2959. mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
  2960. mn->p.req.entry_count = 1;
  2961. mn->p.req.options = cpu_to_le16(options);
  2962. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
  2963. "Dump of Verify Request.\n");
  2964. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
  2965. (uint8_t *)mn, sizeof(*mn));
  2966. rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
  2967. if (rval != QLA_SUCCESS) {
  2968. ql_dbg(ql_dbg_mbx, vha, 0x10cb,
  2969. "Failed to issue verify IOCB (%x).\n", rval);
  2970. goto verify_done;
  2971. }
  2972. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
  2973. "Dump of Verify Response.\n");
  2974. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
  2975. (uint8_t *)mn, sizeof(*mn));
  2976. status[0] = le16_to_cpu(mn->p.rsp.comp_status);
  2977. status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
  2978. le16_to_cpu(mn->p.rsp.failure_code) : 0;
  2979. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
  2980. "cs=%x fc=%x.\n", status[0], status[1]);
  2981. if (status[0] != CS_COMPLETE) {
  2982. rval = QLA_FUNCTION_FAILED;
  2983. if (!(options & VCO_DONT_UPDATE_FW)) {
  2984. ql_dbg(ql_dbg_mbx, vha, 0x10cf,
  2985. "Firmware update failed. Retrying "
  2986. "without update firmware.\n");
  2987. options |= VCO_DONT_UPDATE_FW;
  2988. options &= ~VCO_FORCE_UPDATE;
  2989. retry = 1;
  2990. }
  2991. } else {
  2992. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
  2993. "Firmware updated to %x.\n",
  2994. le32_to_cpu(mn->p.rsp.fw_ver));
  2995. /* NOTE: we only update OP firmware. */
  2996. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  2997. ha->cs84xx->op_fw_version =
  2998. le32_to_cpu(mn->p.rsp.fw_ver);
  2999. spin_unlock_irqrestore(&ha->cs84xx->access_lock,
  3000. flags);
  3001. }
  3002. } while (retry);
  3003. verify_done:
  3004. dma_pool_free(ha->s_dma_pool, mn, mn_dma);
  3005. if (rval != QLA_SUCCESS) {
  3006. ql_dbg(ql_dbg_mbx, vha, 0x10d1,
  3007. "Failed=%x.\n", rval);
  3008. } else {
  3009. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
  3010. "Done %s.\n", __func__);
  3011. }
  3012. return rval;
  3013. }
  3014. int
  3015. qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
  3016. {
  3017. int rval;
  3018. unsigned long flags;
  3019. mbx_cmd_t mc;
  3020. mbx_cmd_t *mcp = &mc;
  3021. struct device_reg_25xxmq __iomem *reg;
  3022. struct qla_hw_data *ha = vha->hw;
  3023. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
  3024. "Entered %s.\n", __func__);
  3025. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3026. mcp->mb[1] = req->options;
  3027. mcp->mb[2] = MSW(LSD(req->dma));
  3028. mcp->mb[3] = LSW(LSD(req->dma));
  3029. mcp->mb[6] = MSW(MSD(req->dma));
  3030. mcp->mb[7] = LSW(MSD(req->dma));
  3031. mcp->mb[5] = req->length;
  3032. if (req->rsp)
  3033. mcp->mb[10] = req->rsp->id;
  3034. mcp->mb[12] = req->qos;
  3035. mcp->mb[11] = req->vp_idx;
  3036. mcp->mb[13] = req->rid;
  3037. if (IS_QLA83XX(ha))
  3038. mcp->mb[15] = 0;
  3039. reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
  3040. QLA_QUE_PAGE * req->id);
  3041. mcp->mb[4] = req->id;
  3042. /* que in ptr index */
  3043. mcp->mb[8] = 0;
  3044. /* que out ptr index */
  3045. mcp->mb[9] = 0;
  3046. mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
  3047. MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3048. mcp->in_mb = MBX_0;
  3049. mcp->flags = MBX_DMA_OUT;
  3050. mcp->tov = MBX_TOV_SECONDS * 2;
  3051. if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
  3052. mcp->in_mb |= MBX_1;
  3053. if (IS_QLA83XX(ha)) {
  3054. mcp->out_mb |= MBX_15;
  3055. /* debug q create issue in SR-IOV */
  3056. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3057. }
  3058. spin_lock_irqsave(&ha->hardware_lock, flags);
  3059. if (!(req->options & BIT_0)) {
  3060. WRT_REG_DWORD(&reg->req_q_in, 0);
  3061. if (!IS_QLA83XX(ha))
  3062. WRT_REG_DWORD(&reg->req_q_out, 0);
  3063. }
  3064. req->req_q_in = &reg->req_q_in;
  3065. req->req_q_out = &reg->req_q_out;
  3066. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3067. rval = qla2x00_mailbox_command(vha, mcp);
  3068. if (rval != QLA_SUCCESS) {
  3069. ql_dbg(ql_dbg_mbx, vha, 0x10d4,
  3070. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3071. } else {
  3072. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
  3073. "Done %s.\n", __func__);
  3074. }
  3075. return rval;
  3076. }
  3077. int
  3078. qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
  3079. {
  3080. int rval;
  3081. unsigned long flags;
  3082. mbx_cmd_t mc;
  3083. mbx_cmd_t *mcp = &mc;
  3084. struct device_reg_25xxmq __iomem *reg;
  3085. struct qla_hw_data *ha = vha->hw;
  3086. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
  3087. "Entered %s.\n", __func__);
  3088. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3089. mcp->mb[1] = rsp->options;
  3090. mcp->mb[2] = MSW(LSD(rsp->dma));
  3091. mcp->mb[3] = LSW(LSD(rsp->dma));
  3092. mcp->mb[6] = MSW(MSD(rsp->dma));
  3093. mcp->mb[7] = LSW(MSD(rsp->dma));
  3094. mcp->mb[5] = rsp->length;
  3095. mcp->mb[14] = rsp->msix->entry;
  3096. mcp->mb[13] = rsp->rid;
  3097. if (IS_QLA83XX(ha))
  3098. mcp->mb[15] = 0;
  3099. reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
  3100. QLA_QUE_PAGE * rsp->id);
  3101. mcp->mb[4] = rsp->id;
  3102. /* que in ptr index */
  3103. mcp->mb[8] = 0;
  3104. /* que out ptr index */
  3105. mcp->mb[9] = 0;
  3106. mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
  3107. |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3108. mcp->in_mb = MBX_0;
  3109. mcp->flags = MBX_DMA_OUT;
  3110. mcp->tov = MBX_TOV_SECONDS * 2;
  3111. if (IS_QLA81XX(ha)) {
  3112. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  3113. mcp->in_mb |= MBX_1;
  3114. } else if (IS_QLA83XX(ha)) {
  3115. mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
  3116. mcp->in_mb |= MBX_1;
  3117. /* debug q create issue in SR-IOV */
  3118. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3119. }
  3120. spin_lock_irqsave(&ha->hardware_lock, flags);
  3121. if (!(rsp->options & BIT_0)) {
  3122. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  3123. if (!IS_QLA83XX(ha))
  3124. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  3125. }
  3126. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3127. rval = qla2x00_mailbox_command(vha, mcp);
  3128. if (rval != QLA_SUCCESS) {
  3129. ql_dbg(ql_dbg_mbx, vha, 0x10d7,
  3130. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3131. } else {
  3132. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
  3133. "Done %s.\n", __func__);
  3134. }
  3135. return rval;
  3136. }
  3137. int
  3138. qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
  3139. {
  3140. int rval;
  3141. mbx_cmd_t mc;
  3142. mbx_cmd_t *mcp = &mc;
  3143. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
  3144. "Entered %s.\n", __func__);
  3145. mcp->mb[0] = MBC_IDC_ACK;
  3146. memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  3147. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3148. mcp->in_mb = MBX_0;
  3149. mcp->tov = MBX_TOV_SECONDS;
  3150. mcp->flags = 0;
  3151. rval = qla2x00_mailbox_command(vha, mcp);
  3152. if (rval != QLA_SUCCESS) {
  3153. ql_dbg(ql_dbg_mbx, vha, 0x10da,
  3154. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3155. } else {
  3156. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
  3157. "Done %s.\n", __func__);
  3158. }
  3159. return rval;
  3160. }
  3161. int
  3162. qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
  3163. {
  3164. int rval;
  3165. mbx_cmd_t mc;
  3166. mbx_cmd_t *mcp = &mc;
  3167. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
  3168. "Entered %s.\n", __func__);
  3169. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3170. return QLA_FUNCTION_FAILED;
  3171. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3172. mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
  3173. mcp->out_mb = MBX_1|MBX_0;
  3174. mcp->in_mb = MBX_1|MBX_0;
  3175. mcp->tov = MBX_TOV_SECONDS;
  3176. mcp->flags = 0;
  3177. rval = qla2x00_mailbox_command(vha, mcp);
  3178. if (rval != QLA_SUCCESS) {
  3179. ql_dbg(ql_dbg_mbx, vha, 0x10dd,
  3180. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3181. rval, mcp->mb[0], mcp->mb[1]);
  3182. } else {
  3183. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
  3184. "Done %s.\n", __func__);
  3185. *sector_size = mcp->mb[1];
  3186. }
  3187. return rval;
  3188. }
  3189. int
  3190. qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
  3191. {
  3192. int rval;
  3193. mbx_cmd_t mc;
  3194. mbx_cmd_t *mcp = &mc;
  3195. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3196. return QLA_FUNCTION_FAILED;
  3197. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
  3198. "Entered %s.\n", __func__);
  3199. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3200. mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
  3201. FAC_OPT_CMD_WRITE_PROTECT;
  3202. mcp->out_mb = MBX_1|MBX_0;
  3203. mcp->in_mb = MBX_1|MBX_0;
  3204. mcp->tov = MBX_TOV_SECONDS;
  3205. mcp->flags = 0;
  3206. rval = qla2x00_mailbox_command(vha, mcp);
  3207. if (rval != QLA_SUCCESS) {
  3208. ql_dbg(ql_dbg_mbx, vha, 0x10e0,
  3209. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3210. rval, mcp->mb[0], mcp->mb[1]);
  3211. } else {
  3212. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
  3213. "Done %s.\n", __func__);
  3214. }
  3215. return rval;
  3216. }
  3217. int
  3218. qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
  3219. {
  3220. int rval;
  3221. mbx_cmd_t mc;
  3222. mbx_cmd_t *mcp = &mc;
  3223. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3224. return QLA_FUNCTION_FAILED;
  3225. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
  3226. "Entered %s.\n", __func__);
  3227. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3228. mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
  3229. mcp->mb[2] = LSW(start);
  3230. mcp->mb[3] = MSW(start);
  3231. mcp->mb[4] = LSW(finish);
  3232. mcp->mb[5] = MSW(finish);
  3233. mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3234. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3235. mcp->tov = MBX_TOV_SECONDS;
  3236. mcp->flags = 0;
  3237. rval = qla2x00_mailbox_command(vha, mcp);
  3238. if (rval != QLA_SUCCESS) {
  3239. ql_dbg(ql_dbg_mbx, vha, 0x10e3,
  3240. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3241. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3242. } else {
  3243. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
  3244. "Done %s.\n", __func__);
  3245. }
  3246. return rval;
  3247. }
  3248. int
  3249. qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
  3250. {
  3251. int rval = 0;
  3252. mbx_cmd_t mc;
  3253. mbx_cmd_t *mcp = &mc;
  3254. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
  3255. "Entered %s.\n", __func__);
  3256. mcp->mb[0] = MBC_RESTART_MPI_FW;
  3257. mcp->out_mb = MBX_0;
  3258. mcp->in_mb = MBX_0|MBX_1;
  3259. mcp->tov = MBX_TOV_SECONDS;
  3260. mcp->flags = 0;
  3261. rval = qla2x00_mailbox_command(vha, mcp);
  3262. if (rval != QLA_SUCCESS) {
  3263. ql_dbg(ql_dbg_mbx, vha, 0x10e6,
  3264. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3265. rval, mcp->mb[0], mcp->mb[1]);
  3266. } else {
  3267. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
  3268. "Done %s.\n", __func__);
  3269. }
  3270. return rval;
  3271. }
  3272. int
  3273. qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3274. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3275. {
  3276. int rval;
  3277. mbx_cmd_t mc;
  3278. mbx_cmd_t *mcp = &mc;
  3279. struct qla_hw_data *ha = vha->hw;
  3280. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
  3281. "Entered %s.\n", __func__);
  3282. if (!IS_FWI2_CAPABLE(ha))
  3283. return QLA_FUNCTION_FAILED;
  3284. if (len == 1)
  3285. opt |= BIT_0;
  3286. mcp->mb[0] = MBC_READ_SFP;
  3287. mcp->mb[1] = dev;
  3288. mcp->mb[2] = MSW(sfp_dma);
  3289. mcp->mb[3] = LSW(sfp_dma);
  3290. mcp->mb[6] = MSW(MSD(sfp_dma));
  3291. mcp->mb[7] = LSW(MSD(sfp_dma));
  3292. mcp->mb[8] = len;
  3293. mcp->mb[9] = off;
  3294. mcp->mb[10] = opt;
  3295. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3296. mcp->in_mb = MBX_1|MBX_0;
  3297. mcp->tov = MBX_TOV_SECONDS;
  3298. mcp->flags = 0;
  3299. rval = qla2x00_mailbox_command(vha, mcp);
  3300. if (opt & BIT_0)
  3301. *sfp = mcp->mb[1];
  3302. if (rval != QLA_SUCCESS) {
  3303. ql_dbg(ql_dbg_mbx, vha, 0x10e9,
  3304. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3305. } else {
  3306. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
  3307. "Done %s.\n", __func__);
  3308. }
  3309. return rval;
  3310. }
  3311. int
  3312. qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3313. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3314. {
  3315. int rval;
  3316. mbx_cmd_t mc;
  3317. mbx_cmd_t *mcp = &mc;
  3318. struct qla_hw_data *ha = vha->hw;
  3319. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
  3320. "Entered %s.\n", __func__);
  3321. if (!IS_FWI2_CAPABLE(ha))
  3322. return QLA_FUNCTION_FAILED;
  3323. if (len == 1)
  3324. opt |= BIT_0;
  3325. if (opt & BIT_0)
  3326. len = *sfp;
  3327. mcp->mb[0] = MBC_WRITE_SFP;
  3328. mcp->mb[1] = dev;
  3329. mcp->mb[2] = MSW(sfp_dma);
  3330. mcp->mb[3] = LSW(sfp_dma);
  3331. mcp->mb[6] = MSW(MSD(sfp_dma));
  3332. mcp->mb[7] = LSW(MSD(sfp_dma));
  3333. mcp->mb[8] = len;
  3334. mcp->mb[9] = off;
  3335. mcp->mb[10] = opt;
  3336. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3337. mcp->in_mb = MBX_1|MBX_0;
  3338. mcp->tov = MBX_TOV_SECONDS;
  3339. mcp->flags = 0;
  3340. rval = qla2x00_mailbox_command(vha, mcp);
  3341. if (rval != QLA_SUCCESS) {
  3342. ql_dbg(ql_dbg_mbx, vha, 0x10ec,
  3343. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3344. } else {
  3345. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
  3346. "Done %s.\n", __func__);
  3347. }
  3348. return rval;
  3349. }
  3350. int
  3351. qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
  3352. uint16_t size_in_bytes, uint16_t *actual_size)
  3353. {
  3354. int rval;
  3355. mbx_cmd_t mc;
  3356. mbx_cmd_t *mcp = &mc;
  3357. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
  3358. "Entered %s.\n", __func__);
  3359. if (!IS_CNA_CAPABLE(vha->hw))
  3360. return QLA_FUNCTION_FAILED;
  3361. mcp->mb[0] = MBC_GET_XGMAC_STATS;
  3362. mcp->mb[2] = MSW(stats_dma);
  3363. mcp->mb[3] = LSW(stats_dma);
  3364. mcp->mb[6] = MSW(MSD(stats_dma));
  3365. mcp->mb[7] = LSW(MSD(stats_dma));
  3366. mcp->mb[8] = size_in_bytes >> 2;
  3367. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  3368. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3369. mcp->tov = MBX_TOV_SECONDS;
  3370. mcp->flags = 0;
  3371. rval = qla2x00_mailbox_command(vha, mcp);
  3372. if (rval != QLA_SUCCESS) {
  3373. ql_dbg(ql_dbg_mbx, vha, 0x10ef,
  3374. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3375. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3376. } else {
  3377. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
  3378. "Done %s.\n", __func__);
  3379. *actual_size = mcp->mb[2] << 2;
  3380. }
  3381. return rval;
  3382. }
  3383. int
  3384. qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
  3385. uint16_t size)
  3386. {
  3387. int rval;
  3388. mbx_cmd_t mc;
  3389. mbx_cmd_t *mcp = &mc;
  3390. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
  3391. "Entered %s.\n", __func__);
  3392. if (!IS_CNA_CAPABLE(vha->hw))
  3393. return QLA_FUNCTION_FAILED;
  3394. mcp->mb[0] = MBC_GET_DCBX_PARAMS;
  3395. mcp->mb[1] = 0;
  3396. mcp->mb[2] = MSW(tlv_dma);
  3397. mcp->mb[3] = LSW(tlv_dma);
  3398. mcp->mb[6] = MSW(MSD(tlv_dma));
  3399. mcp->mb[7] = LSW(MSD(tlv_dma));
  3400. mcp->mb[8] = size;
  3401. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3402. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3403. mcp->tov = MBX_TOV_SECONDS;
  3404. mcp->flags = 0;
  3405. rval = qla2x00_mailbox_command(vha, mcp);
  3406. if (rval != QLA_SUCCESS) {
  3407. ql_dbg(ql_dbg_mbx, vha, 0x10f2,
  3408. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3409. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3410. } else {
  3411. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
  3412. "Done %s.\n", __func__);
  3413. }
  3414. return rval;
  3415. }
  3416. int
  3417. qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
  3418. {
  3419. int rval;
  3420. mbx_cmd_t mc;
  3421. mbx_cmd_t *mcp = &mc;
  3422. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
  3423. "Entered %s.\n", __func__);
  3424. if (!IS_FWI2_CAPABLE(vha->hw))
  3425. return QLA_FUNCTION_FAILED;
  3426. mcp->mb[0] = MBC_READ_RAM_EXTENDED;
  3427. mcp->mb[1] = LSW(risc_addr);
  3428. mcp->mb[8] = MSW(risc_addr);
  3429. mcp->out_mb = MBX_8|MBX_1|MBX_0;
  3430. mcp->in_mb = MBX_3|MBX_2|MBX_0;
  3431. mcp->tov = 30;
  3432. mcp->flags = 0;
  3433. rval = qla2x00_mailbox_command(vha, mcp);
  3434. if (rval != QLA_SUCCESS) {
  3435. ql_dbg(ql_dbg_mbx, vha, 0x10f5,
  3436. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3437. } else {
  3438. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
  3439. "Done %s.\n", __func__);
  3440. *data = mcp->mb[3] << 16 | mcp->mb[2];
  3441. }
  3442. return rval;
  3443. }
  3444. int
  3445. qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3446. uint16_t *mresp)
  3447. {
  3448. int rval;
  3449. mbx_cmd_t mc;
  3450. mbx_cmd_t *mcp = &mc;
  3451. uint32_t iter_cnt = 0x1;
  3452. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
  3453. "Entered %s.\n", __func__);
  3454. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3455. mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
  3456. mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
  3457. /* transfer count */
  3458. mcp->mb[10] = LSW(mreq->transfer_size);
  3459. mcp->mb[11] = MSW(mreq->transfer_size);
  3460. /* send data address */
  3461. mcp->mb[14] = LSW(mreq->send_dma);
  3462. mcp->mb[15] = MSW(mreq->send_dma);
  3463. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3464. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3465. /* receive data address */
  3466. mcp->mb[16] = LSW(mreq->rcv_dma);
  3467. mcp->mb[17] = MSW(mreq->rcv_dma);
  3468. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3469. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3470. /* Iteration count */
  3471. mcp->mb[18] = LSW(iter_cnt);
  3472. mcp->mb[19] = MSW(iter_cnt);
  3473. mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
  3474. MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3475. if (IS_CNA_CAPABLE(vha->hw))
  3476. mcp->out_mb |= MBX_2;
  3477. mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
  3478. mcp->buf_size = mreq->transfer_size;
  3479. mcp->tov = MBX_TOV_SECONDS;
  3480. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3481. rval = qla2x00_mailbox_command(vha, mcp);
  3482. if (rval != QLA_SUCCESS) {
  3483. ql_dbg(ql_dbg_mbx, vha, 0x10f8,
  3484. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
  3485. "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
  3486. mcp->mb[3], mcp->mb[18], mcp->mb[19]);
  3487. } else {
  3488. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
  3489. "Done %s.\n", __func__);
  3490. }
  3491. /* Copy mailbox information */
  3492. memcpy( mresp, mcp->mb, 64);
  3493. return rval;
  3494. }
  3495. int
  3496. qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3497. uint16_t *mresp)
  3498. {
  3499. int rval;
  3500. mbx_cmd_t mc;
  3501. mbx_cmd_t *mcp = &mc;
  3502. struct qla_hw_data *ha = vha->hw;
  3503. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
  3504. "Entered %s.\n", __func__);
  3505. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3506. mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
  3507. mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
  3508. if (IS_CNA_CAPABLE(ha)) {
  3509. mcp->mb[1] |= BIT_15;
  3510. mcp->mb[2] = vha->fcoe_fcf_idx;
  3511. }
  3512. mcp->mb[16] = LSW(mreq->rcv_dma);
  3513. mcp->mb[17] = MSW(mreq->rcv_dma);
  3514. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3515. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3516. mcp->mb[10] = LSW(mreq->transfer_size);
  3517. mcp->mb[14] = LSW(mreq->send_dma);
  3518. mcp->mb[15] = MSW(mreq->send_dma);
  3519. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3520. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3521. mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
  3522. MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3523. if (IS_CNA_CAPABLE(ha))
  3524. mcp->out_mb |= MBX_2;
  3525. mcp->in_mb = MBX_0;
  3526. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
  3527. IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3528. mcp->in_mb |= MBX_1;
  3529. if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3530. mcp->in_mb |= MBX_3;
  3531. mcp->tov = MBX_TOV_SECONDS;
  3532. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3533. mcp->buf_size = mreq->transfer_size;
  3534. rval = qla2x00_mailbox_command(vha, mcp);
  3535. if (rval != QLA_SUCCESS) {
  3536. ql_dbg(ql_dbg_mbx, vha, 0x10fb,
  3537. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3538. rval, mcp->mb[0], mcp->mb[1]);
  3539. } else {
  3540. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
  3541. "Done %s.\n", __func__);
  3542. }
  3543. /* Copy mailbox information */
  3544. memcpy(mresp, mcp->mb, 64);
  3545. return rval;
  3546. }
  3547. int
  3548. qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
  3549. {
  3550. int rval;
  3551. mbx_cmd_t mc;
  3552. mbx_cmd_t *mcp = &mc;
  3553. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
  3554. "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
  3555. mcp->mb[0] = MBC_ISP84XX_RESET;
  3556. mcp->mb[1] = enable_diagnostic;
  3557. mcp->out_mb = MBX_1|MBX_0;
  3558. mcp->in_mb = MBX_1|MBX_0;
  3559. mcp->tov = MBX_TOV_SECONDS;
  3560. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3561. rval = qla2x00_mailbox_command(vha, mcp);
  3562. if (rval != QLA_SUCCESS)
  3563. ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
  3564. else
  3565. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
  3566. "Done %s.\n", __func__);
  3567. return rval;
  3568. }
  3569. int
  3570. qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
  3571. {
  3572. int rval;
  3573. mbx_cmd_t mc;
  3574. mbx_cmd_t *mcp = &mc;
  3575. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
  3576. "Entered %s.\n", __func__);
  3577. if (!IS_FWI2_CAPABLE(vha->hw))
  3578. return QLA_FUNCTION_FAILED;
  3579. mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
  3580. mcp->mb[1] = LSW(risc_addr);
  3581. mcp->mb[2] = LSW(data);
  3582. mcp->mb[3] = MSW(data);
  3583. mcp->mb[8] = MSW(risc_addr);
  3584. mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
  3585. mcp->in_mb = MBX_0;
  3586. mcp->tov = 30;
  3587. mcp->flags = 0;
  3588. rval = qla2x00_mailbox_command(vha, mcp);
  3589. if (rval != QLA_SUCCESS) {
  3590. ql_dbg(ql_dbg_mbx, vha, 0x1101,
  3591. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3592. } else {
  3593. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
  3594. "Done %s.\n", __func__);
  3595. }
  3596. return rval;
  3597. }
  3598. int
  3599. qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
  3600. {
  3601. int rval;
  3602. uint32_t stat, timer;
  3603. uint16_t mb0 = 0;
  3604. struct qla_hw_data *ha = vha->hw;
  3605. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3606. rval = QLA_SUCCESS;
  3607. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
  3608. "Entered %s.\n", __func__);
  3609. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  3610. /* Write the MBC data to the registers */
  3611. WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
  3612. WRT_REG_WORD(&reg->mailbox1, mb[0]);
  3613. WRT_REG_WORD(&reg->mailbox2, mb[1]);
  3614. WRT_REG_WORD(&reg->mailbox3, mb[2]);
  3615. WRT_REG_WORD(&reg->mailbox4, mb[3]);
  3616. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
  3617. /* Poll for MBC interrupt */
  3618. for (timer = 6000000; timer; timer--) {
  3619. /* Check for pending interrupts. */
  3620. stat = RD_REG_DWORD(&reg->host_status);
  3621. if (stat & HSRX_RISC_INT) {
  3622. stat &= 0xff;
  3623. if (stat == 0x1 || stat == 0x2 ||
  3624. stat == 0x10 || stat == 0x11) {
  3625. set_bit(MBX_INTERRUPT,
  3626. &ha->mbx_cmd_flags);
  3627. mb0 = RD_REG_WORD(&reg->mailbox0);
  3628. WRT_REG_DWORD(&reg->hccr,
  3629. HCCRX_CLR_RISC_INT);
  3630. RD_REG_DWORD(&reg->hccr);
  3631. break;
  3632. }
  3633. }
  3634. udelay(5);
  3635. }
  3636. if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
  3637. rval = mb0 & MBS_MASK;
  3638. else
  3639. rval = QLA_FUNCTION_FAILED;
  3640. if (rval != QLA_SUCCESS) {
  3641. ql_dbg(ql_dbg_mbx, vha, 0x1104,
  3642. "Failed=%x mb[0]=%x.\n", rval, mb[0]);
  3643. } else {
  3644. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
  3645. "Done %s.\n", __func__);
  3646. }
  3647. return rval;
  3648. }
  3649. int
  3650. qla2x00_get_data_rate(scsi_qla_host_t *vha)
  3651. {
  3652. int rval;
  3653. mbx_cmd_t mc;
  3654. mbx_cmd_t *mcp = &mc;
  3655. struct qla_hw_data *ha = vha->hw;
  3656. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
  3657. "Entered %s.\n", __func__);
  3658. if (!IS_FWI2_CAPABLE(ha))
  3659. return QLA_FUNCTION_FAILED;
  3660. mcp->mb[0] = MBC_DATA_RATE;
  3661. mcp->mb[1] = 0;
  3662. mcp->out_mb = MBX_1|MBX_0;
  3663. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3664. if (IS_QLA83XX(ha))
  3665. mcp->in_mb |= MBX_3;
  3666. mcp->tov = MBX_TOV_SECONDS;
  3667. mcp->flags = 0;
  3668. rval = qla2x00_mailbox_command(vha, mcp);
  3669. if (rval != QLA_SUCCESS) {
  3670. ql_dbg(ql_dbg_mbx, vha, 0x1107,
  3671. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3672. } else {
  3673. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
  3674. "Done %s.\n", __func__);
  3675. if (mcp->mb[1] != 0x7)
  3676. ha->link_data_rate = mcp->mb[1];
  3677. }
  3678. return rval;
  3679. }
  3680. int
  3681. qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3682. {
  3683. int rval;
  3684. mbx_cmd_t mc;
  3685. mbx_cmd_t *mcp = &mc;
  3686. struct qla_hw_data *ha = vha->hw;
  3687. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
  3688. "Entered %s.\n", __func__);
  3689. if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  3690. return QLA_FUNCTION_FAILED;
  3691. mcp->mb[0] = MBC_GET_PORT_CONFIG;
  3692. mcp->out_mb = MBX_0;
  3693. mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3694. mcp->tov = MBX_TOV_SECONDS;
  3695. mcp->flags = 0;
  3696. rval = qla2x00_mailbox_command(vha, mcp);
  3697. if (rval != QLA_SUCCESS) {
  3698. ql_dbg(ql_dbg_mbx, vha, 0x110a,
  3699. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3700. } else {
  3701. /* Copy all bits to preserve original value */
  3702. memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
  3703. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
  3704. "Done %s.\n", __func__);
  3705. }
  3706. return rval;
  3707. }
  3708. int
  3709. qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3710. {
  3711. int rval;
  3712. mbx_cmd_t mc;
  3713. mbx_cmd_t *mcp = &mc;
  3714. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
  3715. "Entered %s.\n", __func__);
  3716. mcp->mb[0] = MBC_SET_PORT_CONFIG;
  3717. /* Copy all bits to preserve original setting */
  3718. memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
  3719. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3720. mcp->in_mb = MBX_0;
  3721. mcp->tov = MBX_TOV_SECONDS;
  3722. mcp->flags = 0;
  3723. rval = qla2x00_mailbox_command(vha, mcp);
  3724. if (rval != QLA_SUCCESS) {
  3725. ql_dbg(ql_dbg_mbx, vha, 0x110d,
  3726. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3727. } else
  3728. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
  3729. "Done %s.\n", __func__);
  3730. return rval;
  3731. }
  3732. int
  3733. qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
  3734. uint16_t *mb)
  3735. {
  3736. int rval;
  3737. mbx_cmd_t mc;
  3738. mbx_cmd_t *mcp = &mc;
  3739. struct qla_hw_data *ha = vha->hw;
  3740. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
  3741. "Entered %s.\n", __func__);
  3742. if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
  3743. return QLA_FUNCTION_FAILED;
  3744. mcp->mb[0] = MBC_PORT_PARAMS;
  3745. mcp->mb[1] = loop_id;
  3746. if (ha->flags.fcp_prio_enabled)
  3747. mcp->mb[2] = BIT_1;
  3748. else
  3749. mcp->mb[2] = BIT_2;
  3750. mcp->mb[4] = priority & 0xf;
  3751. mcp->mb[9] = vha->vp_idx;
  3752. mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3753. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  3754. mcp->tov = 30;
  3755. mcp->flags = 0;
  3756. rval = qla2x00_mailbox_command(vha, mcp);
  3757. if (mb != NULL) {
  3758. mb[0] = mcp->mb[0];
  3759. mb[1] = mcp->mb[1];
  3760. mb[3] = mcp->mb[3];
  3761. mb[4] = mcp->mb[4];
  3762. }
  3763. if (rval != QLA_SUCCESS) {
  3764. ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
  3765. } else {
  3766. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
  3767. "Done %s.\n", __func__);
  3768. }
  3769. return rval;
  3770. }
  3771. int
  3772. qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp, uint16_t *frac)
  3773. {
  3774. int rval;
  3775. uint8_t byte;
  3776. struct qla_hw_data *ha = vha->hw;
  3777. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ca,
  3778. "Entered %s.\n", __func__);
  3779. /* Integer part */
  3780. rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x01, 1, BIT_13|BIT_0);
  3781. if (rval != QLA_SUCCESS) {
  3782. ql_dbg(ql_dbg_mbx, vha, 0x10c9, "Failed=%x.\n", rval);
  3783. ha->flags.thermal_supported = 0;
  3784. goto fail;
  3785. }
  3786. *temp = byte;
  3787. /* Fraction part */
  3788. rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x10, 1, BIT_13|BIT_0);
  3789. if (rval != QLA_SUCCESS) {
  3790. ql_dbg(ql_dbg_mbx, vha, 0x1019, "Failed=%x.\n", rval);
  3791. ha->flags.thermal_supported = 0;
  3792. goto fail;
  3793. }
  3794. *frac = (byte >> 6) * 25;
  3795. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1018,
  3796. "Done %s.\n", __func__);
  3797. fail:
  3798. return rval;
  3799. }
  3800. int
  3801. qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
  3802. {
  3803. int rval;
  3804. struct qla_hw_data *ha = vha->hw;
  3805. mbx_cmd_t mc;
  3806. mbx_cmd_t *mcp = &mc;
  3807. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
  3808. "Entered %s.\n", __func__);
  3809. if (!IS_FWI2_CAPABLE(ha))
  3810. return QLA_FUNCTION_FAILED;
  3811. memset(mcp, 0, sizeof(mbx_cmd_t));
  3812. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  3813. mcp->mb[1] = 1;
  3814. mcp->out_mb = MBX_1|MBX_0;
  3815. mcp->in_mb = MBX_0;
  3816. mcp->tov = 30;
  3817. mcp->flags = 0;
  3818. rval = qla2x00_mailbox_command(vha, mcp);
  3819. if (rval != QLA_SUCCESS) {
  3820. ql_dbg(ql_dbg_mbx, vha, 0x1016,
  3821. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3822. } else {
  3823. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
  3824. "Done %s.\n", __func__);
  3825. }
  3826. return rval;
  3827. }
  3828. int
  3829. qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
  3830. {
  3831. int rval;
  3832. struct qla_hw_data *ha = vha->hw;
  3833. mbx_cmd_t mc;
  3834. mbx_cmd_t *mcp = &mc;
  3835. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
  3836. "Entered %s.\n", __func__);
  3837. if (!IS_QLA82XX(ha))
  3838. return QLA_FUNCTION_FAILED;
  3839. memset(mcp, 0, sizeof(mbx_cmd_t));
  3840. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  3841. mcp->mb[1] = 0;
  3842. mcp->out_mb = MBX_1|MBX_0;
  3843. mcp->in_mb = MBX_0;
  3844. mcp->tov = 30;
  3845. mcp->flags = 0;
  3846. rval = qla2x00_mailbox_command(vha, mcp);
  3847. if (rval != QLA_SUCCESS) {
  3848. ql_dbg(ql_dbg_mbx, vha, 0x100c,
  3849. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3850. } else {
  3851. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
  3852. "Done %s.\n", __func__);
  3853. }
  3854. return rval;
  3855. }
  3856. int
  3857. qla82xx_md_get_template_size(scsi_qla_host_t *vha)
  3858. {
  3859. struct qla_hw_data *ha = vha->hw;
  3860. mbx_cmd_t mc;
  3861. mbx_cmd_t *mcp = &mc;
  3862. int rval = QLA_FUNCTION_FAILED;
  3863. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
  3864. "Entered %s.\n", __func__);
  3865. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3866. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3867. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3868. mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
  3869. mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
  3870. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  3871. mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  3872. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3873. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3874. mcp->tov = MBX_TOV_SECONDS;
  3875. rval = qla2x00_mailbox_command(vha, mcp);
  3876. /* Always copy back return mailbox values. */
  3877. if (rval != QLA_SUCCESS) {
  3878. ql_dbg(ql_dbg_mbx, vha, 0x1120,
  3879. "mailbox command FAILED=0x%x, subcode=%x.\n",
  3880. (mcp->mb[1] << 16) | mcp->mb[0],
  3881. (mcp->mb[3] << 16) | mcp->mb[2]);
  3882. } else {
  3883. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
  3884. "Done %s.\n", __func__);
  3885. ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
  3886. if (!ha->md_template_size) {
  3887. ql_dbg(ql_dbg_mbx, vha, 0x1122,
  3888. "Null template size obtained.\n");
  3889. rval = QLA_FUNCTION_FAILED;
  3890. }
  3891. }
  3892. return rval;
  3893. }
  3894. int
  3895. qla82xx_md_get_template(scsi_qla_host_t *vha)
  3896. {
  3897. struct qla_hw_data *ha = vha->hw;
  3898. mbx_cmd_t mc;
  3899. mbx_cmd_t *mcp = &mc;
  3900. int rval = QLA_FUNCTION_FAILED;
  3901. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
  3902. "Entered %s.\n", __func__);
  3903. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  3904. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  3905. if (!ha->md_tmplt_hdr) {
  3906. ql_log(ql_log_warn, vha, 0x1124,
  3907. "Unable to allocate memory for Minidump template.\n");
  3908. return rval;
  3909. }
  3910. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3911. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3912. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3913. mcp->mb[2] = LSW(RQST_TMPLT);
  3914. mcp->mb[3] = MSW(RQST_TMPLT);
  3915. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
  3916. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
  3917. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
  3918. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
  3919. mcp->mb[8] = LSW(ha->md_template_size);
  3920. mcp->mb[9] = MSW(ha->md_template_size);
  3921. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3922. mcp->tov = MBX_TOV_SECONDS;
  3923. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  3924. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3925. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  3926. rval = qla2x00_mailbox_command(vha, mcp);
  3927. if (rval != QLA_SUCCESS) {
  3928. ql_dbg(ql_dbg_mbx, vha, 0x1125,
  3929. "mailbox command FAILED=0x%x, subcode=%x.\n",
  3930. ((mcp->mb[1] << 16) | mcp->mb[0]),
  3931. ((mcp->mb[3] << 16) | mcp->mb[2]));
  3932. } else
  3933. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
  3934. "Done %s.\n", __func__);
  3935. return rval;
  3936. }
  3937. int
  3938. qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  3939. {
  3940. int rval;
  3941. struct qla_hw_data *ha = vha->hw;
  3942. mbx_cmd_t mc;
  3943. mbx_cmd_t *mcp = &mc;
  3944. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  3945. return QLA_FUNCTION_FAILED;
  3946. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
  3947. "Entered %s.\n", __func__);
  3948. memset(mcp, 0, sizeof(mbx_cmd_t));
  3949. mcp->mb[0] = MBC_SET_LED_CONFIG;
  3950. mcp->mb[1] = led_cfg[0];
  3951. mcp->mb[2] = led_cfg[1];
  3952. if (IS_QLA8031(ha)) {
  3953. mcp->mb[3] = led_cfg[2];
  3954. mcp->mb[4] = led_cfg[3];
  3955. mcp->mb[5] = led_cfg[4];
  3956. mcp->mb[6] = led_cfg[5];
  3957. }
  3958. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  3959. if (IS_QLA8031(ha))
  3960. mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  3961. mcp->in_mb = MBX_0;
  3962. mcp->tov = 30;
  3963. mcp->flags = 0;
  3964. rval = qla2x00_mailbox_command(vha, mcp);
  3965. if (rval != QLA_SUCCESS) {
  3966. ql_dbg(ql_dbg_mbx, vha, 0x1134,
  3967. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3968. } else {
  3969. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
  3970. "Done %s.\n", __func__);
  3971. }
  3972. return rval;
  3973. }
  3974. int
  3975. qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  3976. {
  3977. int rval;
  3978. struct qla_hw_data *ha = vha->hw;
  3979. mbx_cmd_t mc;
  3980. mbx_cmd_t *mcp = &mc;
  3981. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  3982. return QLA_FUNCTION_FAILED;
  3983. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
  3984. "Entered %s.\n", __func__);
  3985. memset(mcp, 0, sizeof(mbx_cmd_t));
  3986. mcp->mb[0] = MBC_GET_LED_CONFIG;
  3987. mcp->out_mb = MBX_0;
  3988. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3989. if (IS_QLA8031(ha))
  3990. mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  3991. mcp->tov = 30;
  3992. mcp->flags = 0;
  3993. rval = qla2x00_mailbox_command(vha, mcp);
  3994. if (rval != QLA_SUCCESS) {
  3995. ql_dbg(ql_dbg_mbx, vha, 0x1137,
  3996. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3997. } else {
  3998. led_cfg[0] = mcp->mb[1];
  3999. led_cfg[1] = mcp->mb[2];
  4000. if (IS_QLA8031(ha)) {
  4001. led_cfg[2] = mcp->mb[3];
  4002. led_cfg[3] = mcp->mb[4];
  4003. led_cfg[4] = mcp->mb[5];
  4004. led_cfg[5] = mcp->mb[6];
  4005. }
  4006. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
  4007. "Done %s.\n", __func__);
  4008. }
  4009. return rval;
  4010. }
  4011. int
  4012. qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
  4013. {
  4014. int rval;
  4015. struct qla_hw_data *ha = vha->hw;
  4016. mbx_cmd_t mc;
  4017. mbx_cmd_t *mcp = &mc;
  4018. if (!IS_QLA82XX(ha))
  4019. return QLA_FUNCTION_FAILED;
  4020. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
  4021. "Entered %s.\n", __func__);
  4022. memset(mcp, 0, sizeof(mbx_cmd_t));
  4023. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4024. if (enable)
  4025. mcp->mb[7] = 0xE;
  4026. else
  4027. mcp->mb[7] = 0xD;
  4028. mcp->out_mb = MBX_7|MBX_0;
  4029. mcp->in_mb = MBX_0;
  4030. mcp->tov = MBX_TOV_SECONDS;
  4031. mcp->flags = 0;
  4032. rval = qla2x00_mailbox_command(vha, mcp);
  4033. if (rval != QLA_SUCCESS) {
  4034. ql_dbg(ql_dbg_mbx, vha, 0x1128,
  4035. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4036. } else {
  4037. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
  4038. "Done %s.\n", __func__);
  4039. }
  4040. return rval;
  4041. }
  4042. int
  4043. qla83xx_write_remote_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
  4044. {
  4045. int rval;
  4046. struct qla_hw_data *ha = vha->hw;
  4047. mbx_cmd_t mc;
  4048. mbx_cmd_t *mcp = &mc;
  4049. if (!IS_QLA83XX(ha))
  4050. return QLA_FUNCTION_FAILED;
  4051. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
  4052. "Entered %s.\n", __func__);
  4053. mcp->mb[0] = MBC_WRITE_REMOTE_REG;
  4054. mcp->mb[1] = LSW(reg);
  4055. mcp->mb[2] = MSW(reg);
  4056. mcp->mb[3] = LSW(data);
  4057. mcp->mb[4] = MSW(data);
  4058. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4059. mcp->in_mb = MBX_1|MBX_0;
  4060. mcp->tov = MBX_TOV_SECONDS;
  4061. mcp->flags = 0;
  4062. rval = qla2x00_mailbox_command(vha, mcp);
  4063. if (rval != QLA_SUCCESS) {
  4064. ql_dbg(ql_dbg_mbx, vha, 0x1131,
  4065. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4066. } else {
  4067. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
  4068. "Done %s.\n", __func__);
  4069. }
  4070. return rval;
  4071. }
  4072. int
  4073. qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
  4074. {
  4075. int rval;
  4076. struct qla_hw_data *ha = vha->hw;
  4077. mbx_cmd_t mc;
  4078. mbx_cmd_t *mcp = &mc;
  4079. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  4080. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
  4081. "Implicit LOGO Unsupported.\n");
  4082. return QLA_FUNCTION_FAILED;
  4083. }
  4084. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
  4085. "Entering %s.\n", __func__);
  4086. /* Perform Implicit LOGO. */
  4087. mcp->mb[0] = MBC_PORT_LOGOUT;
  4088. mcp->mb[1] = fcport->loop_id;
  4089. mcp->mb[10] = BIT_15;
  4090. mcp->out_mb = MBX_10|MBX_1|MBX_0;
  4091. mcp->in_mb = MBX_0;
  4092. mcp->tov = MBX_TOV_SECONDS;
  4093. mcp->flags = 0;
  4094. rval = qla2x00_mailbox_command(vha, mcp);
  4095. if (rval != QLA_SUCCESS)
  4096. ql_dbg(ql_dbg_mbx, vha, 0x113d,
  4097. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4098. else
  4099. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
  4100. "Done %s.\n", __func__);
  4101. return rval;
  4102. }