qla_init.c 144 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_gbl.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/vmalloc.h>
  12. #include "qla_devtbl.h"
  13. #ifdef CONFIG_SPARC
  14. #include <asm/prom.h>
  15. #endif
  16. /*
  17. * QLogic ISP2x00 Hardware Support Function Prototypes.
  18. */
  19. static int qla2x00_isp_firmware(scsi_qla_host_t *);
  20. static int qla2x00_setup_chip(scsi_qla_host_t *);
  21. static int qla2x00_init_rings(scsi_qla_host_t *);
  22. static int qla2x00_fw_ready(scsi_qla_host_t *);
  23. static int qla2x00_configure_hba(scsi_qla_host_t *);
  24. static int qla2x00_configure_loop(scsi_qla_host_t *);
  25. static int qla2x00_configure_local_loop(scsi_qla_host_t *);
  26. static int qla2x00_configure_fabric(scsi_qla_host_t *);
  27. static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
  28. static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
  29. uint16_t *);
  30. static int qla2x00_restart_isp(scsi_qla_host_t *);
  31. static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
  32. static int qla84xx_init_chip(scsi_qla_host_t *);
  33. static int qla25xx_init_queues(struct qla_hw_data *);
  34. /* SRB Extensions ---------------------------------------------------------- */
  35. void
  36. qla2x00_sp_timeout(unsigned long __data)
  37. {
  38. srb_t *sp = (srb_t *)__data;
  39. struct srb_iocb *iocb;
  40. fc_port_t *fcport = sp->fcport;
  41. struct qla_hw_data *ha = fcport->vha->hw;
  42. struct req_que *req;
  43. unsigned long flags;
  44. spin_lock_irqsave(&ha->hardware_lock, flags);
  45. req = ha->req_q_map[0];
  46. req->outstanding_cmds[sp->handle] = NULL;
  47. iocb = &sp->u.iocb_cmd;
  48. iocb->timeout(sp);
  49. sp->free(fcport->vha, sp);
  50. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  51. }
  52. void
  53. qla2x00_sp_free(void *data, void *ptr)
  54. {
  55. srb_t *sp = (srb_t *)ptr;
  56. struct srb_iocb *iocb = &sp->u.iocb_cmd;
  57. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  58. del_timer(&iocb->timer);
  59. mempool_free(sp, vha->hw->srb_mempool);
  60. QLA_VHA_MARK_NOT_BUSY(vha);
  61. }
  62. /* Asynchronous Login/Logout Routines -------------------------------------- */
  63. static inline unsigned long
  64. qla2x00_get_async_timeout(struct scsi_qla_host *vha)
  65. {
  66. unsigned long tmo;
  67. struct qla_hw_data *ha = vha->hw;
  68. /* Firmware should use switch negotiated r_a_tov for timeout. */
  69. tmo = ha->r_a_tov / 10 * 2;
  70. if (!IS_FWI2_CAPABLE(ha)) {
  71. /*
  72. * Except for earlier ISPs where the timeout is seeded from the
  73. * initialization control block.
  74. */
  75. tmo = ha->login_timeout;
  76. }
  77. return tmo;
  78. }
  79. static void
  80. qla2x00_async_iocb_timeout(void *data)
  81. {
  82. srb_t *sp = (srb_t *)data;
  83. fc_port_t *fcport = sp->fcport;
  84. ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
  85. "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
  86. sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
  87. fcport->d_id.b.al_pa);
  88. fcport->flags &= ~FCF_ASYNC_SENT;
  89. if (sp->type == SRB_LOGIN_CMD) {
  90. struct srb_iocb *lio = &sp->u.iocb_cmd;
  91. qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
  92. /* Retry as needed. */
  93. lio->u.logio.data[0] = MBS_COMMAND_ERROR;
  94. lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  95. QLA_LOGIO_LOGIN_RETRIED : 0;
  96. qla2x00_post_async_login_done_work(fcport->vha, fcport,
  97. lio->u.logio.data);
  98. }
  99. }
  100. static void
  101. qla2x00_async_login_sp_done(void *data, void *ptr, int res)
  102. {
  103. srb_t *sp = (srb_t *)ptr;
  104. struct srb_iocb *lio = &sp->u.iocb_cmd;
  105. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  106. if (!test_bit(UNLOADING, &vha->dpc_flags))
  107. qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
  108. lio->u.logio.data);
  109. sp->free(sp->fcport->vha, sp);
  110. }
  111. int
  112. qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
  113. uint16_t *data)
  114. {
  115. srb_t *sp;
  116. struct srb_iocb *lio;
  117. int rval;
  118. rval = QLA_FUNCTION_FAILED;
  119. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  120. if (!sp)
  121. goto done;
  122. sp->type = SRB_LOGIN_CMD;
  123. sp->name = "login";
  124. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  125. lio = &sp->u.iocb_cmd;
  126. lio->timeout = qla2x00_async_iocb_timeout;
  127. sp->done = qla2x00_async_login_sp_done;
  128. lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
  129. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  130. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  131. rval = qla2x00_start_sp(sp);
  132. if (rval != QLA_SUCCESS)
  133. goto done_free_sp;
  134. ql_dbg(ql_dbg_disc, vha, 0x2072,
  135. "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
  136. "retries=%d.\n", sp->handle, fcport->loop_id,
  137. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  138. fcport->login_retry);
  139. return rval;
  140. done_free_sp:
  141. sp->free(fcport->vha, sp);
  142. done:
  143. return rval;
  144. }
  145. static void
  146. qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
  147. {
  148. srb_t *sp = (srb_t *)ptr;
  149. struct srb_iocb *lio = &sp->u.iocb_cmd;
  150. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  151. if (!test_bit(UNLOADING, &vha->dpc_flags))
  152. qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
  153. lio->u.logio.data);
  154. sp->free(sp->fcport->vha, sp);
  155. }
  156. int
  157. qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
  158. {
  159. srb_t *sp;
  160. struct srb_iocb *lio;
  161. int rval;
  162. rval = QLA_FUNCTION_FAILED;
  163. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  164. if (!sp)
  165. goto done;
  166. sp->type = SRB_LOGOUT_CMD;
  167. sp->name = "logout";
  168. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  169. lio = &sp->u.iocb_cmd;
  170. lio->timeout = qla2x00_async_iocb_timeout;
  171. sp->done = qla2x00_async_logout_sp_done;
  172. rval = qla2x00_start_sp(sp);
  173. if (rval != QLA_SUCCESS)
  174. goto done_free_sp;
  175. ql_dbg(ql_dbg_disc, vha, 0x2070,
  176. "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  177. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  178. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  179. return rval;
  180. done_free_sp:
  181. sp->free(fcport->vha, sp);
  182. done:
  183. return rval;
  184. }
  185. static void
  186. qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
  187. {
  188. srb_t *sp = (srb_t *)ptr;
  189. struct srb_iocb *lio = &sp->u.iocb_cmd;
  190. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  191. if (!test_bit(UNLOADING, &vha->dpc_flags))
  192. qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
  193. lio->u.logio.data);
  194. sp->free(sp->fcport->vha, sp);
  195. }
  196. int
  197. qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
  198. uint16_t *data)
  199. {
  200. srb_t *sp;
  201. struct srb_iocb *lio;
  202. int rval;
  203. rval = QLA_FUNCTION_FAILED;
  204. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  205. if (!sp)
  206. goto done;
  207. sp->type = SRB_ADISC_CMD;
  208. sp->name = "adisc";
  209. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  210. lio = &sp->u.iocb_cmd;
  211. lio->timeout = qla2x00_async_iocb_timeout;
  212. sp->done = qla2x00_async_adisc_sp_done;
  213. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  214. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  215. rval = qla2x00_start_sp(sp);
  216. if (rval != QLA_SUCCESS)
  217. goto done_free_sp;
  218. ql_dbg(ql_dbg_disc, vha, 0x206f,
  219. "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
  220. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  221. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  222. return rval;
  223. done_free_sp:
  224. sp->free(fcport->vha, sp);
  225. done:
  226. return rval;
  227. }
  228. static void
  229. qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
  230. {
  231. srb_t *sp = (srb_t *)ptr;
  232. struct srb_iocb *iocb = &sp->u.iocb_cmd;
  233. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  234. uint32_t flags;
  235. uint16_t lun;
  236. int rval;
  237. if (!test_bit(UNLOADING, &vha->dpc_flags)) {
  238. flags = iocb->u.tmf.flags;
  239. lun = (uint16_t)iocb->u.tmf.lun;
  240. /* Issue Marker IOCB */
  241. rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
  242. vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
  243. flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
  244. if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
  245. ql_dbg(ql_dbg_taskm, vha, 0x8030,
  246. "TM IOCB failed (%x).\n", rval);
  247. }
  248. }
  249. sp->free(sp->fcport->vha, sp);
  250. }
  251. int
  252. qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
  253. uint32_t tag)
  254. {
  255. struct scsi_qla_host *vha = fcport->vha;
  256. srb_t *sp;
  257. struct srb_iocb *tcf;
  258. int rval;
  259. rval = QLA_FUNCTION_FAILED;
  260. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  261. if (!sp)
  262. goto done;
  263. sp->type = SRB_TM_CMD;
  264. sp->name = "tmf";
  265. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  266. tcf = &sp->u.iocb_cmd;
  267. tcf->u.tmf.flags = tm_flags;
  268. tcf->u.tmf.lun = lun;
  269. tcf->u.tmf.data = tag;
  270. tcf->timeout = qla2x00_async_iocb_timeout;
  271. sp->done = qla2x00_async_tm_cmd_done;
  272. rval = qla2x00_start_sp(sp);
  273. if (rval != QLA_SUCCESS)
  274. goto done_free_sp;
  275. ql_dbg(ql_dbg_taskm, vha, 0x802f,
  276. "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  277. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  278. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  279. return rval;
  280. done_free_sp:
  281. sp->free(fcport->vha, sp);
  282. done:
  283. return rval;
  284. }
  285. void
  286. qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  287. uint16_t *data)
  288. {
  289. int rval;
  290. switch (data[0]) {
  291. case MBS_COMMAND_COMPLETE:
  292. /*
  293. * Driver must validate login state - If PRLI not complete,
  294. * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
  295. * requests.
  296. */
  297. rval = qla2x00_get_port_database(vha, fcport, 0);
  298. if (rval == QLA_NOT_LOGGED_IN) {
  299. fcport->flags &= ~FCF_ASYNC_SENT;
  300. fcport->flags |= FCF_LOGIN_NEEDED;
  301. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  302. break;
  303. }
  304. if (rval != QLA_SUCCESS) {
  305. qla2x00_post_async_logout_work(vha, fcport, NULL);
  306. qla2x00_post_async_login_work(vha, fcport, NULL);
  307. break;
  308. }
  309. if (fcport->flags & FCF_FCP2_DEVICE) {
  310. qla2x00_post_async_adisc_work(vha, fcport, data);
  311. break;
  312. }
  313. qla2x00_update_fcport(vha, fcport);
  314. break;
  315. case MBS_COMMAND_ERROR:
  316. fcport->flags &= ~FCF_ASYNC_SENT;
  317. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  318. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  319. else
  320. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  321. break;
  322. case MBS_PORT_ID_USED:
  323. fcport->loop_id = data[1];
  324. qla2x00_post_async_logout_work(vha, fcport, NULL);
  325. qla2x00_post_async_login_work(vha, fcport, NULL);
  326. break;
  327. case MBS_LOOP_ID_USED:
  328. fcport->loop_id++;
  329. rval = qla2x00_find_new_loop_id(vha, fcport);
  330. if (rval != QLA_SUCCESS) {
  331. fcport->flags &= ~FCF_ASYNC_SENT;
  332. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  333. break;
  334. }
  335. qla2x00_post_async_login_work(vha, fcport, NULL);
  336. break;
  337. }
  338. return;
  339. }
  340. void
  341. qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  342. uint16_t *data)
  343. {
  344. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  345. return;
  346. }
  347. void
  348. qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  349. uint16_t *data)
  350. {
  351. if (data[0] == MBS_COMMAND_COMPLETE) {
  352. qla2x00_update_fcport(vha, fcport);
  353. return;
  354. }
  355. /* Retry login. */
  356. fcport->flags &= ~FCF_ASYNC_SENT;
  357. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  358. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  359. else
  360. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  361. return;
  362. }
  363. /****************************************************************************/
  364. /* QLogic ISP2x00 Hardware Support Functions. */
  365. /****************************************************************************/
  366. /*
  367. * qla2x00_initialize_adapter
  368. * Initialize board.
  369. *
  370. * Input:
  371. * ha = adapter block pointer.
  372. *
  373. * Returns:
  374. * 0 = success
  375. */
  376. int
  377. qla2x00_initialize_adapter(scsi_qla_host_t *vha)
  378. {
  379. int rval;
  380. struct qla_hw_data *ha = vha->hw;
  381. struct req_que *req = ha->req_q_map[0];
  382. /* Clear adapter flags. */
  383. vha->flags.online = 0;
  384. ha->flags.chip_reset_done = 0;
  385. vha->flags.reset_active = 0;
  386. ha->flags.pci_channel_io_perm_failure = 0;
  387. ha->flags.eeh_busy = 0;
  388. ha->flags.thermal_supported = 1;
  389. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  390. atomic_set(&vha->loop_state, LOOP_DOWN);
  391. vha->device_flags = DFLG_NO_CABLE;
  392. vha->dpc_flags = 0;
  393. vha->flags.management_server_logged_in = 0;
  394. vha->marker_needed = 0;
  395. ha->isp_abort_cnt = 0;
  396. ha->beacon_blink_led = 0;
  397. set_bit(0, ha->req_qid_map);
  398. set_bit(0, ha->rsp_qid_map);
  399. ql_dbg(ql_dbg_init, vha, 0x0040,
  400. "Configuring PCI space...\n");
  401. rval = ha->isp_ops->pci_config(vha);
  402. if (rval) {
  403. ql_log(ql_log_warn, vha, 0x0044,
  404. "Unable to configure PCI space.\n");
  405. return (rval);
  406. }
  407. ha->isp_ops->reset_chip(vha);
  408. rval = qla2xxx_get_flash_info(vha);
  409. if (rval) {
  410. ql_log(ql_log_fatal, vha, 0x004f,
  411. "Unable to validate FLASH data.\n");
  412. return (rval);
  413. }
  414. ha->isp_ops->get_flash_version(vha, req->ring);
  415. ql_dbg(ql_dbg_init, vha, 0x0061,
  416. "Configure NVRAM parameters...\n");
  417. ha->isp_ops->nvram_config(vha);
  418. if (ha->flags.disable_serdes) {
  419. /* Mask HBA via NVRAM settings? */
  420. ql_log(ql_log_info, vha, 0x0077,
  421. "Masking HBA WWPN "
  422. "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
  423. vha->port_name[0], vha->port_name[1],
  424. vha->port_name[2], vha->port_name[3],
  425. vha->port_name[4], vha->port_name[5],
  426. vha->port_name[6], vha->port_name[7]);
  427. return QLA_FUNCTION_FAILED;
  428. }
  429. ql_dbg(ql_dbg_init, vha, 0x0078,
  430. "Verifying loaded RISC code...\n");
  431. if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
  432. rval = ha->isp_ops->chip_diag(vha);
  433. if (rval)
  434. return (rval);
  435. rval = qla2x00_setup_chip(vha);
  436. if (rval)
  437. return (rval);
  438. }
  439. if (IS_QLA84XX(ha)) {
  440. ha->cs84xx = qla84xx_get_chip(vha);
  441. if (!ha->cs84xx) {
  442. ql_log(ql_log_warn, vha, 0x00d0,
  443. "Unable to configure ISP84XX.\n");
  444. return QLA_FUNCTION_FAILED;
  445. }
  446. }
  447. rval = qla2x00_init_rings(vha);
  448. ha->flags.chip_reset_done = 1;
  449. if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
  450. /* Issue verify 84xx FW IOCB to complete 84xx initialization */
  451. rval = qla84xx_init_chip(vha);
  452. if (rval != QLA_SUCCESS) {
  453. ql_log(ql_log_warn, vha, 0x00d4,
  454. "Unable to initialize ISP84XX.\n");
  455. qla84xx_put_chip(vha);
  456. }
  457. }
  458. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
  459. qla24xx_read_fcp_prio_cfg(vha);
  460. return (rval);
  461. }
  462. /**
  463. * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
  464. * @ha: HA context
  465. *
  466. * Returns 0 on success.
  467. */
  468. int
  469. qla2100_pci_config(scsi_qla_host_t *vha)
  470. {
  471. uint16_t w;
  472. unsigned long flags;
  473. struct qla_hw_data *ha = vha->hw;
  474. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  475. pci_set_master(ha->pdev);
  476. pci_try_set_mwi(ha->pdev);
  477. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  478. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  479. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  480. pci_disable_rom(ha->pdev);
  481. /* Get PCI bus information. */
  482. spin_lock_irqsave(&ha->hardware_lock, flags);
  483. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  484. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  485. return QLA_SUCCESS;
  486. }
  487. /**
  488. * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
  489. * @ha: HA context
  490. *
  491. * Returns 0 on success.
  492. */
  493. int
  494. qla2300_pci_config(scsi_qla_host_t *vha)
  495. {
  496. uint16_t w;
  497. unsigned long flags = 0;
  498. uint32_t cnt;
  499. struct qla_hw_data *ha = vha->hw;
  500. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  501. pci_set_master(ha->pdev);
  502. pci_try_set_mwi(ha->pdev);
  503. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  504. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  505. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  506. w &= ~PCI_COMMAND_INTX_DISABLE;
  507. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  508. /*
  509. * If this is a 2300 card and not 2312, reset the
  510. * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
  511. * the 2310 also reports itself as a 2300 so we need to get the
  512. * fb revision level -- a 6 indicates it really is a 2300 and
  513. * not a 2310.
  514. */
  515. if (IS_QLA2300(ha)) {
  516. spin_lock_irqsave(&ha->hardware_lock, flags);
  517. /* Pause RISC. */
  518. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  519. for (cnt = 0; cnt < 30000; cnt++) {
  520. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
  521. break;
  522. udelay(10);
  523. }
  524. /* Select FPM registers. */
  525. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  526. RD_REG_WORD(&reg->ctrl_status);
  527. /* Get the fb rev level */
  528. ha->fb_rev = RD_FB_CMD_REG(ha, reg);
  529. if (ha->fb_rev == FPM_2300)
  530. pci_clear_mwi(ha->pdev);
  531. /* Deselect FPM registers. */
  532. WRT_REG_WORD(&reg->ctrl_status, 0x0);
  533. RD_REG_WORD(&reg->ctrl_status);
  534. /* Release RISC module. */
  535. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  536. for (cnt = 0; cnt < 30000; cnt++) {
  537. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
  538. break;
  539. udelay(10);
  540. }
  541. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  542. }
  543. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  544. pci_disable_rom(ha->pdev);
  545. /* Get PCI bus information. */
  546. spin_lock_irqsave(&ha->hardware_lock, flags);
  547. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  548. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  549. return QLA_SUCCESS;
  550. }
  551. /**
  552. * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
  553. * @ha: HA context
  554. *
  555. * Returns 0 on success.
  556. */
  557. int
  558. qla24xx_pci_config(scsi_qla_host_t *vha)
  559. {
  560. uint16_t w;
  561. unsigned long flags = 0;
  562. struct qla_hw_data *ha = vha->hw;
  563. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  564. pci_set_master(ha->pdev);
  565. pci_try_set_mwi(ha->pdev);
  566. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  567. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  568. w &= ~PCI_COMMAND_INTX_DISABLE;
  569. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  570. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  571. /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
  572. if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
  573. pcix_set_mmrbc(ha->pdev, 2048);
  574. /* PCIe -- adjust Maximum Read Request Size (2048). */
  575. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  576. pcie_set_readrq(ha->pdev, 2048);
  577. pci_disable_rom(ha->pdev);
  578. ha->chip_revision = ha->pdev->revision;
  579. /* Get PCI bus information. */
  580. spin_lock_irqsave(&ha->hardware_lock, flags);
  581. ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
  582. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  583. return QLA_SUCCESS;
  584. }
  585. /**
  586. * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
  587. * @ha: HA context
  588. *
  589. * Returns 0 on success.
  590. */
  591. int
  592. qla25xx_pci_config(scsi_qla_host_t *vha)
  593. {
  594. uint16_t w;
  595. struct qla_hw_data *ha = vha->hw;
  596. pci_set_master(ha->pdev);
  597. pci_try_set_mwi(ha->pdev);
  598. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  599. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  600. w &= ~PCI_COMMAND_INTX_DISABLE;
  601. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  602. /* PCIe -- adjust Maximum Read Request Size (2048). */
  603. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  604. pcie_set_readrq(ha->pdev, 2048);
  605. pci_disable_rom(ha->pdev);
  606. ha->chip_revision = ha->pdev->revision;
  607. return QLA_SUCCESS;
  608. }
  609. /**
  610. * qla2x00_isp_firmware() - Choose firmware image.
  611. * @ha: HA context
  612. *
  613. * Returns 0 on success.
  614. */
  615. static int
  616. qla2x00_isp_firmware(scsi_qla_host_t *vha)
  617. {
  618. int rval;
  619. uint16_t loop_id, topo, sw_cap;
  620. uint8_t domain, area, al_pa;
  621. struct qla_hw_data *ha = vha->hw;
  622. /* Assume loading risc code */
  623. rval = QLA_FUNCTION_FAILED;
  624. if (ha->flags.disable_risc_code_load) {
  625. ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
  626. /* Verify checksum of loaded RISC code. */
  627. rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
  628. if (rval == QLA_SUCCESS) {
  629. /* And, verify we are not in ROM code. */
  630. rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
  631. &area, &domain, &topo, &sw_cap);
  632. }
  633. }
  634. if (rval)
  635. ql_dbg(ql_dbg_init, vha, 0x007a,
  636. "**** Load RISC code ****.\n");
  637. return (rval);
  638. }
  639. /**
  640. * qla2x00_reset_chip() - Reset ISP chip.
  641. * @ha: HA context
  642. *
  643. * Returns 0 on success.
  644. */
  645. void
  646. qla2x00_reset_chip(scsi_qla_host_t *vha)
  647. {
  648. unsigned long flags = 0;
  649. struct qla_hw_data *ha = vha->hw;
  650. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  651. uint32_t cnt;
  652. uint16_t cmd;
  653. if (unlikely(pci_channel_offline(ha->pdev)))
  654. return;
  655. ha->isp_ops->disable_intrs(ha);
  656. spin_lock_irqsave(&ha->hardware_lock, flags);
  657. /* Turn off master enable */
  658. cmd = 0;
  659. pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
  660. cmd &= ~PCI_COMMAND_MASTER;
  661. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  662. if (!IS_QLA2100(ha)) {
  663. /* Pause RISC. */
  664. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  665. if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
  666. for (cnt = 0; cnt < 30000; cnt++) {
  667. if ((RD_REG_WORD(&reg->hccr) &
  668. HCCR_RISC_PAUSE) != 0)
  669. break;
  670. udelay(100);
  671. }
  672. } else {
  673. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  674. udelay(10);
  675. }
  676. /* Select FPM registers. */
  677. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  678. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  679. /* FPM Soft Reset. */
  680. WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
  681. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  682. /* Toggle Fpm Reset. */
  683. if (!IS_QLA2200(ha)) {
  684. WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
  685. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  686. }
  687. /* Select frame buffer registers. */
  688. WRT_REG_WORD(&reg->ctrl_status, 0x10);
  689. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  690. /* Reset frame buffer FIFOs. */
  691. if (IS_QLA2200(ha)) {
  692. WRT_FB_CMD_REG(ha, reg, 0xa000);
  693. RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
  694. } else {
  695. WRT_FB_CMD_REG(ha, reg, 0x00fc);
  696. /* Read back fb_cmd until zero or 3 seconds max */
  697. for (cnt = 0; cnt < 3000; cnt++) {
  698. if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
  699. break;
  700. udelay(100);
  701. }
  702. }
  703. /* Select RISC module registers. */
  704. WRT_REG_WORD(&reg->ctrl_status, 0);
  705. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  706. /* Reset RISC processor. */
  707. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  708. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  709. /* Release RISC processor. */
  710. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  711. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  712. }
  713. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  714. WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
  715. /* Reset ISP chip. */
  716. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  717. /* Wait for RISC to recover from reset. */
  718. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  719. /*
  720. * It is necessary to for a delay here since the card doesn't
  721. * respond to PCI reads during a reset. On some architectures
  722. * this will result in an MCA.
  723. */
  724. udelay(20);
  725. for (cnt = 30000; cnt; cnt--) {
  726. if ((RD_REG_WORD(&reg->ctrl_status) &
  727. CSR_ISP_SOFT_RESET) == 0)
  728. break;
  729. udelay(100);
  730. }
  731. } else
  732. udelay(10);
  733. /* Reset RISC processor. */
  734. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  735. WRT_REG_WORD(&reg->semaphore, 0);
  736. /* Release RISC processor. */
  737. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  738. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  739. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  740. for (cnt = 0; cnt < 30000; cnt++) {
  741. if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
  742. break;
  743. udelay(100);
  744. }
  745. } else
  746. udelay(100);
  747. /* Turn on master enable */
  748. cmd |= PCI_COMMAND_MASTER;
  749. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  750. /* Disable RISC pause on FPM parity error. */
  751. if (!IS_QLA2100(ha)) {
  752. WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
  753. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  754. }
  755. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  756. }
  757. /**
  758. * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
  759. *
  760. * Returns 0 on success.
  761. */
  762. int
  763. qla81xx_reset_mpi(scsi_qla_host_t *vha)
  764. {
  765. uint16_t mb[4] = {0x1010, 0, 1, 0};
  766. if (!IS_QLA81XX(vha->hw))
  767. return QLA_SUCCESS;
  768. return qla81xx_write_mpi_register(vha, mb);
  769. }
  770. /**
  771. * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
  772. * @ha: HA context
  773. *
  774. * Returns 0 on success.
  775. */
  776. static inline void
  777. qla24xx_reset_risc(scsi_qla_host_t *vha)
  778. {
  779. unsigned long flags = 0;
  780. struct qla_hw_data *ha = vha->hw;
  781. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  782. uint32_t cnt, d2;
  783. uint16_t wd;
  784. static int abts_cnt; /* ISP abort retry counts */
  785. spin_lock_irqsave(&ha->hardware_lock, flags);
  786. /* Reset RISC. */
  787. WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  788. for (cnt = 0; cnt < 30000; cnt++) {
  789. if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
  790. break;
  791. udelay(10);
  792. }
  793. WRT_REG_DWORD(&reg->ctrl_status,
  794. CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  795. pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
  796. udelay(100);
  797. /* Wait for firmware to complete NVRAM accesses. */
  798. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  799. for (cnt = 10000 ; cnt && d2; cnt--) {
  800. udelay(5);
  801. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  802. barrier();
  803. }
  804. /* Wait for soft-reset to complete. */
  805. d2 = RD_REG_DWORD(&reg->ctrl_status);
  806. for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
  807. udelay(5);
  808. d2 = RD_REG_DWORD(&reg->ctrl_status);
  809. barrier();
  810. }
  811. /* If required, do an MPI FW reset now */
  812. if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
  813. if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
  814. if (++abts_cnt < 5) {
  815. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  816. set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
  817. } else {
  818. /*
  819. * We exhausted the ISP abort retries. We have to
  820. * set the board offline.
  821. */
  822. abts_cnt = 0;
  823. vha->flags.online = 0;
  824. }
  825. }
  826. }
  827. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  828. RD_REG_DWORD(&reg->hccr);
  829. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  830. RD_REG_DWORD(&reg->hccr);
  831. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
  832. RD_REG_DWORD(&reg->hccr);
  833. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  834. for (cnt = 6000000 ; cnt && d2; cnt--) {
  835. udelay(5);
  836. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  837. barrier();
  838. }
  839. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  840. if (IS_NOPOLLING_TYPE(ha))
  841. ha->isp_ops->enable_intrs(ha);
  842. }
  843. /**
  844. * qla24xx_reset_chip() - Reset ISP24xx chip.
  845. * @ha: HA context
  846. *
  847. * Returns 0 on success.
  848. */
  849. void
  850. qla24xx_reset_chip(scsi_qla_host_t *vha)
  851. {
  852. struct qla_hw_data *ha = vha->hw;
  853. if (pci_channel_offline(ha->pdev) &&
  854. ha->flags.pci_channel_io_perm_failure) {
  855. return;
  856. }
  857. ha->isp_ops->disable_intrs(ha);
  858. /* Perform RISC reset. */
  859. qla24xx_reset_risc(vha);
  860. }
  861. /**
  862. * qla2x00_chip_diag() - Test chip for proper operation.
  863. * @ha: HA context
  864. *
  865. * Returns 0 on success.
  866. */
  867. int
  868. qla2x00_chip_diag(scsi_qla_host_t *vha)
  869. {
  870. int rval;
  871. struct qla_hw_data *ha = vha->hw;
  872. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  873. unsigned long flags = 0;
  874. uint16_t data;
  875. uint32_t cnt;
  876. uint16_t mb[5];
  877. struct req_que *req = ha->req_q_map[0];
  878. /* Assume a failed state */
  879. rval = QLA_FUNCTION_FAILED;
  880. ql_dbg(ql_dbg_init, vha, 0x007b,
  881. "Testing device at %lx.\n", (u_long)&reg->flash_address);
  882. spin_lock_irqsave(&ha->hardware_lock, flags);
  883. /* Reset ISP chip. */
  884. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  885. /*
  886. * We need to have a delay here since the card will not respond while
  887. * in reset causing an MCA on some architectures.
  888. */
  889. udelay(20);
  890. data = qla2x00_debounce_register(&reg->ctrl_status);
  891. for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
  892. udelay(5);
  893. data = RD_REG_WORD(&reg->ctrl_status);
  894. barrier();
  895. }
  896. if (!cnt)
  897. goto chip_diag_failed;
  898. ql_dbg(ql_dbg_init, vha, 0x007c,
  899. "Reset register cleared by chip reset.\n");
  900. /* Reset RISC processor. */
  901. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  902. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  903. /* Workaround for QLA2312 PCI parity error */
  904. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  905. data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
  906. for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
  907. udelay(5);
  908. data = RD_MAILBOX_REG(ha, reg, 0);
  909. barrier();
  910. }
  911. } else
  912. udelay(10);
  913. if (!cnt)
  914. goto chip_diag_failed;
  915. /* Check product ID of chip */
  916. ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
  917. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  918. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  919. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  920. mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
  921. if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
  922. mb[3] != PROD_ID_3) {
  923. ql_log(ql_log_warn, vha, 0x0062,
  924. "Wrong product ID = 0x%x,0x%x,0x%x.\n",
  925. mb[1], mb[2], mb[3]);
  926. goto chip_diag_failed;
  927. }
  928. ha->product_id[0] = mb[1];
  929. ha->product_id[1] = mb[2];
  930. ha->product_id[2] = mb[3];
  931. ha->product_id[3] = mb[4];
  932. /* Adjust fw RISC transfer size */
  933. if (req->length > 1024)
  934. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
  935. else
  936. ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
  937. req->length;
  938. if (IS_QLA2200(ha) &&
  939. RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
  940. /* Limit firmware transfer size with a 2200A */
  941. ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
  942. ha->device_type |= DT_ISP2200A;
  943. ha->fw_transfer_size = 128;
  944. }
  945. /* Wrap Incoming Mailboxes Test. */
  946. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  947. ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
  948. rval = qla2x00_mbx_reg_test(vha);
  949. if (rval)
  950. ql_log(ql_log_warn, vha, 0x0080,
  951. "Failed mailbox send register test.\n");
  952. else
  953. /* Flag a successful rval */
  954. rval = QLA_SUCCESS;
  955. spin_lock_irqsave(&ha->hardware_lock, flags);
  956. chip_diag_failed:
  957. if (rval)
  958. ql_log(ql_log_info, vha, 0x0081,
  959. "Chip diagnostics **** FAILED ****.\n");
  960. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  961. return (rval);
  962. }
  963. /**
  964. * qla24xx_chip_diag() - Test ISP24xx for proper operation.
  965. * @ha: HA context
  966. *
  967. * Returns 0 on success.
  968. */
  969. int
  970. qla24xx_chip_diag(scsi_qla_host_t *vha)
  971. {
  972. int rval;
  973. struct qla_hw_data *ha = vha->hw;
  974. struct req_que *req = ha->req_q_map[0];
  975. if (IS_QLA82XX(ha))
  976. return QLA_SUCCESS;
  977. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  978. rval = qla2x00_mbx_reg_test(vha);
  979. if (rval) {
  980. ql_log(ql_log_warn, vha, 0x0082,
  981. "Failed mailbox send register test.\n");
  982. } else {
  983. /* Flag a successful rval */
  984. rval = QLA_SUCCESS;
  985. }
  986. return rval;
  987. }
  988. void
  989. qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
  990. {
  991. int rval;
  992. uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
  993. eft_size, fce_size, mq_size;
  994. dma_addr_t tc_dma;
  995. void *tc;
  996. struct qla_hw_data *ha = vha->hw;
  997. struct req_que *req = ha->req_q_map[0];
  998. struct rsp_que *rsp = ha->rsp_q_map[0];
  999. if (ha->fw_dump) {
  1000. ql_dbg(ql_dbg_init, vha, 0x00bd,
  1001. "Firmware dump already allocated.\n");
  1002. return;
  1003. }
  1004. ha->fw_dumped = 0;
  1005. fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
  1006. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  1007. fixed_size = sizeof(struct qla2100_fw_dump);
  1008. } else if (IS_QLA23XX(ha)) {
  1009. fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
  1010. mem_size = (ha->fw_memory_size - 0x11000 + 1) *
  1011. sizeof(uint16_t);
  1012. } else if (IS_FWI2_CAPABLE(ha)) {
  1013. if (IS_QLA83XX(ha))
  1014. fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
  1015. else if (IS_QLA81XX(ha))
  1016. fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
  1017. else if (IS_QLA25XX(ha))
  1018. fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
  1019. else
  1020. fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
  1021. mem_size = (ha->fw_memory_size - 0x100000 + 1) *
  1022. sizeof(uint32_t);
  1023. if (ha->mqenable) {
  1024. if (!IS_QLA83XX(ha))
  1025. mq_size = sizeof(struct qla2xxx_mq_chain);
  1026. /*
  1027. * Allocate maximum buffer size for all queues.
  1028. * Resizing must be done at end-of-dump processing.
  1029. */
  1030. mq_size += ha->max_req_queues *
  1031. (req->length * sizeof(request_t));
  1032. mq_size += ha->max_rsp_queues *
  1033. (rsp->length * sizeof(response_t));
  1034. }
  1035. /* Allocate memory for Fibre Channel Event Buffer. */
  1036. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  1037. goto try_eft;
  1038. tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
  1039. GFP_KERNEL);
  1040. if (!tc) {
  1041. ql_log(ql_log_warn, vha, 0x00be,
  1042. "Unable to allocate (%d KB) for FCE.\n",
  1043. FCE_SIZE / 1024);
  1044. goto try_eft;
  1045. }
  1046. memset(tc, 0, FCE_SIZE);
  1047. rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
  1048. ha->fce_mb, &ha->fce_bufs);
  1049. if (rval) {
  1050. ql_log(ql_log_warn, vha, 0x00bf,
  1051. "Unable to initialize FCE (%d).\n", rval);
  1052. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
  1053. tc_dma);
  1054. ha->flags.fce_enabled = 0;
  1055. goto try_eft;
  1056. }
  1057. ql_dbg(ql_dbg_init, vha, 0x00c0,
  1058. "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
  1059. fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
  1060. ha->flags.fce_enabled = 1;
  1061. ha->fce_dma = tc_dma;
  1062. ha->fce = tc;
  1063. try_eft:
  1064. /* Allocate memory for Extended Trace Buffer. */
  1065. tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
  1066. GFP_KERNEL);
  1067. if (!tc) {
  1068. ql_log(ql_log_warn, vha, 0x00c1,
  1069. "Unable to allocate (%d KB) for EFT.\n",
  1070. EFT_SIZE / 1024);
  1071. goto cont_alloc;
  1072. }
  1073. memset(tc, 0, EFT_SIZE);
  1074. rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
  1075. if (rval) {
  1076. ql_log(ql_log_warn, vha, 0x00c2,
  1077. "Unable to initialize EFT (%d).\n", rval);
  1078. dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
  1079. tc_dma);
  1080. goto cont_alloc;
  1081. }
  1082. ql_dbg(ql_dbg_init, vha, 0x00c3,
  1083. "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
  1084. eft_size = EFT_SIZE;
  1085. ha->eft_dma = tc_dma;
  1086. ha->eft = tc;
  1087. }
  1088. cont_alloc:
  1089. req_q_size = req->length * sizeof(request_t);
  1090. rsp_q_size = rsp->length * sizeof(response_t);
  1091. dump_size = offsetof(struct qla2xxx_fw_dump, isp);
  1092. dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
  1093. ha->chain_offset = dump_size;
  1094. dump_size += mq_size + fce_size;
  1095. ha->fw_dump = vmalloc(dump_size);
  1096. if (!ha->fw_dump) {
  1097. ql_log(ql_log_warn, vha, 0x00c4,
  1098. "Unable to allocate (%d KB) for firmware dump.\n",
  1099. dump_size / 1024);
  1100. if (ha->fce) {
  1101. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  1102. ha->fce_dma);
  1103. ha->fce = NULL;
  1104. ha->fce_dma = 0;
  1105. }
  1106. if (ha->eft) {
  1107. dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
  1108. ha->eft_dma);
  1109. ha->eft = NULL;
  1110. ha->eft_dma = 0;
  1111. }
  1112. return;
  1113. }
  1114. ql_dbg(ql_dbg_init, vha, 0x00c5,
  1115. "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
  1116. ha->fw_dump_len = dump_size;
  1117. ha->fw_dump->signature[0] = 'Q';
  1118. ha->fw_dump->signature[1] = 'L';
  1119. ha->fw_dump->signature[2] = 'G';
  1120. ha->fw_dump->signature[3] = 'C';
  1121. ha->fw_dump->version = __constant_htonl(1);
  1122. ha->fw_dump->fixed_size = htonl(fixed_size);
  1123. ha->fw_dump->mem_size = htonl(mem_size);
  1124. ha->fw_dump->req_q_size = htonl(req_q_size);
  1125. ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
  1126. ha->fw_dump->eft_size = htonl(eft_size);
  1127. ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
  1128. ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
  1129. ha->fw_dump->header_size =
  1130. htonl(offsetof(struct qla2xxx_fw_dump, isp));
  1131. }
  1132. static int
  1133. qla81xx_mpi_sync(scsi_qla_host_t *vha)
  1134. {
  1135. #define MPS_MASK 0xe0
  1136. int rval;
  1137. uint16_t dc;
  1138. uint32_t dw;
  1139. if (!IS_QLA81XX(vha->hw))
  1140. return QLA_SUCCESS;
  1141. rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
  1142. if (rval != QLA_SUCCESS) {
  1143. ql_log(ql_log_warn, vha, 0x0105,
  1144. "Unable to acquire semaphore.\n");
  1145. goto done;
  1146. }
  1147. pci_read_config_word(vha->hw->pdev, 0x54, &dc);
  1148. rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
  1149. if (rval != QLA_SUCCESS) {
  1150. ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
  1151. goto done_release;
  1152. }
  1153. dc &= MPS_MASK;
  1154. if (dc == (dw & MPS_MASK))
  1155. goto done_release;
  1156. dw &= ~MPS_MASK;
  1157. dw |= dc;
  1158. rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
  1159. if (rval != QLA_SUCCESS) {
  1160. ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
  1161. }
  1162. done_release:
  1163. rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
  1164. if (rval != QLA_SUCCESS) {
  1165. ql_log(ql_log_warn, vha, 0x006d,
  1166. "Unable to release semaphore.\n");
  1167. }
  1168. done:
  1169. return rval;
  1170. }
  1171. /**
  1172. * qla2x00_setup_chip() - Load and start RISC firmware.
  1173. * @ha: HA context
  1174. *
  1175. * Returns 0 on success.
  1176. */
  1177. static int
  1178. qla2x00_setup_chip(scsi_qla_host_t *vha)
  1179. {
  1180. int rval;
  1181. uint32_t srisc_address = 0;
  1182. struct qla_hw_data *ha = vha->hw;
  1183. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1184. unsigned long flags;
  1185. uint16_t fw_major_version;
  1186. if (IS_QLA82XX(ha)) {
  1187. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1188. if (rval == QLA_SUCCESS) {
  1189. qla2x00_stop_firmware(vha);
  1190. goto enable_82xx_npiv;
  1191. } else
  1192. goto failed;
  1193. }
  1194. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1195. /* Disable SRAM, Instruction RAM and GP RAM parity. */
  1196. spin_lock_irqsave(&ha->hardware_lock, flags);
  1197. WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
  1198. RD_REG_WORD(&reg->hccr);
  1199. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1200. }
  1201. qla81xx_mpi_sync(vha);
  1202. /* Load firmware sequences */
  1203. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1204. if (rval == QLA_SUCCESS) {
  1205. ql_dbg(ql_dbg_init, vha, 0x00c9,
  1206. "Verifying Checksum of loaded RISC code.\n");
  1207. rval = qla2x00_verify_checksum(vha, srisc_address);
  1208. if (rval == QLA_SUCCESS) {
  1209. /* Start firmware execution. */
  1210. ql_dbg(ql_dbg_init, vha, 0x00ca,
  1211. "Starting firmware.\n");
  1212. rval = qla2x00_execute_fw(vha, srisc_address);
  1213. /* Retrieve firmware information. */
  1214. if (rval == QLA_SUCCESS) {
  1215. enable_82xx_npiv:
  1216. fw_major_version = ha->fw_major_version;
  1217. if (IS_QLA82XX(ha))
  1218. qla82xx_check_md_needed(vha);
  1219. else
  1220. rval = qla2x00_get_fw_version(vha);
  1221. if (rval != QLA_SUCCESS)
  1222. goto failed;
  1223. ha->flags.npiv_supported = 0;
  1224. if (IS_QLA2XXX_MIDTYPE(ha) &&
  1225. (ha->fw_attributes & BIT_2)) {
  1226. ha->flags.npiv_supported = 1;
  1227. if ((!ha->max_npiv_vports) ||
  1228. ((ha->max_npiv_vports + 1) %
  1229. MIN_MULTI_ID_FABRIC))
  1230. ha->max_npiv_vports =
  1231. MIN_MULTI_ID_FABRIC - 1;
  1232. }
  1233. qla2x00_get_resource_cnts(vha, NULL,
  1234. &ha->fw_xcb_count, NULL, NULL,
  1235. &ha->max_npiv_vports, NULL);
  1236. if (!fw_major_version && ql2xallocfwdump
  1237. && !IS_QLA82XX(ha))
  1238. qla2x00_alloc_fw_dump(vha);
  1239. }
  1240. } else {
  1241. ql_log(ql_log_fatal, vha, 0x00cd,
  1242. "ISP Firmware failed checksum.\n");
  1243. goto failed;
  1244. }
  1245. }
  1246. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1247. /* Enable proper parity. */
  1248. spin_lock_irqsave(&ha->hardware_lock, flags);
  1249. if (IS_QLA2300(ha))
  1250. /* SRAM parity */
  1251. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
  1252. else
  1253. /* SRAM, Instruction RAM and GP RAM parity */
  1254. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
  1255. RD_REG_WORD(&reg->hccr);
  1256. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1257. }
  1258. if (IS_QLA83XX(ha))
  1259. goto skip_fac_check;
  1260. if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
  1261. uint32_t size;
  1262. rval = qla81xx_fac_get_sector_size(vha, &size);
  1263. if (rval == QLA_SUCCESS) {
  1264. ha->flags.fac_supported = 1;
  1265. ha->fdt_block_size = size << 2;
  1266. } else {
  1267. ql_log(ql_log_warn, vha, 0x00ce,
  1268. "Unsupported FAC firmware (%d.%02d.%02d).\n",
  1269. ha->fw_major_version, ha->fw_minor_version,
  1270. ha->fw_subminor_version);
  1271. skip_fac_check:
  1272. if (IS_QLA83XX(ha)) {
  1273. ha->flags.fac_supported = 0;
  1274. rval = QLA_SUCCESS;
  1275. }
  1276. }
  1277. }
  1278. failed:
  1279. if (rval) {
  1280. ql_log(ql_log_fatal, vha, 0x00cf,
  1281. "Setup chip ****FAILED****.\n");
  1282. }
  1283. return (rval);
  1284. }
  1285. /**
  1286. * qla2x00_init_response_q_entries() - Initializes response queue entries.
  1287. * @ha: HA context
  1288. *
  1289. * Beginning of request ring has initialization control block already built
  1290. * by nvram config routine.
  1291. *
  1292. * Returns 0 on success.
  1293. */
  1294. void
  1295. qla2x00_init_response_q_entries(struct rsp_que *rsp)
  1296. {
  1297. uint16_t cnt;
  1298. response_t *pkt;
  1299. rsp->ring_ptr = rsp->ring;
  1300. rsp->ring_index = 0;
  1301. rsp->status_srb = NULL;
  1302. pkt = rsp->ring_ptr;
  1303. for (cnt = 0; cnt < rsp->length; cnt++) {
  1304. pkt->signature = RESPONSE_PROCESSED;
  1305. pkt++;
  1306. }
  1307. }
  1308. /**
  1309. * qla2x00_update_fw_options() - Read and process firmware options.
  1310. * @ha: HA context
  1311. *
  1312. * Returns 0 on success.
  1313. */
  1314. void
  1315. qla2x00_update_fw_options(scsi_qla_host_t *vha)
  1316. {
  1317. uint16_t swing, emphasis, tx_sens, rx_sens;
  1318. struct qla_hw_data *ha = vha->hw;
  1319. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  1320. qla2x00_get_fw_options(vha, ha->fw_options);
  1321. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  1322. return;
  1323. /* Serial Link options. */
  1324. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
  1325. "Serial link options.\n");
  1326. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
  1327. (uint8_t *)&ha->fw_seriallink_options,
  1328. sizeof(ha->fw_seriallink_options));
  1329. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  1330. if (ha->fw_seriallink_options[3] & BIT_2) {
  1331. ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
  1332. /* 1G settings */
  1333. swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
  1334. emphasis = (ha->fw_seriallink_options[2] &
  1335. (BIT_4 | BIT_3)) >> 3;
  1336. tx_sens = ha->fw_seriallink_options[0] &
  1337. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1338. rx_sens = (ha->fw_seriallink_options[0] &
  1339. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1340. ha->fw_options[10] = (emphasis << 14) | (swing << 8);
  1341. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1342. if (rx_sens == 0x0)
  1343. rx_sens = 0x3;
  1344. ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
  1345. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1346. ha->fw_options[10] |= BIT_5 |
  1347. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1348. (tx_sens & (BIT_1 | BIT_0));
  1349. /* 2G settings */
  1350. swing = (ha->fw_seriallink_options[2] &
  1351. (BIT_7 | BIT_6 | BIT_5)) >> 5;
  1352. emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
  1353. tx_sens = ha->fw_seriallink_options[1] &
  1354. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1355. rx_sens = (ha->fw_seriallink_options[1] &
  1356. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1357. ha->fw_options[11] = (emphasis << 14) | (swing << 8);
  1358. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1359. if (rx_sens == 0x0)
  1360. rx_sens = 0x3;
  1361. ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
  1362. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1363. ha->fw_options[11] |= BIT_5 |
  1364. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1365. (tx_sens & (BIT_1 | BIT_0));
  1366. }
  1367. /* FCP2 options. */
  1368. /* Return command IOCBs without waiting for an ABTS to complete. */
  1369. ha->fw_options[3] |= BIT_13;
  1370. /* LED scheme. */
  1371. if (ha->flags.enable_led_scheme)
  1372. ha->fw_options[2] |= BIT_12;
  1373. /* Detect ISP6312. */
  1374. if (IS_QLA6312(ha))
  1375. ha->fw_options[2] |= BIT_13;
  1376. /* Update firmware options. */
  1377. qla2x00_set_fw_options(vha, ha->fw_options);
  1378. }
  1379. void
  1380. qla24xx_update_fw_options(scsi_qla_host_t *vha)
  1381. {
  1382. int rval;
  1383. struct qla_hw_data *ha = vha->hw;
  1384. if (IS_QLA82XX(ha))
  1385. return;
  1386. /* Update Serial Link options. */
  1387. if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
  1388. return;
  1389. rval = qla2x00_set_serdes_params(vha,
  1390. le16_to_cpu(ha->fw_seriallink_options24[1]),
  1391. le16_to_cpu(ha->fw_seriallink_options24[2]),
  1392. le16_to_cpu(ha->fw_seriallink_options24[3]));
  1393. if (rval != QLA_SUCCESS) {
  1394. ql_log(ql_log_warn, vha, 0x0104,
  1395. "Unable to update Serial Link options (%x).\n", rval);
  1396. }
  1397. }
  1398. void
  1399. qla2x00_config_rings(struct scsi_qla_host *vha)
  1400. {
  1401. struct qla_hw_data *ha = vha->hw;
  1402. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1403. struct req_que *req = ha->req_q_map[0];
  1404. struct rsp_que *rsp = ha->rsp_q_map[0];
  1405. /* Setup ring parameters in initialization control block. */
  1406. ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
  1407. ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
  1408. ha->init_cb->request_q_length = cpu_to_le16(req->length);
  1409. ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
  1410. ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1411. ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1412. ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1413. ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1414. WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
  1415. WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
  1416. WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
  1417. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
  1418. RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
  1419. }
  1420. void
  1421. qla24xx_config_rings(struct scsi_qla_host *vha)
  1422. {
  1423. struct qla_hw_data *ha = vha->hw;
  1424. device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
  1425. struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
  1426. struct qla_msix_entry *msix;
  1427. struct init_cb_24xx *icb;
  1428. uint16_t rid = 0;
  1429. struct req_que *req = ha->req_q_map[0];
  1430. struct rsp_que *rsp = ha->rsp_q_map[0];
  1431. /* Setup ring parameters in initialization control block. */
  1432. icb = (struct init_cb_24xx *)ha->init_cb;
  1433. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  1434. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  1435. icb->request_q_length = cpu_to_le16(req->length);
  1436. icb->response_q_length = cpu_to_le16(rsp->length);
  1437. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1438. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1439. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1440. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1441. if (ha->mqenable || IS_QLA83XX(ha)) {
  1442. icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
  1443. icb->rid = __constant_cpu_to_le16(rid);
  1444. if (ha->flags.msix_enabled) {
  1445. msix = &ha->msix_entries[1];
  1446. ql_dbg(ql_dbg_init, vha, 0x00fd,
  1447. "Registering vector 0x%x for base que.\n",
  1448. msix->entry);
  1449. icb->msix = cpu_to_le16(msix->entry);
  1450. }
  1451. /* Use alternate PCI bus number */
  1452. if (MSB(rid))
  1453. icb->firmware_options_2 |=
  1454. __constant_cpu_to_le32(BIT_19);
  1455. /* Use alternate PCI devfn */
  1456. if (LSB(rid))
  1457. icb->firmware_options_2 |=
  1458. __constant_cpu_to_le32(BIT_18);
  1459. /* Use Disable MSIX Handshake mode for capable adapters */
  1460. if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
  1461. (ha->flags.msix_enabled)) {
  1462. icb->firmware_options_2 &=
  1463. __constant_cpu_to_le32(~BIT_22);
  1464. ha->flags.disable_msix_handshake = 1;
  1465. ql_dbg(ql_dbg_init, vha, 0x00fe,
  1466. "MSIX Handshake Disable Mode turned on.\n");
  1467. } else {
  1468. icb->firmware_options_2 |=
  1469. __constant_cpu_to_le32(BIT_22);
  1470. }
  1471. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
  1472. WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
  1473. WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
  1474. WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
  1475. WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
  1476. } else {
  1477. WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
  1478. WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
  1479. WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
  1480. WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
  1481. }
  1482. /* PCI posting */
  1483. RD_REG_DWORD(&ioreg->hccr);
  1484. }
  1485. /**
  1486. * qla2x00_init_rings() - Initializes firmware.
  1487. * @ha: HA context
  1488. *
  1489. * Beginning of request ring has initialization control block already built
  1490. * by nvram config routine.
  1491. *
  1492. * Returns 0 on success.
  1493. */
  1494. static int
  1495. qla2x00_init_rings(scsi_qla_host_t *vha)
  1496. {
  1497. int rval;
  1498. unsigned long flags = 0;
  1499. int cnt, que;
  1500. struct qla_hw_data *ha = vha->hw;
  1501. struct req_que *req;
  1502. struct rsp_que *rsp;
  1503. struct mid_init_cb_24xx *mid_init_cb =
  1504. (struct mid_init_cb_24xx *) ha->init_cb;
  1505. spin_lock_irqsave(&ha->hardware_lock, flags);
  1506. /* Clear outstanding commands array. */
  1507. for (que = 0; que < ha->max_req_queues; que++) {
  1508. req = ha->req_q_map[que];
  1509. if (!req)
  1510. continue;
  1511. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
  1512. req->outstanding_cmds[cnt] = NULL;
  1513. req->current_outstanding_cmd = 1;
  1514. /* Initialize firmware. */
  1515. req->ring_ptr = req->ring;
  1516. req->ring_index = 0;
  1517. req->cnt = req->length;
  1518. }
  1519. for (que = 0; que < ha->max_rsp_queues; que++) {
  1520. rsp = ha->rsp_q_map[que];
  1521. if (!rsp)
  1522. continue;
  1523. /* Initialize response queue entries */
  1524. qla2x00_init_response_q_entries(rsp);
  1525. }
  1526. spin_lock(&ha->vport_slock);
  1527. spin_unlock(&ha->vport_slock);
  1528. ha->isp_ops->config_rings(vha);
  1529. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1530. /* Update any ISP specific firmware options before initialization. */
  1531. ha->isp_ops->update_fw_options(vha);
  1532. ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
  1533. if (ha->flags.npiv_supported) {
  1534. if (ha->operating_mode == LOOP)
  1535. ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
  1536. mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
  1537. }
  1538. if (IS_FWI2_CAPABLE(ha)) {
  1539. mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
  1540. mid_init_cb->init_cb.execution_throttle =
  1541. cpu_to_le16(ha->fw_xcb_count);
  1542. }
  1543. rval = qla2x00_init_firmware(vha, ha->init_cb_size);
  1544. if (rval) {
  1545. ql_log(ql_log_fatal, vha, 0x00d2,
  1546. "Init Firmware **** FAILED ****.\n");
  1547. } else {
  1548. ql_dbg(ql_dbg_init, vha, 0x00d3,
  1549. "Init Firmware -- success.\n");
  1550. }
  1551. return (rval);
  1552. }
  1553. /**
  1554. * qla2x00_fw_ready() - Waits for firmware ready.
  1555. * @ha: HA context
  1556. *
  1557. * Returns 0 on success.
  1558. */
  1559. static int
  1560. qla2x00_fw_ready(scsi_qla_host_t *vha)
  1561. {
  1562. int rval;
  1563. unsigned long wtime, mtime, cs84xx_time;
  1564. uint16_t min_wait; /* Minimum wait time if loop is down */
  1565. uint16_t wait_time; /* Wait time if loop is coming ready */
  1566. uint16_t state[5];
  1567. struct qla_hw_data *ha = vha->hw;
  1568. rval = QLA_SUCCESS;
  1569. /* 20 seconds for loop down. */
  1570. min_wait = 20;
  1571. /*
  1572. * Firmware should take at most one RATOV to login, plus 5 seconds for
  1573. * our own processing.
  1574. */
  1575. if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
  1576. wait_time = min_wait;
  1577. }
  1578. /* Min wait time if loop down */
  1579. mtime = jiffies + (min_wait * HZ);
  1580. /* wait time before firmware ready */
  1581. wtime = jiffies + (wait_time * HZ);
  1582. /* Wait for ISP to finish LIP */
  1583. if (!vha->flags.init_done)
  1584. ql_log(ql_log_info, vha, 0x801e,
  1585. "Waiting for LIP to complete.\n");
  1586. do {
  1587. rval = qla2x00_get_firmware_state(vha, state);
  1588. if (rval == QLA_SUCCESS) {
  1589. if (state[0] < FSTATE_LOSS_OF_SYNC) {
  1590. vha->device_flags &= ~DFLG_NO_CABLE;
  1591. }
  1592. if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
  1593. ql_dbg(ql_dbg_taskm, vha, 0x801f,
  1594. "fw_state=%x 84xx=%x.\n", state[0],
  1595. state[2]);
  1596. if ((state[2] & FSTATE_LOGGED_IN) &&
  1597. (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
  1598. ql_dbg(ql_dbg_taskm, vha, 0x8028,
  1599. "Sending verify iocb.\n");
  1600. cs84xx_time = jiffies;
  1601. rval = qla84xx_init_chip(vha);
  1602. if (rval != QLA_SUCCESS) {
  1603. ql_log(ql_log_warn,
  1604. vha, 0x8007,
  1605. "Init chip failed.\n");
  1606. break;
  1607. }
  1608. /* Add time taken to initialize. */
  1609. cs84xx_time = jiffies - cs84xx_time;
  1610. wtime += cs84xx_time;
  1611. mtime += cs84xx_time;
  1612. ql_dbg(ql_dbg_taskm, vha, 0x8008,
  1613. "Increasing wait time by %ld. "
  1614. "New time %ld.\n", cs84xx_time,
  1615. wtime);
  1616. }
  1617. } else if (state[0] == FSTATE_READY) {
  1618. ql_dbg(ql_dbg_taskm, vha, 0x8037,
  1619. "F/W Ready - OK.\n");
  1620. qla2x00_get_retry_cnt(vha, &ha->retry_count,
  1621. &ha->login_timeout, &ha->r_a_tov);
  1622. rval = QLA_SUCCESS;
  1623. break;
  1624. }
  1625. rval = QLA_FUNCTION_FAILED;
  1626. if (atomic_read(&vha->loop_down_timer) &&
  1627. state[0] != FSTATE_READY) {
  1628. /* Loop down. Timeout on min_wait for states
  1629. * other than Wait for Login.
  1630. */
  1631. if (time_after_eq(jiffies, mtime)) {
  1632. ql_log(ql_log_info, vha, 0x8038,
  1633. "Cable is unplugged...\n");
  1634. vha->device_flags |= DFLG_NO_CABLE;
  1635. break;
  1636. }
  1637. }
  1638. } else {
  1639. /* Mailbox cmd failed. Timeout on min_wait. */
  1640. if (time_after_eq(jiffies, mtime) ||
  1641. ha->flags.isp82xx_fw_hung)
  1642. break;
  1643. }
  1644. if (time_after_eq(jiffies, wtime))
  1645. break;
  1646. /* Delay for a while */
  1647. msleep(500);
  1648. } while (1);
  1649. ql_dbg(ql_dbg_taskm, vha, 0x803a,
  1650. "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
  1651. state[1], state[2], state[3], state[4], jiffies);
  1652. if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
  1653. ql_log(ql_log_warn, vha, 0x803b,
  1654. "Firmware ready **** FAILED ****.\n");
  1655. }
  1656. return (rval);
  1657. }
  1658. /*
  1659. * qla2x00_configure_hba
  1660. * Setup adapter context.
  1661. *
  1662. * Input:
  1663. * ha = adapter state pointer.
  1664. *
  1665. * Returns:
  1666. * 0 = success
  1667. *
  1668. * Context:
  1669. * Kernel context.
  1670. */
  1671. static int
  1672. qla2x00_configure_hba(scsi_qla_host_t *vha)
  1673. {
  1674. int rval;
  1675. uint16_t loop_id;
  1676. uint16_t topo;
  1677. uint16_t sw_cap;
  1678. uint8_t al_pa;
  1679. uint8_t area;
  1680. uint8_t domain;
  1681. char connect_type[22];
  1682. struct qla_hw_data *ha = vha->hw;
  1683. /* Get host addresses. */
  1684. rval = qla2x00_get_adapter_id(vha,
  1685. &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
  1686. if (rval != QLA_SUCCESS) {
  1687. if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
  1688. IS_CNA_CAPABLE(ha) ||
  1689. (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
  1690. ql_dbg(ql_dbg_disc, vha, 0x2008,
  1691. "Loop is in a transition state.\n");
  1692. } else {
  1693. ql_log(ql_log_warn, vha, 0x2009,
  1694. "Unable to get host loop ID.\n");
  1695. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1696. }
  1697. return (rval);
  1698. }
  1699. if (topo == 4) {
  1700. ql_log(ql_log_info, vha, 0x200a,
  1701. "Cannot get topology - retrying.\n");
  1702. return (QLA_FUNCTION_FAILED);
  1703. }
  1704. vha->loop_id = loop_id;
  1705. /* initialize */
  1706. ha->min_external_loopid = SNS_FIRST_LOOP_ID;
  1707. ha->operating_mode = LOOP;
  1708. ha->switch_cap = 0;
  1709. switch (topo) {
  1710. case 0:
  1711. ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
  1712. ha->current_topology = ISP_CFG_NL;
  1713. strcpy(connect_type, "(Loop)");
  1714. break;
  1715. case 1:
  1716. ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
  1717. ha->switch_cap = sw_cap;
  1718. ha->current_topology = ISP_CFG_FL;
  1719. strcpy(connect_type, "(FL_Port)");
  1720. break;
  1721. case 2:
  1722. ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
  1723. ha->operating_mode = P2P;
  1724. ha->current_topology = ISP_CFG_N;
  1725. strcpy(connect_type, "(N_Port-to-N_Port)");
  1726. break;
  1727. case 3:
  1728. ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
  1729. ha->switch_cap = sw_cap;
  1730. ha->operating_mode = P2P;
  1731. ha->current_topology = ISP_CFG_F;
  1732. strcpy(connect_type, "(F_Port)");
  1733. break;
  1734. default:
  1735. ql_dbg(ql_dbg_disc, vha, 0x200f,
  1736. "HBA in unknown topology %x, using NL.\n", topo);
  1737. ha->current_topology = ISP_CFG_NL;
  1738. strcpy(connect_type, "(Loop)");
  1739. break;
  1740. }
  1741. /* Save Host port and loop ID. */
  1742. /* byte order - Big Endian */
  1743. vha->d_id.b.domain = domain;
  1744. vha->d_id.b.area = area;
  1745. vha->d_id.b.al_pa = al_pa;
  1746. if (!vha->flags.init_done)
  1747. ql_log(ql_log_info, vha, 0x2010,
  1748. "Topology - %s, Host Loop address 0x%x.\n",
  1749. connect_type, vha->loop_id);
  1750. if (rval) {
  1751. ql_log(ql_log_warn, vha, 0x2011,
  1752. "%s FAILED\n", __func__);
  1753. } else {
  1754. ql_dbg(ql_dbg_disc, vha, 0x2012,
  1755. "%s success\n", __func__);
  1756. }
  1757. return(rval);
  1758. }
  1759. inline void
  1760. qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
  1761. char *def)
  1762. {
  1763. char *st, *en;
  1764. uint16_t index;
  1765. struct qla_hw_data *ha = vha->hw;
  1766. int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
  1767. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
  1768. if (memcmp(model, BINZERO, len) != 0) {
  1769. strncpy(ha->model_number, model, len);
  1770. st = en = ha->model_number;
  1771. en += len - 1;
  1772. while (en > st) {
  1773. if (*en != 0x20 && *en != 0x00)
  1774. break;
  1775. *en-- = '\0';
  1776. }
  1777. index = (ha->pdev->subsystem_device & 0xff);
  1778. if (use_tbl &&
  1779. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1780. index < QLA_MODEL_NAMES)
  1781. strncpy(ha->model_desc,
  1782. qla2x00_model_name[index * 2 + 1],
  1783. sizeof(ha->model_desc) - 1);
  1784. } else {
  1785. index = (ha->pdev->subsystem_device & 0xff);
  1786. if (use_tbl &&
  1787. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1788. index < QLA_MODEL_NAMES) {
  1789. strcpy(ha->model_number,
  1790. qla2x00_model_name[index * 2]);
  1791. strncpy(ha->model_desc,
  1792. qla2x00_model_name[index * 2 + 1],
  1793. sizeof(ha->model_desc) - 1);
  1794. } else {
  1795. strcpy(ha->model_number, def);
  1796. }
  1797. }
  1798. if (IS_FWI2_CAPABLE(ha))
  1799. qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
  1800. sizeof(ha->model_desc));
  1801. }
  1802. /* On sparc systems, obtain port and node WWN from firmware
  1803. * properties.
  1804. */
  1805. static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
  1806. {
  1807. #ifdef CONFIG_SPARC
  1808. struct qla_hw_data *ha = vha->hw;
  1809. struct pci_dev *pdev = ha->pdev;
  1810. struct device_node *dp = pci_device_to_OF_node(pdev);
  1811. const u8 *val;
  1812. int len;
  1813. val = of_get_property(dp, "port-wwn", &len);
  1814. if (val && len >= WWN_SIZE)
  1815. memcpy(nv->port_name, val, WWN_SIZE);
  1816. val = of_get_property(dp, "node-wwn", &len);
  1817. if (val && len >= WWN_SIZE)
  1818. memcpy(nv->node_name, val, WWN_SIZE);
  1819. #endif
  1820. }
  1821. /*
  1822. * NVRAM configuration for ISP 2xxx
  1823. *
  1824. * Input:
  1825. * ha = adapter block pointer.
  1826. *
  1827. * Output:
  1828. * initialization control block in response_ring
  1829. * host adapters parameters in host adapter block
  1830. *
  1831. * Returns:
  1832. * 0 = success.
  1833. */
  1834. int
  1835. qla2x00_nvram_config(scsi_qla_host_t *vha)
  1836. {
  1837. int rval;
  1838. uint8_t chksum = 0;
  1839. uint16_t cnt;
  1840. uint8_t *dptr1, *dptr2;
  1841. struct qla_hw_data *ha = vha->hw;
  1842. init_cb_t *icb = ha->init_cb;
  1843. nvram_t *nv = ha->nvram;
  1844. uint8_t *ptr = ha->nvram;
  1845. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1846. rval = QLA_SUCCESS;
  1847. /* Determine NVRAM starting address. */
  1848. ha->nvram_size = sizeof(nvram_t);
  1849. ha->nvram_base = 0;
  1850. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
  1851. if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
  1852. ha->nvram_base = 0x80;
  1853. /* Get NVRAM data and calculate checksum. */
  1854. ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
  1855. for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
  1856. chksum += *ptr++;
  1857. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
  1858. "Contents of NVRAM.\n");
  1859. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
  1860. (uint8_t *)nv, ha->nvram_size);
  1861. /* Bad NVRAM data, set defaults parameters. */
  1862. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
  1863. nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
  1864. /* Reset NVRAM data. */
  1865. ql_log(ql_log_warn, vha, 0x0064,
  1866. "Inconsistent NVRAM "
  1867. "detected: checksum=0x%x id=%c version=0x%x.\n",
  1868. chksum, nv->id[0], nv->nvram_version);
  1869. ql_log(ql_log_warn, vha, 0x0065,
  1870. "Falling back to "
  1871. "functioning (yet invalid -- WWPN) defaults.\n");
  1872. /*
  1873. * Set default initialization control block.
  1874. */
  1875. memset(nv, 0, ha->nvram_size);
  1876. nv->parameter_block_version = ICB_VERSION;
  1877. if (IS_QLA23XX(ha)) {
  1878. nv->firmware_options[0] = BIT_2 | BIT_1;
  1879. nv->firmware_options[1] = BIT_7 | BIT_5;
  1880. nv->add_firmware_options[0] = BIT_5;
  1881. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1882. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1883. nv->special_options[1] = BIT_7;
  1884. } else if (IS_QLA2200(ha)) {
  1885. nv->firmware_options[0] = BIT_2 | BIT_1;
  1886. nv->firmware_options[1] = BIT_7 | BIT_5;
  1887. nv->add_firmware_options[0] = BIT_5;
  1888. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1889. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1890. } else if (IS_QLA2100(ha)) {
  1891. nv->firmware_options[0] = BIT_3 | BIT_1;
  1892. nv->firmware_options[1] = BIT_5;
  1893. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1894. }
  1895. nv->max_iocb_allocation = __constant_cpu_to_le16(256);
  1896. nv->execution_throttle = __constant_cpu_to_le16(16);
  1897. nv->retry_count = 8;
  1898. nv->retry_delay = 1;
  1899. nv->port_name[0] = 33;
  1900. nv->port_name[3] = 224;
  1901. nv->port_name[4] = 139;
  1902. qla2xxx_nvram_wwn_from_ofw(vha, nv);
  1903. nv->login_timeout = 4;
  1904. /*
  1905. * Set default host adapter parameters
  1906. */
  1907. nv->host_p[1] = BIT_2;
  1908. nv->reset_delay = 5;
  1909. nv->port_down_retry_count = 8;
  1910. nv->max_luns_per_target = __constant_cpu_to_le16(8);
  1911. nv->link_down_timeout = 60;
  1912. rval = 1;
  1913. }
  1914. #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
  1915. /*
  1916. * The SN2 does not provide BIOS emulation which means you can't change
  1917. * potentially bogus BIOS settings. Force the use of default settings
  1918. * for link rate and frame size. Hope that the rest of the settings
  1919. * are valid.
  1920. */
  1921. if (ia64_platform_is("sn2")) {
  1922. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1923. if (IS_QLA23XX(ha))
  1924. nv->special_options[1] = BIT_7;
  1925. }
  1926. #endif
  1927. /* Reset Initialization control block */
  1928. memset(icb, 0, ha->init_cb_size);
  1929. /*
  1930. * Setup driver NVRAM options.
  1931. */
  1932. nv->firmware_options[0] |= (BIT_6 | BIT_1);
  1933. nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
  1934. nv->firmware_options[1] |= (BIT_5 | BIT_0);
  1935. nv->firmware_options[1] &= ~BIT_4;
  1936. if (IS_QLA23XX(ha)) {
  1937. nv->firmware_options[0] |= BIT_2;
  1938. nv->firmware_options[0] &= ~BIT_3;
  1939. nv->firmware_options[0] &= ~BIT_6;
  1940. nv->add_firmware_options[1] |= BIT_5 | BIT_4;
  1941. if (IS_QLA2300(ha)) {
  1942. if (ha->fb_rev == FPM_2310) {
  1943. strcpy(ha->model_number, "QLA2310");
  1944. } else {
  1945. strcpy(ha->model_number, "QLA2300");
  1946. }
  1947. } else {
  1948. qla2x00_set_model_info(vha, nv->model_number,
  1949. sizeof(nv->model_number), "QLA23xx");
  1950. }
  1951. } else if (IS_QLA2200(ha)) {
  1952. nv->firmware_options[0] |= BIT_2;
  1953. /*
  1954. * 'Point-to-point preferred, else loop' is not a safe
  1955. * connection mode setting.
  1956. */
  1957. if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
  1958. (BIT_5 | BIT_4)) {
  1959. /* Force 'loop preferred, else point-to-point'. */
  1960. nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
  1961. nv->add_firmware_options[0] |= BIT_5;
  1962. }
  1963. strcpy(ha->model_number, "QLA22xx");
  1964. } else /*if (IS_QLA2100(ha))*/ {
  1965. strcpy(ha->model_number, "QLA2100");
  1966. }
  1967. /*
  1968. * Copy over NVRAM RISC parameter block to initialization control block.
  1969. */
  1970. dptr1 = (uint8_t *)icb;
  1971. dptr2 = (uint8_t *)&nv->parameter_block_version;
  1972. cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
  1973. while (cnt--)
  1974. *dptr1++ = *dptr2++;
  1975. /* Copy 2nd half. */
  1976. dptr1 = (uint8_t *)icb->add_firmware_options;
  1977. cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
  1978. while (cnt--)
  1979. *dptr1++ = *dptr2++;
  1980. /* Use alternate WWN? */
  1981. if (nv->host_p[1] & BIT_7) {
  1982. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  1983. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  1984. }
  1985. /* Prepare nodename */
  1986. if ((icb->firmware_options[1] & BIT_6) == 0) {
  1987. /*
  1988. * Firmware will apply the following mask if the nodename was
  1989. * not provided.
  1990. */
  1991. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  1992. icb->node_name[0] &= 0xF0;
  1993. }
  1994. /*
  1995. * Set host adapter parameters.
  1996. */
  1997. /*
  1998. * BIT_7 in the host-parameters section allows for modification to
  1999. * internal driver logging.
  2000. */
  2001. if (nv->host_p[0] & BIT_7)
  2002. ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
  2003. ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
  2004. /* Always load RISC code on non ISP2[12]00 chips. */
  2005. if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
  2006. ha->flags.disable_risc_code_load = 0;
  2007. ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
  2008. ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
  2009. ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
  2010. ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
  2011. ha->flags.disable_serdes = 0;
  2012. ha->operating_mode =
  2013. (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
  2014. memcpy(ha->fw_seriallink_options, nv->seriallink_options,
  2015. sizeof(ha->fw_seriallink_options));
  2016. /* save HBA serial number */
  2017. ha->serial0 = icb->port_name[5];
  2018. ha->serial1 = icb->port_name[6];
  2019. ha->serial2 = icb->port_name[7];
  2020. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  2021. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  2022. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  2023. ha->retry_count = nv->retry_count;
  2024. /* Set minimum login_timeout to 4 seconds. */
  2025. if (nv->login_timeout != ql2xlogintimeout)
  2026. nv->login_timeout = ql2xlogintimeout;
  2027. if (nv->login_timeout < 4)
  2028. nv->login_timeout = 4;
  2029. ha->login_timeout = nv->login_timeout;
  2030. icb->login_timeout = nv->login_timeout;
  2031. /* Set minimum RATOV to 100 tenths of a second. */
  2032. ha->r_a_tov = 100;
  2033. ha->loop_reset_delay = nv->reset_delay;
  2034. /* Link Down Timeout = 0:
  2035. *
  2036. * When Port Down timer expires we will start returning
  2037. * I/O's to OS with "DID_NO_CONNECT".
  2038. *
  2039. * Link Down Timeout != 0:
  2040. *
  2041. * The driver waits for the link to come up after link down
  2042. * before returning I/Os to OS with "DID_NO_CONNECT".
  2043. */
  2044. if (nv->link_down_timeout == 0) {
  2045. ha->loop_down_abort_time =
  2046. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  2047. } else {
  2048. ha->link_down_timeout = nv->link_down_timeout;
  2049. ha->loop_down_abort_time =
  2050. (LOOP_DOWN_TIME - ha->link_down_timeout);
  2051. }
  2052. /*
  2053. * Need enough time to try and get the port back.
  2054. */
  2055. ha->port_down_retry_count = nv->port_down_retry_count;
  2056. if (qlport_down_retry)
  2057. ha->port_down_retry_count = qlport_down_retry;
  2058. /* Set login_retry_count */
  2059. ha->login_retry_count = nv->retry_count;
  2060. if (ha->port_down_retry_count == nv->port_down_retry_count &&
  2061. ha->port_down_retry_count > 3)
  2062. ha->login_retry_count = ha->port_down_retry_count;
  2063. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  2064. ha->login_retry_count = ha->port_down_retry_count;
  2065. if (ql2xloginretrycount)
  2066. ha->login_retry_count = ql2xloginretrycount;
  2067. icb->lun_enables = __constant_cpu_to_le16(0);
  2068. icb->command_resource_count = 0;
  2069. icb->immediate_notify_resource_count = 0;
  2070. icb->timeout = __constant_cpu_to_le16(0);
  2071. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2072. /* Enable RIO */
  2073. icb->firmware_options[0] &= ~BIT_3;
  2074. icb->add_firmware_options[0] &=
  2075. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2076. icb->add_firmware_options[0] |= BIT_2;
  2077. icb->response_accumulation_timer = 3;
  2078. icb->interrupt_delay_timer = 5;
  2079. vha->flags.process_response_queue = 1;
  2080. } else {
  2081. /* Enable ZIO. */
  2082. if (!vha->flags.init_done) {
  2083. ha->zio_mode = icb->add_firmware_options[0] &
  2084. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2085. ha->zio_timer = icb->interrupt_delay_timer ?
  2086. icb->interrupt_delay_timer: 2;
  2087. }
  2088. icb->add_firmware_options[0] &=
  2089. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2090. vha->flags.process_response_queue = 0;
  2091. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  2092. ha->zio_mode = QLA_ZIO_MODE_6;
  2093. ql_log(ql_log_info, vha, 0x0068,
  2094. "ZIO mode %d enabled; timer delay (%d us).\n",
  2095. ha->zio_mode, ha->zio_timer * 100);
  2096. icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
  2097. icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
  2098. vha->flags.process_response_queue = 1;
  2099. }
  2100. }
  2101. if (rval) {
  2102. ql_log(ql_log_warn, vha, 0x0069,
  2103. "NVRAM configuration failed.\n");
  2104. }
  2105. return (rval);
  2106. }
  2107. static void
  2108. qla2x00_rport_del(void *data)
  2109. {
  2110. fc_port_t *fcport = data;
  2111. struct fc_rport *rport;
  2112. unsigned long flags;
  2113. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2114. rport = fcport->drport ? fcport->drport: fcport->rport;
  2115. fcport->drport = NULL;
  2116. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2117. if (rport)
  2118. fc_remote_port_delete(rport);
  2119. }
  2120. /**
  2121. * qla2x00_alloc_fcport() - Allocate a generic fcport.
  2122. * @ha: HA context
  2123. * @flags: allocation flags
  2124. *
  2125. * Returns a pointer to the allocated fcport, or NULL, if none available.
  2126. */
  2127. fc_port_t *
  2128. qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
  2129. {
  2130. fc_port_t *fcport;
  2131. fcport = kzalloc(sizeof(fc_port_t), flags);
  2132. if (!fcport)
  2133. return NULL;
  2134. /* Setup fcport template structure. */
  2135. fcport->vha = vha;
  2136. fcport->port_type = FCT_UNKNOWN;
  2137. fcport->loop_id = FC_NO_LOOP_ID;
  2138. qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
  2139. fcport->supported_classes = FC_COS_UNSPECIFIED;
  2140. return fcport;
  2141. }
  2142. /*
  2143. * qla2x00_configure_loop
  2144. * Updates Fibre Channel Device Database with what is actually on loop.
  2145. *
  2146. * Input:
  2147. * ha = adapter block pointer.
  2148. *
  2149. * Returns:
  2150. * 0 = success.
  2151. * 1 = error.
  2152. * 2 = database was full and device was not configured.
  2153. */
  2154. static int
  2155. qla2x00_configure_loop(scsi_qla_host_t *vha)
  2156. {
  2157. int rval;
  2158. unsigned long flags, save_flags;
  2159. struct qla_hw_data *ha = vha->hw;
  2160. rval = QLA_SUCCESS;
  2161. /* Get Initiator ID */
  2162. if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
  2163. rval = qla2x00_configure_hba(vha);
  2164. if (rval != QLA_SUCCESS) {
  2165. ql_dbg(ql_dbg_disc, vha, 0x2013,
  2166. "Unable to configure HBA.\n");
  2167. return (rval);
  2168. }
  2169. }
  2170. save_flags = flags = vha->dpc_flags;
  2171. ql_dbg(ql_dbg_disc, vha, 0x2014,
  2172. "Configure loop -- dpc flags = 0x%lx.\n", flags);
  2173. /*
  2174. * If we have both an RSCN and PORT UPDATE pending then handle them
  2175. * both at the same time.
  2176. */
  2177. clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2178. clear_bit(RSCN_UPDATE, &vha->dpc_flags);
  2179. qla2x00_get_data_rate(vha);
  2180. /* Determine what we need to do */
  2181. if (ha->current_topology == ISP_CFG_FL &&
  2182. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2183. set_bit(RSCN_UPDATE, &flags);
  2184. } else if (ha->current_topology == ISP_CFG_F &&
  2185. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2186. set_bit(RSCN_UPDATE, &flags);
  2187. clear_bit(LOCAL_LOOP_UPDATE, &flags);
  2188. } else if (ha->current_topology == ISP_CFG_N) {
  2189. clear_bit(RSCN_UPDATE, &flags);
  2190. } else if (!vha->flags.online ||
  2191. (test_bit(ABORT_ISP_ACTIVE, &flags))) {
  2192. set_bit(RSCN_UPDATE, &flags);
  2193. set_bit(LOCAL_LOOP_UPDATE, &flags);
  2194. }
  2195. if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
  2196. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2197. ql_dbg(ql_dbg_disc, vha, 0x2015,
  2198. "Loop resync needed, failing.\n");
  2199. rval = QLA_FUNCTION_FAILED;
  2200. } else
  2201. rval = qla2x00_configure_local_loop(vha);
  2202. }
  2203. if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
  2204. if (LOOP_TRANSITION(vha)) {
  2205. ql_dbg(ql_dbg_disc, vha, 0x201e,
  2206. "Needs RSCN update and loop transition.\n");
  2207. rval = QLA_FUNCTION_FAILED;
  2208. }
  2209. else
  2210. rval = qla2x00_configure_fabric(vha);
  2211. }
  2212. if (rval == QLA_SUCCESS) {
  2213. if (atomic_read(&vha->loop_down_timer) ||
  2214. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2215. rval = QLA_FUNCTION_FAILED;
  2216. } else {
  2217. atomic_set(&vha->loop_state, LOOP_READY);
  2218. ql_dbg(ql_dbg_disc, vha, 0x2069,
  2219. "LOOP READY.\n");
  2220. }
  2221. }
  2222. if (rval) {
  2223. ql_dbg(ql_dbg_disc, vha, 0x206a,
  2224. "%s *** FAILED ***.\n", __func__);
  2225. } else {
  2226. ql_dbg(ql_dbg_disc, vha, 0x206b,
  2227. "%s: exiting normally.\n", __func__);
  2228. }
  2229. /* Restore state if a resync event occurred during processing */
  2230. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2231. if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
  2232. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2233. if (test_bit(RSCN_UPDATE, &save_flags)) {
  2234. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  2235. }
  2236. }
  2237. return (rval);
  2238. }
  2239. /*
  2240. * qla2x00_configure_local_loop
  2241. * Updates Fibre Channel Device Database with local loop devices.
  2242. *
  2243. * Input:
  2244. * ha = adapter block pointer.
  2245. *
  2246. * Returns:
  2247. * 0 = success.
  2248. */
  2249. static int
  2250. qla2x00_configure_local_loop(scsi_qla_host_t *vha)
  2251. {
  2252. int rval, rval2;
  2253. int found_devs;
  2254. int found;
  2255. fc_port_t *fcport, *new_fcport;
  2256. uint16_t index;
  2257. uint16_t entries;
  2258. char *id_iter;
  2259. uint16_t loop_id;
  2260. uint8_t domain, area, al_pa;
  2261. struct qla_hw_data *ha = vha->hw;
  2262. found_devs = 0;
  2263. new_fcport = NULL;
  2264. entries = MAX_FIBRE_DEVICES_LOOP;
  2265. ql_dbg(ql_dbg_disc, vha, 0x2016,
  2266. "Getting FCAL position map.\n");
  2267. if (ql2xextended_error_logging & ql_dbg_disc)
  2268. qla2x00_get_fcal_position_map(vha, NULL);
  2269. /* Get list of logged in devices. */
  2270. memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
  2271. rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
  2272. &entries);
  2273. if (rval != QLA_SUCCESS)
  2274. goto cleanup_allocation;
  2275. ql_dbg(ql_dbg_disc, vha, 0x2017,
  2276. "Entries in ID list (%d).\n", entries);
  2277. ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
  2278. (uint8_t *)ha->gid_list,
  2279. entries * sizeof(struct gid_list_info));
  2280. /* Allocate temporary fcport for any new fcports discovered. */
  2281. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2282. if (new_fcport == NULL) {
  2283. ql_log(ql_log_warn, vha, 0x2018,
  2284. "Memory allocation failed for fcport.\n");
  2285. rval = QLA_MEMORY_ALLOC_FAILED;
  2286. goto cleanup_allocation;
  2287. }
  2288. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2289. /*
  2290. * Mark local devices that were present with FCF_DEVICE_LOST for now.
  2291. */
  2292. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2293. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2294. fcport->port_type != FCT_BROADCAST &&
  2295. (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2296. ql_dbg(ql_dbg_disc, vha, 0x2019,
  2297. "Marking port lost loop_id=0x%04x.\n",
  2298. fcport->loop_id);
  2299. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2300. }
  2301. }
  2302. /* Add devices to port list. */
  2303. id_iter = (char *)ha->gid_list;
  2304. for (index = 0; index < entries; index++) {
  2305. domain = ((struct gid_list_info *)id_iter)->domain;
  2306. area = ((struct gid_list_info *)id_iter)->area;
  2307. al_pa = ((struct gid_list_info *)id_iter)->al_pa;
  2308. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  2309. loop_id = (uint16_t)
  2310. ((struct gid_list_info *)id_iter)->loop_id_2100;
  2311. else
  2312. loop_id = le16_to_cpu(
  2313. ((struct gid_list_info *)id_iter)->loop_id);
  2314. id_iter += ha->gid_list_info_size;
  2315. /* Bypass reserved domain fields. */
  2316. if ((domain & 0xf0) == 0xf0)
  2317. continue;
  2318. /* Bypass if not same domain and area of adapter. */
  2319. if (area && domain &&
  2320. (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
  2321. continue;
  2322. /* Bypass invalid local loop ID. */
  2323. if (loop_id > LAST_LOCAL_LOOP_ID)
  2324. continue;
  2325. /* Fill in member data. */
  2326. new_fcport->d_id.b.domain = domain;
  2327. new_fcport->d_id.b.area = area;
  2328. new_fcport->d_id.b.al_pa = al_pa;
  2329. new_fcport->loop_id = loop_id;
  2330. rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
  2331. if (rval2 != QLA_SUCCESS) {
  2332. ql_dbg(ql_dbg_disc, vha, 0x201a,
  2333. "Failed to retrieve fcport information "
  2334. "-- get_port_database=%x, loop_id=0x%04x.\n",
  2335. rval2, new_fcport->loop_id);
  2336. ql_dbg(ql_dbg_disc, vha, 0x201b,
  2337. "Scheduling resync.\n");
  2338. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2339. continue;
  2340. }
  2341. /* Check for matching device in port list. */
  2342. found = 0;
  2343. fcport = NULL;
  2344. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2345. if (memcmp(new_fcport->port_name, fcport->port_name,
  2346. WWN_SIZE))
  2347. continue;
  2348. fcport->flags &= ~FCF_FABRIC_DEVICE;
  2349. fcport->loop_id = new_fcport->loop_id;
  2350. fcport->port_type = new_fcport->port_type;
  2351. fcport->d_id.b24 = new_fcport->d_id.b24;
  2352. memcpy(fcport->node_name, new_fcport->node_name,
  2353. WWN_SIZE);
  2354. found++;
  2355. break;
  2356. }
  2357. if (!found) {
  2358. /* New device, add to fcports list. */
  2359. list_add_tail(&new_fcport->list, &vha->vp_fcports);
  2360. /* Allocate a new replacement fcport. */
  2361. fcport = new_fcport;
  2362. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2363. if (new_fcport == NULL) {
  2364. ql_log(ql_log_warn, vha, 0x201c,
  2365. "Failed to allocate memory for fcport.\n");
  2366. rval = QLA_MEMORY_ALLOC_FAILED;
  2367. goto cleanup_allocation;
  2368. }
  2369. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2370. }
  2371. /* Base iIDMA settings on HBA port speed. */
  2372. fcport->fp_speed = ha->link_data_rate;
  2373. qla2x00_update_fcport(vha, fcport);
  2374. found_devs++;
  2375. }
  2376. cleanup_allocation:
  2377. kfree(new_fcport);
  2378. if (rval != QLA_SUCCESS) {
  2379. ql_dbg(ql_dbg_disc, vha, 0x201d,
  2380. "Configure local loop error exit: rval=%x.\n", rval);
  2381. }
  2382. return (rval);
  2383. }
  2384. static void
  2385. qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2386. {
  2387. #define LS_UNKNOWN 2
  2388. static char *link_speeds[] = { "1", "2", "?", "4", "8", "10" };
  2389. char *link_speed;
  2390. int rval;
  2391. uint16_t mb[4];
  2392. struct qla_hw_data *ha = vha->hw;
  2393. if (!IS_IIDMA_CAPABLE(ha))
  2394. return;
  2395. if (atomic_read(&fcport->state) != FCS_ONLINE)
  2396. return;
  2397. if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
  2398. fcport->fp_speed > ha->link_data_rate)
  2399. return;
  2400. rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
  2401. mb);
  2402. if (rval != QLA_SUCCESS) {
  2403. ql_dbg(ql_dbg_disc, vha, 0x2004,
  2404. "Unable to adjust iIDMA "
  2405. "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
  2406. "%04x.\n", fcport->port_name[0], fcport->port_name[1],
  2407. fcport->port_name[2], fcport->port_name[3],
  2408. fcport->port_name[4], fcport->port_name[5],
  2409. fcport->port_name[6], fcport->port_name[7], rval,
  2410. fcport->fp_speed, mb[0], mb[1]);
  2411. } else {
  2412. link_speed = link_speeds[LS_UNKNOWN];
  2413. if (fcport->fp_speed < 5)
  2414. link_speed = link_speeds[fcport->fp_speed];
  2415. else if (fcport->fp_speed == 0x13)
  2416. link_speed = link_speeds[5];
  2417. ql_dbg(ql_dbg_disc, vha, 0x2005,
  2418. "iIDMA adjusted to %s GB/s "
  2419. "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
  2420. fcport->port_name[0], fcport->port_name[1],
  2421. fcport->port_name[2], fcport->port_name[3],
  2422. fcport->port_name[4], fcport->port_name[5],
  2423. fcport->port_name[6], fcport->port_name[7]);
  2424. }
  2425. }
  2426. static void
  2427. qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
  2428. {
  2429. struct fc_rport_identifiers rport_ids;
  2430. struct fc_rport *rport;
  2431. unsigned long flags;
  2432. qla2x00_rport_del(fcport);
  2433. rport_ids.node_name = wwn_to_u64(fcport->node_name);
  2434. rport_ids.port_name = wwn_to_u64(fcport->port_name);
  2435. rport_ids.port_id = fcport->d_id.b.domain << 16 |
  2436. fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
  2437. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2438. fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
  2439. if (!rport) {
  2440. ql_log(ql_log_warn, vha, 0x2006,
  2441. "Unable to allocate fc remote port.\n");
  2442. return;
  2443. }
  2444. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2445. *((fc_port_t **)rport->dd_data) = fcport;
  2446. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2447. rport->supported_classes = fcport->supported_classes;
  2448. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2449. if (fcport->port_type == FCT_INITIATOR)
  2450. rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
  2451. if (fcport->port_type == FCT_TARGET)
  2452. rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
  2453. fc_remote_port_rolechg(rport, rport_ids.roles);
  2454. }
  2455. /*
  2456. * qla2x00_update_fcport
  2457. * Updates device on list.
  2458. *
  2459. * Input:
  2460. * ha = adapter block pointer.
  2461. * fcport = port structure pointer.
  2462. *
  2463. * Return:
  2464. * 0 - Success
  2465. * BIT_0 - error
  2466. *
  2467. * Context:
  2468. * Kernel context.
  2469. */
  2470. void
  2471. qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2472. {
  2473. fcport->vha = vha;
  2474. fcport->login_retry = 0;
  2475. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  2476. qla2x00_iidma_fcport(vha, fcport);
  2477. qla24xx_update_fcport_fcp_prio(vha, fcport);
  2478. qla2x00_reg_remote_port(vha, fcport);
  2479. qla2x00_set_fcport_state(fcport, FCS_ONLINE);
  2480. }
  2481. /*
  2482. * qla2x00_configure_fabric
  2483. * Setup SNS devices with loop ID's.
  2484. *
  2485. * Input:
  2486. * ha = adapter block pointer.
  2487. *
  2488. * Returns:
  2489. * 0 = success.
  2490. * BIT_0 = error
  2491. */
  2492. static int
  2493. qla2x00_configure_fabric(scsi_qla_host_t *vha)
  2494. {
  2495. int rval;
  2496. fc_port_t *fcport, *fcptemp;
  2497. uint16_t next_loopid;
  2498. uint16_t mb[MAILBOX_REGISTER_COUNT];
  2499. uint16_t loop_id;
  2500. LIST_HEAD(new_fcports);
  2501. struct qla_hw_data *ha = vha->hw;
  2502. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2503. /* If FL port exists, then SNS is present */
  2504. if (IS_FWI2_CAPABLE(ha))
  2505. loop_id = NPH_F_PORT;
  2506. else
  2507. loop_id = SNS_FL_PORT;
  2508. rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
  2509. if (rval != QLA_SUCCESS) {
  2510. ql_dbg(ql_dbg_disc, vha, 0x201f,
  2511. "MBX_GET_PORT_NAME failed, No FL Port.\n");
  2512. vha->device_flags &= ~SWITCH_FOUND;
  2513. return (QLA_SUCCESS);
  2514. }
  2515. vha->device_flags |= SWITCH_FOUND;
  2516. do {
  2517. /* FDMI support. */
  2518. if (ql2xfdmienable &&
  2519. test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
  2520. qla2x00_fdmi_register(vha);
  2521. /* Ensure we are logged into the SNS. */
  2522. if (IS_FWI2_CAPABLE(ha))
  2523. loop_id = NPH_SNS;
  2524. else
  2525. loop_id = SIMPLE_NAME_SERVER;
  2526. rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
  2527. 0xfc, mb, BIT_1|BIT_0);
  2528. if (rval != QLA_SUCCESS) {
  2529. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2530. return rval;
  2531. }
  2532. if (mb[0] != MBS_COMMAND_COMPLETE) {
  2533. ql_dbg(ql_dbg_disc, vha, 0x2042,
  2534. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  2535. "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
  2536. mb[2], mb[6], mb[7]);
  2537. return (QLA_SUCCESS);
  2538. }
  2539. if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
  2540. if (qla2x00_rft_id(vha)) {
  2541. /* EMPTY */
  2542. ql_dbg(ql_dbg_disc, vha, 0x2045,
  2543. "Register FC-4 TYPE failed.\n");
  2544. }
  2545. if (qla2x00_rff_id(vha)) {
  2546. /* EMPTY */
  2547. ql_dbg(ql_dbg_disc, vha, 0x2049,
  2548. "Register FC-4 Features failed.\n");
  2549. }
  2550. if (qla2x00_rnn_id(vha)) {
  2551. /* EMPTY */
  2552. ql_dbg(ql_dbg_disc, vha, 0x204f,
  2553. "Register Node Name failed.\n");
  2554. } else if (qla2x00_rsnn_nn(vha)) {
  2555. /* EMPTY */
  2556. ql_dbg(ql_dbg_disc, vha, 0x2053,
  2557. "Register Symobilic Node Name failed.\n");
  2558. }
  2559. }
  2560. #define QLA_FCPORT_SCAN 1
  2561. #define QLA_FCPORT_FOUND 2
  2562. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2563. fcport->scan_state = QLA_FCPORT_SCAN;
  2564. }
  2565. rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
  2566. if (rval != QLA_SUCCESS)
  2567. break;
  2568. /*
  2569. * Logout all previous fabric devices marked lost, except
  2570. * FCP2 devices.
  2571. */
  2572. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2573. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2574. break;
  2575. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
  2576. continue;
  2577. if (fcport->scan_state == QLA_FCPORT_SCAN &&
  2578. atomic_read(&fcport->state) == FCS_ONLINE) {
  2579. qla2x00_mark_device_lost(vha, fcport,
  2580. ql2xplogiabsentdevice, 0);
  2581. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2582. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2583. fcport->port_type != FCT_INITIATOR &&
  2584. fcport->port_type != FCT_BROADCAST) {
  2585. ha->isp_ops->fabric_logout(vha,
  2586. fcport->loop_id,
  2587. fcport->d_id.b.domain,
  2588. fcport->d_id.b.area,
  2589. fcport->d_id.b.al_pa);
  2590. fcport->loop_id = FC_NO_LOOP_ID;
  2591. }
  2592. }
  2593. }
  2594. /* Starting free loop ID. */
  2595. next_loopid = ha->min_external_loopid;
  2596. /*
  2597. * Scan through our port list and login entries that need to be
  2598. * logged in.
  2599. */
  2600. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2601. if (atomic_read(&vha->loop_down_timer) ||
  2602. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2603. break;
  2604. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  2605. (fcport->flags & FCF_LOGIN_NEEDED) == 0)
  2606. continue;
  2607. if (fcport->loop_id == FC_NO_LOOP_ID) {
  2608. fcport->loop_id = next_loopid;
  2609. rval = qla2x00_find_new_loop_id(
  2610. base_vha, fcport);
  2611. if (rval != QLA_SUCCESS) {
  2612. /* Ran out of IDs to use */
  2613. break;
  2614. }
  2615. }
  2616. /* Login and update database */
  2617. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2618. }
  2619. /* Exit if out of loop IDs. */
  2620. if (rval != QLA_SUCCESS) {
  2621. break;
  2622. }
  2623. /*
  2624. * Login and add the new devices to our port list.
  2625. */
  2626. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2627. if (atomic_read(&vha->loop_down_timer) ||
  2628. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2629. break;
  2630. /* Find a new loop ID to use. */
  2631. fcport->loop_id = next_loopid;
  2632. rval = qla2x00_find_new_loop_id(base_vha, fcport);
  2633. if (rval != QLA_SUCCESS) {
  2634. /* Ran out of IDs to use */
  2635. break;
  2636. }
  2637. /* Login and update database */
  2638. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2639. list_move_tail(&fcport->list, &vha->vp_fcports);
  2640. }
  2641. } while (0);
  2642. /* Free all new device structures not processed. */
  2643. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2644. list_del(&fcport->list);
  2645. kfree(fcport);
  2646. }
  2647. if (rval) {
  2648. ql_dbg(ql_dbg_disc, vha, 0x2068,
  2649. "Configure fabric error exit rval=%d.\n", rval);
  2650. }
  2651. return (rval);
  2652. }
  2653. /*
  2654. * qla2x00_find_all_fabric_devs
  2655. *
  2656. * Input:
  2657. * ha = adapter block pointer.
  2658. * dev = database device entry pointer.
  2659. *
  2660. * Returns:
  2661. * 0 = success.
  2662. *
  2663. * Context:
  2664. * Kernel context.
  2665. */
  2666. static int
  2667. qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
  2668. struct list_head *new_fcports)
  2669. {
  2670. int rval;
  2671. uint16_t loop_id;
  2672. fc_port_t *fcport, *new_fcport, *fcptemp;
  2673. int found;
  2674. sw_info_t *swl;
  2675. int swl_idx;
  2676. int first_dev, last_dev;
  2677. port_id_t wrap = {}, nxt_d_id;
  2678. struct qla_hw_data *ha = vha->hw;
  2679. struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
  2680. struct scsi_qla_host *tvp;
  2681. rval = QLA_SUCCESS;
  2682. /* Try GID_PT to get device list, else GAN. */
  2683. if (!ha->swl)
  2684. ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
  2685. GFP_KERNEL);
  2686. swl = ha->swl;
  2687. if (!swl) {
  2688. /*EMPTY*/
  2689. ql_dbg(ql_dbg_disc, vha, 0x2054,
  2690. "GID_PT allocations failed, fallback on GA_NXT.\n");
  2691. } else {
  2692. memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
  2693. if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
  2694. swl = NULL;
  2695. } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
  2696. swl = NULL;
  2697. } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
  2698. swl = NULL;
  2699. } else if (ql2xiidmaenable &&
  2700. qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
  2701. qla2x00_gpsc(vha, swl);
  2702. }
  2703. /* If other queries succeeded probe for FC-4 type */
  2704. if (swl)
  2705. qla2x00_gff_id(vha, swl);
  2706. }
  2707. swl_idx = 0;
  2708. /* Allocate temporary fcport for any new fcports discovered. */
  2709. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2710. if (new_fcport == NULL) {
  2711. ql_log(ql_log_warn, vha, 0x205e,
  2712. "Failed to allocate memory for fcport.\n");
  2713. return (QLA_MEMORY_ALLOC_FAILED);
  2714. }
  2715. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2716. /* Set start port ID scan at adapter ID. */
  2717. first_dev = 1;
  2718. last_dev = 0;
  2719. /* Starting free loop ID. */
  2720. loop_id = ha->min_external_loopid;
  2721. for (; loop_id <= ha->max_loop_id; loop_id++) {
  2722. if (qla2x00_is_reserved_id(vha, loop_id))
  2723. continue;
  2724. if (ha->current_topology == ISP_CFG_FL &&
  2725. (atomic_read(&vha->loop_down_timer) ||
  2726. LOOP_TRANSITION(vha))) {
  2727. atomic_set(&vha->loop_down_timer, 0);
  2728. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2729. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2730. break;
  2731. }
  2732. if (swl != NULL) {
  2733. if (last_dev) {
  2734. wrap.b24 = new_fcport->d_id.b24;
  2735. } else {
  2736. new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
  2737. memcpy(new_fcport->node_name,
  2738. swl[swl_idx].node_name, WWN_SIZE);
  2739. memcpy(new_fcport->port_name,
  2740. swl[swl_idx].port_name, WWN_SIZE);
  2741. memcpy(new_fcport->fabric_port_name,
  2742. swl[swl_idx].fabric_port_name, WWN_SIZE);
  2743. new_fcport->fp_speed = swl[swl_idx].fp_speed;
  2744. new_fcport->fc4_type = swl[swl_idx].fc4_type;
  2745. if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
  2746. last_dev = 1;
  2747. }
  2748. swl_idx++;
  2749. }
  2750. } else {
  2751. /* Send GA_NXT to the switch */
  2752. rval = qla2x00_ga_nxt(vha, new_fcport);
  2753. if (rval != QLA_SUCCESS) {
  2754. ql_log(ql_log_warn, vha, 0x2064,
  2755. "SNS scan failed -- assuming "
  2756. "zero-entry result.\n");
  2757. list_for_each_entry_safe(fcport, fcptemp,
  2758. new_fcports, list) {
  2759. list_del(&fcport->list);
  2760. kfree(fcport);
  2761. }
  2762. rval = QLA_SUCCESS;
  2763. break;
  2764. }
  2765. }
  2766. /* If wrap on switch device list, exit. */
  2767. if (first_dev) {
  2768. wrap.b24 = new_fcport->d_id.b24;
  2769. first_dev = 0;
  2770. } else if (new_fcport->d_id.b24 == wrap.b24) {
  2771. ql_dbg(ql_dbg_disc, vha, 0x2065,
  2772. "Device wrap (%02x%02x%02x).\n",
  2773. new_fcport->d_id.b.domain,
  2774. new_fcport->d_id.b.area,
  2775. new_fcport->d_id.b.al_pa);
  2776. break;
  2777. }
  2778. /* Bypass if same physical adapter. */
  2779. if (new_fcport->d_id.b24 == base_vha->d_id.b24)
  2780. continue;
  2781. /* Bypass virtual ports of the same host. */
  2782. found = 0;
  2783. if (ha->num_vhosts) {
  2784. unsigned long flags;
  2785. spin_lock_irqsave(&ha->vport_slock, flags);
  2786. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2787. if (new_fcport->d_id.b24 == vp->d_id.b24) {
  2788. found = 1;
  2789. break;
  2790. }
  2791. }
  2792. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2793. if (found)
  2794. continue;
  2795. }
  2796. /* Bypass if same domain and area of adapter. */
  2797. if (((new_fcport->d_id.b24 & 0xffff00) ==
  2798. (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
  2799. ISP_CFG_FL)
  2800. continue;
  2801. /* Bypass reserved domain fields. */
  2802. if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
  2803. continue;
  2804. /* Bypass ports whose FCP-4 type is not FCP_SCSI */
  2805. if (ql2xgffidenable &&
  2806. (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
  2807. new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
  2808. continue;
  2809. /* Locate matching device in database. */
  2810. found = 0;
  2811. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2812. if (memcmp(new_fcport->port_name, fcport->port_name,
  2813. WWN_SIZE))
  2814. continue;
  2815. fcport->scan_state = QLA_FCPORT_FOUND;
  2816. found++;
  2817. /* Update port state. */
  2818. memcpy(fcport->fabric_port_name,
  2819. new_fcport->fabric_port_name, WWN_SIZE);
  2820. fcport->fp_speed = new_fcport->fp_speed;
  2821. /*
  2822. * If address the same and state FCS_ONLINE, nothing
  2823. * changed.
  2824. */
  2825. if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
  2826. atomic_read(&fcport->state) == FCS_ONLINE) {
  2827. break;
  2828. }
  2829. /*
  2830. * If device was not a fabric device before.
  2831. */
  2832. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2833. fcport->d_id.b24 = new_fcport->d_id.b24;
  2834. fcport->loop_id = FC_NO_LOOP_ID;
  2835. fcport->flags |= (FCF_FABRIC_DEVICE |
  2836. FCF_LOGIN_NEEDED);
  2837. break;
  2838. }
  2839. /*
  2840. * Port ID changed or device was marked to be updated;
  2841. * Log it out if still logged in and mark it for
  2842. * relogin later.
  2843. */
  2844. fcport->d_id.b24 = new_fcport->d_id.b24;
  2845. fcport->flags |= FCF_LOGIN_NEEDED;
  2846. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2847. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2848. (fcport->flags & FCF_ASYNC_SENT) == 0 &&
  2849. fcport->port_type != FCT_INITIATOR &&
  2850. fcport->port_type != FCT_BROADCAST) {
  2851. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  2852. fcport->d_id.b.domain, fcport->d_id.b.area,
  2853. fcport->d_id.b.al_pa);
  2854. fcport->loop_id = FC_NO_LOOP_ID;
  2855. }
  2856. break;
  2857. }
  2858. if (found)
  2859. continue;
  2860. /* If device was not in our fcports list, then add it. */
  2861. list_add_tail(&new_fcport->list, new_fcports);
  2862. /* Allocate a new replacement fcport. */
  2863. nxt_d_id.b24 = new_fcport->d_id.b24;
  2864. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2865. if (new_fcport == NULL) {
  2866. ql_log(ql_log_warn, vha, 0x2066,
  2867. "Memory allocation failed for fcport.\n");
  2868. return (QLA_MEMORY_ALLOC_FAILED);
  2869. }
  2870. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2871. new_fcport->d_id.b24 = nxt_d_id.b24;
  2872. }
  2873. kfree(new_fcport);
  2874. return (rval);
  2875. }
  2876. /*
  2877. * qla2x00_find_new_loop_id
  2878. * Scan through our port list and find a new usable loop ID.
  2879. *
  2880. * Input:
  2881. * ha: adapter state pointer.
  2882. * dev: port structure pointer.
  2883. *
  2884. * Returns:
  2885. * qla2x00 local function return status code.
  2886. *
  2887. * Context:
  2888. * Kernel context.
  2889. */
  2890. int
  2891. qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
  2892. {
  2893. int rval;
  2894. int found;
  2895. fc_port_t *fcport;
  2896. uint16_t first_loop_id;
  2897. struct qla_hw_data *ha = vha->hw;
  2898. struct scsi_qla_host *vp;
  2899. struct scsi_qla_host *tvp;
  2900. unsigned long flags = 0;
  2901. rval = QLA_SUCCESS;
  2902. /* Save starting loop ID. */
  2903. first_loop_id = dev->loop_id;
  2904. for (;;) {
  2905. /* Skip loop ID if already used by adapter. */
  2906. if (dev->loop_id == vha->loop_id)
  2907. dev->loop_id++;
  2908. /* Skip reserved loop IDs. */
  2909. while (qla2x00_is_reserved_id(vha, dev->loop_id))
  2910. dev->loop_id++;
  2911. /* Reset loop ID if passed the end. */
  2912. if (dev->loop_id > ha->max_loop_id) {
  2913. /* first loop ID. */
  2914. dev->loop_id = ha->min_external_loopid;
  2915. }
  2916. /* Check for loop ID being already in use. */
  2917. found = 0;
  2918. fcport = NULL;
  2919. spin_lock_irqsave(&ha->vport_slock, flags);
  2920. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2921. list_for_each_entry(fcport, &vp->vp_fcports, list) {
  2922. if (fcport->loop_id == dev->loop_id &&
  2923. fcport != dev) {
  2924. /* ID possibly in use */
  2925. found++;
  2926. break;
  2927. }
  2928. }
  2929. if (found)
  2930. break;
  2931. }
  2932. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2933. /* If not in use then it is free to use. */
  2934. if (!found) {
  2935. ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
  2936. "Assigning new loopid=%x, portid=%x.\n",
  2937. dev->loop_id, dev->d_id.b24);
  2938. break;
  2939. }
  2940. /* ID in use. Try next value. */
  2941. dev->loop_id++;
  2942. /* If wrap around. No free ID to use. */
  2943. if (dev->loop_id == first_loop_id) {
  2944. dev->loop_id = FC_NO_LOOP_ID;
  2945. rval = QLA_FUNCTION_FAILED;
  2946. break;
  2947. }
  2948. }
  2949. return (rval);
  2950. }
  2951. /*
  2952. * qla2x00_fabric_dev_login
  2953. * Login fabric target device and update FC port database.
  2954. *
  2955. * Input:
  2956. * ha: adapter state pointer.
  2957. * fcport: port structure list pointer.
  2958. * next_loopid: contains value of a new loop ID that can be used
  2959. * by the next login attempt.
  2960. *
  2961. * Returns:
  2962. * qla2x00 local function return status code.
  2963. *
  2964. * Context:
  2965. * Kernel context.
  2966. */
  2967. static int
  2968. qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  2969. uint16_t *next_loopid)
  2970. {
  2971. int rval;
  2972. int retry;
  2973. uint8_t opts;
  2974. struct qla_hw_data *ha = vha->hw;
  2975. rval = QLA_SUCCESS;
  2976. retry = 0;
  2977. if (IS_ALOGIO_CAPABLE(ha)) {
  2978. if (fcport->flags & FCF_ASYNC_SENT)
  2979. return rval;
  2980. fcport->flags |= FCF_ASYNC_SENT;
  2981. rval = qla2x00_post_async_login_work(vha, fcport, NULL);
  2982. if (!rval)
  2983. return rval;
  2984. }
  2985. fcport->flags &= ~FCF_ASYNC_SENT;
  2986. rval = qla2x00_fabric_login(vha, fcport, next_loopid);
  2987. if (rval == QLA_SUCCESS) {
  2988. /* Send an ADISC to FCP2 devices.*/
  2989. opts = 0;
  2990. if (fcport->flags & FCF_FCP2_DEVICE)
  2991. opts |= BIT_1;
  2992. rval = qla2x00_get_port_database(vha, fcport, opts);
  2993. if (rval != QLA_SUCCESS) {
  2994. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  2995. fcport->d_id.b.domain, fcport->d_id.b.area,
  2996. fcport->d_id.b.al_pa);
  2997. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  2998. } else {
  2999. qla2x00_update_fcport(vha, fcport);
  3000. }
  3001. } else {
  3002. /* Retry Login. */
  3003. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3004. }
  3005. return (rval);
  3006. }
  3007. /*
  3008. * qla2x00_fabric_login
  3009. * Issue fabric login command.
  3010. *
  3011. * Input:
  3012. * ha = adapter block pointer.
  3013. * device = pointer to FC device type structure.
  3014. *
  3015. * Returns:
  3016. * 0 - Login successfully
  3017. * 1 - Login failed
  3018. * 2 - Initiator device
  3019. * 3 - Fatal error
  3020. */
  3021. int
  3022. qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3023. uint16_t *next_loopid)
  3024. {
  3025. int rval;
  3026. int retry;
  3027. uint16_t tmp_loopid;
  3028. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3029. struct qla_hw_data *ha = vha->hw;
  3030. retry = 0;
  3031. tmp_loopid = 0;
  3032. for (;;) {
  3033. ql_dbg(ql_dbg_disc, vha, 0x2000,
  3034. "Trying Fabric Login w/loop id 0x%04x for port "
  3035. "%02x%02x%02x.\n",
  3036. fcport->loop_id, fcport->d_id.b.domain,
  3037. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3038. /* Login fcport on switch. */
  3039. rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
  3040. fcport->d_id.b.domain, fcport->d_id.b.area,
  3041. fcport->d_id.b.al_pa, mb, BIT_0);
  3042. if (rval != QLA_SUCCESS) {
  3043. return rval;
  3044. }
  3045. if (mb[0] == MBS_PORT_ID_USED) {
  3046. /*
  3047. * Device has another loop ID. The firmware team
  3048. * recommends the driver perform an implicit login with
  3049. * the specified ID again. The ID we just used is save
  3050. * here so we return with an ID that can be tried by
  3051. * the next login.
  3052. */
  3053. retry++;
  3054. tmp_loopid = fcport->loop_id;
  3055. fcport->loop_id = mb[1];
  3056. ql_dbg(ql_dbg_disc, vha, 0x2001,
  3057. "Fabric Login: port in use - next loop "
  3058. "id=0x%04x, port id= %02x%02x%02x.\n",
  3059. fcport->loop_id, fcport->d_id.b.domain,
  3060. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3061. } else if (mb[0] == MBS_COMMAND_COMPLETE) {
  3062. /*
  3063. * Login succeeded.
  3064. */
  3065. if (retry) {
  3066. /* A retry occurred before. */
  3067. *next_loopid = tmp_loopid;
  3068. } else {
  3069. /*
  3070. * No retry occurred before. Just increment the
  3071. * ID value for next login.
  3072. */
  3073. *next_loopid = (fcport->loop_id + 1);
  3074. }
  3075. if (mb[1] & BIT_0) {
  3076. fcport->port_type = FCT_INITIATOR;
  3077. } else {
  3078. fcport->port_type = FCT_TARGET;
  3079. if (mb[1] & BIT_1) {
  3080. fcport->flags |= FCF_FCP2_DEVICE;
  3081. }
  3082. }
  3083. if (mb[10] & BIT_0)
  3084. fcport->supported_classes |= FC_COS_CLASS2;
  3085. if (mb[10] & BIT_1)
  3086. fcport->supported_classes |= FC_COS_CLASS3;
  3087. rval = QLA_SUCCESS;
  3088. break;
  3089. } else if (mb[0] == MBS_LOOP_ID_USED) {
  3090. /*
  3091. * Loop ID already used, try next loop ID.
  3092. */
  3093. fcport->loop_id++;
  3094. rval = qla2x00_find_new_loop_id(vha, fcport);
  3095. if (rval != QLA_SUCCESS) {
  3096. /* Ran out of loop IDs to use */
  3097. break;
  3098. }
  3099. } else if (mb[0] == MBS_COMMAND_ERROR) {
  3100. /*
  3101. * Firmware possibly timed out during login. If NO
  3102. * retries are left to do then the device is declared
  3103. * dead.
  3104. */
  3105. *next_loopid = fcport->loop_id;
  3106. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3107. fcport->d_id.b.domain, fcport->d_id.b.area,
  3108. fcport->d_id.b.al_pa);
  3109. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3110. rval = 1;
  3111. break;
  3112. } else {
  3113. /*
  3114. * unrecoverable / not handled error
  3115. */
  3116. ql_dbg(ql_dbg_disc, vha, 0x2002,
  3117. "Failed=%x port_id=%02x%02x%02x loop_id=%x "
  3118. "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
  3119. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  3120. fcport->loop_id, jiffies);
  3121. *next_loopid = fcport->loop_id;
  3122. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3123. fcport->d_id.b.domain, fcport->d_id.b.area,
  3124. fcport->d_id.b.al_pa);
  3125. fcport->loop_id = FC_NO_LOOP_ID;
  3126. fcport->login_retry = 0;
  3127. rval = 3;
  3128. break;
  3129. }
  3130. }
  3131. return (rval);
  3132. }
  3133. /*
  3134. * qla2x00_local_device_login
  3135. * Issue local device login command.
  3136. *
  3137. * Input:
  3138. * ha = adapter block pointer.
  3139. * loop_id = loop id of device to login to.
  3140. *
  3141. * Returns (Where's the #define!!!!):
  3142. * 0 - Login successfully
  3143. * 1 - Login failed
  3144. * 3 - Fatal error
  3145. */
  3146. int
  3147. qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
  3148. {
  3149. int rval;
  3150. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3151. memset(mb, 0, sizeof(mb));
  3152. rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
  3153. if (rval == QLA_SUCCESS) {
  3154. /* Interrogate mailbox registers for any errors */
  3155. if (mb[0] == MBS_COMMAND_ERROR)
  3156. rval = 1;
  3157. else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
  3158. /* device not in PCB table */
  3159. rval = 3;
  3160. }
  3161. return (rval);
  3162. }
  3163. /*
  3164. * qla2x00_loop_resync
  3165. * Resync with fibre channel devices.
  3166. *
  3167. * Input:
  3168. * ha = adapter block pointer.
  3169. *
  3170. * Returns:
  3171. * 0 = success
  3172. */
  3173. int
  3174. qla2x00_loop_resync(scsi_qla_host_t *vha)
  3175. {
  3176. int rval = QLA_SUCCESS;
  3177. uint32_t wait_time;
  3178. struct req_que *req;
  3179. struct rsp_que *rsp;
  3180. if (vha->hw->flags.cpu_affinity_enabled)
  3181. req = vha->hw->req_q_map[0];
  3182. else
  3183. req = vha->req;
  3184. rsp = req->rsp;
  3185. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3186. if (vha->flags.online) {
  3187. if (!(rval = qla2x00_fw_ready(vha))) {
  3188. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3189. wait_time = 256;
  3190. do {
  3191. /* Issue a marker after FW becomes ready. */
  3192. qla2x00_marker(vha, req, rsp, 0, 0,
  3193. MK_SYNC_ALL);
  3194. vha->marker_needed = 0;
  3195. /* Remap devices on Loop. */
  3196. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3197. qla2x00_configure_loop(vha);
  3198. wait_time--;
  3199. } while (!atomic_read(&vha->loop_down_timer) &&
  3200. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3201. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3202. &vha->dpc_flags)));
  3203. }
  3204. }
  3205. if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3206. return (QLA_FUNCTION_FAILED);
  3207. if (rval)
  3208. ql_dbg(ql_dbg_disc, vha, 0x206c,
  3209. "%s *** FAILED ***.\n", __func__);
  3210. return (rval);
  3211. }
  3212. /*
  3213. * qla2x00_perform_loop_resync
  3214. * Description: This function will set the appropriate flags and call
  3215. * qla2x00_loop_resync. If successful loop will be resynced
  3216. * Arguments : scsi_qla_host_t pointer
  3217. * returm : Success or Failure
  3218. */
  3219. int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
  3220. {
  3221. int32_t rval = 0;
  3222. if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
  3223. /*Configure the flags so that resync happens properly*/
  3224. atomic_set(&ha->loop_down_timer, 0);
  3225. if (!(ha->device_flags & DFLG_NO_CABLE)) {
  3226. atomic_set(&ha->loop_state, LOOP_UP);
  3227. set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
  3228. set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
  3229. set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
  3230. rval = qla2x00_loop_resync(ha);
  3231. } else
  3232. atomic_set(&ha->loop_state, LOOP_DEAD);
  3233. clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
  3234. }
  3235. return rval;
  3236. }
  3237. void
  3238. qla2x00_update_fcports(scsi_qla_host_t *base_vha)
  3239. {
  3240. fc_port_t *fcport;
  3241. struct scsi_qla_host *vha;
  3242. struct qla_hw_data *ha = base_vha->hw;
  3243. unsigned long flags;
  3244. spin_lock_irqsave(&ha->vport_slock, flags);
  3245. /* Go with deferred removal of rport references. */
  3246. list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
  3247. atomic_inc(&vha->vref_count);
  3248. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3249. if (fcport->drport &&
  3250. atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
  3251. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3252. qla2x00_rport_del(fcport);
  3253. spin_lock_irqsave(&ha->vport_slock, flags);
  3254. }
  3255. }
  3256. atomic_dec(&vha->vref_count);
  3257. }
  3258. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3259. }
  3260. /*
  3261. * qla82xx_quiescent_state_cleanup
  3262. * Description: This function will block the new I/Os
  3263. * Its not aborting any I/Os as context
  3264. * is not destroyed during quiescence
  3265. * Arguments: scsi_qla_host_t
  3266. * return : void
  3267. */
  3268. void
  3269. qla82xx_quiescent_state_cleanup(scsi_qla_host_t *vha)
  3270. {
  3271. struct qla_hw_data *ha = vha->hw;
  3272. struct scsi_qla_host *vp;
  3273. ql_dbg(ql_dbg_p3p, vha, 0xb002,
  3274. "Performing ISP error recovery - ha=%p.\n", ha);
  3275. atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
  3276. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3277. atomic_set(&vha->loop_state, LOOP_DOWN);
  3278. qla2x00_mark_all_devices_lost(vha, 0);
  3279. list_for_each_entry(vp, &ha->vp_list, list)
  3280. qla2x00_mark_all_devices_lost(vha, 0);
  3281. } else {
  3282. if (!atomic_read(&vha->loop_down_timer))
  3283. atomic_set(&vha->loop_down_timer,
  3284. LOOP_DOWN_TIME);
  3285. }
  3286. /* Wait for pending cmds to complete */
  3287. qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
  3288. }
  3289. void
  3290. qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
  3291. {
  3292. struct qla_hw_data *ha = vha->hw;
  3293. struct scsi_qla_host *vp;
  3294. unsigned long flags;
  3295. fc_port_t *fcport;
  3296. /* For ISP82XX, driver waits for completion of the commands.
  3297. * online flag should be set.
  3298. */
  3299. if (!IS_QLA82XX(ha))
  3300. vha->flags.online = 0;
  3301. ha->flags.chip_reset_done = 0;
  3302. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3303. vha->qla_stats.total_isp_aborts++;
  3304. ql_log(ql_log_info, vha, 0x00af,
  3305. "Performing ISP error recovery - ha=%p.\n", ha);
  3306. /* For ISP82XX, reset_chip is just disabling interrupts.
  3307. * Driver waits for the completion of the commands.
  3308. * the interrupts need to be enabled.
  3309. */
  3310. if (!IS_QLA82XX(ha))
  3311. ha->isp_ops->reset_chip(vha);
  3312. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  3313. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3314. atomic_set(&vha->loop_state, LOOP_DOWN);
  3315. qla2x00_mark_all_devices_lost(vha, 0);
  3316. spin_lock_irqsave(&ha->vport_slock, flags);
  3317. list_for_each_entry(vp, &ha->vp_list, list) {
  3318. atomic_inc(&vp->vref_count);
  3319. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3320. qla2x00_mark_all_devices_lost(vp, 0);
  3321. spin_lock_irqsave(&ha->vport_slock, flags);
  3322. atomic_dec(&vp->vref_count);
  3323. }
  3324. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3325. } else {
  3326. if (!atomic_read(&vha->loop_down_timer))
  3327. atomic_set(&vha->loop_down_timer,
  3328. LOOP_DOWN_TIME);
  3329. }
  3330. /* Clear all async request states across all VPs. */
  3331. list_for_each_entry(fcport, &vha->vp_fcports, list)
  3332. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3333. spin_lock_irqsave(&ha->vport_slock, flags);
  3334. list_for_each_entry(vp, &ha->vp_list, list) {
  3335. atomic_inc(&vp->vref_count);
  3336. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3337. list_for_each_entry(fcport, &vp->vp_fcports, list)
  3338. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3339. spin_lock_irqsave(&ha->vport_slock, flags);
  3340. atomic_dec(&vp->vref_count);
  3341. }
  3342. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3343. if (!ha->flags.eeh_busy) {
  3344. /* Make sure for ISP 82XX IO DMA is complete */
  3345. if (IS_QLA82XX(ha)) {
  3346. qla82xx_chip_reset_cleanup(vha);
  3347. ql_log(ql_log_info, vha, 0x00b4,
  3348. "Done chip reset cleanup.\n");
  3349. /* Done waiting for pending commands.
  3350. * Reset the online flag.
  3351. */
  3352. vha->flags.online = 0;
  3353. }
  3354. /* Requeue all commands in outstanding command list. */
  3355. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3356. }
  3357. }
  3358. /*
  3359. * qla2x00_abort_isp
  3360. * Resets ISP and aborts all outstanding commands.
  3361. *
  3362. * Input:
  3363. * ha = adapter block pointer.
  3364. *
  3365. * Returns:
  3366. * 0 = success
  3367. */
  3368. int
  3369. qla2x00_abort_isp(scsi_qla_host_t *vha)
  3370. {
  3371. int rval;
  3372. uint8_t status = 0;
  3373. struct qla_hw_data *ha = vha->hw;
  3374. struct scsi_qla_host *vp;
  3375. struct req_que *req = ha->req_q_map[0];
  3376. unsigned long flags;
  3377. if (vha->flags.online) {
  3378. qla2x00_abort_isp_cleanup(vha);
  3379. if (unlikely(pci_channel_offline(ha->pdev) &&
  3380. ha->flags.pci_channel_io_perm_failure)) {
  3381. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3382. status = 0;
  3383. return status;
  3384. }
  3385. ha->isp_ops->get_flash_version(vha, req->ring);
  3386. ha->isp_ops->nvram_config(vha);
  3387. if (!qla2x00_restart_isp(vha)) {
  3388. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3389. if (!atomic_read(&vha->loop_down_timer)) {
  3390. /*
  3391. * Issue marker command only when we are going
  3392. * to start the I/O .
  3393. */
  3394. vha->marker_needed = 1;
  3395. }
  3396. vha->flags.online = 1;
  3397. ha->isp_ops->enable_intrs(ha);
  3398. ha->isp_abort_cnt = 0;
  3399. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3400. if (IS_QLA81XX(ha) || IS_QLA8031(ha))
  3401. qla2x00_get_fw_version(vha);
  3402. if (ha->fce) {
  3403. ha->flags.fce_enabled = 1;
  3404. memset(ha->fce, 0,
  3405. fce_calc_size(ha->fce_bufs));
  3406. rval = qla2x00_enable_fce_trace(vha,
  3407. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  3408. &ha->fce_bufs);
  3409. if (rval) {
  3410. ql_log(ql_log_warn, vha, 0x8033,
  3411. "Unable to reinitialize FCE "
  3412. "(%d).\n", rval);
  3413. ha->flags.fce_enabled = 0;
  3414. }
  3415. }
  3416. if (ha->eft) {
  3417. memset(ha->eft, 0, EFT_SIZE);
  3418. rval = qla2x00_enable_eft_trace(vha,
  3419. ha->eft_dma, EFT_NUM_BUFFERS);
  3420. if (rval) {
  3421. ql_log(ql_log_warn, vha, 0x8034,
  3422. "Unable to reinitialize EFT "
  3423. "(%d).\n", rval);
  3424. }
  3425. }
  3426. } else { /* failed the ISP abort */
  3427. vha->flags.online = 1;
  3428. if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  3429. if (ha->isp_abort_cnt == 0) {
  3430. ql_log(ql_log_fatal, vha, 0x8035,
  3431. "ISP error recover failed - "
  3432. "board disabled.\n");
  3433. /*
  3434. * The next call disables the board
  3435. * completely.
  3436. */
  3437. ha->isp_ops->reset_adapter(vha);
  3438. vha->flags.online = 0;
  3439. clear_bit(ISP_ABORT_RETRY,
  3440. &vha->dpc_flags);
  3441. status = 0;
  3442. } else { /* schedule another ISP abort */
  3443. ha->isp_abort_cnt--;
  3444. ql_dbg(ql_dbg_taskm, vha, 0x8020,
  3445. "ISP abort - retry remaining %d.\n",
  3446. ha->isp_abort_cnt);
  3447. status = 1;
  3448. }
  3449. } else {
  3450. ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
  3451. ql_dbg(ql_dbg_taskm, vha, 0x8021,
  3452. "ISP error recovery - retrying (%d) "
  3453. "more times.\n", ha->isp_abort_cnt);
  3454. set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3455. status = 1;
  3456. }
  3457. }
  3458. }
  3459. if (!status) {
  3460. ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
  3461. spin_lock_irqsave(&ha->vport_slock, flags);
  3462. list_for_each_entry(vp, &ha->vp_list, list) {
  3463. if (vp->vp_idx) {
  3464. atomic_inc(&vp->vref_count);
  3465. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3466. qla2x00_vp_abort_isp(vp);
  3467. spin_lock_irqsave(&ha->vport_slock, flags);
  3468. atomic_dec(&vp->vref_count);
  3469. }
  3470. }
  3471. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3472. } else {
  3473. ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
  3474. __func__);
  3475. }
  3476. return(status);
  3477. }
  3478. /*
  3479. * qla2x00_restart_isp
  3480. * restarts the ISP after a reset
  3481. *
  3482. * Input:
  3483. * ha = adapter block pointer.
  3484. *
  3485. * Returns:
  3486. * 0 = success
  3487. */
  3488. static int
  3489. qla2x00_restart_isp(scsi_qla_host_t *vha)
  3490. {
  3491. int status = 0;
  3492. uint32_t wait_time;
  3493. struct qla_hw_data *ha = vha->hw;
  3494. struct req_que *req = ha->req_q_map[0];
  3495. struct rsp_que *rsp = ha->rsp_q_map[0];
  3496. /* If firmware needs to be loaded */
  3497. if (qla2x00_isp_firmware(vha)) {
  3498. vha->flags.online = 0;
  3499. status = ha->isp_ops->chip_diag(vha);
  3500. if (!status)
  3501. status = qla2x00_setup_chip(vha);
  3502. }
  3503. if (!status && !(status = qla2x00_init_rings(vha))) {
  3504. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3505. ha->flags.chip_reset_done = 1;
  3506. /* Initialize the queues in use */
  3507. qla25xx_init_queues(ha);
  3508. status = qla2x00_fw_ready(vha);
  3509. if (!status) {
  3510. ql_dbg(ql_dbg_taskm, vha, 0x8031,
  3511. "Start configure loop status = %d.\n", status);
  3512. /* Issue a marker after FW becomes ready. */
  3513. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  3514. vha->flags.online = 1;
  3515. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3516. wait_time = 256;
  3517. do {
  3518. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3519. qla2x00_configure_loop(vha);
  3520. wait_time--;
  3521. } while (!atomic_read(&vha->loop_down_timer) &&
  3522. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3523. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3524. &vha->dpc_flags)));
  3525. }
  3526. /* if no cable then assume it's good */
  3527. if ((vha->device_flags & DFLG_NO_CABLE))
  3528. status = 0;
  3529. ql_dbg(ql_dbg_taskm, vha, 0x8032,
  3530. "Configure loop done, status = 0x%x.\n", status);
  3531. }
  3532. return (status);
  3533. }
  3534. static int
  3535. qla25xx_init_queues(struct qla_hw_data *ha)
  3536. {
  3537. struct rsp_que *rsp = NULL;
  3538. struct req_que *req = NULL;
  3539. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  3540. int ret = -1;
  3541. int i;
  3542. for (i = 1; i < ha->max_rsp_queues; i++) {
  3543. rsp = ha->rsp_q_map[i];
  3544. if (rsp) {
  3545. rsp->options &= ~BIT_0;
  3546. ret = qla25xx_init_rsp_que(base_vha, rsp);
  3547. if (ret != QLA_SUCCESS)
  3548. ql_dbg(ql_dbg_init, base_vha, 0x00ff,
  3549. "%s Rsp que: %d init failed.\n",
  3550. __func__, rsp->id);
  3551. else
  3552. ql_dbg(ql_dbg_init, base_vha, 0x0100,
  3553. "%s Rsp que: %d inited.\n",
  3554. __func__, rsp->id);
  3555. }
  3556. }
  3557. for (i = 1; i < ha->max_req_queues; i++) {
  3558. req = ha->req_q_map[i];
  3559. if (req) {
  3560. /* Clear outstanding commands array. */
  3561. req->options &= ~BIT_0;
  3562. ret = qla25xx_init_req_que(base_vha, req);
  3563. if (ret != QLA_SUCCESS)
  3564. ql_dbg(ql_dbg_init, base_vha, 0x0101,
  3565. "%s Req que: %d init failed.\n",
  3566. __func__, req->id);
  3567. else
  3568. ql_dbg(ql_dbg_init, base_vha, 0x0102,
  3569. "%s Req que: %d inited.\n",
  3570. __func__, req->id);
  3571. }
  3572. }
  3573. return ret;
  3574. }
  3575. /*
  3576. * qla2x00_reset_adapter
  3577. * Reset adapter.
  3578. *
  3579. * Input:
  3580. * ha = adapter block pointer.
  3581. */
  3582. void
  3583. qla2x00_reset_adapter(scsi_qla_host_t *vha)
  3584. {
  3585. unsigned long flags = 0;
  3586. struct qla_hw_data *ha = vha->hw;
  3587. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3588. vha->flags.online = 0;
  3589. ha->isp_ops->disable_intrs(ha);
  3590. spin_lock_irqsave(&ha->hardware_lock, flags);
  3591. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  3592. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3593. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  3594. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3595. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3596. }
  3597. void
  3598. qla24xx_reset_adapter(scsi_qla_host_t *vha)
  3599. {
  3600. unsigned long flags = 0;
  3601. struct qla_hw_data *ha = vha->hw;
  3602. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3603. if (IS_QLA82XX(ha))
  3604. return;
  3605. vha->flags.online = 0;
  3606. ha->isp_ops->disable_intrs(ha);
  3607. spin_lock_irqsave(&ha->hardware_lock, flags);
  3608. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  3609. RD_REG_DWORD(&reg->hccr);
  3610. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  3611. RD_REG_DWORD(&reg->hccr);
  3612. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3613. if (IS_NOPOLLING_TYPE(ha))
  3614. ha->isp_ops->enable_intrs(ha);
  3615. }
  3616. /* On sparc systems, obtain port and node WWN from firmware
  3617. * properties.
  3618. */
  3619. static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
  3620. struct nvram_24xx *nv)
  3621. {
  3622. #ifdef CONFIG_SPARC
  3623. struct qla_hw_data *ha = vha->hw;
  3624. struct pci_dev *pdev = ha->pdev;
  3625. struct device_node *dp = pci_device_to_OF_node(pdev);
  3626. const u8 *val;
  3627. int len;
  3628. val = of_get_property(dp, "port-wwn", &len);
  3629. if (val && len >= WWN_SIZE)
  3630. memcpy(nv->port_name, val, WWN_SIZE);
  3631. val = of_get_property(dp, "node-wwn", &len);
  3632. if (val && len >= WWN_SIZE)
  3633. memcpy(nv->node_name, val, WWN_SIZE);
  3634. #endif
  3635. }
  3636. int
  3637. qla24xx_nvram_config(scsi_qla_host_t *vha)
  3638. {
  3639. int rval;
  3640. struct init_cb_24xx *icb;
  3641. struct nvram_24xx *nv;
  3642. uint32_t *dptr;
  3643. uint8_t *dptr1, *dptr2;
  3644. uint32_t chksum;
  3645. uint16_t cnt;
  3646. struct qla_hw_data *ha = vha->hw;
  3647. rval = QLA_SUCCESS;
  3648. icb = (struct init_cb_24xx *)ha->init_cb;
  3649. nv = ha->nvram;
  3650. /* Determine NVRAM starting address. */
  3651. if (ha->flags.port0) {
  3652. ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
  3653. ha->vpd_base = FA_NVRAM_VPD0_ADDR;
  3654. } else {
  3655. ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
  3656. ha->vpd_base = FA_NVRAM_VPD1_ADDR;
  3657. }
  3658. ha->nvram_size = sizeof(struct nvram_24xx);
  3659. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  3660. if (IS_QLA82XX(ha))
  3661. ha->vpd_size = FA_VPD_SIZE_82XX;
  3662. /* Get VPD data into cache */
  3663. ha->vpd = ha->nvram + VPD_OFFSET;
  3664. ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
  3665. ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
  3666. /* Get NVRAM data into cache and calculate checksum. */
  3667. dptr = (uint32_t *)nv;
  3668. ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
  3669. ha->nvram_size);
  3670. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  3671. chksum += le32_to_cpu(*dptr++);
  3672. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
  3673. "Contents of NVRAM\n");
  3674. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
  3675. (uint8_t *)nv, ha->nvram_size);
  3676. /* Bad NVRAM data, set defaults parameters. */
  3677. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  3678. || nv->id[3] != ' ' ||
  3679. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  3680. /* Reset NVRAM data. */
  3681. ql_log(ql_log_warn, vha, 0x006b,
  3682. "Inconsistent NVRAM detected: checksum=0x%x id=%c "
  3683. "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
  3684. ql_log(ql_log_warn, vha, 0x006c,
  3685. "Falling back to functioning (yet invalid -- WWPN) "
  3686. "defaults.\n");
  3687. /*
  3688. * Set default initialization control block.
  3689. */
  3690. memset(nv, 0, ha->nvram_size);
  3691. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  3692. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  3693. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  3694. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3695. nv->exchange_count = __constant_cpu_to_le16(0);
  3696. nv->hard_address = __constant_cpu_to_le16(124);
  3697. nv->port_name[0] = 0x21;
  3698. nv->port_name[1] = 0x00 + ha->port_no;
  3699. nv->port_name[2] = 0x00;
  3700. nv->port_name[3] = 0xe0;
  3701. nv->port_name[4] = 0x8b;
  3702. nv->port_name[5] = 0x1c;
  3703. nv->port_name[6] = 0x55;
  3704. nv->port_name[7] = 0x86;
  3705. nv->node_name[0] = 0x20;
  3706. nv->node_name[1] = 0x00;
  3707. nv->node_name[2] = 0x00;
  3708. nv->node_name[3] = 0xe0;
  3709. nv->node_name[4] = 0x8b;
  3710. nv->node_name[5] = 0x1c;
  3711. nv->node_name[6] = 0x55;
  3712. nv->node_name[7] = 0x86;
  3713. qla24xx_nvram_wwn_from_ofw(vha, nv);
  3714. nv->login_retry_count = __constant_cpu_to_le16(8);
  3715. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  3716. nv->login_timeout = __constant_cpu_to_le16(0);
  3717. nv->firmware_options_1 =
  3718. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  3719. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  3720. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  3721. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  3722. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  3723. nv->efi_parameters = __constant_cpu_to_le32(0);
  3724. nv->reset_delay = 5;
  3725. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  3726. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  3727. nv->link_down_timeout = __constant_cpu_to_le16(30);
  3728. rval = 1;
  3729. }
  3730. /* Reset Initialization control block */
  3731. memset(icb, 0, ha->init_cb_size);
  3732. /* Copy 1st segment. */
  3733. dptr1 = (uint8_t *)icb;
  3734. dptr2 = (uint8_t *)&nv->version;
  3735. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  3736. while (cnt--)
  3737. *dptr1++ = *dptr2++;
  3738. icb->login_retry_count = nv->login_retry_count;
  3739. icb->link_down_on_nos = nv->link_down_on_nos;
  3740. /* Copy 2nd segment. */
  3741. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  3742. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  3743. cnt = (uint8_t *)&icb->reserved_3 -
  3744. (uint8_t *)&icb->interrupt_delay_timer;
  3745. while (cnt--)
  3746. *dptr1++ = *dptr2++;
  3747. /*
  3748. * Setup driver NVRAM options.
  3749. */
  3750. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  3751. "QLA2462");
  3752. /* Use alternate WWN? */
  3753. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  3754. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  3755. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  3756. }
  3757. /* Prepare nodename */
  3758. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  3759. /*
  3760. * Firmware will apply the following mask if the nodename was
  3761. * not provided.
  3762. */
  3763. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  3764. icb->node_name[0] &= 0xF0;
  3765. }
  3766. /* Set host adapter parameters. */
  3767. ha->flags.disable_risc_code_load = 0;
  3768. ha->flags.enable_lip_reset = 0;
  3769. ha->flags.enable_lip_full_login =
  3770. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  3771. ha->flags.enable_target_reset =
  3772. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  3773. ha->flags.enable_led_scheme = 0;
  3774. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  3775. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  3776. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  3777. memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
  3778. sizeof(ha->fw_seriallink_options24));
  3779. /* save HBA serial number */
  3780. ha->serial0 = icb->port_name[5];
  3781. ha->serial1 = icb->port_name[6];
  3782. ha->serial2 = icb->port_name[7];
  3783. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  3784. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  3785. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3786. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  3787. /* Set minimum login_timeout to 4 seconds. */
  3788. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  3789. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  3790. if (le16_to_cpu(nv->login_timeout) < 4)
  3791. nv->login_timeout = __constant_cpu_to_le16(4);
  3792. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  3793. icb->login_timeout = nv->login_timeout;
  3794. /* Set minimum RATOV to 100 tenths of a second. */
  3795. ha->r_a_tov = 100;
  3796. ha->loop_reset_delay = nv->reset_delay;
  3797. /* Link Down Timeout = 0:
  3798. *
  3799. * When Port Down timer expires we will start returning
  3800. * I/O's to OS with "DID_NO_CONNECT".
  3801. *
  3802. * Link Down Timeout != 0:
  3803. *
  3804. * The driver waits for the link to come up after link down
  3805. * before returning I/Os to OS with "DID_NO_CONNECT".
  3806. */
  3807. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  3808. ha->loop_down_abort_time =
  3809. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  3810. } else {
  3811. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  3812. ha->loop_down_abort_time =
  3813. (LOOP_DOWN_TIME - ha->link_down_timeout);
  3814. }
  3815. /* Need enough time to try and get the port back. */
  3816. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  3817. if (qlport_down_retry)
  3818. ha->port_down_retry_count = qlport_down_retry;
  3819. /* Set login_retry_count */
  3820. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  3821. if (ha->port_down_retry_count ==
  3822. le16_to_cpu(nv->port_down_retry_count) &&
  3823. ha->port_down_retry_count > 3)
  3824. ha->login_retry_count = ha->port_down_retry_count;
  3825. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  3826. ha->login_retry_count = ha->port_down_retry_count;
  3827. if (ql2xloginretrycount)
  3828. ha->login_retry_count = ql2xloginretrycount;
  3829. /* Enable ZIO. */
  3830. if (!vha->flags.init_done) {
  3831. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  3832. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3833. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  3834. le16_to_cpu(icb->interrupt_delay_timer): 2;
  3835. }
  3836. icb->firmware_options_2 &= __constant_cpu_to_le32(
  3837. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  3838. vha->flags.process_response_queue = 0;
  3839. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  3840. ha->zio_mode = QLA_ZIO_MODE_6;
  3841. ql_log(ql_log_info, vha, 0x006f,
  3842. "ZIO mode %d enabled; timer delay (%d us).\n",
  3843. ha->zio_mode, ha->zio_timer * 100);
  3844. icb->firmware_options_2 |= cpu_to_le32(
  3845. (uint32_t)ha->zio_mode);
  3846. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  3847. vha->flags.process_response_queue = 1;
  3848. }
  3849. if (rval) {
  3850. ql_log(ql_log_warn, vha, 0x0070,
  3851. "NVRAM configuration failed.\n");
  3852. }
  3853. return (rval);
  3854. }
  3855. static int
  3856. qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
  3857. uint32_t faddr)
  3858. {
  3859. int rval = QLA_SUCCESS;
  3860. int segments, fragment;
  3861. uint32_t *dcode, dlen;
  3862. uint32_t risc_addr;
  3863. uint32_t risc_size;
  3864. uint32_t i;
  3865. struct qla_hw_data *ha = vha->hw;
  3866. struct req_que *req = ha->req_q_map[0];
  3867. ql_dbg(ql_dbg_init, vha, 0x008b,
  3868. "FW: Loading firmware from flash (%x).\n", faddr);
  3869. rval = QLA_SUCCESS;
  3870. segments = FA_RISC_CODE_SEGMENTS;
  3871. dcode = (uint32_t *)req->ring;
  3872. *srisc_addr = 0;
  3873. /* Validate firmware image by checking version. */
  3874. qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
  3875. for (i = 0; i < 4; i++)
  3876. dcode[i] = be32_to_cpu(dcode[i]);
  3877. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  3878. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  3879. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  3880. dcode[3] == 0)) {
  3881. ql_log(ql_log_fatal, vha, 0x008c,
  3882. "Unable to verify the integrity of flash firmware "
  3883. "image.\n");
  3884. ql_log(ql_log_fatal, vha, 0x008d,
  3885. "Firmware data: %08x %08x %08x %08x.\n",
  3886. dcode[0], dcode[1], dcode[2], dcode[3]);
  3887. return QLA_FUNCTION_FAILED;
  3888. }
  3889. while (segments && rval == QLA_SUCCESS) {
  3890. /* Read segment's load information. */
  3891. qla24xx_read_flash_data(vha, dcode, faddr, 4);
  3892. risc_addr = be32_to_cpu(dcode[2]);
  3893. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  3894. risc_size = be32_to_cpu(dcode[3]);
  3895. fragment = 0;
  3896. while (risc_size > 0 && rval == QLA_SUCCESS) {
  3897. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  3898. if (dlen > risc_size)
  3899. dlen = risc_size;
  3900. ql_dbg(ql_dbg_init, vha, 0x008e,
  3901. "Loading risc segment@ risc addr %x "
  3902. "number of dwords 0x%x offset 0x%x.\n",
  3903. risc_addr, dlen, faddr);
  3904. qla24xx_read_flash_data(vha, dcode, faddr, dlen);
  3905. for (i = 0; i < dlen; i++)
  3906. dcode[i] = swab32(dcode[i]);
  3907. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  3908. dlen);
  3909. if (rval) {
  3910. ql_log(ql_log_fatal, vha, 0x008f,
  3911. "Failed to load segment %d of firmware.\n",
  3912. fragment);
  3913. break;
  3914. }
  3915. faddr += dlen;
  3916. risc_addr += dlen;
  3917. risc_size -= dlen;
  3918. fragment++;
  3919. }
  3920. /* Next segment. */
  3921. segments--;
  3922. }
  3923. return rval;
  3924. }
  3925. #define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
  3926. int
  3927. qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  3928. {
  3929. int rval;
  3930. int i, fragment;
  3931. uint16_t *wcode, *fwcode;
  3932. uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
  3933. struct fw_blob *blob;
  3934. struct qla_hw_data *ha = vha->hw;
  3935. struct req_que *req = ha->req_q_map[0];
  3936. /* Load firmware blob. */
  3937. blob = qla2x00_request_firmware(vha);
  3938. if (!blob) {
  3939. ql_log(ql_log_info, vha, 0x0083,
  3940. "Fimware image unavailable.\n");
  3941. ql_log(ql_log_info, vha, 0x0084,
  3942. "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
  3943. return QLA_FUNCTION_FAILED;
  3944. }
  3945. rval = QLA_SUCCESS;
  3946. wcode = (uint16_t *)req->ring;
  3947. *srisc_addr = 0;
  3948. fwcode = (uint16_t *)blob->fw->data;
  3949. fwclen = 0;
  3950. /* Validate firmware image by checking version. */
  3951. if (blob->fw->size < 8 * sizeof(uint16_t)) {
  3952. ql_log(ql_log_fatal, vha, 0x0085,
  3953. "Unable to verify integrity of firmware image (%Zd).\n",
  3954. blob->fw->size);
  3955. goto fail_fw_integrity;
  3956. }
  3957. for (i = 0; i < 4; i++)
  3958. wcode[i] = be16_to_cpu(fwcode[i + 4]);
  3959. if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
  3960. wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
  3961. wcode[2] == 0 && wcode[3] == 0)) {
  3962. ql_log(ql_log_fatal, vha, 0x0086,
  3963. "Unable to verify integrity of firmware image.\n");
  3964. ql_log(ql_log_fatal, vha, 0x0087,
  3965. "Firmware data: %04x %04x %04x %04x.\n",
  3966. wcode[0], wcode[1], wcode[2], wcode[3]);
  3967. goto fail_fw_integrity;
  3968. }
  3969. seg = blob->segs;
  3970. while (*seg && rval == QLA_SUCCESS) {
  3971. risc_addr = *seg;
  3972. *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
  3973. risc_size = be16_to_cpu(fwcode[3]);
  3974. /* Validate firmware image size. */
  3975. fwclen += risc_size * sizeof(uint16_t);
  3976. if (blob->fw->size < fwclen) {
  3977. ql_log(ql_log_fatal, vha, 0x0088,
  3978. "Unable to verify integrity of firmware image "
  3979. "(%Zd).\n", blob->fw->size);
  3980. goto fail_fw_integrity;
  3981. }
  3982. fragment = 0;
  3983. while (risc_size > 0 && rval == QLA_SUCCESS) {
  3984. wlen = (uint16_t)(ha->fw_transfer_size >> 1);
  3985. if (wlen > risc_size)
  3986. wlen = risc_size;
  3987. ql_dbg(ql_dbg_init, vha, 0x0089,
  3988. "Loading risc segment@ risc addr %x number of "
  3989. "words 0x%x.\n", risc_addr, wlen);
  3990. for (i = 0; i < wlen; i++)
  3991. wcode[i] = swab16(fwcode[i]);
  3992. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  3993. wlen);
  3994. if (rval) {
  3995. ql_log(ql_log_fatal, vha, 0x008a,
  3996. "Failed to load segment %d of firmware.\n",
  3997. fragment);
  3998. break;
  3999. }
  4000. fwcode += wlen;
  4001. risc_addr += wlen;
  4002. risc_size -= wlen;
  4003. fragment++;
  4004. }
  4005. /* Next segment. */
  4006. seg++;
  4007. }
  4008. return rval;
  4009. fail_fw_integrity:
  4010. return QLA_FUNCTION_FAILED;
  4011. }
  4012. static int
  4013. qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4014. {
  4015. int rval;
  4016. int segments, fragment;
  4017. uint32_t *dcode, dlen;
  4018. uint32_t risc_addr;
  4019. uint32_t risc_size;
  4020. uint32_t i;
  4021. struct fw_blob *blob;
  4022. uint32_t *fwcode, fwclen;
  4023. struct qla_hw_data *ha = vha->hw;
  4024. struct req_que *req = ha->req_q_map[0];
  4025. /* Load firmware blob. */
  4026. blob = qla2x00_request_firmware(vha);
  4027. if (!blob) {
  4028. ql_log(ql_log_warn, vha, 0x0090,
  4029. "Fimware image unavailable.\n");
  4030. ql_log(ql_log_warn, vha, 0x0091,
  4031. "Firmware images can be retrieved from: "
  4032. QLA_FW_URL ".\n");
  4033. return QLA_FUNCTION_FAILED;
  4034. }
  4035. ql_dbg(ql_dbg_init, vha, 0x0092,
  4036. "FW: Loading via request-firmware.\n");
  4037. rval = QLA_SUCCESS;
  4038. segments = FA_RISC_CODE_SEGMENTS;
  4039. dcode = (uint32_t *)req->ring;
  4040. *srisc_addr = 0;
  4041. fwcode = (uint32_t *)blob->fw->data;
  4042. fwclen = 0;
  4043. /* Validate firmware image by checking version. */
  4044. if (blob->fw->size < 8 * sizeof(uint32_t)) {
  4045. ql_log(ql_log_fatal, vha, 0x0093,
  4046. "Unable to verify integrity of firmware image (%Zd).\n",
  4047. blob->fw->size);
  4048. goto fail_fw_integrity;
  4049. }
  4050. for (i = 0; i < 4; i++)
  4051. dcode[i] = be32_to_cpu(fwcode[i + 4]);
  4052. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4053. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4054. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4055. dcode[3] == 0)) {
  4056. ql_log(ql_log_fatal, vha, 0x0094,
  4057. "Unable to verify integrity of firmware image (%Zd).\n",
  4058. blob->fw->size);
  4059. ql_log(ql_log_fatal, vha, 0x0095,
  4060. "Firmware data: %08x %08x %08x %08x.\n",
  4061. dcode[0], dcode[1], dcode[2], dcode[3]);
  4062. goto fail_fw_integrity;
  4063. }
  4064. while (segments && rval == QLA_SUCCESS) {
  4065. risc_addr = be32_to_cpu(fwcode[2]);
  4066. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4067. risc_size = be32_to_cpu(fwcode[3]);
  4068. /* Validate firmware image size. */
  4069. fwclen += risc_size * sizeof(uint32_t);
  4070. if (blob->fw->size < fwclen) {
  4071. ql_log(ql_log_fatal, vha, 0x0096,
  4072. "Unable to verify integrity of firmware image "
  4073. "(%Zd).\n", blob->fw->size);
  4074. goto fail_fw_integrity;
  4075. }
  4076. fragment = 0;
  4077. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4078. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4079. if (dlen > risc_size)
  4080. dlen = risc_size;
  4081. ql_dbg(ql_dbg_init, vha, 0x0097,
  4082. "Loading risc segment@ risc addr %x "
  4083. "number of dwords 0x%x.\n", risc_addr, dlen);
  4084. for (i = 0; i < dlen; i++)
  4085. dcode[i] = swab32(fwcode[i]);
  4086. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4087. dlen);
  4088. if (rval) {
  4089. ql_log(ql_log_fatal, vha, 0x0098,
  4090. "Failed to load segment %d of firmware.\n",
  4091. fragment);
  4092. break;
  4093. }
  4094. fwcode += dlen;
  4095. risc_addr += dlen;
  4096. risc_size -= dlen;
  4097. fragment++;
  4098. }
  4099. /* Next segment. */
  4100. segments--;
  4101. }
  4102. return rval;
  4103. fail_fw_integrity:
  4104. return QLA_FUNCTION_FAILED;
  4105. }
  4106. int
  4107. qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4108. {
  4109. int rval;
  4110. if (ql2xfwloadbin == 1)
  4111. return qla81xx_load_risc(vha, srisc_addr);
  4112. /*
  4113. * FW Load priority:
  4114. * 1) Firmware via request-firmware interface (.bin file).
  4115. * 2) Firmware residing in flash.
  4116. */
  4117. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4118. if (rval == QLA_SUCCESS)
  4119. return rval;
  4120. return qla24xx_load_risc_flash(vha, srisc_addr,
  4121. vha->hw->flt_region_fw);
  4122. }
  4123. int
  4124. qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4125. {
  4126. int rval;
  4127. struct qla_hw_data *ha = vha->hw;
  4128. if (ql2xfwloadbin == 2)
  4129. goto try_blob_fw;
  4130. /*
  4131. * FW Load priority:
  4132. * 1) Firmware residing in flash.
  4133. * 2) Firmware via request-firmware interface (.bin file).
  4134. * 3) Golden-Firmware residing in flash -- limited operation.
  4135. */
  4136. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
  4137. if (rval == QLA_SUCCESS)
  4138. return rval;
  4139. try_blob_fw:
  4140. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4141. if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
  4142. return rval;
  4143. ql_log(ql_log_info, vha, 0x0099,
  4144. "Attempting to fallback to golden firmware.\n");
  4145. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
  4146. if (rval != QLA_SUCCESS)
  4147. return rval;
  4148. ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
  4149. ha->flags.running_gold_fw = 1;
  4150. return rval;
  4151. }
  4152. void
  4153. qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
  4154. {
  4155. int ret, retries;
  4156. struct qla_hw_data *ha = vha->hw;
  4157. if (ha->flags.pci_channel_io_perm_failure)
  4158. return;
  4159. if (!IS_FWI2_CAPABLE(ha))
  4160. return;
  4161. if (!ha->fw_major_version)
  4162. return;
  4163. ret = qla2x00_stop_firmware(vha);
  4164. for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
  4165. ret != QLA_INVALID_COMMAND && retries ; retries--) {
  4166. ha->isp_ops->reset_chip(vha);
  4167. if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
  4168. continue;
  4169. if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
  4170. continue;
  4171. ql_log(ql_log_info, vha, 0x8015,
  4172. "Attempting retry of stop-firmware command.\n");
  4173. ret = qla2x00_stop_firmware(vha);
  4174. }
  4175. }
  4176. int
  4177. qla24xx_configure_vhba(scsi_qla_host_t *vha)
  4178. {
  4179. int rval = QLA_SUCCESS;
  4180. int rval2;
  4181. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4182. struct qla_hw_data *ha = vha->hw;
  4183. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  4184. struct req_que *req;
  4185. struct rsp_que *rsp;
  4186. if (!vha->vp_idx)
  4187. return -EINVAL;
  4188. rval = qla2x00_fw_ready(base_vha);
  4189. if (ha->flags.cpu_affinity_enabled)
  4190. req = ha->req_q_map[0];
  4191. else
  4192. req = vha->req;
  4193. rsp = req->rsp;
  4194. if (rval == QLA_SUCCESS) {
  4195. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4196. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4197. }
  4198. vha->flags.management_server_logged_in = 0;
  4199. /* Login to SNS first */
  4200. rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
  4201. BIT_1);
  4202. if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
  4203. if (rval2 == QLA_MEMORY_ALLOC_FAILED)
  4204. ql_dbg(ql_dbg_init, vha, 0x0120,
  4205. "Failed SNS login: loop_id=%x, rval2=%d\n",
  4206. NPH_SNS, rval2);
  4207. else
  4208. ql_dbg(ql_dbg_init, vha, 0x0103,
  4209. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
  4210. "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
  4211. NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
  4212. return (QLA_FUNCTION_FAILED);
  4213. }
  4214. atomic_set(&vha->loop_down_timer, 0);
  4215. atomic_set(&vha->loop_state, LOOP_UP);
  4216. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4217. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4218. rval = qla2x00_loop_resync(base_vha);
  4219. return rval;
  4220. }
  4221. /* 84XX Support **************************************************************/
  4222. static LIST_HEAD(qla_cs84xx_list);
  4223. static DEFINE_MUTEX(qla_cs84xx_mutex);
  4224. static struct qla_chip_state_84xx *
  4225. qla84xx_get_chip(struct scsi_qla_host *vha)
  4226. {
  4227. struct qla_chip_state_84xx *cs84xx;
  4228. struct qla_hw_data *ha = vha->hw;
  4229. mutex_lock(&qla_cs84xx_mutex);
  4230. /* Find any shared 84xx chip. */
  4231. list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
  4232. if (cs84xx->bus == ha->pdev->bus) {
  4233. kref_get(&cs84xx->kref);
  4234. goto done;
  4235. }
  4236. }
  4237. cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
  4238. if (!cs84xx)
  4239. goto done;
  4240. kref_init(&cs84xx->kref);
  4241. spin_lock_init(&cs84xx->access_lock);
  4242. mutex_init(&cs84xx->fw_update_mutex);
  4243. cs84xx->bus = ha->pdev->bus;
  4244. list_add_tail(&cs84xx->list, &qla_cs84xx_list);
  4245. done:
  4246. mutex_unlock(&qla_cs84xx_mutex);
  4247. return cs84xx;
  4248. }
  4249. static void
  4250. __qla84xx_chip_release(struct kref *kref)
  4251. {
  4252. struct qla_chip_state_84xx *cs84xx =
  4253. container_of(kref, struct qla_chip_state_84xx, kref);
  4254. mutex_lock(&qla_cs84xx_mutex);
  4255. list_del(&cs84xx->list);
  4256. mutex_unlock(&qla_cs84xx_mutex);
  4257. kfree(cs84xx);
  4258. }
  4259. void
  4260. qla84xx_put_chip(struct scsi_qla_host *vha)
  4261. {
  4262. struct qla_hw_data *ha = vha->hw;
  4263. if (ha->cs84xx)
  4264. kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
  4265. }
  4266. static int
  4267. qla84xx_init_chip(scsi_qla_host_t *vha)
  4268. {
  4269. int rval;
  4270. uint16_t status[2];
  4271. struct qla_hw_data *ha = vha->hw;
  4272. mutex_lock(&ha->cs84xx->fw_update_mutex);
  4273. rval = qla84xx_verify_chip(vha, status);
  4274. mutex_unlock(&ha->cs84xx->fw_update_mutex);
  4275. return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
  4276. QLA_SUCCESS;
  4277. }
  4278. /* 81XX Support **************************************************************/
  4279. int
  4280. qla81xx_nvram_config(scsi_qla_host_t *vha)
  4281. {
  4282. int rval;
  4283. struct init_cb_81xx *icb;
  4284. struct nvram_81xx *nv;
  4285. uint32_t *dptr;
  4286. uint8_t *dptr1, *dptr2;
  4287. uint32_t chksum;
  4288. uint16_t cnt;
  4289. struct qla_hw_data *ha = vha->hw;
  4290. rval = QLA_SUCCESS;
  4291. icb = (struct init_cb_81xx *)ha->init_cb;
  4292. nv = ha->nvram;
  4293. /* Determine NVRAM starting address. */
  4294. ha->nvram_size = sizeof(struct nvram_81xx);
  4295. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  4296. /* Get VPD data into cache */
  4297. ha->vpd = ha->nvram + VPD_OFFSET;
  4298. ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
  4299. ha->vpd_size);
  4300. /* Get NVRAM data into cache and calculate checksum. */
  4301. ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
  4302. ha->nvram_size);
  4303. dptr = (uint32_t *)nv;
  4304. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  4305. chksum += le32_to_cpu(*dptr++);
  4306. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
  4307. "Contents of NVRAM:\n");
  4308. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
  4309. (uint8_t *)nv, ha->nvram_size);
  4310. /* Bad NVRAM data, set defaults parameters. */
  4311. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  4312. || nv->id[3] != ' ' ||
  4313. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  4314. /* Reset NVRAM data. */
  4315. ql_log(ql_log_info, vha, 0x0073,
  4316. "Inconsistent NVRAM detected: checksum=0x%x id=%c "
  4317. "version=0x%x.\n", chksum, nv->id[0],
  4318. le16_to_cpu(nv->nvram_version));
  4319. ql_log(ql_log_info, vha, 0x0074,
  4320. "Falling back to functioning (yet invalid -- WWPN) "
  4321. "defaults.\n");
  4322. /*
  4323. * Set default initialization control block.
  4324. */
  4325. memset(nv, 0, ha->nvram_size);
  4326. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  4327. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  4328. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  4329. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4330. nv->exchange_count = __constant_cpu_to_le16(0);
  4331. nv->port_name[0] = 0x21;
  4332. nv->port_name[1] = 0x00 + ha->port_no;
  4333. nv->port_name[2] = 0x00;
  4334. nv->port_name[3] = 0xe0;
  4335. nv->port_name[4] = 0x8b;
  4336. nv->port_name[5] = 0x1c;
  4337. nv->port_name[6] = 0x55;
  4338. nv->port_name[7] = 0x86;
  4339. nv->node_name[0] = 0x20;
  4340. nv->node_name[1] = 0x00;
  4341. nv->node_name[2] = 0x00;
  4342. nv->node_name[3] = 0xe0;
  4343. nv->node_name[4] = 0x8b;
  4344. nv->node_name[5] = 0x1c;
  4345. nv->node_name[6] = 0x55;
  4346. nv->node_name[7] = 0x86;
  4347. nv->login_retry_count = __constant_cpu_to_le16(8);
  4348. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  4349. nv->login_timeout = __constant_cpu_to_le16(0);
  4350. nv->firmware_options_1 =
  4351. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  4352. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  4353. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  4354. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  4355. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  4356. nv->efi_parameters = __constant_cpu_to_le32(0);
  4357. nv->reset_delay = 5;
  4358. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  4359. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  4360. nv->link_down_timeout = __constant_cpu_to_le16(180);
  4361. nv->enode_mac[0] = 0x00;
  4362. nv->enode_mac[1] = 0xC0;
  4363. nv->enode_mac[2] = 0xDD;
  4364. nv->enode_mac[3] = 0x04;
  4365. nv->enode_mac[4] = 0x05;
  4366. nv->enode_mac[5] = 0x06 + ha->port_no;
  4367. rval = 1;
  4368. }
  4369. /* Reset Initialization control block */
  4370. memset(icb, 0, ha->init_cb_size);
  4371. /* Copy 1st segment. */
  4372. dptr1 = (uint8_t *)icb;
  4373. dptr2 = (uint8_t *)&nv->version;
  4374. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  4375. while (cnt--)
  4376. *dptr1++ = *dptr2++;
  4377. icb->login_retry_count = nv->login_retry_count;
  4378. /* Copy 2nd segment. */
  4379. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  4380. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  4381. cnt = (uint8_t *)&icb->reserved_5 -
  4382. (uint8_t *)&icb->interrupt_delay_timer;
  4383. while (cnt--)
  4384. *dptr1++ = *dptr2++;
  4385. memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
  4386. /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
  4387. if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
  4388. icb->enode_mac[0] = 0x00;
  4389. icb->enode_mac[1] = 0xC0;
  4390. icb->enode_mac[2] = 0xDD;
  4391. icb->enode_mac[3] = 0x04;
  4392. icb->enode_mac[4] = 0x05;
  4393. icb->enode_mac[5] = 0x06 + ha->port_no;
  4394. }
  4395. /* Use extended-initialization control block. */
  4396. memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
  4397. /*
  4398. * Setup driver NVRAM options.
  4399. */
  4400. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  4401. "QLE8XXX");
  4402. /* Use alternate WWN? */
  4403. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  4404. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  4405. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  4406. }
  4407. /* Prepare nodename */
  4408. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  4409. /*
  4410. * Firmware will apply the following mask if the nodename was
  4411. * not provided.
  4412. */
  4413. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  4414. icb->node_name[0] &= 0xF0;
  4415. }
  4416. /* Set host adapter parameters. */
  4417. ha->flags.disable_risc_code_load = 0;
  4418. ha->flags.enable_lip_reset = 0;
  4419. ha->flags.enable_lip_full_login =
  4420. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  4421. ha->flags.enable_target_reset =
  4422. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  4423. ha->flags.enable_led_scheme = 0;
  4424. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  4425. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  4426. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  4427. /* save HBA serial number */
  4428. ha->serial0 = icb->port_name[5];
  4429. ha->serial1 = icb->port_name[6];
  4430. ha->serial2 = icb->port_name[7];
  4431. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  4432. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  4433. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4434. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  4435. /* Set minimum login_timeout to 4 seconds. */
  4436. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  4437. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  4438. if (le16_to_cpu(nv->login_timeout) < 4)
  4439. nv->login_timeout = __constant_cpu_to_le16(4);
  4440. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  4441. icb->login_timeout = nv->login_timeout;
  4442. /* Set minimum RATOV to 100 tenths of a second. */
  4443. ha->r_a_tov = 100;
  4444. ha->loop_reset_delay = nv->reset_delay;
  4445. /* Link Down Timeout = 0:
  4446. *
  4447. * When Port Down timer expires we will start returning
  4448. * I/O's to OS with "DID_NO_CONNECT".
  4449. *
  4450. * Link Down Timeout != 0:
  4451. *
  4452. * The driver waits for the link to come up after link down
  4453. * before returning I/Os to OS with "DID_NO_CONNECT".
  4454. */
  4455. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  4456. ha->loop_down_abort_time =
  4457. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  4458. } else {
  4459. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  4460. ha->loop_down_abort_time =
  4461. (LOOP_DOWN_TIME - ha->link_down_timeout);
  4462. }
  4463. /* Need enough time to try and get the port back. */
  4464. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  4465. if (qlport_down_retry)
  4466. ha->port_down_retry_count = qlport_down_retry;
  4467. /* Set login_retry_count */
  4468. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  4469. if (ha->port_down_retry_count ==
  4470. le16_to_cpu(nv->port_down_retry_count) &&
  4471. ha->port_down_retry_count > 3)
  4472. ha->login_retry_count = ha->port_down_retry_count;
  4473. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  4474. ha->login_retry_count = ha->port_down_retry_count;
  4475. if (ql2xloginretrycount)
  4476. ha->login_retry_count = ql2xloginretrycount;
  4477. /* if not running MSI-X we need handshaking on interrupts */
  4478. if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
  4479. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
  4480. /* Enable ZIO. */
  4481. if (!vha->flags.init_done) {
  4482. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  4483. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  4484. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  4485. le16_to_cpu(icb->interrupt_delay_timer): 2;
  4486. }
  4487. icb->firmware_options_2 &= __constant_cpu_to_le32(
  4488. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  4489. vha->flags.process_response_queue = 0;
  4490. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  4491. ha->zio_mode = QLA_ZIO_MODE_6;
  4492. ql_log(ql_log_info, vha, 0x0075,
  4493. "ZIO mode %d enabled; timer delay (%d us).\n",
  4494. ha->zio_mode,
  4495. ha->zio_timer * 100);
  4496. icb->firmware_options_2 |= cpu_to_le32(
  4497. (uint32_t)ha->zio_mode);
  4498. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  4499. vha->flags.process_response_queue = 1;
  4500. }
  4501. if (rval) {
  4502. ql_log(ql_log_warn, vha, 0x0076,
  4503. "NVRAM configuration failed.\n");
  4504. }
  4505. return (rval);
  4506. }
  4507. int
  4508. qla82xx_restart_isp(scsi_qla_host_t *vha)
  4509. {
  4510. int status, rval;
  4511. uint32_t wait_time;
  4512. struct qla_hw_data *ha = vha->hw;
  4513. struct req_que *req = ha->req_q_map[0];
  4514. struct rsp_que *rsp = ha->rsp_q_map[0];
  4515. struct scsi_qla_host *vp;
  4516. unsigned long flags;
  4517. status = qla2x00_init_rings(vha);
  4518. if (!status) {
  4519. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4520. ha->flags.chip_reset_done = 1;
  4521. status = qla2x00_fw_ready(vha);
  4522. if (!status) {
  4523. ql_log(ql_log_info, vha, 0x803c,
  4524. "Start configure loop, status =%d.\n", status);
  4525. /* Issue a marker after FW becomes ready. */
  4526. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4527. vha->flags.online = 1;
  4528. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  4529. wait_time = 256;
  4530. do {
  4531. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4532. qla2x00_configure_loop(vha);
  4533. wait_time--;
  4534. } while (!atomic_read(&vha->loop_down_timer) &&
  4535. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
  4536. wait_time &&
  4537. (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
  4538. }
  4539. /* if no cable then assume it's good */
  4540. if ((vha->device_flags & DFLG_NO_CABLE))
  4541. status = 0;
  4542. ql_log(ql_log_info, vha, 0x8000,
  4543. "Configure loop done, status = 0x%x.\n", status);
  4544. }
  4545. if (!status) {
  4546. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4547. if (!atomic_read(&vha->loop_down_timer)) {
  4548. /*
  4549. * Issue marker command only when we are going
  4550. * to start the I/O .
  4551. */
  4552. vha->marker_needed = 1;
  4553. }
  4554. vha->flags.online = 1;
  4555. ha->isp_ops->enable_intrs(ha);
  4556. ha->isp_abort_cnt = 0;
  4557. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  4558. /* Update the firmware version */
  4559. status = qla82xx_check_md_needed(vha);
  4560. if (ha->fce) {
  4561. ha->flags.fce_enabled = 1;
  4562. memset(ha->fce, 0,
  4563. fce_calc_size(ha->fce_bufs));
  4564. rval = qla2x00_enable_fce_trace(vha,
  4565. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  4566. &ha->fce_bufs);
  4567. if (rval) {
  4568. ql_log(ql_log_warn, vha, 0x8001,
  4569. "Unable to reinitialize FCE (%d).\n",
  4570. rval);
  4571. ha->flags.fce_enabled = 0;
  4572. }
  4573. }
  4574. if (ha->eft) {
  4575. memset(ha->eft, 0, EFT_SIZE);
  4576. rval = qla2x00_enable_eft_trace(vha,
  4577. ha->eft_dma, EFT_NUM_BUFFERS);
  4578. if (rval) {
  4579. ql_log(ql_log_warn, vha, 0x8010,
  4580. "Unable to reinitialize EFT (%d).\n",
  4581. rval);
  4582. }
  4583. }
  4584. }
  4585. if (!status) {
  4586. ql_dbg(ql_dbg_taskm, vha, 0x8011,
  4587. "qla82xx_restart_isp succeeded.\n");
  4588. spin_lock_irqsave(&ha->vport_slock, flags);
  4589. list_for_each_entry(vp, &ha->vp_list, list) {
  4590. if (vp->vp_idx) {
  4591. atomic_inc(&vp->vref_count);
  4592. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4593. qla2x00_vp_abort_isp(vp);
  4594. spin_lock_irqsave(&ha->vport_slock, flags);
  4595. atomic_dec(&vp->vref_count);
  4596. }
  4597. }
  4598. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4599. } else {
  4600. ql_log(ql_log_warn, vha, 0x8016,
  4601. "qla82xx_restart_isp **** FAILED ****.\n");
  4602. }
  4603. return status;
  4604. }
  4605. void
  4606. qla81xx_update_fw_options(scsi_qla_host_t *vha)
  4607. {
  4608. struct qla_hw_data *ha = vha->hw;
  4609. if (!ql2xetsenable)
  4610. return;
  4611. /* Enable ETS Burst. */
  4612. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  4613. ha->fw_options[2] |= BIT_9;
  4614. qla2x00_set_fw_options(vha, ha->fw_options);
  4615. }
  4616. /*
  4617. * qla24xx_get_fcp_prio
  4618. * Gets the fcp cmd priority value for the logged in port.
  4619. * Looks for a match of the port descriptors within
  4620. * each of the fcp prio config entries. If a match is found,
  4621. * the tag (priority) value is returned.
  4622. *
  4623. * Input:
  4624. * vha = scsi host structure pointer.
  4625. * fcport = port structure pointer.
  4626. *
  4627. * Return:
  4628. * non-zero (if found)
  4629. * -1 (if not found)
  4630. *
  4631. * Context:
  4632. * Kernel context
  4633. */
  4634. static int
  4635. qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4636. {
  4637. int i, entries;
  4638. uint8_t pid_match, wwn_match;
  4639. int priority;
  4640. uint32_t pid1, pid2;
  4641. uint64_t wwn1, wwn2;
  4642. struct qla_fcp_prio_entry *pri_entry;
  4643. struct qla_hw_data *ha = vha->hw;
  4644. if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
  4645. return -1;
  4646. priority = -1;
  4647. entries = ha->fcp_prio_cfg->num_entries;
  4648. pri_entry = &ha->fcp_prio_cfg->entry[0];
  4649. for (i = 0; i < entries; i++) {
  4650. pid_match = wwn_match = 0;
  4651. if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
  4652. pri_entry++;
  4653. continue;
  4654. }
  4655. /* check source pid for a match */
  4656. if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
  4657. pid1 = pri_entry->src_pid & INVALID_PORT_ID;
  4658. pid2 = vha->d_id.b24 & INVALID_PORT_ID;
  4659. if (pid1 == INVALID_PORT_ID)
  4660. pid_match++;
  4661. else if (pid1 == pid2)
  4662. pid_match++;
  4663. }
  4664. /* check destination pid for a match */
  4665. if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
  4666. pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
  4667. pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
  4668. if (pid1 == INVALID_PORT_ID)
  4669. pid_match++;
  4670. else if (pid1 == pid2)
  4671. pid_match++;
  4672. }
  4673. /* check source WWN for a match */
  4674. if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
  4675. wwn1 = wwn_to_u64(vha->port_name);
  4676. wwn2 = wwn_to_u64(pri_entry->src_wwpn);
  4677. if (wwn2 == (uint64_t)-1)
  4678. wwn_match++;
  4679. else if (wwn1 == wwn2)
  4680. wwn_match++;
  4681. }
  4682. /* check destination WWN for a match */
  4683. if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
  4684. wwn1 = wwn_to_u64(fcport->port_name);
  4685. wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
  4686. if (wwn2 == (uint64_t)-1)
  4687. wwn_match++;
  4688. else if (wwn1 == wwn2)
  4689. wwn_match++;
  4690. }
  4691. if (pid_match == 2 || wwn_match == 2) {
  4692. /* Found a matching entry */
  4693. if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
  4694. priority = pri_entry->tag;
  4695. break;
  4696. }
  4697. pri_entry++;
  4698. }
  4699. return priority;
  4700. }
  4701. /*
  4702. * qla24xx_update_fcport_fcp_prio
  4703. * Activates fcp priority for the logged in fc port
  4704. *
  4705. * Input:
  4706. * vha = scsi host structure pointer.
  4707. * fcp = port structure pointer.
  4708. *
  4709. * Return:
  4710. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4711. *
  4712. * Context:
  4713. * Kernel context.
  4714. */
  4715. int
  4716. qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4717. {
  4718. int ret;
  4719. int priority;
  4720. uint16_t mb[5];
  4721. if (fcport->port_type != FCT_TARGET ||
  4722. fcport->loop_id == FC_NO_LOOP_ID)
  4723. return QLA_FUNCTION_FAILED;
  4724. priority = qla24xx_get_fcp_prio(vha, fcport);
  4725. if (priority < 0)
  4726. return QLA_FUNCTION_FAILED;
  4727. if (IS_QLA82XX(vha->hw)) {
  4728. fcport->fcp_prio = priority & 0xf;
  4729. return QLA_SUCCESS;
  4730. }
  4731. ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
  4732. if (ret == QLA_SUCCESS) {
  4733. if (fcport->fcp_prio != priority)
  4734. ql_dbg(ql_dbg_user, vha, 0x709e,
  4735. "Updated FCP_CMND priority - value=%d loop_id=%d "
  4736. "port_id=%02x%02x%02x.\n", priority,
  4737. fcport->loop_id, fcport->d_id.b.domain,
  4738. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  4739. fcport->fcp_prio = priority & 0xf;
  4740. } else
  4741. ql_dbg(ql_dbg_user, vha, 0x704f,
  4742. "Unable to update FCP_CMND priority - ret=0x%x for "
  4743. "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
  4744. fcport->d_id.b.domain, fcport->d_id.b.area,
  4745. fcport->d_id.b.al_pa);
  4746. return ret;
  4747. }
  4748. /*
  4749. * qla24xx_update_all_fcp_prio
  4750. * Activates fcp priority for all the logged in ports
  4751. *
  4752. * Input:
  4753. * ha = adapter block pointer.
  4754. *
  4755. * Return:
  4756. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4757. *
  4758. * Context:
  4759. * Kernel context.
  4760. */
  4761. int
  4762. qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
  4763. {
  4764. int ret;
  4765. fc_port_t *fcport;
  4766. ret = QLA_FUNCTION_FAILED;
  4767. /* We need to set priority for all logged in ports */
  4768. list_for_each_entry(fcport, &vha->vp_fcports, list)
  4769. ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
  4770. return ret;
  4771. }