cx23885-cards.c 47 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include <linux/firmware.h>
  27. #include <misc/altera.h>
  28. #include "cx23885.h"
  29. #include "tuner-xc2028.h"
  30. #include "netup-eeprom.h"
  31. #include "netup-init.h"
  32. #include "altera-ci.h"
  33. #include "xc4000.h"
  34. #include "xc5000.h"
  35. #include "cx23888-ir.h"
  36. static unsigned int netup_card_rev = 1;
  37. module_param(netup_card_rev, int, 0644);
  38. MODULE_PARM_DESC(netup_card_rev,
  39. "NetUP Dual DVB-T/C CI card revision");
  40. static unsigned int enable_885_ir;
  41. module_param(enable_885_ir, int, 0644);
  42. MODULE_PARM_DESC(enable_885_ir,
  43. "Enable integrated IR controller for supported\n"
  44. "\t\t CX2388[57] boards that are wired for it:\n"
  45. "\t\t\tHVR-1250 (reported safe)\n"
  46. "\t\t\tTeVii S470 (reported unsafe)\n"
  47. "\t\t This can cause an interrupt storm with some cards.\n"
  48. "\t\t Default: 0 [Disabled]");
  49. /* ------------------------------------------------------------------ */
  50. /* board config info */
  51. struct cx23885_board cx23885_boards[] = {
  52. [CX23885_BOARD_UNKNOWN] = {
  53. .name = "UNKNOWN/GENERIC",
  54. /* Ensure safe default for unknown boards */
  55. .clk_freq = 0,
  56. .input = {{
  57. .type = CX23885_VMUX_COMPOSITE1,
  58. .vmux = 0,
  59. }, {
  60. .type = CX23885_VMUX_COMPOSITE2,
  61. .vmux = 1,
  62. }, {
  63. .type = CX23885_VMUX_COMPOSITE3,
  64. .vmux = 2,
  65. }, {
  66. .type = CX23885_VMUX_COMPOSITE4,
  67. .vmux = 3,
  68. } },
  69. },
  70. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  71. .name = "Hauppauge WinTV-HVR1800lp",
  72. .portc = CX23885_MPEG_DVB,
  73. .input = {{
  74. .type = CX23885_VMUX_TELEVISION,
  75. .vmux = 0,
  76. .gpio0 = 0xff00,
  77. }, {
  78. .type = CX23885_VMUX_DEBUG,
  79. .vmux = 0,
  80. .gpio0 = 0xff01,
  81. }, {
  82. .type = CX23885_VMUX_COMPOSITE1,
  83. .vmux = 1,
  84. .gpio0 = 0xff02,
  85. }, {
  86. .type = CX23885_VMUX_SVIDEO,
  87. .vmux = 2,
  88. .gpio0 = 0xff02,
  89. } },
  90. },
  91. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  92. .name = "Hauppauge WinTV-HVR1800",
  93. .porta = CX23885_ANALOG_VIDEO,
  94. .portb = CX23885_MPEG_ENCODER,
  95. .portc = CX23885_MPEG_DVB,
  96. .tuner_type = TUNER_PHILIPS_TDA8290,
  97. .tuner_addr = 0x42, /* 0x84 >> 1 */
  98. .tuner_bus = 1,
  99. .input = {{
  100. .type = CX23885_VMUX_TELEVISION,
  101. .vmux = CX25840_VIN7_CH3 |
  102. CX25840_VIN5_CH2 |
  103. CX25840_VIN2_CH1,
  104. .amux = CX25840_AUDIO8,
  105. .gpio0 = 0,
  106. }, {
  107. .type = CX23885_VMUX_COMPOSITE1,
  108. .vmux = CX25840_VIN7_CH3 |
  109. CX25840_VIN4_CH2 |
  110. CX25840_VIN6_CH1,
  111. .amux = CX25840_AUDIO7,
  112. .gpio0 = 0,
  113. }, {
  114. .type = CX23885_VMUX_SVIDEO,
  115. .vmux = CX25840_VIN7_CH3 |
  116. CX25840_VIN4_CH2 |
  117. CX25840_VIN8_CH1 |
  118. CX25840_SVIDEO_ON,
  119. .amux = CX25840_AUDIO7,
  120. .gpio0 = 0,
  121. } },
  122. },
  123. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  124. .name = "Hauppauge WinTV-HVR1250",
  125. .porta = CX23885_ANALOG_VIDEO,
  126. .portc = CX23885_MPEG_DVB,
  127. #ifdef MT2131_NO_ANALOG_SUPPORT_YET
  128. .tuner_type = TUNER_PHILIPS_TDA8290,
  129. .tuner_addr = 0x42, /* 0x84 >> 1 */
  130. .tuner_bus = 1,
  131. #endif
  132. .force_bff = 1,
  133. .input = {{
  134. #ifdef MT2131_NO_ANALOG_SUPPORT_YET
  135. .type = CX23885_VMUX_TELEVISION,
  136. .vmux = CX25840_VIN7_CH3 |
  137. CX25840_VIN5_CH2 |
  138. CX25840_VIN2_CH1,
  139. .amux = CX25840_AUDIO8,
  140. .gpio0 = 0xff00,
  141. }, {
  142. #endif
  143. .type = CX23885_VMUX_COMPOSITE1,
  144. .vmux = CX25840_VIN7_CH3 |
  145. CX25840_VIN4_CH2 |
  146. CX25840_VIN6_CH1,
  147. .amux = CX25840_AUDIO7,
  148. .gpio0 = 0xff02,
  149. }, {
  150. .type = CX23885_VMUX_SVIDEO,
  151. .vmux = CX25840_VIN7_CH3 |
  152. CX25840_VIN4_CH2 |
  153. CX25840_VIN8_CH1 |
  154. CX25840_SVIDEO_ON,
  155. .amux = CX25840_AUDIO7,
  156. .gpio0 = 0xff02,
  157. } },
  158. },
  159. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  160. .name = "DViCO FusionHDTV5 Express",
  161. .portb = CX23885_MPEG_DVB,
  162. },
  163. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  164. .name = "Hauppauge WinTV-HVR1500Q",
  165. .portc = CX23885_MPEG_DVB,
  166. },
  167. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  168. .name = "Hauppauge WinTV-HVR1500",
  169. .porta = CX23885_ANALOG_VIDEO,
  170. .portc = CX23885_MPEG_DVB,
  171. .tuner_type = TUNER_XC2028,
  172. .tuner_addr = 0x61, /* 0xc2 >> 1 */
  173. .input = {{
  174. .type = CX23885_VMUX_TELEVISION,
  175. .vmux = CX25840_VIN7_CH3 |
  176. CX25840_VIN5_CH2 |
  177. CX25840_VIN2_CH1,
  178. .gpio0 = 0,
  179. }, {
  180. .type = CX23885_VMUX_COMPOSITE1,
  181. .vmux = CX25840_VIN7_CH3 |
  182. CX25840_VIN4_CH2 |
  183. CX25840_VIN6_CH1,
  184. .gpio0 = 0,
  185. }, {
  186. .type = CX23885_VMUX_SVIDEO,
  187. .vmux = CX25840_VIN7_CH3 |
  188. CX25840_VIN4_CH2 |
  189. CX25840_VIN8_CH1 |
  190. CX25840_SVIDEO_ON,
  191. .gpio0 = 0,
  192. } },
  193. },
  194. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  195. .name = "Hauppauge WinTV-HVR1200",
  196. .portc = CX23885_MPEG_DVB,
  197. },
  198. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  199. .name = "Hauppauge WinTV-HVR1700",
  200. .portc = CX23885_MPEG_DVB,
  201. },
  202. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  203. .name = "Hauppauge WinTV-HVR1400",
  204. .portc = CX23885_MPEG_DVB,
  205. },
  206. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  207. .name = "DViCO FusionHDTV7 Dual Express",
  208. .portb = CX23885_MPEG_DVB,
  209. .portc = CX23885_MPEG_DVB,
  210. },
  211. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  212. .name = "DViCO FusionHDTV DVB-T Dual Express",
  213. .portb = CX23885_MPEG_DVB,
  214. .portc = CX23885_MPEG_DVB,
  215. },
  216. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  217. .name = "Leadtek Winfast PxDVR3200 H",
  218. .portc = CX23885_MPEG_DVB,
  219. },
  220. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
  221. .name = "Leadtek Winfast PxDVR3200 H XC4000",
  222. .porta = CX23885_ANALOG_VIDEO,
  223. .portc = CX23885_MPEG_DVB,
  224. .tuner_type = TUNER_XC4000,
  225. .tuner_addr = 0x61,
  226. .radio_type = UNSET,
  227. .radio_addr = ADDR_UNSET,
  228. .input = {{
  229. .type = CX23885_VMUX_TELEVISION,
  230. .vmux = CX25840_VIN2_CH1 |
  231. CX25840_VIN5_CH2 |
  232. CX25840_NONE0_CH3,
  233. }, {
  234. .type = CX23885_VMUX_COMPOSITE1,
  235. .vmux = CX25840_COMPOSITE1,
  236. }, {
  237. .type = CX23885_VMUX_SVIDEO,
  238. .vmux = CX25840_SVIDEO_LUMA3 |
  239. CX25840_SVIDEO_CHROMA4,
  240. }, {
  241. .type = CX23885_VMUX_COMPONENT,
  242. .vmux = CX25840_VIN7_CH1 |
  243. CX25840_VIN6_CH2 |
  244. CX25840_VIN8_CH3 |
  245. CX25840_COMPONENT_ON,
  246. } },
  247. },
  248. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  249. .name = "Compro VideoMate E650F",
  250. .portc = CX23885_MPEG_DVB,
  251. },
  252. [CX23885_BOARD_TBS_6920] = {
  253. .name = "TurboSight TBS 6920",
  254. .portb = CX23885_MPEG_DVB,
  255. },
  256. [CX23885_BOARD_TEVII_S470] = {
  257. .name = "TeVii S470",
  258. .portb = CX23885_MPEG_DVB,
  259. },
  260. [CX23885_BOARD_DVBWORLD_2005] = {
  261. .name = "DVBWorld DVB-S2 2005",
  262. .portb = CX23885_MPEG_DVB,
  263. },
  264. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  265. .ci_type = 1,
  266. .name = "NetUP Dual DVB-S2 CI",
  267. .portb = CX23885_MPEG_DVB,
  268. .portc = CX23885_MPEG_DVB,
  269. },
  270. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  271. .name = "Hauppauge WinTV-HVR1270",
  272. .portc = CX23885_MPEG_DVB,
  273. },
  274. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  275. .name = "Hauppauge WinTV-HVR1275",
  276. .portc = CX23885_MPEG_DVB,
  277. },
  278. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  279. .name = "Hauppauge WinTV-HVR1255",
  280. .porta = CX23885_ANALOG_VIDEO,
  281. .portc = CX23885_MPEG_DVB,
  282. .tuner_type = TUNER_ABSENT,
  283. .tuner_addr = 0x42, /* 0x84 >> 1 */
  284. .force_bff = 1,
  285. .input = {{
  286. .type = CX23885_VMUX_TELEVISION,
  287. .vmux = CX25840_VIN7_CH3 |
  288. CX25840_VIN5_CH2 |
  289. CX25840_VIN2_CH1 |
  290. CX25840_DIF_ON,
  291. .amux = CX25840_AUDIO8,
  292. }, {
  293. .type = CX23885_VMUX_COMPOSITE1,
  294. .vmux = CX25840_VIN7_CH3 |
  295. CX25840_VIN4_CH2 |
  296. CX25840_VIN6_CH1,
  297. .amux = CX25840_AUDIO7,
  298. }, {
  299. .type = CX23885_VMUX_SVIDEO,
  300. .vmux = CX25840_VIN7_CH3 |
  301. CX25840_VIN4_CH2 |
  302. CX25840_VIN8_CH1 |
  303. CX25840_SVIDEO_ON,
  304. .amux = CX25840_AUDIO7,
  305. } },
  306. },
  307. [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
  308. .name = "Hauppauge WinTV-HVR1255",
  309. .porta = CX23885_ANALOG_VIDEO,
  310. .portc = CX23885_MPEG_DVB,
  311. .tuner_type = TUNER_ABSENT,
  312. .tuner_addr = 0x42, /* 0x84 >> 1 */
  313. .force_bff = 1,
  314. .input = {{
  315. .type = CX23885_VMUX_TELEVISION,
  316. .vmux = CX25840_VIN7_CH3 |
  317. CX25840_VIN5_CH2 |
  318. CX25840_VIN2_CH1 |
  319. CX25840_DIF_ON,
  320. .amux = CX25840_AUDIO8,
  321. }, {
  322. .type = CX23885_VMUX_SVIDEO,
  323. .vmux = CX25840_VIN7_CH3 |
  324. CX25840_VIN4_CH2 |
  325. CX25840_VIN8_CH1 |
  326. CX25840_SVIDEO_ON,
  327. .amux = CX25840_AUDIO7,
  328. } },
  329. },
  330. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  331. .name = "Hauppauge WinTV-HVR1210",
  332. .portc = CX23885_MPEG_DVB,
  333. },
  334. [CX23885_BOARD_MYGICA_X8506] = {
  335. .name = "Mygica X8506 DMB-TH",
  336. .tuner_type = TUNER_XC5000,
  337. .tuner_addr = 0x61,
  338. .tuner_bus = 1,
  339. .porta = CX23885_ANALOG_VIDEO,
  340. .portb = CX23885_MPEG_DVB,
  341. .input = {
  342. {
  343. .type = CX23885_VMUX_TELEVISION,
  344. .vmux = CX25840_COMPOSITE2,
  345. },
  346. {
  347. .type = CX23885_VMUX_COMPOSITE1,
  348. .vmux = CX25840_COMPOSITE8,
  349. },
  350. {
  351. .type = CX23885_VMUX_SVIDEO,
  352. .vmux = CX25840_SVIDEO_LUMA3 |
  353. CX25840_SVIDEO_CHROMA4,
  354. },
  355. {
  356. .type = CX23885_VMUX_COMPONENT,
  357. .vmux = CX25840_COMPONENT_ON |
  358. CX25840_VIN1_CH1 |
  359. CX25840_VIN6_CH2 |
  360. CX25840_VIN7_CH3,
  361. },
  362. },
  363. },
  364. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  365. .name = "Magic-Pro ProHDTV Extreme 2",
  366. .tuner_type = TUNER_XC5000,
  367. .tuner_addr = 0x61,
  368. .tuner_bus = 1,
  369. .porta = CX23885_ANALOG_VIDEO,
  370. .portb = CX23885_MPEG_DVB,
  371. .input = {
  372. {
  373. .type = CX23885_VMUX_TELEVISION,
  374. .vmux = CX25840_COMPOSITE2,
  375. },
  376. {
  377. .type = CX23885_VMUX_COMPOSITE1,
  378. .vmux = CX25840_COMPOSITE8,
  379. },
  380. {
  381. .type = CX23885_VMUX_SVIDEO,
  382. .vmux = CX25840_SVIDEO_LUMA3 |
  383. CX25840_SVIDEO_CHROMA4,
  384. },
  385. {
  386. .type = CX23885_VMUX_COMPONENT,
  387. .vmux = CX25840_COMPONENT_ON |
  388. CX25840_VIN1_CH1 |
  389. CX25840_VIN6_CH2 |
  390. CX25840_VIN7_CH3,
  391. },
  392. },
  393. },
  394. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  395. .name = "Hauppauge WinTV-HVR1850",
  396. .porta = CX23885_ANALOG_VIDEO,
  397. .portb = CX23885_MPEG_ENCODER,
  398. .portc = CX23885_MPEG_DVB,
  399. .tuner_type = TUNER_ABSENT,
  400. .tuner_addr = 0x42, /* 0x84 >> 1 */
  401. .force_bff = 1,
  402. .input = {{
  403. .type = CX23885_VMUX_TELEVISION,
  404. .vmux = CX25840_VIN7_CH3 |
  405. CX25840_VIN5_CH2 |
  406. CX25840_VIN2_CH1 |
  407. CX25840_DIF_ON,
  408. .amux = CX25840_AUDIO8,
  409. }, {
  410. .type = CX23885_VMUX_COMPOSITE1,
  411. .vmux = CX25840_VIN7_CH3 |
  412. CX25840_VIN4_CH2 |
  413. CX25840_VIN6_CH1,
  414. .amux = CX25840_AUDIO7,
  415. }, {
  416. .type = CX23885_VMUX_SVIDEO,
  417. .vmux = CX25840_VIN7_CH3 |
  418. CX25840_VIN4_CH2 |
  419. CX25840_VIN8_CH1 |
  420. CX25840_SVIDEO_ON,
  421. .amux = CX25840_AUDIO7,
  422. } },
  423. },
  424. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  425. .name = "Compro VideoMate E800",
  426. .portc = CX23885_MPEG_DVB,
  427. },
  428. [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
  429. .name = "Hauppauge WinTV-HVR1290",
  430. .portc = CX23885_MPEG_DVB,
  431. },
  432. [CX23885_BOARD_MYGICA_X8558PRO] = {
  433. .name = "Mygica X8558 PRO DMB-TH",
  434. .portb = CX23885_MPEG_DVB,
  435. .portc = CX23885_MPEG_DVB,
  436. },
  437. [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
  438. .name = "LEADTEK WinFast PxTV1200",
  439. .porta = CX23885_ANALOG_VIDEO,
  440. .tuner_type = TUNER_XC2028,
  441. .tuner_addr = 0x61,
  442. .tuner_bus = 1,
  443. .input = {{
  444. .type = CX23885_VMUX_TELEVISION,
  445. .vmux = CX25840_VIN2_CH1 |
  446. CX25840_VIN5_CH2 |
  447. CX25840_NONE0_CH3,
  448. }, {
  449. .type = CX23885_VMUX_COMPOSITE1,
  450. .vmux = CX25840_COMPOSITE1,
  451. }, {
  452. .type = CX23885_VMUX_SVIDEO,
  453. .vmux = CX25840_SVIDEO_LUMA3 |
  454. CX25840_SVIDEO_CHROMA4,
  455. }, {
  456. .type = CX23885_VMUX_COMPONENT,
  457. .vmux = CX25840_VIN7_CH1 |
  458. CX25840_VIN6_CH2 |
  459. CX25840_VIN8_CH3 |
  460. CX25840_COMPONENT_ON,
  461. } },
  462. },
  463. [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
  464. .name = "GoTView X5 3D Hybrid",
  465. .tuner_type = TUNER_XC5000,
  466. .tuner_addr = 0x64,
  467. .tuner_bus = 1,
  468. .porta = CX23885_ANALOG_VIDEO,
  469. .portb = CX23885_MPEG_DVB,
  470. .input = {{
  471. .type = CX23885_VMUX_TELEVISION,
  472. .vmux = CX25840_VIN2_CH1 |
  473. CX25840_VIN5_CH2,
  474. .gpio0 = 0x02,
  475. }, {
  476. .type = CX23885_VMUX_COMPOSITE1,
  477. .vmux = CX23885_VMUX_COMPOSITE1,
  478. }, {
  479. .type = CX23885_VMUX_SVIDEO,
  480. .vmux = CX25840_SVIDEO_LUMA3 |
  481. CX25840_SVIDEO_CHROMA4,
  482. } },
  483. },
  484. [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
  485. .ci_type = 2,
  486. .name = "NetUP Dual DVB-T/C-CI RF",
  487. .porta = CX23885_ANALOG_VIDEO,
  488. .portb = CX23885_MPEG_DVB,
  489. .portc = CX23885_MPEG_DVB,
  490. .num_fds_portb = 2,
  491. .num_fds_portc = 2,
  492. .tuner_type = TUNER_XC5000,
  493. .tuner_addr = 0x64,
  494. .input = { {
  495. .type = CX23885_VMUX_TELEVISION,
  496. .vmux = CX25840_COMPOSITE1,
  497. } },
  498. },
  499. [CX23885_BOARD_MPX885] = {
  500. .name = "MPX-885",
  501. .porta = CX23885_ANALOG_VIDEO,
  502. .input = {{
  503. .type = CX23885_VMUX_COMPOSITE1,
  504. .vmux = CX25840_COMPOSITE1,
  505. .amux = CX25840_AUDIO6,
  506. .gpio0 = 0,
  507. }, {
  508. .type = CX23885_VMUX_COMPOSITE2,
  509. .vmux = CX25840_COMPOSITE2,
  510. .amux = CX25840_AUDIO6,
  511. .gpio0 = 0,
  512. }, {
  513. .type = CX23885_VMUX_COMPOSITE3,
  514. .vmux = CX25840_COMPOSITE3,
  515. .amux = CX25840_AUDIO7,
  516. .gpio0 = 0,
  517. }, {
  518. .type = CX23885_VMUX_COMPOSITE4,
  519. .vmux = CX25840_COMPOSITE4,
  520. .amux = CX25840_AUDIO7,
  521. .gpio0 = 0,
  522. } },
  523. },
  524. [CX23885_BOARD_MYGICA_X8507] = {
  525. .name = "Mygica X8507",
  526. .tuner_type = TUNER_XC5000,
  527. .tuner_addr = 0x61,
  528. .tuner_bus = 1,
  529. .porta = CX23885_ANALOG_VIDEO,
  530. .input = {
  531. {
  532. .type = CX23885_VMUX_TELEVISION,
  533. .vmux = CX25840_COMPOSITE2,
  534. .amux = CX25840_AUDIO8,
  535. },
  536. {
  537. .type = CX23885_VMUX_COMPOSITE1,
  538. .vmux = CX25840_COMPOSITE8,
  539. },
  540. {
  541. .type = CX23885_VMUX_SVIDEO,
  542. .vmux = CX25840_SVIDEO_LUMA3 |
  543. CX25840_SVIDEO_CHROMA4,
  544. },
  545. {
  546. .type = CX23885_VMUX_COMPONENT,
  547. .vmux = CX25840_COMPONENT_ON |
  548. CX25840_VIN1_CH1 |
  549. CX25840_VIN6_CH2 |
  550. CX25840_VIN7_CH3,
  551. },
  552. },
  553. },
  554. [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
  555. .name = "TerraTec Cinergy T PCIe Dual",
  556. .portb = CX23885_MPEG_DVB,
  557. .portc = CX23885_MPEG_DVB,
  558. },
  559. [CX23885_BOARD_TEVII_S471] = {
  560. .name = "TeVii S471",
  561. .portb = CX23885_MPEG_DVB,
  562. }
  563. };
  564. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  565. /* ------------------------------------------------------------------ */
  566. /* PCI subsystem IDs */
  567. struct cx23885_subid cx23885_subids[] = {
  568. {
  569. .subvendor = 0x0070,
  570. .subdevice = 0x3400,
  571. .card = CX23885_BOARD_UNKNOWN,
  572. }, {
  573. .subvendor = 0x0070,
  574. .subdevice = 0x7600,
  575. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  576. }, {
  577. .subvendor = 0x0070,
  578. .subdevice = 0x7800,
  579. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  580. }, {
  581. .subvendor = 0x0070,
  582. .subdevice = 0x7801,
  583. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  584. }, {
  585. .subvendor = 0x0070,
  586. .subdevice = 0x7809,
  587. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  588. }, {
  589. .subvendor = 0x0070,
  590. .subdevice = 0x7911,
  591. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  592. }, {
  593. .subvendor = 0x18ac,
  594. .subdevice = 0xd500,
  595. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  596. }, {
  597. .subvendor = 0x0070,
  598. .subdevice = 0x7790,
  599. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  600. }, {
  601. .subvendor = 0x0070,
  602. .subdevice = 0x7797,
  603. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  604. }, {
  605. .subvendor = 0x0070,
  606. .subdevice = 0x7710,
  607. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  608. }, {
  609. .subvendor = 0x0070,
  610. .subdevice = 0x7717,
  611. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  612. }, {
  613. .subvendor = 0x0070,
  614. .subdevice = 0x71d1,
  615. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  616. }, {
  617. .subvendor = 0x0070,
  618. .subdevice = 0x71d3,
  619. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  620. }, {
  621. .subvendor = 0x0070,
  622. .subdevice = 0x8101,
  623. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  624. }, {
  625. .subvendor = 0x0070,
  626. .subdevice = 0x8010,
  627. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  628. }, {
  629. .subvendor = 0x18ac,
  630. .subdevice = 0xd618,
  631. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  632. }, {
  633. .subvendor = 0x18ac,
  634. .subdevice = 0xdb78,
  635. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  636. }, {
  637. .subvendor = 0x107d,
  638. .subdevice = 0x6681,
  639. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  640. }, {
  641. .subvendor = 0x107d,
  642. .subdevice = 0x6f39,
  643. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
  644. }, {
  645. .subvendor = 0x185b,
  646. .subdevice = 0xe800,
  647. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  648. }, {
  649. .subvendor = 0x6920,
  650. .subdevice = 0x8888,
  651. .card = CX23885_BOARD_TBS_6920,
  652. }, {
  653. .subvendor = 0xd470,
  654. .subdevice = 0x9022,
  655. .card = CX23885_BOARD_TEVII_S470,
  656. }, {
  657. .subvendor = 0x0001,
  658. .subdevice = 0x2005,
  659. .card = CX23885_BOARD_DVBWORLD_2005,
  660. }, {
  661. .subvendor = 0x1b55,
  662. .subdevice = 0x2a2c,
  663. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  664. }, {
  665. .subvendor = 0x0070,
  666. .subdevice = 0x2211,
  667. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  668. }, {
  669. .subvendor = 0x0070,
  670. .subdevice = 0x2215,
  671. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  672. }, {
  673. .subvendor = 0x0070,
  674. .subdevice = 0x221d,
  675. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  676. }, {
  677. .subvendor = 0x0070,
  678. .subdevice = 0x2251,
  679. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  680. }, {
  681. .subvendor = 0x0070,
  682. .subdevice = 0x2259,
  683. .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
  684. }, {
  685. .subvendor = 0x0070,
  686. .subdevice = 0x2291,
  687. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  688. }, {
  689. .subvendor = 0x0070,
  690. .subdevice = 0x2295,
  691. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  692. }, {
  693. .subvendor = 0x0070,
  694. .subdevice = 0x2299,
  695. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  696. }, {
  697. .subvendor = 0x0070,
  698. .subdevice = 0x229d,
  699. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  700. }, {
  701. .subvendor = 0x0070,
  702. .subdevice = 0x22f0,
  703. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  704. }, {
  705. .subvendor = 0x0070,
  706. .subdevice = 0x22f1,
  707. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  708. }, {
  709. .subvendor = 0x0070,
  710. .subdevice = 0x22f2,
  711. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  712. }, {
  713. .subvendor = 0x0070,
  714. .subdevice = 0x22f3,
  715. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  716. }, {
  717. .subvendor = 0x0070,
  718. .subdevice = 0x22f4,
  719. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  720. }, {
  721. .subvendor = 0x0070,
  722. .subdevice = 0x22f5,
  723. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  724. }, {
  725. .subvendor = 0x14f1,
  726. .subdevice = 0x8651,
  727. .card = CX23885_BOARD_MYGICA_X8506,
  728. }, {
  729. .subvendor = 0x14f1,
  730. .subdevice = 0x8657,
  731. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  732. }, {
  733. .subvendor = 0x0070,
  734. .subdevice = 0x8541,
  735. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  736. }, {
  737. .subvendor = 0x1858,
  738. .subdevice = 0xe800,
  739. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  740. }, {
  741. .subvendor = 0x0070,
  742. .subdevice = 0x8551,
  743. .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
  744. }, {
  745. .subvendor = 0x14f1,
  746. .subdevice = 0x8578,
  747. .card = CX23885_BOARD_MYGICA_X8558PRO,
  748. }, {
  749. .subvendor = 0x107d,
  750. .subdevice = 0x6f22,
  751. .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
  752. }, {
  753. .subvendor = 0x5654,
  754. .subdevice = 0x2390,
  755. .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
  756. }, {
  757. .subvendor = 0x1b55,
  758. .subdevice = 0xe2e4,
  759. .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
  760. }, {
  761. .subvendor = 0x14f1,
  762. .subdevice = 0x8502,
  763. .card = CX23885_BOARD_MYGICA_X8507,
  764. }, {
  765. .subvendor = 0x153b,
  766. .subdevice = 0x117e,
  767. .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
  768. }, {
  769. .subvendor = 0xd471,
  770. .subdevice = 0x9022,
  771. .card = CX23885_BOARD_TEVII_S471,
  772. },
  773. };
  774. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  775. void cx23885_card_list(struct cx23885_dev *dev)
  776. {
  777. int i;
  778. if (0 == dev->pci->subsystem_vendor &&
  779. 0 == dev->pci->subsystem_device) {
  780. printk(KERN_INFO
  781. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  782. "%s: be autodetected. Pass card=<n> insmod option\n"
  783. "%s: to workaround that. Redirect complaints to the\n"
  784. "%s: vendor of the TV card. Best regards,\n"
  785. "%s: -- tux\n",
  786. dev->name, dev->name, dev->name, dev->name, dev->name);
  787. } else {
  788. printk(KERN_INFO
  789. "%s: Your board isn't known (yet) to the driver.\n"
  790. "%s: Try to pick one of the existing card configs via\n"
  791. "%s: card=<n> insmod option. Updating to the latest\n"
  792. "%s: version might help as well.\n",
  793. dev->name, dev->name, dev->name, dev->name);
  794. }
  795. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  796. dev->name);
  797. for (i = 0; i < cx23885_bcount; i++)
  798. printk(KERN_INFO "%s: card=%d -> %s\n",
  799. dev->name, i, cx23885_boards[i].name);
  800. }
  801. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  802. {
  803. struct tveeprom tv;
  804. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  805. eeprom_data);
  806. /* Make sure we support the board model */
  807. switch (tv.model) {
  808. case 22001:
  809. /* WinTV-HVR1270 (PCIe, Retail, half height)
  810. * ATSC/QAM and basic analog, IR Blast */
  811. case 22009:
  812. /* WinTV-HVR1210 (PCIe, Retail, half height)
  813. * DVB-T and basic analog, IR Blast */
  814. case 22011:
  815. /* WinTV-HVR1270 (PCIe, Retail, half height)
  816. * ATSC/QAM and basic analog, IR Recv */
  817. case 22019:
  818. /* WinTV-HVR1210 (PCIe, Retail, half height)
  819. * DVB-T and basic analog, IR Recv */
  820. case 22021:
  821. /* WinTV-HVR1275 (PCIe, Retail, half height)
  822. * ATSC/QAM and basic analog, IR Recv */
  823. case 22029:
  824. /* WinTV-HVR1210 (PCIe, Retail, half height)
  825. * DVB-T and basic analog, IR Recv */
  826. case 22101:
  827. /* WinTV-HVR1270 (PCIe, Retail, full height)
  828. * ATSC/QAM and basic analog, IR Blast */
  829. case 22109:
  830. /* WinTV-HVR1210 (PCIe, Retail, full height)
  831. * DVB-T and basic analog, IR Blast */
  832. case 22111:
  833. /* WinTV-HVR1270 (PCIe, Retail, full height)
  834. * ATSC/QAM and basic analog, IR Recv */
  835. case 22119:
  836. /* WinTV-HVR1210 (PCIe, Retail, full height)
  837. * DVB-T and basic analog, IR Recv */
  838. case 22121:
  839. /* WinTV-HVR1275 (PCIe, Retail, full height)
  840. * ATSC/QAM and basic analog, IR Recv */
  841. case 22129:
  842. /* WinTV-HVR1210 (PCIe, Retail, full height)
  843. * DVB-T and basic analog, IR Recv */
  844. case 71009:
  845. /* WinTV-HVR1200 (PCIe, Retail, full height)
  846. * DVB-T and basic analog */
  847. case 71359:
  848. /* WinTV-HVR1200 (PCIe, OEM, half height)
  849. * DVB-T and basic analog */
  850. case 71439:
  851. /* WinTV-HVR1200 (PCIe, OEM, half height)
  852. * DVB-T and basic analog */
  853. case 71449:
  854. /* WinTV-HVR1200 (PCIe, OEM, full height)
  855. * DVB-T and basic analog */
  856. case 71939:
  857. /* WinTV-HVR1200 (PCIe, OEM, half height)
  858. * DVB-T and basic analog */
  859. case 71949:
  860. /* WinTV-HVR1200 (PCIe, OEM, full height)
  861. * DVB-T and basic analog */
  862. case 71959:
  863. /* WinTV-HVR1200 (PCIe, OEM, full height)
  864. * DVB-T and basic analog */
  865. case 71979:
  866. /* WinTV-HVR1200 (PCIe, OEM, half height)
  867. * DVB-T and basic analog */
  868. case 71999:
  869. /* WinTV-HVR1200 (PCIe, OEM, full height)
  870. * DVB-T and basic analog */
  871. case 76601:
  872. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  873. channel ATSC and MPEG2 HW Encoder */
  874. case 77001:
  875. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  876. and Basic analog */
  877. case 77011:
  878. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  879. and Basic analog */
  880. case 77041:
  881. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  882. and Basic analog */
  883. case 77051:
  884. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  885. and Basic analog */
  886. case 78011:
  887. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  888. Dual channel ATSC and MPEG2 HW Encoder */
  889. case 78501:
  890. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  891. Dual channel ATSC and MPEG2 HW Encoder */
  892. case 78521:
  893. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  894. Dual channel ATSC and MPEG2 HW Encoder */
  895. case 78531:
  896. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  897. Dual channel ATSC and MPEG2 HW Encoder */
  898. case 78631:
  899. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  900. Dual channel ATSC and MPEG2 HW Encoder */
  901. case 79001:
  902. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  903. ATSC and Basic analog */
  904. case 79101:
  905. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  906. ATSC and Basic analog */
  907. case 79501:
  908. /* WinTV-HVR1250 (PCIe, No IR, half height,
  909. ATSC [at least] and Basic analog) */
  910. case 79561:
  911. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  912. ATSC and Basic analog */
  913. case 79571:
  914. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  915. ATSC and Basic analog */
  916. case 79671:
  917. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  918. ATSC and Basic analog */
  919. case 80019:
  920. /* WinTV-HVR1400 (Express Card, Retail, IR,
  921. * DVB-T and Basic analog */
  922. case 81509:
  923. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  924. * DVB-T and MPEG2 HW Encoder */
  925. case 81519:
  926. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  927. * DVB-T and MPEG2 HW Encoder */
  928. break;
  929. case 85021:
  930. /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
  931. Dual channel ATSC and MPEG2 HW Encoder */
  932. break;
  933. case 85721:
  934. /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
  935. Dual channel ATSC and Basic analog */
  936. break;
  937. default:
  938. printk(KERN_WARNING "%s: warning: "
  939. "unknown hauppauge model #%d\n",
  940. dev->name, tv.model);
  941. break;
  942. }
  943. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  944. dev->name, tv.model);
  945. }
  946. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  947. {
  948. struct cx23885_tsport *port = priv;
  949. struct cx23885_dev *dev = port->dev;
  950. u32 bitmask = 0;
  951. if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
  952. return 0;
  953. if (command != 0) {
  954. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  955. __func__, command);
  956. return -EINVAL;
  957. }
  958. switch (dev->board) {
  959. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  960. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  961. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  962. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  963. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  964. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  965. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  966. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  967. /* Tuner Reset Command */
  968. bitmask = 0x04;
  969. break;
  970. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  971. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  972. /* Two identical tuners on two different i2c buses,
  973. * we need to reset the correct gpio. */
  974. if (port->nr == 1)
  975. bitmask = 0x01;
  976. else if (port->nr == 2)
  977. bitmask = 0x04;
  978. break;
  979. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  980. /* Tuner Reset Command */
  981. bitmask = 0x02;
  982. break;
  983. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  984. altera_ci_tuner_reset(dev, port->nr);
  985. break;
  986. }
  987. if (bitmask) {
  988. /* Drive the tuner into reset and back out */
  989. cx_clear(GP0_IO, bitmask);
  990. mdelay(200);
  991. cx_set(GP0_IO, bitmask);
  992. }
  993. return 0;
  994. }
  995. void cx23885_gpio_setup(struct cx23885_dev *dev)
  996. {
  997. switch (dev->board) {
  998. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  999. /* GPIO-0 cx24227 demodulator reset */
  1000. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1001. break;
  1002. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1003. /* GPIO-0 cx24227 demodulator */
  1004. /* GPIO-2 xc3028 tuner */
  1005. /* Put the parts into reset */
  1006. cx_set(GP0_IO, 0x00050000);
  1007. cx_clear(GP0_IO, 0x00000005);
  1008. msleep(5);
  1009. /* Bring the parts out of reset */
  1010. cx_set(GP0_IO, 0x00050005);
  1011. break;
  1012. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1013. /* GPIO-0 cx24227 demodulator reset */
  1014. /* GPIO-2 xc5000 tuner reset */
  1015. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  1016. break;
  1017. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1018. /* GPIO-0 656_CLK */
  1019. /* GPIO-1 656_D0 */
  1020. /* GPIO-2 8295A Reset */
  1021. /* GPIO-3-10 cx23417 data0-7 */
  1022. /* GPIO-11-14 cx23417 addr0-3 */
  1023. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1024. /* GPIO-19 IR_RX */
  1025. /* CX23417 GPIO's */
  1026. /* EIO15 Zilog Reset */
  1027. /* EIO14 S5H1409/CX24227 Reset */
  1028. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  1029. /* Put the demod into reset and protect the eeprom */
  1030. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  1031. mdelay(100);
  1032. /* Bring the demod and blaster out of reset */
  1033. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  1034. mdelay(100);
  1035. /* Force the TDA8295A into reset and back */
  1036. cx23885_gpio_enable(dev, GPIO_2, 1);
  1037. cx23885_gpio_set(dev, GPIO_2);
  1038. mdelay(20);
  1039. cx23885_gpio_clear(dev, GPIO_2);
  1040. mdelay(20);
  1041. cx23885_gpio_set(dev, GPIO_2);
  1042. mdelay(20);
  1043. break;
  1044. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1045. /* GPIO-0 tda10048 demodulator reset */
  1046. /* GPIO-2 tda18271 tuner reset */
  1047. /* Put the parts into reset and back */
  1048. cx_set(GP0_IO, 0x00050000);
  1049. mdelay(20);
  1050. cx_clear(GP0_IO, 0x00000005);
  1051. mdelay(20);
  1052. cx_set(GP0_IO, 0x00050005);
  1053. break;
  1054. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1055. /* GPIO-0 TDA10048 demodulator reset */
  1056. /* GPIO-2 TDA8295A Reset */
  1057. /* GPIO-3-10 cx23417 data0-7 */
  1058. /* GPIO-11-14 cx23417 addr0-3 */
  1059. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1060. /* The following GPIO's are on the interna AVCore (cx25840) */
  1061. /* GPIO-19 IR_RX */
  1062. /* GPIO-20 IR_TX 416/DVBT Select */
  1063. /* GPIO-21 IIS DAT */
  1064. /* GPIO-22 IIS WCLK */
  1065. /* GPIO-23 IIS BCLK */
  1066. /* Put the parts into reset and back */
  1067. cx_set(GP0_IO, 0x00050000);
  1068. mdelay(20);
  1069. cx_clear(GP0_IO, 0x00000005);
  1070. mdelay(20);
  1071. cx_set(GP0_IO, 0x00050005);
  1072. break;
  1073. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1074. /* GPIO-0 Dibcom7000p demodulator reset */
  1075. /* GPIO-2 xc3028L tuner reset */
  1076. /* GPIO-13 LED */
  1077. /* Put the parts into reset and back */
  1078. cx_set(GP0_IO, 0x00050000);
  1079. mdelay(20);
  1080. cx_clear(GP0_IO, 0x00000005);
  1081. mdelay(20);
  1082. cx_set(GP0_IO, 0x00050005);
  1083. break;
  1084. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1085. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  1086. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  1087. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  1088. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  1089. /* Put the parts into reset and back */
  1090. cx_set(GP0_IO, 0x000f0000);
  1091. mdelay(20);
  1092. cx_clear(GP0_IO, 0x0000000f);
  1093. mdelay(20);
  1094. cx_set(GP0_IO, 0x000f000f);
  1095. break;
  1096. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1097. /* GPIO-0 portb xc3028 reset */
  1098. /* GPIO-1 portb zl10353 reset */
  1099. /* GPIO-2 portc xc3028 reset */
  1100. /* GPIO-3 portc zl10353 reset */
  1101. /* Put the parts into reset and back */
  1102. cx_set(GP0_IO, 0x000f0000);
  1103. mdelay(20);
  1104. cx_clear(GP0_IO, 0x0000000f);
  1105. mdelay(20);
  1106. cx_set(GP0_IO, 0x000f000f);
  1107. break;
  1108. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1109. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1110. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1111. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1112. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1113. /* GPIO-2 xc3028 tuner reset */
  1114. /* The following GPIO's are on the internal AVCore (cx25840) */
  1115. /* GPIO-? zl10353 demod reset */
  1116. /* Put the parts into reset and back */
  1117. cx_set(GP0_IO, 0x00040000);
  1118. mdelay(20);
  1119. cx_clear(GP0_IO, 0x00000004);
  1120. mdelay(20);
  1121. cx_set(GP0_IO, 0x00040004);
  1122. break;
  1123. case CX23885_BOARD_TBS_6920:
  1124. cx_write(MC417_CTL, 0x00000036);
  1125. cx_write(MC417_OEN, 0x00001000);
  1126. cx_set(MC417_RWD, 0x00000002);
  1127. mdelay(200);
  1128. cx_clear(MC417_RWD, 0x00000800);
  1129. mdelay(200);
  1130. cx_set(MC417_RWD, 0x00000800);
  1131. mdelay(200);
  1132. break;
  1133. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1134. /* GPIO-0 INTA from CiMax1
  1135. GPIO-1 INTB from CiMax2
  1136. GPIO-2 reset chips
  1137. GPIO-3 to GPIO-10 data/addr for CA
  1138. GPIO-11 ~CS0 to CiMax1
  1139. GPIO-12 ~CS1 to CiMax2
  1140. GPIO-13 ADL0 load LSB addr
  1141. GPIO-14 ADL1 load MSB addr
  1142. GPIO-15 ~RDY from CiMax
  1143. GPIO-17 ~RD to CiMax
  1144. GPIO-18 ~WR to CiMax
  1145. */
  1146. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  1147. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  1148. cx_clear(GP0_IO, 0x00030004);
  1149. mdelay(100);/* reset delay */
  1150. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  1151. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  1152. /* GPIO-15 IN as ~ACK, rest as OUT */
  1153. cx_write(MC417_OEN, 0x00001000);
  1154. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  1155. cx_write(MC417_RWD, 0x0000c300);
  1156. /* enable irq */
  1157. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1158. break;
  1159. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1160. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1161. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1162. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1163. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1164. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  1165. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  1166. /* GPIO-9 Demod reset */
  1167. /* Put the parts into reset and back */
  1168. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  1169. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  1170. cx23885_gpio_clear(dev, GPIO_9);
  1171. mdelay(20);
  1172. cx23885_gpio_set(dev, GPIO_9);
  1173. break;
  1174. case CX23885_BOARD_MYGICA_X8506:
  1175. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1176. case CX23885_BOARD_MYGICA_X8507:
  1177. /* GPIO-0 (0)Analog / (1)Digital TV */
  1178. /* GPIO-1 reset XC5000 */
  1179. /* GPIO-2 reset LGS8GL5 / LGS8G75 */
  1180. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  1181. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  1182. mdelay(100);
  1183. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  1184. mdelay(100);
  1185. break;
  1186. case CX23885_BOARD_MYGICA_X8558PRO:
  1187. /* GPIO-0 reset first ATBM8830 */
  1188. /* GPIO-1 reset second ATBM8830 */
  1189. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  1190. cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
  1191. mdelay(100);
  1192. cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
  1193. mdelay(100);
  1194. break;
  1195. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1196. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1197. /* GPIO-0 656_CLK */
  1198. /* GPIO-1 656_D0 */
  1199. /* GPIO-2 Wake# */
  1200. /* GPIO-3-10 cx23417 data0-7 */
  1201. /* GPIO-11-14 cx23417 addr0-3 */
  1202. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1203. /* GPIO-19 IR_RX */
  1204. /* GPIO-20 C_IR_TX */
  1205. /* GPIO-21 I2S DAT */
  1206. /* GPIO-22 I2S WCLK */
  1207. /* GPIO-23 I2S BCLK */
  1208. /* ALT GPIO: EXP GPIO LATCH */
  1209. /* CX23417 GPIO's */
  1210. /* GPIO-14 S5H1411/CX24228 Reset */
  1211. /* GPIO-13 EEPROM write protect */
  1212. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  1213. /* Put the demod into reset and protect the eeprom */
  1214. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  1215. mdelay(100);
  1216. /* Bring the demod out of reset */
  1217. mc417_gpio_set(dev, GPIO_14);
  1218. mdelay(100);
  1219. /* CX24228 GPIO */
  1220. /* Connected to IF / Mux */
  1221. break;
  1222. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1223. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1224. break;
  1225. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1226. /* GPIO-0 ~INT in
  1227. GPIO-1 TMS out
  1228. GPIO-2 ~reset chips out
  1229. GPIO-3 to GPIO-10 data/addr for CA in/out
  1230. GPIO-11 ~CS out
  1231. GPIO-12 ADDR out
  1232. GPIO-13 ~WR out
  1233. GPIO-14 ~RD out
  1234. GPIO-15 ~RDY in
  1235. GPIO-16 TCK out
  1236. GPIO-17 TDO in
  1237. GPIO-18 TDI out
  1238. */
  1239. cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
  1240. /* GPIO-0 as INT, reset & TMS low */
  1241. cx_clear(GP0_IO, 0x00010006);
  1242. mdelay(100);/* reset delay */
  1243. cx_set(GP0_IO, 0x00000004); /* reset high */
  1244. cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
  1245. /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
  1246. cx_write(MC417_OEN, 0x00005000);
  1247. /* ~RD, ~WR high; ADDR low; ~CS high */
  1248. cx_write(MC417_RWD, 0x00000d00);
  1249. /* enable irq */
  1250. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1251. break;
  1252. }
  1253. }
  1254. int cx23885_ir_init(struct cx23885_dev *dev)
  1255. {
  1256. static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
  1257. {
  1258. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1259. .pin = CX23885_PIN_IR_RX_GPIO19,
  1260. .function = CX23885_PAD_IR_RX,
  1261. .value = 0,
  1262. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1263. }, {
  1264. .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
  1265. .pin = CX23885_PIN_IR_TX_GPIO20,
  1266. .function = CX23885_PAD_IR_TX,
  1267. .value = 0,
  1268. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1269. }
  1270. };
  1271. const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
  1272. static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
  1273. {
  1274. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1275. .pin = CX23885_PIN_IR_RX_GPIO19,
  1276. .function = CX23885_PAD_IR_RX,
  1277. .value = 0,
  1278. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1279. }
  1280. };
  1281. const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
  1282. struct v4l2_subdev_ir_parameters params;
  1283. int ret = 0;
  1284. switch (dev->board) {
  1285. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1286. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1287. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1288. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1289. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1290. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1291. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1292. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1293. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1294. /* FIXME: Implement me */
  1295. break;
  1296. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1297. ret = cx23888_ir_probe(dev);
  1298. if (ret)
  1299. break;
  1300. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1301. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1302. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1303. break;
  1304. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1305. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1306. ret = cx23888_ir_probe(dev);
  1307. if (ret)
  1308. break;
  1309. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1310. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1311. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1312. /*
  1313. * For these boards we need to invert the Tx output via the
  1314. * IR controller to have the LED off while idle
  1315. */
  1316. v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
  1317. params.enable = false;
  1318. params.shutdown = false;
  1319. params.invert_level = true;
  1320. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1321. params.shutdown = true;
  1322. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1323. break;
  1324. case CX23885_BOARD_TEVII_S470:
  1325. if (!enable_885_ir)
  1326. break;
  1327. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1328. if (dev->sd_ir == NULL) {
  1329. ret = -ENODEV;
  1330. break;
  1331. }
  1332. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1333. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1334. break;
  1335. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1336. if (!enable_885_ir)
  1337. break;
  1338. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1339. if (dev->sd_ir == NULL) {
  1340. ret = -ENODEV;
  1341. break;
  1342. }
  1343. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1344. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1345. break;
  1346. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1347. request_module("ir-kbd-i2c");
  1348. break;
  1349. }
  1350. return ret;
  1351. }
  1352. void cx23885_ir_fini(struct cx23885_dev *dev)
  1353. {
  1354. switch (dev->board) {
  1355. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1356. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1357. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1358. cx23885_irq_remove(dev, PCI_MSK_IR);
  1359. cx23888_ir_remove(dev);
  1360. dev->sd_ir = NULL;
  1361. break;
  1362. case CX23885_BOARD_TEVII_S470:
  1363. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1364. cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
  1365. /* sd_ir is a duplicate pointer to the AV Core, just clear it */
  1366. dev->sd_ir = NULL;
  1367. break;
  1368. }
  1369. }
  1370. int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
  1371. {
  1372. int data;
  1373. int tdo = 0;
  1374. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  1375. /*TMS*/
  1376. data = ((cx_read(GP0_IO)) & (~0x00000002));
  1377. data |= (tms ? 0x00020002 : 0x00020000);
  1378. cx_write(GP0_IO, data);
  1379. /*TDI*/
  1380. data = ((cx_read(MC417_RWD)) & (~0x0000a000));
  1381. data |= (tdi ? 0x00008000 : 0);
  1382. cx_write(MC417_RWD, data);
  1383. if (read_tdo)
  1384. tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
  1385. cx_write(MC417_RWD, data | 0x00002000);
  1386. udelay(1);
  1387. /*TCK*/
  1388. cx_write(MC417_RWD, data);
  1389. return tdo;
  1390. }
  1391. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  1392. {
  1393. switch (dev->board) {
  1394. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1395. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1396. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1397. if (dev->sd_ir)
  1398. cx23885_irq_add_enable(dev, PCI_MSK_IR);
  1399. break;
  1400. case CX23885_BOARD_TEVII_S470:
  1401. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1402. if (dev->sd_ir)
  1403. cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
  1404. break;
  1405. }
  1406. }
  1407. void cx23885_card_setup(struct cx23885_dev *dev)
  1408. {
  1409. struct cx23885_tsport *ts1 = &dev->ts1;
  1410. struct cx23885_tsport *ts2 = &dev->ts2;
  1411. static u8 eeprom[256];
  1412. if (dev->i2c_bus[0].i2c_rc == 0) {
  1413. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1414. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  1415. eeprom, sizeof(eeprom));
  1416. }
  1417. switch (dev->board) {
  1418. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1419. if (dev->i2c_bus[0].i2c_rc == 0) {
  1420. if (eeprom[0x80] != 0x84)
  1421. hauppauge_eeprom(dev, eeprom+0xc0);
  1422. else
  1423. hauppauge_eeprom(dev, eeprom+0x80);
  1424. }
  1425. break;
  1426. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1427. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1428. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1429. if (dev->i2c_bus[0].i2c_rc == 0)
  1430. hauppauge_eeprom(dev, eeprom+0x80);
  1431. break;
  1432. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1433. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1434. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1435. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1436. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1437. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1438. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1439. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1440. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1441. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1442. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1443. if (dev->i2c_bus[0].i2c_rc == 0)
  1444. hauppauge_eeprom(dev, eeprom+0xc0);
  1445. break;
  1446. }
  1447. switch (dev->board) {
  1448. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1449. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1450. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1451. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1452. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1453. /* break omitted intentionally */
  1454. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  1455. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1456. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1457. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1458. break;
  1459. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1460. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1461. /* Defaults for VID B - Analog encoder */
  1462. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  1463. ts1->gen_ctrl_val = 0x10e;
  1464. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1465. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1466. /* APB_TSVALERR_POL (active low)*/
  1467. ts1->vld_misc_val = 0x2000;
  1468. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  1469. cx_write(0x130184, 0xc);
  1470. /* Defaults for VID C */
  1471. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1472. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1473. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1474. break;
  1475. case CX23885_BOARD_TBS_6920:
  1476. ts1->gen_ctrl_val = 0x4; /* Parallel */
  1477. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1478. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1479. break;
  1480. case CX23885_BOARD_TEVII_S470:
  1481. case CX23885_BOARD_TEVII_S471:
  1482. case CX23885_BOARD_DVBWORLD_2005:
  1483. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1484. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1485. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1486. break;
  1487. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1488. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1489. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1490. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1491. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1492. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1493. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1494. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1495. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1496. break;
  1497. case CX23885_BOARD_MYGICA_X8506:
  1498. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1499. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1500. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1501. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1502. break;
  1503. case CX23885_BOARD_MYGICA_X8558PRO:
  1504. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1505. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1506. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1507. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1508. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1509. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1510. break;
  1511. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1512. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1513. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1514. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1515. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1516. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1517. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1518. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1519. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1520. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1521. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1522. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1523. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1524. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1525. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1526. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1527. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1528. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1529. default:
  1530. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1531. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1532. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1533. }
  1534. /* Certain boards support analog, or require the avcore to be
  1535. * loaded, ensure this happens.
  1536. */
  1537. switch (dev->board) {
  1538. case CX23885_BOARD_TEVII_S470:
  1539. /* Currently only enabled for the integrated IR controller */
  1540. if (!enable_885_ir)
  1541. break;
  1542. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1543. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1544. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1545. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1546. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1547. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1548. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1549. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1550. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1551. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1552. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1553. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1554. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1555. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1556. case CX23885_BOARD_MYGICA_X8506:
  1557. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1558. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1559. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1560. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1561. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1562. case CX23885_BOARD_MPX885:
  1563. case CX23885_BOARD_MYGICA_X8507:
  1564. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1565. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  1566. &dev->i2c_bus[2].i2c_adap,
  1567. "cx25840", 0x88 >> 1, NULL);
  1568. if (dev->sd_cx25840) {
  1569. dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
  1570. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  1571. }
  1572. break;
  1573. }
  1574. /* AUX-PLL 27MHz CLK */
  1575. switch (dev->board) {
  1576. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1577. netup_initialize(dev);
  1578. break;
  1579. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1580. int ret;
  1581. const struct firmware *fw;
  1582. const char *filename = "dvb-netup-altera-01.fw";
  1583. char *action = "configure";
  1584. static struct netup_card_info cinfo;
  1585. struct altera_config netup_config = {
  1586. .dev = dev,
  1587. .action = action,
  1588. .jtag_io = netup_jtag_io,
  1589. };
  1590. netup_initialize(dev);
  1591. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1592. if (netup_card_rev)
  1593. cinfo.rev = netup_card_rev;
  1594. switch (cinfo.rev) {
  1595. case 0x4:
  1596. filename = "dvb-netup-altera-04.fw";
  1597. break;
  1598. default:
  1599. filename = "dvb-netup-altera-01.fw";
  1600. break;
  1601. }
  1602. printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
  1603. cinfo.rev, filename);
  1604. ret = request_firmware(&fw, filename, &dev->pci->dev);
  1605. if (ret != 0)
  1606. printk(KERN_ERR "did not find the firmware file. (%s) "
  1607. "Please see linux/Documentation/dvb/ for more details "
  1608. "on firmware-problems.", filename);
  1609. else
  1610. altera_init(&netup_config, fw);
  1611. release_firmware(fw);
  1612. break;
  1613. }
  1614. }
  1615. }
  1616. /* ------------------------------------------------------------------ */