i915_debugfs.c 57 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "intel_drv.h"
  35. #include "intel_ringbuffer.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #define DRM_I915_RING_DEBUG 1
  39. #if defined(CONFIG_DEBUG_FS)
  40. enum {
  41. ACTIVE_LIST,
  42. INACTIVE_LIST,
  43. PINNED_LIST,
  44. };
  45. static const char *yesno(int v)
  46. {
  47. return v ? "yes" : "no";
  48. }
  49. static int i915_capabilities(struct seq_file *m, void *data)
  50. {
  51. struct drm_info_node *node = (struct drm_info_node *) m->private;
  52. struct drm_device *dev = node->minor->dev;
  53. const struct intel_device_info *info = INTEL_INFO(dev);
  54. seq_printf(m, "gen: %d\n", info->gen);
  55. seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  56. #define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  57. #define DEV_INFO_SEP ;
  58. DEV_INFO_FLAGS;
  59. #undef DEV_INFO_FLAG
  60. #undef DEV_INFO_SEP
  61. return 0;
  62. }
  63. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  64. {
  65. if (obj->user_pin_count > 0)
  66. return "P";
  67. else if (obj->pin_count > 0)
  68. return "p";
  69. else
  70. return " ";
  71. }
  72. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  73. {
  74. switch (obj->tiling_mode) {
  75. default:
  76. case I915_TILING_NONE: return " ";
  77. case I915_TILING_X: return "X";
  78. case I915_TILING_Y: return "Y";
  79. }
  80. }
  81. static const char *cache_level_str(int type)
  82. {
  83. switch (type) {
  84. case I915_CACHE_NONE: return " uncached";
  85. case I915_CACHE_LLC: return " snooped (LLC)";
  86. case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
  87. default: return "";
  88. }
  89. }
  90. static void
  91. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  92. {
  93. seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d %d%s%s%s",
  94. &obj->base,
  95. get_pin_flag(obj),
  96. get_tiling_flag(obj),
  97. obj->base.size / 1024,
  98. obj->base.read_domains,
  99. obj->base.write_domain,
  100. obj->last_read_seqno,
  101. obj->last_write_seqno,
  102. obj->last_fenced_seqno,
  103. cache_level_str(obj->cache_level),
  104. obj->dirty ? " dirty" : "",
  105. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  106. if (obj->base.name)
  107. seq_printf(m, " (name: %d)", obj->base.name);
  108. if (obj->fence_reg != I915_FENCE_REG_NONE)
  109. seq_printf(m, " (fence: %d)", obj->fence_reg);
  110. if (obj->gtt_space != NULL)
  111. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  112. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  113. if (obj->pin_mappable || obj->fault_mappable) {
  114. char s[3], *t = s;
  115. if (obj->pin_mappable)
  116. *t++ = 'p';
  117. if (obj->fault_mappable)
  118. *t++ = 'f';
  119. *t = '\0';
  120. seq_printf(m, " (%s mappable)", s);
  121. }
  122. if (obj->ring != NULL)
  123. seq_printf(m, " (%s)", obj->ring->name);
  124. }
  125. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  126. {
  127. struct drm_info_node *node = (struct drm_info_node *) m->private;
  128. uintptr_t list = (uintptr_t) node->info_ent->data;
  129. struct list_head *head;
  130. struct drm_device *dev = node->minor->dev;
  131. drm_i915_private_t *dev_priv = dev->dev_private;
  132. struct drm_i915_gem_object *obj;
  133. size_t total_obj_size, total_gtt_size;
  134. int count, ret;
  135. ret = mutex_lock_interruptible(&dev->struct_mutex);
  136. if (ret)
  137. return ret;
  138. switch (list) {
  139. case ACTIVE_LIST:
  140. seq_printf(m, "Active:\n");
  141. head = &dev_priv->mm.active_list;
  142. break;
  143. case INACTIVE_LIST:
  144. seq_printf(m, "Inactive:\n");
  145. head = &dev_priv->mm.inactive_list;
  146. break;
  147. default:
  148. mutex_unlock(&dev->struct_mutex);
  149. return -EINVAL;
  150. }
  151. total_obj_size = total_gtt_size = count = 0;
  152. list_for_each_entry(obj, head, mm_list) {
  153. seq_printf(m, " ");
  154. describe_obj(m, obj);
  155. seq_printf(m, "\n");
  156. total_obj_size += obj->base.size;
  157. total_gtt_size += obj->gtt_space->size;
  158. count++;
  159. }
  160. mutex_unlock(&dev->struct_mutex);
  161. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  162. count, total_obj_size, total_gtt_size);
  163. return 0;
  164. }
  165. #define count_objects(list, member) do { \
  166. list_for_each_entry(obj, list, member) { \
  167. size += obj->gtt_space->size; \
  168. ++count; \
  169. if (obj->map_and_fenceable) { \
  170. mappable_size += obj->gtt_space->size; \
  171. ++mappable_count; \
  172. } \
  173. } \
  174. } while (0)
  175. static int i915_gem_object_info(struct seq_file *m, void* data)
  176. {
  177. struct drm_info_node *node = (struct drm_info_node *) m->private;
  178. struct drm_device *dev = node->minor->dev;
  179. struct drm_i915_private *dev_priv = dev->dev_private;
  180. u32 count, mappable_count;
  181. size_t size, mappable_size;
  182. struct drm_i915_gem_object *obj;
  183. int ret;
  184. ret = mutex_lock_interruptible(&dev->struct_mutex);
  185. if (ret)
  186. return ret;
  187. seq_printf(m, "%u objects, %zu bytes\n",
  188. dev_priv->mm.object_count,
  189. dev_priv->mm.object_memory);
  190. size = count = mappable_size = mappable_count = 0;
  191. count_objects(&dev_priv->mm.gtt_list, gtt_list);
  192. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  193. count, mappable_count, size, mappable_size);
  194. size = count = mappable_size = mappable_count = 0;
  195. count_objects(&dev_priv->mm.active_list, mm_list);
  196. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  197. count, mappable_count, size, mappable_size);
  198. size = count = mappable_size = mappable_count = 0;
  199. count_objects(&dev_priv->mm.inactive_list, mm_list);
  200. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  201. count, mappable_count, size, mappable_size);
  202. size = count = mappable_size = mappable_count = 0;
  203. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  204. if (obj->fault_mappable) {
  205. size += obj->gtt_space->size;
  206. ++count;
  207. }
  208. if (obj->pin_mappable) {
  209. mappable_size += obj->gtt_space->size;
  210. ++mappable_count;
  211. }
  212. }
  213. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  214. mappable_count, mappable_size);
  215. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  216. count, size);
  217. seq_printf(m, "%zu [%zu] gtt total\n",
  218. dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
  219. mutex_unlock(&dev->struct_mutex);
  220. return 0;
  221. }
  222. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  223. {
  224. struct drm_info_node *node = (struct drm_info_node *) m->private;
  225. struct drm_device *dev = node->minor->dev;
  226. uintptr_t list = (uintptr_t) node->info_ent->data;
  227. struct drm_i915_private *dev_priv = dev->dev_private;
  228. struct drm_i915_gem_object *obj;
  229. size_t total_obj_size, total_gtt_size;
  230. int count, ret;
  231. ret = mutex_lock_interruptible(&dev->struct_mutex);
  232. if (ret)
  233. return ret;
  234. total_obj_size = total_gtt_size = count = 0;
  235. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  236. if (list == PINNED_LIST && obj->pin_count == 0)
  237. continue;
  238. seq_printf(m, " ");
  239. describe_obj(m, obj);
  240. seq_printf(m, "\n");
  241. total_obj_size += obj->base.size;
  242. total_gtt_size += obj->gtt_space->size;
  243. count++;
  244. }
  245. mutex_unlock(&dev->struct_mutex);
  246. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  247. count, total_obj_size, total_gtt_size);
  248. return 0;
  249. }
  250. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  251. {
  252. struct drm_info_node *node = (struct drm_info_node *) m->private;
  253. struct drm_device *dev = node->minor->dev;
  254. unsigned long flags;
  255. struct intel_crtc *crtc;
  256. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  257. const char pipe = pipe_name(crtc->pipe);
  258. const char plane = plane_name(crtc->plane);
  259. struct intel_unpin_work *work;
  260. spin_lock_irqsave(&dev->event_lock, flags);
  261. work = crtc->unpin_work;
  262. if (work == NULL) {
  263. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  264. pipe, plane);
  265. } else {
  266. if (!work->pending) {
  267. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  268. pipe, plane);
  269. } else {
  270. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  271. pipe, plane);
  272. }
  273. if (work->enable_stall_check)
  274. seq_printf(m, "Stall check enabled, ");
  275. else
  276. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  277. seq_printf(m, "%d prepares\n", work->pending);
  278. if (work->old_fb_obj) {
  279. struct drm_i915_gem_object *obj = work->old_fb_obj;
  280. if (obj)
  281. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  282. }
  283. if (work->pending_flip_obj) {
  284. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  285. if (obj)
  286. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  287. }
  288. }
  289. spin_unlock_irqrestore(&dev->event_lock, flags);
  290. }
  291. return 0;
  292. }
  293. static int i915_gem_request_info(struct seq_file *m, void *data)
  294. {
  295. struct drm_info_node *node = (struct drm_info_node *) m->private;
  296. struct drm_device *dev = node->minor->dev;
  297. drm_i915_private_t *dev_priv = dev->dev_private;
  298. struct drm_i915_gem_request *gem_request;
  299. int ret, count;
  300. ret = mutex_lock_interruptible(&dev->struct_mutex);
  301. if (ret)
  302. return ret;
  303. count = 0;
  304. if (!list_empty(&dev_priv->ring[RCS].request_list)) {
  305. seq_printf(m, "Render requests:\n");
  306. list_for_each_entry(gem_request,
  307. &dev_priv->ring[RCS].request_list,
  308. list) {
  309. seq_printf(m, " %d @ %d\n",
  310. gem_request->seqno,
  311. (int) (jiffies - gem_request->emitted_jiffies));
  312. }
  313. count++;
  314. }
  315. if (!list_empty(&dev_priv->ring[VCS].request_list)) {
  316. seq_printf(m, "BSD requests:\n");
  317. list_for_each_entry(gem_request,
  318. &dev_priv->ring[VCS].request_list,
  319. list) {
  320. seq_printf(m, " %d @ %d\n",
  321. gem_request->seqno,
  322. (int) (jiffies - gem_request->emitted_jiffies));
  323. }
  324. count++;
  325. }
  326. if (!list_empty(&dev_priv->ring[BCS].request_list)) {
  327. seq_printf(m, "BLT requests:\n");
  328. list_for_each_entry(gem_request,
  329. &dev_priv->ring[BCS].request_list,
  330. list) {
  331. seq_printf(m, " %d @ %d\n",
  332. gem_request->seqno,
  333. (int) (jiffies - gem_request->emitted_jiffies));
  334. }
  335. count++;
  336. }
  337. mutex_unlock(&dev->struct_mutex);
  338. if (count == 0)
  339. seq_printf(m, "No requests\n");
  340. return 0;
  341. }
  342. static void i915_ring_seqno_info(struct seq_file *m,
  343. struct intel_ring_buffer *ring)
  344. {
  345. if (ring->get_seqno) {
  346. seq_printf(m, "Current sequence (%s): %d\n",
  347. ring->name, ring->get_seqno(ring));
  348. }
  349. }
  350. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  351. {
  352. struct drm_info_node *node = (struct drm_info_node *) m->private;
  353. struct drm_device *dev = node->minor->dev;
  354. drm_i915_private_t *dev_priv = dev->dev_private;
  355. int ret, i;
  356. ret = mutex_lock_interruptible(&dev->struct_mutex);
  357. if (ret)
  358. return ret;
  359. for (i = 0; i < I915_NUM_RINGS; i++)
  360. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  361. mutex_unlock(&dev->struct_mutex);
  362. return 0;
  363. }
  364. static int i915_interrupt_info(struct seq_file *m, void *data)
  365. {
  366. struct drm_info_node *node = (struct drm_info_node *) m->private;
  367. struct drm_device *dev = node->minor->dev;
  368. drm_i915_private_t *dev_priv = dev->dev_private;
  369. int ret, i, pipe;
  370. ret = mutex_lock_interruptible(&dev->struct_mutex);
  371. if (ret)
  372. return ret;
  373. if (IS_VALLEYVIEW(dev)) {
  374. seq_printf(m, "Display IER:\t%08x\n",
  375. I915_READ(VLV_IER));
  376. seq_printf(m, "Display IIR:\t%08x\n",
  377. I915_READ(VLV_IIR));
  378. seq_printf(m, "Display IIR_RW:\t%08x\n",
  379. I915_READ(VLV_IIR_RW));
  380. seq_printf(m, "Display IMR:\t%08x\n",
  381. I915_READ(VLV_IMR));
  382. for_each_pipe(pipe)
  383. seq_printf(m, "Pipe %c stat:\t%08x\n",
  384. pipe_name(pipe),
  385. I915_READ(PIPESTAT(pipe)));
  386. seq_printf(m, "Master IER:\t%08x\n",
  387. I915_READ(VLV_MASTER_IER));
  388. seq_printf(m, "Render IER:\t%08x\n",
  389. I915_READ(GTIER));
  390. seq_printf(m, "Render IIR:\t%08x\n",
  391. I915_READ(GTIIR));
  392. seq_printf(m, "Render IMR:\t%08x\n",
  393. I915_READ(GTIMR));
  394. seq_printf(m, "PM IER:\t\t%08x\n",
  395. I915_READ(GEN6_PMIER));
  396. seq_printf(m, "PM IIR:\t\t%08x\n",
  397. I915_READ(GEN6_PMIIR));
  398. seq_printf(m, "PM IMR:\t\t%08x\n",
  399. I915_READ(GEN6_PMIMR));
  400. seq_printf(m, "Port hotplug:\t%08x\n",
  401. I915_READ(PORT_HOTPLUG_EN));
  402. seq_printf(m, "DPFLIPSTAT:\t%08x\n",
  403. I915_READ(VLV_DPFLIPSTAT));
  404. seq_printf(m, "DPINVGTT:\t%08x\n",
  405. I915_READ(DPINVGTT));
  406. } else if (!HAS_PCH_SPLIT(dev)) {
  407. seq_printf(m, "Interrupt enable: %08x\n",
  408. I915_READ(IER));
  409. seq_printf(m, "Interrupt identity: %08x\n",
  410. I915_READ(IIR));
  411. seq_printf(m, "Interrupt mask: %08x\n",
  412. I915_READ(IMR));
  413. for_each_pipe(pipe)
  414. seq_printf(m, "Pipe %c stat: %08x\n",
  415. pipe_name(pipe),
  416. I915_READ(PIPESTAT(pipe)));
  417. } else {
  418. seq_printf(m, "North Display Interrupt enable: %08x\n",
  419. I915_READ(DEIER));
  420. seq_printf(m, "North Display Interrupt identity: %08x\n",
  421. I915_READ(DEIIR));
  422. seq_printf(m, "North Display Interrupt mask: %08x\n",
  423. I915_READ(DEIMR));
  424. seq_printf(m, "South Display Interrupt enable: %08x\n",
  425. I915_READ(SDEIER));
  426. seq_printf(m, "South Display Interrupt identity: %08x\n",
  427. I915_READ(SDEIIR));
  428. seq_printf(m, "South Display Interrupt mask: %08x\n",
  429. I915_READ(SDEIMR));
  430. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  431. I915_READ(GTIER));
  432. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  433. I915_READ(GTIIR));
  434. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  435. I915_READ(GTIMR));
  436. }
  437. seq_printf(m, "Interrupts received: %d\n",
  438. atomic_read(&dev_priv->irq_received));
  439. for (i = 0; i < I915_NUM_RINGS; i++) {
  440. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  441. seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
  442. dev_priv->ring[i].name,
  443. I915_READ_IMR(&dev_priv->ring[i]));
  444. }
  445. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  446. }
  447. mutex_unlock(&dev->struct_mutex);
  448. return 0;
  449. }
  450. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  451. {
  452. struct drm_info_node *node = (struct drm_info_node *) m->private;
  453. struct drm_device *dev = node->minor->dev;
  454. drm_i915_private_t *dev_priv = dev->dev_private;
  455. int i, ret;
  456. ret = mutex_lock_interruptible(&dev->struct_mutex);
  457. if (ret)
  458. return ret;
  459. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  460. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  461. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  462. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  463. seq_printf(m, "Fenced object[%2d] = ", i);
  464. if (obj == NULL)
  465. seq_printf(m, "unused");
  466. else
  467. describe_obj(m, obj);
  468. seq_printf(m, "\n");
  469. }
  470. mutex_unlock(&dev->struct_mutex);
  471. return 0;
  472. }
  473. static int i915_hws_info(struct seq_file *m, void *data)
  474. {
  475. struct drm_info_node *node = (struct drm_info_node *) m->private;
  476. struct drm_device *dev = node->minor->dev;
  477. drm_i915_private_t *dev_priv = dev->dev_private;
  478. struct intel_ring_buffer *ring;
  479. const volatile u32 __iomem *hws;
  480. int i;
  481. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  482. hws = (volatile u32 __iomem *)ring->status_page.page_addr;
  483. if (hws == NULL)
  484. return 0;
  485. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  486. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  487. i * 4,
  488. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  489. }
  490. return 0;
  491. }
  492. static const char *ring_str(int ring)
  493. {
  494. switch (ring) {
  495. case RCS: return "render";
  496. case VCS: return "bsd";
  497. case BCS: return "blt";
  498. default: return "";
  499. }
  500. }
  501. static const char *pin_flag(int pinned)
  502. {
  503. if (pinned > 0)
  504. return " P";
  505. else if (pinned < 0)
  506. return " p";
  507. else
  508. return "";
  509. }
  510. static const char *tiling_flag(int tiling)
  511. {
  512. switch (tiling) {
  513. default:
  514. case I915_TILING_NONE: return "";
  515. case I915_TILING_X: return " X";
  516. case I915_TILING_Y: return " Y";
  517. }
  518. }
  519. static const char *dirty_flag(int dirty)
  520. {
  521. return dirty ? " dirty" : "";
  522. }
  523. static const char *purgeable_flag(int purgeable)
  524. {
  525. return purgeable ? " purgeable" : "";
  526. }
  527. static void print_error_buffers(struct seq_file *m,
  528. const char *name,
  529. struct drm_i915_error_buffer *err,
  530. int count)
  531. {
  532. seq_printf(m, "%s [%d]:\n", name, count);
  533. while (count--) {
  534. seq_printf(m, " %08x %8u %04x %04x %x %x%s%s%s%s%s%s%s",
  535. err->gtt_offset,
  536. err->size,
  537. err->read_domains,
  538. err->write_domain,
  539. err->rseqno, err->wseqno,
  540. pin_flag(err->pinned),
  541. tiling_flag(err->tiling),
  542. dirty_flag(err->dirty),
  543. purgeable_flag(err->purgeable),
  544. err->ring != -1 ? " " : "",
  545. ring_str(err->ring),
  546. cache_level_str(err->cache_level));
  547. if (err->name)
  548. seq_printf(m, " (name: %d)", err->name);
  549. if (err->fence_reg != I915_FENCE_REG_NONE)
  550. seq_printf(m, " (fence: %d)", err->fence_reg);
  551. seq_printf(m, "\n");
  552. err++;
  553. }
  554. }
  555. static void i915_ring_error_state(struct seq_file *m,
  556. struct drm_device *dev,
  557. struct drm_i915_error_state *error,
  558. unsigned ring)
  559. {
  560. BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
  561. seq_printf(m, "%s command stream:\n", ring_str(ring));
  562. seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
  563. seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
  564. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
  565. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
  566. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
  567. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
  568. if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
  569. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  570. seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
  571. }
  572. if (INTEL_INFO(dev)->gen >= 4)
  573. seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
  574. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
  575. seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
  576. if (INTEL_INFO(dev)->gen >= 6) {
  577. seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
  578. seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
  579. seq_printf(m, " SYNC_0: 0x%08x\n",
  580. error->semaphore_mboxes[ring][0]);
  581. seq_printf(m, " SYNC_1: 0x%08x\n",
  582. error->semaphore_mboxes[ring][1]);
  583. }
  584. seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
  585. seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
  586. seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
  587. seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
  588. }
  589. struct i915_error_state_file_priv {
  590. struct drm_device *dev;
  591. struct drm_i915_error_state *error;
  592. };
  593. static int i915_error_state(struct seq_file *m, void *unused)
  594. {
  595. struct i915_error_state_file_priv *error_priv = m->private;
  596. struct drm_device *dev = error_priv->dev;
  597. drm_i915_private_t *dev_priv = dev->dev_private;
  598. struct drm_i915_error_state *error = error_priv->error;
  599. struct intel_ring_buffer *ring;
  600. int i, j, page, offset, elt;
  601. if (!error) {
  602. seq_printf(m, "no error state collected\n");
  603. return 0;
  604. }
  605. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  606. error->time.tv_usec);
  607. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  608. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  609. seq_printf(m, "IER: 0x%08x\n", error->ier);
  610. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  611. seq_printf(m, "CCID: 0x%08x\n", error->ccid);
  612. for (i = 0; i < dev_priv->num_fence_regs; i++)
  613. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  614. if (INTEL_INFO(dev)->gen >= 6) {
  615. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  616. seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
  617. }
  618. for_each_ring(ring, dev_priv, i)
  619. i915_ring_error_state(m, dev, error, i);
  620. if (error->active_bo)
  621. print_error_buffers(m, "Active",
  622. error->active_bo,
  623. error->active_bo_count);
  624. if (error->pinned_bo)
  625. print_error_buffers(m, "Pinned",
  626. error->pinned_bo,
  627. error->pinned_bo_count);
  628. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  629. struct drm_i915_error_object *obj;
  630. if ((obj = error->ring[i].batchbuffer)) {
  631. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  632. dev_priv->ring[i].name,
  633. obj->gtt_offset);
  634. offset = 0;
  635. for (page = 0; page < obj->page_count; page++) {
  636. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  637. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  638. offset += 4;
  639. }
  640. }
  641. }
  642. if (error->ring[i].num_requests) {
  643. seq_printf(m, "%s --- %d requests\n",
  644. dev_priv->ring[i].name,
  645. error->ring[i].num_requests);
  646. for (j = 0; j < error->ring[i].num_requests; j++) {
  647. seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
  648. error->ring[i].requests[j].seqno,
  649. error->ring[i].requests[j].jiffies,
  650. error->ring[i].requests[j].tail);
  651. }
  652. }
  653. if ((obj = error->ring[i].ringbuffer)) {
  654. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  655. dev_priv->ring[i].name,
  656. obj->gtt_offset);
  657. offset = 0;
  658. for (page = 0; page < obj->page_count; page++) {
  659. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  660. seq_printf(m, "%08x : %08x\n",
  661. offset,
  662. obj->pages[page][elt]);
  663. offset += 4;
  664. }
  665. }
  666. }
  667. }
  668. if (error->overlay)
  669. intel_overlay_print_error_state(m, error->overlay);
  670. if (error->display)
  671. intel_display_print_error_state(m, dev, error->display);
  672. return 0;
  673. }
  674. static ssize_t
  675. i915_error_state_write(struct file *filp,
  676. const char __user *ubuf,
  677. size_t cnt,
  678. loff_t *ppos)
  679. {
  680. struct seq_file *m = filp->private_data;
  681. struct i915_error_state_file_priv *error_priv = m->private;
  682. struct drm_device *dev = error_priv->dev;
  683. int ret;
  684. DRM_DEBUG_DRIVER("Resetting error state\n");
  685. ret = mutex_lock_interruptible(&dev->struct_mutex);
  686. if (ret)
  687. return ret;
  688. i915_destroy_error_state(dev);
  689. mutex_unlock(&dev->struct_mutex);
  690. return cnt;
  691. }
  692. static int i915_error_state_open(struct inode *inode, struct file *file)
  693. {
  694. struct drm_device *dev = inode->i_private;
  695. drm_i915_private_t *dev_priv = dev->dev_private;
  696. struct i915_error_state_file_priv *error_priv;
  697. unsigned long flags;
  698. error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
  699. if (!error_priv)
  700. return -ENOMEM;
  701. error_priv->dev = dev;
  702. spin_lock_irqsave(&dev_priv->error_lock, flags);
  703. error_priv->error = dev_priv->first_error;
  704. if (error_priv->error)
  705. kref_get(&error_priv->error->ref);
  706. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  707. return single_open(file, i915_error_state, error_priv);
  708. }
  709. static int i915_error_state_release(struct inode *inode, struct file *file)
  710. {
  711. struct seq_file *m = file->private_data;
  712. struct i915_error_state_file_priv *error_priv = m->private;
  713. if (error_priv->error)
  714. kref_put(&error_priv->error->ref, i915_error_state_free);
  715. kfree(error_priv);
  716. return single_release(inode, file);
  717. }
  718. static const struct file_operations i915_error_state_fops = {
  719. .owner = THIS_MODULE,
  720. .open = i915_error_state_open,
  721. .read = seq_read,
  722. .write = i915_error_state_write,
  723. .llseek = default_llseek,
  724. .release = i915_error_state_release,
  725. };
  726. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  727. {
  728. struct drm_info_node *node = (struct drm_info_node *) m->private;
  729. struct drm_device *dev = node->minor->dev;
  730. drm_i915_private_t *dev_priv = dev->dev_private;
  731. u16 crstanddelay;
  732. int ret;
  733. ret = mutex_lock_interruptible(&dev->struct_mutex);
  734. if (ret)
  735. return ret;
  736. crstanddelay = I915_READ16(CRSTANDVID);
  737. mutex_unlock(&dev->struct_mutex);
  738. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  739. return 0;
  740. }
  741. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  742. {
  743. struct drm_info_node *node = (struct drm_info_node *) m->private;
  744. struct drm_device *dev = node->minor->dev;
  745. drm_i915_private_t *dev_priv = dev->dev_private;
  746. int ret;
  747. if (IS_GEN5(dev)) {
  748. u16 rgvswctl = I915_READ16(MEMSWCTL);
  749. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  750. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  751. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  752. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  753. MEMSTAT_VID_SHIFT);
  754. seq_printf(m, "Current P-state: %d\n",
  755. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  756. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  757. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  758. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  759. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  760. u32 rpstat;
  761. u32 rpupei, rpcurup, rpprevup;
  762. u32 rpdownei, rpcurdown, rpprevdown;
  763. int max_freq;
  764. /* RPSTAT1 is in the GT power well */
  765. ret = mutex_lock_interruptible(&dev->struct_mutex);
  766. if (ret)
  767. return ret;
  768. gen6_gt_force_wake_get(dev_priv);
  769. rpstat = I915_READ(GEN6_RPSTAT1);
  770. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  771. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  772. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  773. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  774. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  775. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  776. gen6_gt_force_wake_put(dev_priv);
  777. mutex_unlock(&dev->struct_mutex);
  778. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  779. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  780. seq_printf(m, "Render p-state ratio: %d\n",
  781. (gt_perf_status & 0xff00) >> 8);
  782. seq_printf(m, "Render p-state VID: %d\n",
  783. gt_perf_status & 0xff);
  784. seq_printf(m, "Render p-state limit: %d\n",
  785. rp_state_limits & 0xff);
  786. seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
  787. GEN6_CAGF_SHIFT) * 50);
  788. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  789. GEN6_CURICONT_MASK);
  790. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  791. GEN6_CURBSYTAVG_MASK);
  792. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  793. GEN6_CURBSYTAVG_MASK);
  794. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  795. GEN6_CURIAVG_MASK);
  796. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  797. GEN6_CURBSYTAVG_MASK);
  798. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  799. GEN6_CURBSYTAVG_MASK);
  800. max_freq = (rp_state_cap & 0xff0000) >> 16;
  801. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  802. max_freq * 50);
  803. max_freq = (rp_state_cap & 0xff00) >> 8;
  804. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  805. max_freq * 50);
  806. max_freq = rp_state_cap & 0xff;
  807. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  808. max_freq * 50);
  809. } else {
  810. seq_printf(m, "no P-state info available\n");
  811. }
  812. return 0;
  813. }
  814. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  815. {
  816. struct drm_info_node *node = (struct drm_info_node *) m->private;
  817. struct drm_device *dev = node->minor->dev;
  818. drm_i915_private_t *dev_priv = dev->dev_private;
  819. u32 delayfreq;
  820. int ret, i;
  821. ret = mutex_lock_interruptible(&dev->struct_mutex);
  822. if (ret)
  823. return ret;
  824. for (i = 0; i < 16; i++) {
  825. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  826. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  827. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  828. }
  829. mutex_unlock(&dev->struct_mutex);
  830. return 0;
  831. }
  832. static inline int MAP_TO_MV(int map)
  833. {
  834. return 1250 - (map * 25);
  835. }
  836. static int i915_inttoext_table(struct seq_file *m, void *unused)
  837. {
  838. struct drm_info_node *node = (struct drm_info_node *) m->private;
  839. struct drm_device *dev = node->minor->dev;
  840. drm_i915_private_t *dev_priv = dev->dev_private;
  841. u32 inttoext;
  842. int ret, i;
  843. ret = mutex_lock_interruptible(&dev->struct_mutex);
  844. if (ret)
  845. return ret;
  846. for (i = 1; i <= 32; i++) {
  847. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  848. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  849. }
  850. mutex_unlock(&dev->struct_mutex);
  851. return 0;
  852. }
  853. static int ironlake_drpc_info(struct seq_file *m)
  854. {
  855. struct drm_info_node *node = (struct drm_info_node *) m->private;
  856. struct drm_device *dev = node->minor->dev;
  857. drm_i915_private_t *dev_priv = dev->dev_private;
  858. u32 rgvmodectl, rstdbyctl;
  859. u16 crstandvid;
  860. int ret;
  861. ret = mutex_lock_interruptible(&dev->struct_mutex);
  862. if (ret)
  863. return ret;
  864. rgvmodectl = I915_READ(MEMMODECTL);
  865. rstdbyctl = I915_READ(RSTDBYCTL);
  866. crstandvid = I915_READ16(CRSTANDVID);
  867. mutex_unlock(&dev->struct_mutex);
  868. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  869. "yes" : "no");
  870. seq_printf(m, "Boost freq: %d\n",
  871. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  872. MEMMODE_BOOST_FREQ_SHIFT);
  873. seq_printf(m, "HW control enabled: %s\n",
  874. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  875. seq_printf(m, "SW control enabled: %s\n",
  876. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  877. seq_printf(m, "Gated voltage change: %s\n",
  878. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  879. seq_printf(m, "Starting frequency: P%d\n",
  880. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  881. seq_printf(m, "Max P-state: P%d\n",
  882. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  883. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  884. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  885. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  886. seq_printf(m, "Render standby enabled: %s\n",
  887. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  888. seq_printf(m, "Current RS state: ");
  889. switch (rstdbyctl & RSX_STATUS_MASK) {
  890. case RSX_STATUS_ON:
  891. seq_printf(m, "on\n");
  892. break;
  893. case RSX_STATUS_RC1:
  894. seq_printf(m, "RC1\n");
  895. break;
  896. case RSX_STATUS_RC1E:
  897. seq_printf(m, "RC1E\n");
  898. break;
  899. case RSX_STATUS_RS1:
  900. seq_printf(m, "RS1\n");
  901. break;
  902. case RSX_STATUS_RS2:
  903. seq_printf(m, "RS2 (RC6)\n");
  904. break;
  905. case RSX_STATUS_RS3:
  906. seq_printf(m, "RC3 (RC6+)\n");
  907. break;
  908. default:
  909. seq_printf(m, "unknown\n");
  910. break;
  911. }
  912. return 0;
  913. }
  914. static int gen6_drpc_info(struct seq_file *m)
  915. {
  916. struct drm_info_node *node = (struct drm_info_node *) m->private;
  917. struct drm_device *dev = node->minor->dev;
  918. struct drm_i915_private *dev_priv = dev->dev_private;
  919. u32 rpmodectl1, gt_core_status, rcctl1;
  920. unsigned forcewake_count;
  921. int count=0, ret;
  922. ret = mutex_lock_interruptible(&dev->struct_mutex);
  923. if (ret)
  924. return ret;
  925. spin_lock_irq(&dev_priv->gt_lock);
  926. forcewake_count = dev_priv->forcewake_count;
  927. spin_unlock_irq(&dev_priv->gt_lock);
  928. if (forcewake_count) {
  929. seq_printf(m, "RC information inaccurate because somebody "
  930. "holds a forcewake reference \n");
  931. } else {
  932. /* NB: we cannot use forcewake, else we read the wrong values */
  933. while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
  934. udelay(10);
  935. seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
  936. }
  937. gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
  938. trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
  939. rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
  940. rcctl1 = I915_READ(GEN6_RC_CONTROL);
  941. mutex_unlock(&dev->struct_mutex);
  942. seq_printf(m, "Video Turbo Mode: %s\n",
  943. yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
  944. seq_printf(m, "HW control enabled: %s\n",
  945. yesno(rpmodectl1 & GEN6_RP_ENABLE));
  946. seq_printf(m, "SW control enabled: %s\n",
  947. yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
  948. GEN6_RP_MEDIA_SW_MODE));
  949. seq_printf(m, "RC1e Enabled: %s\n",
  950. yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
  951. seq_printf(m, "RC6 Enabled: %s\n",
  952. yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
  953. seq_printf(m, "Deep RC6 Enabled: %s\n",
  954. yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
  955. seq_printf(m, "Deepest RC6 Enabled: %s\n",
  956. yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
  957. seq_printf(m, "Current RC state: ");
  958. switch (gt_core_status & GEN6_RCn_MASK) {
  959. case GEN6_RC0:
  960. if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
  961. seq_printf(m, "Core Power Down\n");
  962. else
  963. seq_printf(m, "on\n");
  964. break;
  965. case GEN6_RC3:
  966. seq_printf(m, "RC3\n");
  967. break;
  968. case GEN6_RC6:
  969. seq_printf(m, "RC6\n");
  970. break;
  971. case GEN6_RC7:
  972. seq_printf(m, "RC7\n");
  973. break;
  974. default:
  975. seq_printf(m, "Unknown\n");
  976. break;
  977. }
  978. seq_printf(m, "Core Power Down: %s\n",
  979. yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
  980. /* Not exactly sure what this is */
  981. seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
  982. I915_READ(GEN6_GT_GFX_RC6_LOCKED));
  983. seq_printf(m, "RC6 residency since boot: %u\n",
  984. I915_READ(GEN6_GT_GFX_RC6));
  985. seq_printf(m, "RC6+ residency since boot: %u\n",
  986. I915_READ(GEN6_GT_GFX_RC6p));
  987. seq_printf(m, "RC6++ residency since boot: %u\n",
  988. I915_READ(GEN6_GT_GFX_RC6pp));
  989. return 0;
  990. }
  991. static int i915_drpc_info(struct seq_file *m, void *unused)
  992. {
  993. struct drm_info_node *node = (struct drm_info_node *) m->private;
  994. struct drm_device *dev = node->minor->dev;
  995. if (IS_GEN6(dev) || IS_GEN7(dev))
  996. return gen6_drpc_info(m);
  997. else
  998. return ironlake_drpc_info(m);
  999. }
  1000. static int i915_fbc_status(struct seq_file *m, void *unused)
  1001. {
  1002. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1003. struct drm_device *dev = node->minor->dev;
  1004. drm_i915_private_t *dev_priv = dev->dev_private;
  1005. if (!I915_HAS_FBC(dev)) {
  1006. seq_printf(m, "FBC unsupported on this chipset\n");
  1007. return 0;
  1008. }
  1009. if (intel_fbc_enabled(dev)) {
  1010. seq_printf(m, "FBC enabled\n");
  1011. } else {
  1012. seq_printf(m, "FBC disabled: ");
  1013. switch (dev_priv->no_fbc_reason) {
  1014. case FBC_NO_OUTPUT:
  1015. seq_printf(m, "no outputs");
  1016. break;
  1017. case FBC_STOLEN_TOO_SMALL:
  1018. seq_printf(m, "not enough stolen memory");
  1019. break;
  1020. case FBC_UNSUPPORTED_MODE:
  1021. seq_printf(m, "mode not supported");
  1022. break;
  1023. case FBC_MODE_TOO_LARGE:
  1024. seq_printf(m, "mode too large");
  1025. break;
  1026. case FBC_BAD_PLANE:
  1027. seq_printf(m, "FBC unsupported on plane");
  1028. break;
  1029. case FBC_NOT_TILED:
  1030. seq_printf(m, "scanout buffer not tiled");
  1031. break;
  1032. case FBC_MULTIPLE_PIPES:
  1033. seq_printf(m, "multiple pipes are enabled");
  1034. break;
  1035. case FBC_MODULE_PARAM:
  1036. seq_printf(m, "disabled per module param (default off)");
  1037. break;
  1038. default:
  1039. seq_printf(m, "unknown reason");
  1040. }
  1041. seq_printf(m, "\n");
  1042. }
  1043. return 0;
  1044. }
  1045. static int i915_sr_status(struct seq_file *m, void *unused)
  1046. {
  1047. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1048. struct drm_device *dev = node->minor->dev;
  1049. drm_i915_private_t *dev_priv = dev->dev_private;
  1050. bool sr_enabled = false;
  1051. if (HAS_PCH_SPLIT(dev))
  1052. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  1053. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  1054. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  1055. else if (IS_I915GM(dev))
  1056. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  1057. else if (IS_PINEVIEW(dev))
  1058. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  1059. seq_printf(m, "self-refresh: %s\n",
  1060. sr_enabled ? "enabled" : "disabled");
  1061. return 0;
  1062. }
  1063. static int i915_emon_status(struct seq_file *m, void *unused)
  1064. {
  1065. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1066. struct drm_device *dev = node->minor->dev;
  1067. drm_i915_private_t *dev_priv = dev->dev_private;
  1068. unsigned long temp, chipset, gfx;
  1069. int ret;
  1070. if (!IS_GEN5(dev))
  1071. return -ENODEV;
  1072. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1073. if (ret)
  1074. return ret;
  1075. temp = i915_mch_val(dev_priv);
  1076. chipset = i915_chipset_val(dev_priv);
  1077. gfx = i915_gfx_val(dev_priv);
  1078. mutex_unlock(&dev->struct_mutex);
  1079. seq_printf(m, "GMCH temp: %ld\n", temp);
  1080. seq_printf(m, "Chipset power: %ld\n", chipset);
  1081. seq_printf(m, "GFX power: %ld\n", gfx);
  1082. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  1083. return 0;
  1084. }
  1085. static int i915_ring_freq_table(struct seq_file *m, void *unused)
  1086. {
  1087. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1088. struct drm_device *dev = node->minor->dev;
  1089. drm_i915_private_t *dev_priv = dev->dev_private;
  1090. int ret;
  1091. int gpu_freq, ia_freq;
  1092. if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
  1093. seq_printf(m, "unsupported on this chipset\n");
  1094. return 0;
  1095. }
  1096. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1097. if (ret)
  1098. return ret;
  1099. seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
  1100. for (gpu_freq = dev_priv->rps.min_delay;
  1101. gpu_freq <= dev_priv->rps.max_delay;
  1102. gpu_freq++) {
  1103. I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
  1104. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
  1105. GEN6_PCODE_READ_MIN_FREQ_TABLE);
  1106. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
  1107. GEN6_PCODE_READY) == 0, 10)) {
  1108. DRM_ERROR("pcode read of freq table timed out\n");
  1109. continue;
  1110. }
  1111. ia_freq = I915_READ(GEN6_PCODE_DATA);
  1112. seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
  1113. }
  1114. mutex_unlock(&dev->struct_mutex);
  1115. return 0;
  1116. }
  1117. static int i915_gfxec(struct seq_file *m, void *unused)
  1118. {
  1119. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1120. struct drm_device *dev = node->minor->dev;
  1121. drm_i915_private_t *dev_priv = dev->dev_private;
  1122. int ret;
  1123. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1124. if (ret)
  1125. return ret;
  1126. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  1127. mutex_unlock(&dev->struct_mutex);
  1128. return 0;
  1129. }
  1130. static int i915_opregion(struct seq_file *m, void *unused)
  1131. {
  1132. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1133. struct drm_device *dev = node->minor->dev;
  1134. drm_i915_private_t *dev_priv = dev->dev_private;
  1135. struct intel_opregion *opregion = &dev_priv->opregion;
  1136. void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
  1137. int ret;
  1138. if (data == NULL)
  1139. return -ENOMEM;
  1140. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1141. if (ret)
  1142. goto out;
  1143. if (opregion->header) {
  1144. memcpy_fromio(data, opregion->header, OPREGION_SIZE);
  1145. seq_write(m, data, OPREGION_SIZE);
  1146. }
  1147. mutex_unlock(&dev->struct_mutex);
  1148. out:
  1149. kfree(data);
  1150. return 0;
  1151. }
  1152. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  1153. {
  1154. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1155. struct drm_device *dev = node->minor->dev;
  1156. drm_i915_private_t *dev_priv = dev->dev_private;
  1157. struct intel_fbdev *ifbdev;
  1158. struct intel_framebuffer *fb;
  1159. int ret;
  1160. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1161. if (ret)
  1162. return ret;
  1163. ifbdev = dev_priv->fbdev;
  1164. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1165. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  1166. fb->base.width,
  1167. fb->base.height,
  1168. fb->base.depth,
  1169. fb->base.bits_per_pixel);
  1170. describe_obj(m, fb->obj);
  1171. seq_printf(m, "\n");
  1172. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1173. if (&fb->base == ifbdev->helper.fb)
  1174. continue;
  1175. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  1176. fb->base.width,
  1177. fb->base.height,
  1178. fb->base.depth,
  1179. fb->base.bits_per_pixel);
  1180. describe_obj(m, fb->obj);
  1181. seq_printf(m, "\n");
  1182. }
  1183. mutex_unlock(&dev->mode_config.mutex);
  1184. return 0;
  1185. }
  1186. static int i915_context_status(struct seq_file *m, void *unused)
  1187. {
  1188. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1189. struct drm_device *dev = node->minor->dev;
  1190. drm_i915_private_t *dev_priv = dev->dev_private;
  1191. int ret;
  1192. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1193. if (ret)
  1194. return ret;
  1195. if (dev_priv->pwrctx) {
  1196. seq_printf(m, "power context ");
  1197. describe_obj(m, dev_priv->pwrctx);
  1198. seq_printf(m, "\n");
  1199. }
  1200. if (dev_priv->renderctx) {
  1201. seq_printf(m, "render context ");
  1202. describe_obj(m, dev_priv->renderctx);
  1203. seq_printf(m, "\n");
  1204. }
  1205. mutex_unlock(&dev->mode_config.mutex);
  1206. return 0;
  1207. }
  1208. static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  1209. {
  1210. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1211. struct drm_device *dev = node->minor->dev;
  1212. struct drm_i915_private *dev_priv = dev->dev_private;
  1213. unsigned forcewake_count;
  1214. spin_lock_irq(&dev_priv->gt_lock);
  1215. forcewake_count = dev_priv->forcewake_count;
  1216. spin_unlock_irq(&dev_priv->gt_lock);
  1217. seq_printf(m, "forcewake count = %u\n", forcewake_count);
  1218. return 0;
  1219. }
  1220. static const char *swizzle_string(unsigned swizzle)
  1221. {
  1222. switch(swizzle) {
  1223. case I915_BIT_6_SWIZZLE_NONE:
  1224. return "none";
  1225. case I915_BIT_6_SWIZZLE_9:
  1226. return "bit9";
  1227. case I915_BIT_6_SWIZZLE_9_10:
  1228. return "bit9/bit10";
  1229. case I915_BIT_6_SWIZZLE_9_11:
  1230. return "bit9/bit11";
  1231. case I915_BIT_6_SWIZZLE_9_10_11:
  1232. return "bit9/bit10/bit11";
  1233. case I915_BIT_6_SWIZZLE_9_17:
  1234. return "bit9/bit17";
  1235. case I915_BIT_6_SWIZZLE_9_10_17:
  1236. return "bit9/bit10/bit17";
  1237. case I915_BIT_6_SWIZZLE_UNKNOWN:
  1238. return "unkown";
  1239. }
  1240. return "bug";
  1241. }
  1242. static int i915_swizzle_info(struct seq_file *m, void *data)
  1243. {
  1244. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1245. struct drm_device *dev = node->minor->dev;
  1246. struct drm_i915_private *dev_priv = dev->dev_private;
  1247. int ret;
  1248. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1249. if (ret)
  1250. return ret;
  1251. seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
  1252. swizzle_string(dev_priv->mm.bit_6_swizzle_x));
  1253. seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
  1254. swizzle_string(dev_priv->mm.bit_6_swizzle_y));
  1255. if (IS_GEN3(dev) || IS_GEN4(dev)) {
  1256. seq_printf(m, "DDC = 0x%08x\n",
  1257. I915_READ(DCC));
  1258. seq_printf(m, "C0DRB3 = 0x%04x\n",
  1259. I915_READ16(C0DRB3));
  1260. seq_printf(m, "C1DRB3 = 0x%04x\n",
  1261. I915_READ16(C1DRB3));
  1262. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  1263. seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
  1264. I915_READ(MAD_DIMM_C0));
  1265. seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
  1266. I915_READ(MAD_DIMM_C1));
  1267. seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
  1268. I915_READ(MAD_DIMM_C2));
  1269. seq_printf(m, "TILECTL = 0x%08x\n",
  1270. I915_READ(TILECTL));
  1271. seq_printf(m, "ARB_MODE = 0x%08x\n",
  1272. I915_READ(ARB_MODE));
  1273. seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
  1274. I915_READ(DISP_ARB_CTL));
  1275. }
  1276. mutex_unlock(&dev->struct_mutex);
  1277. return 0;
  1278. }
  1279. static int i915_ppgtt_info(struct seq_file *m, void *data)
  1280. {
  1281. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1282. struct drm_device *dev = node->minor->dev;
  1283. struct drm_i915_private *dev_priv = dev->dev_private;
  1284. struct intel_ring_buffer *ring;
  1285. int i, ret;
  1286. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1287. if (ret)
  1288. return ret;
  1289. if (INTEL_INFO(dev)->gen == 6)
  1290. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
  1291. for (i = 0; i < I915_NUM_RINGS; i++) {
  1292. ring = &dev_priv->ring[i];
  1293. seq_printf(m, "%s\n", ring->name);
  1294. if (INTEL_INFO(dev)->gen == 7)
  1295. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
  1296. seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
  1297. seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
  1298. seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
  1299. }
  1300. if (dev_priv->mm.aliasing_ppgtt) {
  1301. struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  1302. seq_printf(m, "aliasing PPGTT:\n");
  1303. seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
  1304. }
  1305. seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
  1306. mutex_unlock(&dev->struct_mutex);
  1307. return 0;
  1308. }
  1309. static int i915_dpio_info(struct seq_file *m, void *data)
  1310. {
  1311. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1312. struct drm_device *dev = node->minor->dev;
  1313. struct drm_i915_private *dev_priv = dev->dev_private;
  1314. int ret;
  1315. if (!IS_VALLEYVIEW(dev)) {
  1316. seq_printf(m, "unsupported\n");
  1317. return 0;
  1318. }
  1319. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1320. if (ret)
  1321. return ret;
  1322. seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
  1323. seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
  1324. intel_dpio_read(dev_priv, _DPIO_DIV_A));
  1325. seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
  1326. intel_dpio_read(dev_priv, _DPIO_DIV_B));
  1327. seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
  1328. intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
  1329. seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
  1330. intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
  1331. seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
  1332. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
  1333. seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
  1334. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
  1335. seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
  1336. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
  1337. seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
  1338. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
  1339. seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
  1340. intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
  1341. mutex_unlock(&dev->mode_config.mutex);
  1342. return 0;
  1343. }
  1344. static ssize_t
  1345. i915_wedged_read(struct file *filp,
  1346. char __user *ubuf,
  1347. size_t max,
  1348. loff_t *ppos)
  1349. {
  1350. struct drm_device *dev = filp->private_data;
  1351. drm_i915_private_t *dev_priv = dev->dev_private;
  1352. char buf[80];
  1353. int len;
  1354. len = snprintf(buf, sizeof(buf),
  1355. "wedged : %d\n",
  1356. atomic_read(&dev_priv->mm.wedged));
  1357. if (len > sizeof(buf))
  1358. len = sizeof(buf);
  1359. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1360. }
  1361. static ssize_t
  1362. i915_wedged_write(struct file *filp,
  1363. const char __user *ubuf,
  1364. size_t cnt,
  1365. loff_t *ppos)
  1366. {
  1367. struct drm_device *dev = filp->private_data;
  1368. char buf[20];
  1369. int val = 1;
  1370. if (cnt > 0) {
  1371. if (cnt > sizeof(buf) - 1)
  1372. return -EINVAL;
  1373. if (copy_from_user(buf, ubuf, cnt))
  1374. return -EFAULT;
  1375. buf[cnt] = 0;
  1376. val = simple_strtoul(buf, NULL, 0);
  1377. }
  1378. DRM_INFO("Manually setting wedged to %d\n", val);
  1379. i915_handle_error(dev, val);
  1380. return cnt;
  1381. }
  1382. static const struct file_operations i915_wedged_fops = {
  1383. .owner = THIS_MODULE,
  1384. .open = simple_open,
  1385. .read = i915_wedged_read,
  1386. .write = i915_wedged_write,
  1387. .llseek = default_llseek,
  1388. };
  1389. static ssize_t
  1390. i915_ring_stop_read(struct file *filp,
  1391. char __user *ubuf,
  1392. size_t max,
  1393. loff_t *ppos)
  1394. {
  1395. struct drm_device *dev = filp->private_data;
  1396. drm_i915_private_t *dev_priv = dev->dev_private;
  1397. char buf[20];
  1398. int len;
  1399. len = snprintf(buf, sizeof(buf),
  1400. "0x%08x\n", dev_priv->stop_rings);
  1401. if (len > sizeof(buf))
  1402. len = sizeof(buf);
  1403. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1404. }
  1405. static ssize_t
  1406. i915_ring_stop_write(struct file *filp,
  1407. const char __user *ubuf,
  1408. size_t cnt,
  1409. loff_t *ppos)
  1410. {
  1411. struct drm_device *dev = filp->private_data;
  1412. struct drm_i915_private *dev_priv = dev->dev_private;
  1413. char buf[20];
  1414. int val = 0, ret;
  1415. if (cnt > 0) {
  1416. if (cnt > sizeof(buf) - 1)
  1417. return -EINVAL;
  1418. if (copy_from_user(buf, ubuf, cnt))
  1419. return -EFAULT;
  1420. buf[cnt] = 0;
  1421. val = simple_strtoul(buf, NULL, 0);
  1422. }
  1423. DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
  1424. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1425. if (ret)
  1426. return ret;
  1427. dev_priv->stop_rings = val;
  1428. mutex_unlock(&dev->struct_mutex);
  1429. return cnt;
  1430. }
  1431. static const struct file_operations i915_ring_stop_fops = {
  1432. .owner = THIS_MODULE,
  1433. .open = simple_open,
  1434. .read = i915_ring_stop_read,
  1435. .write = i915_ring_stop_write,
  1436. .llseek = default_llseek,
  1437. };
  1438. static ssize_t
  1439. i915_max_freq_read(struct file *filp,
  1440. char __user *ubuf,
  1441. size_t max,
  1442. loff_t *ppos)
  1443. {
  1444. struct drm_device *dev = filp->private_data;
  1445. drm_i915_private_t *dev_priv = dev->dev_private;
  1446. char buf[80];
  1447. int len, ret;
  1448. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1449. return -ENODEV;
  1450. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1451. if (ret)
  1452. return ret;
  1453. len = snprintf(buf, sizeof(buf),
  1454. "max freq: %d\n", dev_priv->rps.max_delay * 50);
  1455. mutex_unlock(&dev->struct_mutex);
  1456. if (len > sizeof(buf))
  1457. len = sizeof(buf);
  1458. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1459. }
  1460. static ssize_t
  1461. i915_max_freq_write(struct file *filp,
  1462. const char __user *ubuf,
  1463. size_t cnt,
  1464. loff_t *ppos)
  1465. {
  1466. struct drm_device *dev = filp->private_data;
  1467. struct drm_i915_private *dev_priv = dev->dev_private;
  1468. char buf[20];
  1469. int val = 1, ret;
  1470. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1471. return -ENODEV;
  1472. if (cnt > 0) {
  1473. if (cnt > sizeof(buf) - 1)
  1474. return -EINVAL;
  1475. if (copy_from_user(buf, ubuf, cnt))
  1476. return -EFAULT;
  1477. buf[cnt] = 0;
  1478. val = simple_strtoul(buf, NULL, 0);
  1479. }
  1480. DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
  1481. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1482. if (ret)
  1483. return ret;
  1484. /*
  1485. * Turbo will still be enabled, but won't go above the set value.
  1486. */
  1487. dev_priv->rps.max_delay = val / 50;
  1488. gen6_set_rps(dev, val / 50);
  1489. mutex_unlock(&dev->struct_mutex);
  1490. return cnt;
  1491. }
  1492. static const struct file_operations i915_max_freq_fops = {
  1493. .owner = THIS_MODULE,
  1494. .open = simple_open,
  1495. .read = i915_max_freq_read,
  1496. .write = i915_max_freq_write,
  1497. .llseek = default_llseek,
  1498. };
  1499. static ssize_t
  1500. i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max,
  1501. loff_t *ppos)
  1502. {
  1503. struct drm_device *dev = filp->private_data;
  1504. drm_i915_private_t *dev_priv = dev->dev_private;
  1505. char buf[80];
  1506. int len, ret;
  1507. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1508. return -ENODEV;
  1509. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1510. if (ret)
  1511. return ret;
  1512. len = snprintf(buf, sizeof(buf),
  1513. "min freq: %d\n", dev_priv->rps.min_delay * 50);
  1514. mutex_unlock(&dev->struct_mutex);
  1515. if (len > sizeof(buf))
  1516. len = sizeof(buf);
  1517. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1518. }
  1519. static ssize_t
  1520. i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt,
  1521. loff_t *ppos)
  1522. {
  1523. struct drm_device *dev = filp->private_data;
  1524. struct drm_i915_private *dev_priv = dev->dev_private;
  1525. char buf[20];
  1526. int val = 1, ret;
  1527. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1528. return -ENODEV;
  1529. if (cnt > 0) {
  1530. if (cnt > sizeof(buf) - 1)
  1531. return -EINVAL;
  1532. if (copy_from_user(buf, ubuf, cnt))
  1533. return -EFAULT;
  1534. buf[cnt] = 0;
  1535. val = simple_strtoul(buf, NULL, 0);
  1536. }
  1537. DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val);
  1538. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1539. if (ret)
  1540. return ret;
  1541. /*
  1542. * Turbo will still be enabled, but won't go below the set value.
  1543. */
  1544. dev_priv->rps.min_delay = val / 50;
  1545. gen6_set_rps(dev, val / 50);
  1546. mutex_unlock(&dev->struct_mutex);
  1547. return cnt;
  1548. }
  1549. static const struct file_operations i915_min_freq_fops = {
  1550. .owner = THIS_MODULE,
  1551. .open = simple_open,
  1552. .read = i915_min_freq_read,
  1553. .write = i915_min_freq_write,
  1554. .llseek = default_llseek,
  1555. };
  1556. static ssize_t
  1557. i915_cache_sharing_read(struct file *filp,
  1558. char __user *ubuf,
  1559. size_t max,
  1560. loff_t *ppos)
  1561. {
  1562. struct drm_device *dev = filp->private_data;
  1563. drm_i915_private_t *dev_priv = dev->dev_private;
  1564. char buf[80];
  1565. u32 snpcr;
  1566. int len, ret;
  1567. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1568. return -ENODEV;
  1569. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1570. if (ret)
  1571. return ret;
  1572. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1573. mutex_unlock(&dev_priv->dev->struct_mutex);
  1574. len = snprintf(buf, sizeof(buf),
  1575. "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
  1576. GEN6_MBC_SNPCR_SHIFT);
  1577. if (len > sizeof(buf))
  1578. len = sizeof(buf);
  1579. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1580. }
  1581. static ssize_t
  1582. i915_cache_sharing_write(struct file *filp,
  1583. const char __user *ubuf,
  1584. size_t cnt,
  1585. loff_t *ppos)
  1586. {
  1587. struct drm_device *dev = filp->private_data;
  1588. struct drm_i915_private *dev_priv = dev->dev_private;
  1589. char buf[20];
  1590. u32 snpcr;
  1591. int val = 1;
  1592. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1593. return -ENODEV;
  1594. if (cnt > 0) {
  1595. if (cnt > sizeof(buf) - 1)
  1596. return -EINVAL;
  1597. if (copy_from_user(buf, ubuf, cnt))
  1598. return -EFAULT;
  1599. buf[cnt] = 0;
  1600. val = simple_strtoul(buf, NULL, 0);
  1601. }
  1602. if (val < 0 || val > 3)
  1603. return -EINVAL;
  1604. DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
  1605. /* Update the cache sharing policy here as well */
  1606. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1607. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  1608. snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
  1609. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  1610. return cnt;
  1611. }
  1612. static const struct file_operations i915_cache_sharing_fops = {
  1613. .owner = THIS_MODULE,
  1614. .open = simple_open,
  1615. .read = i915_cache_sharing_read,
  1616. .write = i915_cache_sharing_write,
  1617. .llseek = default_llseek,
  1618. };
  1619. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1620. * allocated we need to hook into the minor for release. */
  1621. static int
  1622. drm_add_fake_info_node(struct drm_minor *minor,
  1623. struct dentry *ent,
  1624. const void *key)
  1625. {
  1626. struct drm_info_node *node;
  1627. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1628. if (node == NULL) {
  1629. debugfs_remove(ent);
  1630. return -ENOMEM;
  1631. }
  1632. node->minor = minor;
  1633. node->dent = ent;
  1634. node->info_ent = (void *) key;
  1635. mutex_lock(&minor->debugfs_lock);
  1636. list_add(&node->list, &minor->debugfs_list);
  1637. mutex_unlock(&minor->debugfs_lock);
  1638. return 0;
  1639. }
  1640. static int i915_forcewake_open(struct inode *inode, struct file *file)
  1641. {
  1642. struct drm_device *dev = inode->i_private;
  1643. struct drm_i915_private *dev_priv = dev->dev_private;
  1644. int ret;
  1645. if (INTEL_INFO(dev)->gen < 6)
  1646. return 0;
  1647. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1648. if (ret)
  1649. return ret;
  1650. gen6_gt_force_wake_get(dev_priv);
  1651. mutex_unlock(&dev->struct_mutex);
  1652. return 0;
  1653. }
  1654. static int i915_forcewake_release(struct inode *inode, struct file *file)
  1655. {
  1656. struct drm_device *dev = inode->i_private;
  1657. struct drm_i915_private *dev_priv = dev->dev_private;
  1658. int ret;
  1659. if (INTEL_INFO(dev)->gen < 6)
  1660. return 0;
  1661. /*
  1662. * It's bad that we can potentially hang userspace if struct_mutex gets
  1663. * forever stuck. However, if we cannot acquire this lock it means that
  1664. * almost certainly the driver has hung, is not unload-able. Therefore
  1665. * hanging here is probably a minor inconvenience not to be seen my
  1666. * almost every user.
  1667. */
  1668. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1669. if (ret)
  1670. return ret;
  1671. gen6_gt_force_wake_put(dev_priv);
  1672. mutex_unlock(&dev->struct_mutex);
  1673. return 0;
  1674. }
  1675. static const struct file_operations i915_forcewake_fops = {
  1676. .owner = THIS_MODULE,
  1677. .open = i915_forcewake_open,
  1678. .release = i915_forcewake_release,
  1679. };
  1680. static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
  1681. {
  1682. struct drm_device *dev = minor->dev;
  1683. struct dentry *ent;
  1684. ent = debugfs_create_file("i915_forcewake_user",
  1685. S_IRUSR,
  1686. root, dev,
  1687. &i915_forcewake_fops);
  1688. if (IS_ERR(ent))
  1689. return PTR_ERR(ent);
  1690. return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
  1691. }
  1692. static int i915_debugfs_create(struct dentry *root,
  1693. struct drm_minor *minor,
  1694. const char *name,
  1695. const struct file_operations *fops)
  1696. {
  1697. struct drm_device *dev = minor->dev;
  1698. struct dentry *ent;
  1699. ent = debugfs_create_file(name,
  1700. S_IRUGO | S_IWUSR,
  1701. root, dev,
  1702. fops);
  1703. if (IS_ERR(ent))
  1704. return PTR_ERR(ent);
  1705. return drm_add_fake_info_node(minor, ent, fops);
  1706. }
  1707. static struct drm_info_list i915_debugfs_list[] = {
  1708. {"i915_capabilities", i915_capabilities, 0},
  1709. {"i915_gem_objects", i915_gem_object_info, 0},
  1710. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1711. {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
  1712. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1713. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1714. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1715. {"i915_gem_request", i915_gem_request_info, 0},
  1716. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1717. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1718. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1719. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1720. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1721. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1722. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1723. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1724. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1725. {"i915_inttoext_table", i915_inttoext_table, 0},
  1726. {"i915_drpc_info", i915_drpc_info, 0},
  1727. {"i915_emon_status", i915_emon_status, 0},
  1728. {"i915_ring_freq_table", i915_ring_freq_table, 0},
  1729. {"i915_gfxec", i915_gfxec, 0},
  1730. {"i915_fbc_status", i915_fbc_status, 0},
  1731. {"i915_sr_status", i915_sr_status, 0},
  1732. {"i915_opregion", i915_opregion, 0},
  1733. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1734. {"i915_context_status", i915_context_status, 0},
  1735. {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
  1736. {"i915_swizzle_info", i915_swizzle_info, 0},
  1737. {"i915_ppgtt_info", i915_ppgtt_info, 0},
  1738. {"i915_dpio", i915_dpio_info, 0},
  1739. };
  1740. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1741. int i915_debugfs_init(struct drm_minor *minor)
  1742. {
  1743. int ret;
  1744. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1745. "i915_wedged",
  1746. &i915_wedged_fops);
  1747. if (ret)
  1748. return ret;
  1749. ret = i915_forcewake_create(minor->debugfs_root, minor);
  1750. if (ret)
  1751. return ret;
  1752. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1753. "i915_max_freq",
  1754. &i915_max_freq_fops);
  1755. if (ret)
  1756. return ret;
  1757. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1758. "i915_min_freq",
  1759. &i915_min_freq_fops);
  1760. if (ret)
  1761. return ret;
  1762. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1763. "i915_cache_sharing",
  1764. &i915_cache_sharing_fops);
  1765. if (ret)
  1766. return ret;
  1767. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1768. "i915_ring_stop",
  1769. &i915_ring_stop_fops);
  1770. if (ret)
  1771. return ret;
  1772. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1773. "i915_error_state",
  1774. &i915_error_state_fops);
  1775. if (ret)
  1776. return ret;
  1777. return drm_debugfs_create_files(i915_debugfs_list,
  1778. I915_DEBUGFS_ENTRIES,
  1779. minor->debugfs_root, minor);
  1780. }
  1781. void i915_debugfs_cleanup(struct drm_minor *minor)
  1782. {
  1783. drm_debugfs_remove_files(i915_debugfs_list,
  1784. I915_DEBUGFS_ENTRIES, minor);
  1785. drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
  1786. 1, minor);
  1787. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1788. 1, minor);
  1789. drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
  1790. 1, minor);
  1791. drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
  1792. 1, minor);
  1793. drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
  1794. 1, minor);
  1795. drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
  1796. 1, minor);
  1797. drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
  1798. 1, minor);
  1799. }
  1800. #endif /* CONFIG_DEBUG_FS */