sun4m_smp.c 6.3 KB

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  1. /*
  2. * sun4m SMP support.
  3. *
  4. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  5. */
  6. #include <linux/clockchips.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/profile.h>
  9. #include <linux/delay.h>
  10. #include <linux/sched.h>
  11. #include <linux/cpu.h>
  12. #include <asm/cacheflush.h>
  13. #include <asm/switch_to.h>
  14. #include <asm/tlbflush.h>
  15. #include <asm/timer.h>
  16. #include <asm/oplib.h>
  17. #include "irq.h"
  18. #include "kernel.h"
  19. #define IRQ_IPI_SINGLE 12
  20. #define IRQ_IPI_MASK 13
  21. #define IRQ_IPI_RESCHED 14
  22. #define IRQ_CROSS_CALL 15
  23. static inline unsigned long
  24. swap_ulong(volatile unsigned long *ptr, unsigned long val)
  25. {
  26. __asm__ __volatile__("swap [%1], %0\n\t" :
  27. "=&r" (val), "=&r" (ptr) :
  28. "0" (val), "1" (ptr));
  29. return val;
  30. }
  31. static void smp4m_ipi_init(void);
  32. void __cpuinit smp4m_callin(void)
  33. {
  34. int cpuid = hard_smp_processor_id();
  35. local_ops->cache_all();
  36. local_ops->tlb_all();
  37. notify_cpu_starting(cpuid);
  38. register_percpu_ce(cpuid);
  39. calibrate_delay();
  40. smp_store_cpu_info(cpuid);
  41. local_ops->cache_all();
  42. local_ops->tlb_all();
  43. /*
  44. * Unblock the master CPU _only_ when the scheduler state
  45. * of all secondary CPUs will be up-to-date, so after
  46. * the SMP initialization the master will be just allowed
  47. * to call the scheduler code.
  48. */
  49. /* Allow master to continue. */
  50. swap_ulong(&cpu_callin_map[cpuid], 1);
  51. /* XXX: What's up with all the flushes? */
  52. local_ops->cache_all();
  53. local_ops->tlb_all();
  54. /* Fix idle thread fields. */
  55. __asm__ __volatile__("ld [%0], %%g6\n\t"
  56. : : "r" (&current_set[cpuid])
  57. : "memory" /* paranoid */);
  58. /* Attach to the address space of init_task. */
  59. atomic_inc(&init_mm.mm_count);
  60. current->active_mm = &init_mm;
  61. while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
  62. mb();
  63. local_irq_enable();
  64. set_cpu_online(cpuid, true);
  65. }
  66. /*
  67. * Cycle through the processors asking the PROM to start each one.
  68. */
  69. void __init smp4m_boot_cpus(void)
  70. {
  71. smp4m_ipi_init();
  72. sun4m_unmask_profile_irq();
  73. local_ops->cache_all();
  74. }
  75. int __cpuinit smp4m_boot_one_cpu(int i)
  76. {
  77. unsigned long *entry = &sun4m_cpu_startup;
  78. struct task_struct *p;
  79. int timeout;
  80. int cpu_node;
  81. cpu_find_by_mid(i, &cpu_node);
  82. /* Cook up an idler for this guy. */
  83. p = fork_idle(i);
  84. current_set[i] = task_thread_info(p);
  85. /* See trampoline.S for details... */
  86. entry += ((i - 1) * 3);
  87. /*
  88. * Initialize the contexts table
  89. * Since the call to prom_startcpu() trashes the structure,
  90. * we need to re-initialize it for each cpu
  91. */
  92. smp_penguin_ctable.which_io = 0;
  93. smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
  94. smp_penguin_ctable.reg_size = 0;
  95. /* whirrr, whirrr, whirrrrrrrrr... */
  96. printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
  97. local_ops->cache_all();
  98. prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
  99. /* wheee... it's going... */
  100. for (timeout = 0; timeout < 10000; timeout++) {
  101. if (cpu_callin_map[i])
  102. break;
  103. udelay(200);
  104. }
  105. if (!(cpu_callin_map[i])) {
  106. printk(KERN_ERR "Processor %d is stuck.\n", i);
  107. return -ENODEV;
  108. }
  109. local_ops->cache_all();
  110. return 0;
  111. }
  112. void __init smp4m_smp_done(void)
  113. {
  114. int i, first;
  115. int *prev;
  116. /* setup cpu list for irq rotation */
  117. first = 0;
  118. prev = &first;
  119. for_each_online_cpu(i) {
  120. *prev = i;
  121. prev = &cpu_data(i).next;
  122. }
  123. *prev = first;
  124. local_ops->cache_all();
  125. /* Ok, they are spinning and ready to go. */
  126. }
  127. /* Initialize IPIs on the SUN4M SMP machine */
  128. static void __init smp4m_ipi_init(void)
  129. {
  130. }
  131. static void smp4m_ipi_resched(int cpu)
  132. {
  133. set_cpu_int(cpu, IRQ_IPI_RESCHED);
  134. }
  135. static void smp4m_ipi_single(int cpu)
  136. {
  137. set_cpu_int(cpu, IRQ_IPI_SINGLE);
  138. }
  139. static void smp4m_ipi_mask_one(int cpu)
  140. {
  141. set_cpu_int(cpu, IRQ_IPI_MASK);
  142. }
  143. static struct smp_funcall {
  144. smpfunc_t func;
  145. unsigned long arg1;
  146. unsigned long arg2;
  147. unsigned long arg3;
  148. unsigned long arg4;
  149. unsigned long arg5;
  150. unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
  151. unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
  152. } ccall_info;
  153. static DEFINE_SPINLOCK(cross_call_lock);
  154. /* Cross calls must be serialized, at least currently. */
  155. static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
  156. unsigned long arg2, unsigned long arg3,
  157. unsigned long arg4)
  158. {
  159. register int ncpus = SUN4M_NCPUS;
  160. unsigned long flags;
  161. spin_lock_irqsave(&cross_call_lock, flags);
  162. /* Init function glue. */
  163. ccall_info.func = func;
  164. ccall_info.arg1 = arg1;
  165. ccall_info.arg2 = arg2;
  166. ccall_info.arg3 = arg3;
  167. ccall_info.arg4 = arg4;
  168. ccall_info.arg5 = 0;
  169. /* Init receive/complete mapping, plus fire the IPI's off. */
  170. {
  171. register int i;
  172. cpumask_clear_cpu(smp_processor_id(), &mask);
  173. cpumask_and(&mask, cpu_online_mask, &mask);
  174. for (i = 0; i < ncpus; i++) {
  175. if (cpumask_test_cpu(i, &mask)) {
  176. ccall_info.processors_in[i] = 0;
  177. ccall_info.processors_out[i] = 0;
  178. set_cpu_int(i, IRQ_CROSS_CALL);
  179. } else {
  180. ccall_info.processors_in[i] = 1;
  181. ccall_info.processors_out[i] = 1;
  182. }
  183. }
  184. }
  185. {
  186. register int i;
  187. i = 0;
  188. do {
  189. if (!cpumask_test_cpu(i, &mask))
  190. continue;
  191. while (!ccall_info.processors_in[i])
  192. barrier();
  193. } while (++i < ncpus);
  194. i = 0;
  195. do {
  196. if (!cpumask_test_cpu(i, &mask))
  197. continue;
  198. while (!ccall_info.processors_out[i])
  199. barrier();
  200. } while (++i < ncpus);
  201. }
  202. spin_unlock_irqrestore(&cross_call_lock, flags);
  203. }
  204. /* Running cross calls. */
  205. void smp4m_cross_call_irq(void)
  206. {
  207. int i = smp_processor_id();
  208. ccall_info.processors_in[i] = 1;
  209. ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
  210. ccall_info.arg4, ccall_info.arg5);
  211. ccall_info.processors_out[i] = 1;
  212. }
  213. void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
  214. {
  215. struct pt_regs *old_regs;
  216. struct clock_event_device *ce;
  217. int cpu = smp_processor_id();
  218. old_regs = set_irq_regs(regs);
  219. ce = &per_cpu(sparc32_clockevent, cpu);
  220. if (ce->mode & CLOCK_EVT_MODE_PERIODIC)
  221. sun4m_clear_profile_irq(cpu);
  222. else
  223. load_profile_irq(cpu, 0); /* Is this needless? */
  224. irq_enter();
  225. ce->event_handler(ce);
  226. irq_exit();
  227. set_irq_regs(old_regs);
  228. }
  229. void __init sun4m_init_smp(void)
  230. {
  231. BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
  232. BTFIXUPSET_CALL(smp_ipi_resched, smp4m_ipi_resched, BTFIXUPCALL_NORM);
  233. BTFIXUPSET_CALL(smp_ipi_single, smp4m_ipi_single, BTFIXUPCALL_NORM);
  234. BTFIXUPSET_CALL(smp_ipi_mask_one, smp4m_ipi_mask_one, BTFIXUPCALL_NORM);
  235. }