sun4d_smp.c 9.4 KB

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  1. /* Sparc SS1000/SC2000 SMP support.
  2. *
  3. * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  4. *
  5. * Based on sun4m's smp.c, which is:
  6. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  7. */
  8. #include <linux/clockchips.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/profile.h>
  11. #include <linux/delay.h>
  12. #include <linux/sched.h>
  13. #include <linux/cpu.h>
  14. #include <asm/cacheflush.h>
  15. #include <asm/switch_to.h>
  16. #include <asm/tlbflush.h>
  17. #include <asm/timer.h>
  18. #include <asm/oplib.h>
  19. #include <asm/sbi.h>
  20. #include <asm/mmu.h>
  21. #include "kernel.h"
  22. #include "irq.h"
  23. #define IRQ_CROSS_CALL 15
  24. static volatile int smp_processors_ready;
  25. static int smp_highest_cpu;
  26. static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
  27. {
  28. __asm__ __volatile__("swap [%1], %0\n\t" :
  29. "=&r" (val), "=&r" (ptr) :
  30. "0" (val), "1" (ptr));
  31. return val;
  32. }
  33. static void smp4d_ipi_init(void);
  34. static unsigned char cpu_leds[32];
  35. static inline void show_leds(int cpuid)
  36. {
  37. cpuid &= 0x1e;
  38. __asm__ __volatile__ ("stba %0, [%1] %2" : :
  39. "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
  40. "r" (ECSR_BASE(cpuid) | BB_LEDS),
  41. "i" (ASI_M_CTL));
  42. }
  43. void __cpuinit smp4d_callin(void)
  44. {
  45. int cpuid = hard_smp_processor_id();
  46. unsigned long flags;
  47. /* Show we are alive */
  48. cpu_leds[cpuid] = 0x6;
  49. show_leds(cpuid);
  50. /* Enable level15 interrupt, disable level14 interrupt for now */
  51. cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);
  52. local_ops->cache_all();
  53. local_ops->tlb_all();
  54. notify_cpu_starting(cpuid);
  55. /*
  56. * Unblock the master CPU _only_ when the scheduler state
  57. * of all secondary CPUs will be up-to-date, so after
  58. * the SMP initialization the master will be just allowed
  59. * to call the scheduler code.
  60. */
  61. /* Get our local ticker going. */
  62. register_percpu_ce(cpuid);
  63. calibrate_delay();
  64. smp_store_cpu_info(cpuid);
  65. local_ops->cache_all();
  66. local_ops->tlb_all();
  67. /* Allow master to continue. */
  68. sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
  69. local_ops->cache_all();
  70. local_ops->tlb_all();
  71. while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
  72. barrier();
  73. while (current_set[cpuid]->cpu != cpuid)
  74. barrier();
  75. /* Fix idle thread fields. */
  76. __asm__ __volatile__("ld [%0], %%g6\n\t"
  77. : : "r" (&current_set[cpuid])
  78. : "memory" /* paranoid */);
  79. cpu_leds[cpuid] = 0x9;
  80. show_leds(cpuid);
  81. /* Attach to the address space of init_task. */
  82. atomic_inc(&init_mm.mm_count);
  83. current->active_mm = &init_mm;
  84. local_ops->cache_all();
  85. local_ops->tlb_all();
  86. local_irq_enable(); /* We don't allow PIL 14 yet */
  87. while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
  88. barrier();
  89. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  90. cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
  91. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  92. set_cpu_online(cpuid, true);
  93. }
  94. /*
  95. * Cycle through the processors asking the PROM to start each one.
  96. */
  97. void __init smp4d_boot_cpus(void)
  98. {
  99. smp4d_ipi_init();
  100. if (boot_cpu_id)
  101. current_set[0] = NULL;
  102. local_ops->cache_all();
  103. }
  104. int __cpuinit smp4d_boot_one_cpu(int i)
  105. {
  106. unsigned long *entry = &sun4d_cpu_startup;
  107. struct task_struct *p;
  108. int timeout;
  109. int cpu_node;
  110. cpu_find_by_instance(i, &cpu_node, NULL);
  111. /* Cook up an idler for this guy. */
  112. p = fork_idle(i);
  113. current_set[i] = task_thread_info(p);
  114. /*
  115. * Initialize the contexts table
  116. * Since the call to prom_startcpu() trashes the structure,
  117. * we need to re-initialize it for each cpu
  118. */
  119. smp_penguin_ctable.which_io = 0;
  120. smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
  121. smp_penguin_ctable.reg_size = 0;
  122. /* whirrr, whirrr, whirrrrrrrrr... */
  123. printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
  124. local_ops->cache_all();
  125. prom_startcpu(cpu_node,
  126. &smp_penguin_ctable, 0, (char *)entry);
  127. printk(KERN_INFO "prom_startcpu returned :)\n");
  128. /* wheee... it's going... */
  129. for (timeout = 0; timeout < 10000; timeout++) {
  130. if (cpu_callin_map[i])
  131. break;
  132. udelay(200);
  133. }
  134. if (!(cpu_callin_map[i])) {
  135. printk(KERN_ERR "Processor %d is stuck.\n", i);
  136. return -ENODEV;
  137. }
  138. local_ops->cache_all();
  139. return 0;
  140. }
  141. void __init smp4d_smp_done(void)
  142. {
  143. int i, first;
  144. int *prev;
  145. /* setup cpu list for irq rotation */
  146. first = 0;
  147. prev = &first;
  148. for_each_online_cpu(i) {
  149. *prev = i;
  150. prev = &cpu_data(i).next;
  151. }
  152. *prev = first;
  153. local_ops->cache_all();
  154. /* Ok, they are spinning and ready to go. */
  155. smp_processors_ready = 1;
  156. sun4d_distribute_irqs();
  157. }
  158. /* Memory structure giving interrupt handler information about IPI generated */
  159. struct sun4d_ipi_work {
  160. int single;
  161. int msk;
  162. int resched;
  163. };
  164. static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);
  165. /* Initialize IPIs on the SUN4D SMP machine */
  166. static void __init smp4d_ipi_init(void)
  167. {
  168. int cpu;
  169. struct sun4d_ipi_work *work;
  170. printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);
  171. for_each_possible_cpu(cpu) {
  172. work = &per_cpu(sun4d_ipi_work, cpu);
  173. work->single = work->msk = work->resched = 0;
  174. }
  175. }
  176. void sun4d_ipi_interrupt(void)
  177. {
  178. struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work);
  179. if (work->single) {
  180. work->single = 0;
  181. smp_call_function_single_interrupt();
  182. }
  183. if (work->msk) {
  184. work->msk = 0;
  185. smp_call_function_interrupt();
  186. }
  187. if (work->resched) {
  188. work->resched = 0;
  189. smp_resched_interrupt();
  190. }
  191. }
  192. static void smp4d_ipi_single(int cpu)
  193. {
  194. struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
  195. /* Mark work */
  196. work->single = 1;
  197. /* Generate IRQ on the CPU */
  198. sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
  199. }
  200. static void smp4d_ipi_mask_one(int cpu)
  201. {
  202. struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
  203. /* Mark work */
  204. work->msk = 1;
  205. /* Generate IRQ on the CPU */
  206. sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
  207. }
  208. static void smp4d_ipi_resched(int cpu)
  209. {
  210. struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
  211. /* Mark work */
  212. work->resched = 1;
  213. /* Generate IRQ on the CPU (any IRQ will cause resched) */
  214. sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
  215. }
  216. static struct smp_funcall {
  217. smpfunc_t func;
  218. unsigned long arg1;
  219. unsigned long arg2;
  220. unsigned long arg3;
  221. unsigned long arg4;
  222. unsigned long arg5;
  223. unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
  224. unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
  225. } ccall_info __attribute__((aligned(8)));
  226. static DEFINE_SPINLOCK(cross_call_lock);
  227. /* Cross calls must be serialized, at least currently. */
  228. static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
  229. unsigned long arg2, unsigned long arg3,
  230. unsigned long arg4)
  231. {
  232. if (smp_processors_ready) {
  233. register int high = smp_highest_cpu;
  234. unsigned long flags;
  235. spin_lock_irqsave(&cross_call_lock, flags);
  236. {
  237. /*
  238. * If you make changes here, make sure
  239. * gcc generates proper code...
  240. */
  241. register smpfunc_t f asm("i0") = func;
  242. register unsigned long a1 asm("i1") = arg1;
  243. register unsigned long a2 asm("i2") = arg2;
  244. register unsigned long a3 asm("i3") = arg3;
  245. register unsigned long a4 asm("i4") = arg4;
  246. register unsigned long a5 asm("i5") = 0;
  247. __asm__ __volatile__(
  248. "std %0, [%6]\n\t"
  249. "std %2, [%6 + 8]\n\t"
  250. "std %4, [%6 + 16]\n\t" : :
  251. "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
  252. "r" (&ccall_info.func));
  253. }
  254. /* Init receive/complete mapping, plus fire the IPI's off. */
  255. {
  256. register int i;
  257. cpumask_clear_cpu(smp_processor_id(), &mask);
  258. cpumask_and(&mask, cpu_online_mask, &mask);
  259. for (i = 0; i <= high; i++) {
  260. if (cpumask_test_cpu(i, &mask)) {
  261. ccall_info.processors_in[i] = 0;
  262. ccall_info.processors_out[i] = 0;
  263. sun4d_send_ipi(i, IRQ_CROSS_CALL);
  264. }
  265. }
  266. }
  267. {
  268. register int i;
  269. i = 0;
  270. do {
  271. if (!cpumask_test_cpu(i, &mask))
  272. continue;
  273. while (!ccall_info.processors_in[i])
  274. barrier();
  275. } while (++i <= high);
  276. i = 0;
  277. do {
  278. if (!cpumask_test_cpu(i, &mask))
  279. continue;
  280. while (!ccall_info.processors_out[i])
  281. barrier();
  282. } while (++i <= high);
  283. }
  284. spin_unlock_irqrestore(&cross_call_lock, flags);
  285. }
  286. }
  287. /* Running cross calls. */
  288. void smp4d_cross_call_irq(void)
  289. {
  290. int i = hard_smp_processor_id();
  291. ccall_info.processors_in[i] = 1;
  292. ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
  293. ccall_info.arg4, ccall_info.arg5);
  294. ccall_info.processors_out[i] = 1;
  295. }
  296. void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
  297. {
  298. struct pt_regs *old_regs;
  299. int cpu = hard_smp_processor_id();
  300. struct clock_event_device *ce;
  301. static int cpu_tick[NR_CPUS];
  302. static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
  303. old_regs = set_irq_regs(regs);
  304. bw_get_prof_limit(cpu);
  305. bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
  306. cpu_tick[cpu]++;
  307. if (!(cpu_tick[cpu] & 15)) {
  308. if (cpu_tick[cpu] == 0x60)
  309. cpu_tick[cpu] = 0;
  310. cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
  311. show_leds(cpu);
  312. }
  313. ce = &per_cpu(sparc32_clockevent, cpu);
  314. irq_enter();
  315. ce->event_handler(ce);
  316. irq_exit();
  317. set_irq_regs(old_regs);
  318. }
  319. void __init sun4d_init_smp(void)
  320. {
  321. int i;
  322. /* Patch ipi15 trap table */
  323. t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
  324. /* And set btfixup... */
  325. BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
  326. BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM);
  327. BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM);
  328. BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM);
  329. for (i = 0; i < NR_CPUS; i++) {
  330. ccall_info.processors_in[i] = 1;
  331. ccall_info.processors_out[i] = 1;
  332. }
  333. }