at91rm9200.c 9.8 KB

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  1. /*
  2. * arch/arm/mach-at91/at91rm9200.c
  3. *
  4. * Copyright (C) 2005 SAN People
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. */
  12. #include <linux/module.h>
  13. #include <asm/irq.h>
  14. #include <asm/mach/arch.h>
  15. #include <asm/mach/map.h>
  16. #include <asm/system_misc.h>
  17. #include <mach/at91rm9200.h>
  18. #include <mach/at91_pmc.h>
  19. #include <mach/at91_st.h>
  20. #include <mach/cpu.h>
  21. #include "soc.h"
  22. #include "generic.h"
  23. #include "clock.h"
  24. #include "sam9_smc.h"
  25. /* --------------------------------------------------------------------
  26. * Clocks
  27. * -------------------------------------------------------------------- */
  28. /*
  29. * The peripheral clocks.
  30. */
  31. static struct clk udc_clk = {
  32. .name = "udc_clk",
  33. .pmc_mask = 1 << AT91RM9200_ID_UDP,
  34. .type = CLK_TYPE_PERIPHERAL,
  35. };
  36. static struct clk ohci_clk = {
  37. .name = "ohci_clk",
  38. .pmc_mask = 1 << AT91RM9200_ID_UHP,
  39. .type = CLK_TYPE_PERIPHERAL,
  40. };
  41. static struct clk ether_clk = {
  42. .name = "ether_clk",
  43. .pmc_mask = 1 << AT91RM9200_ID_EMAC,
  44. .type = CLK_TYPE_PERIPHERAL,
  45. };
  46. static struct clk mmc_clk = {
  47. .name = "mci_clk",
  48. .pmc_mask = 1 << AT91RM9200_ID_MCI,
  49. .type = CLK_TYPE_PERIPHERAL,
  50. };
  51. static struct clk twi_clk = {
  52. .name = "twi_clk",
  53. .pmc_mask = 1 << AT91RM9200_ID_TWI,
  54. .type = CLK_TYPE_PERIPHERAL,
  55. };
  56. static struct clk usart0_clk = {
  57. .name = "usart0_clk",
  58. .pmc_mask = 1 << AT91RM9200_ID_US0,
  59. .type = CLK_TYPE_PERIPHERAL,
  60. };
  61. static struct clk usart1_clk = {
  62. .name = "usart1_clk",
  63. .pmc_mask = 1 << AT91RM9200_ID_US1,
  64. .type = CLK_TYPE_PERIPHERAL,
  65. };
  66. static struct clk usart2_clk = {
  67. .name = "usart2_clk",
  68. .pmc_mask = 1 << AT91RM9200_ID_US2,
  69. .type = CLK_TYPE_PERIPHERAL,
  70. };
  71. static struct clk usart3_clk = {
  72. .name = "usart3_clk",
  73. .pmc_mask = 1 << AT91RM9200_ID_US3,
  74. .type = CLK_TYPE_PERIPHERAL,
  75. };
  76. static struct clk spi_clk = {
  77. .name = "spi_clk",
  78. .pmc_mask = 1 << AT91RM9200_ID_SPI,
  79. .type = CLK_TYPE_PERIPHERAL,
  80. };
  81. static struct clk pioA_clk = {
  82. .name = "pioA_clk",
  83. .pmc_mask = 1 << AT91RM9200_ID_PIOA,
  84. .type = CLK_TYPE_PERIPHERAL,
  85. };
  86. static struct clk pioB_clk = {
  87. .name = "pioB_clk",
  88. .pmc_mask = 1 << AT91RM9200_ID_PIOB,
  89. .type = CLK_TYPE_PERIPHERAL,
  90. };
  91. static struct clk pioC_clk = {
  92. .name = "pioC_clk",
  93. .pmc_mask = 1 << AT91RM9200_ID_PIOC,
  94. .type = CLK_TYPE_PERIPHERAL,
  95. };
  96. static struct clk pioD_clk = {
  97. .name = "pioD_clk",
  98. .pmc_mask = 1 << AT91RM9200_ID_PIOD,
  99. .type = CLK_TYPE_PERIPHERAL,
  100. };
  101. static struct clk ssc0_clk = {
  102. .name = "ssc0_clk",
  103. .pmc_mask = 1 << AT91RM9200_ID_SSC0,
  104. .type = CLK_TYPE_PERIPHERAL,
  105. };
  106. static struct clk ssc1_clk = {
  107. .name = "ssc1_clk",
  108. .pmc_mask = 1 << AT91RM9200_ID_SSC1,
  109. .type = CLK_TYPE_PERIPHERAL,
  110. };
  111. static struct clk ssc2_clk = {
  112. .name = "ssc2_clk",
  113. .pmc_mask = 1 << AT91RM9200_ID_SSC2,
  114. .type = CLK_TYPE_PERIPHERAL,
  115. };
  116. static struct clk tc0_clk = {
  117. .name = "tc0_clk",
  118. .pmc_mask = 1 << AT91RM9200_ID_TC0,
  119. .type = CLK_TYPE_PERIPHERAL,
  120. };
  121. static struct clk tc1_clk = {
  122. .name = "tc1_clk",
  123. .pmc_mask = 1 << AT91RM9200_ID_TC1,
  124. .type = CLK_TYPE_PERIPHERAL,
  125. };
  126. static struct clk tc2_clk = {
  127. .name = "tc2_clk",
  128. .pmc_mask = 1 << AT91RM9200_ID_TC2,
  129. .type = CLK_TYPE_PERIPHERAL,
  130. };
  131. static struct clk tc3_clk = {
  132. .name = "tc3_clk",
  133. .pmc_mask = 1 << AT91RM9200_ID_TC3,
  134. .type = CLK_TYPE_PERIPHERAL,
  135. };
  136. static struct clk tc4_clk = {
  137. .name = "tc4_clk",
  138. .pmc_mask = 1 << AT91RM9200_ID_TC4,
  139. .type = CLK_TYPE_PERIPHERAL,
  140. };
  141. static struct clk tc5_clk = {
  142. .name = "tc5_clk",
  143. .pmc_mask = 1 << AT91RM9200_ID_TC5,
  144. .type = CLK_TYPE_PERIPHERAL,
  145. };
  146. static struct clk *periph_clocks[] __initdata = {
  147. &pioA_clk,
  148. &pioB_clk,
  149. &pioC_clk,
  150. &pioD_clk,
  151. &usart0_clk,
  152. &usart1_clk,
  153. &usart2_clk,
  154. &usart3_clk,
  155. &mmc_clk,
  156. &udc_clk,
  157. &twi_clk,
  158. &spi_clk,
  159. &ssc0_clk,
  160. &ssc1_clk,
  161. &ssc2_clk,
  162. &tc0_clk,
  163. &tc1_clk,
  164. &tc2_clk,
  165. &tc3_clk,
  166. &tc4_clk,
  167. &tc5_clk,
  168. &ohci_clk,
  169. &ether_clk,
  170. // irq0 .. irq6
  171. };
  172. static struct clk_lookup periph_clocks_lookups[] = {
  173. CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
  174. CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
  175. CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
  176. CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
  177. CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
  178. CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
  179. CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
  180. CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
  181. CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
  182. /* fake hclk clock */
  183. CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
  184. CLKDEV_CON_ID("pioA", &pioA_clk),
  185. CLKDEV_CON_ID("pioB", &pioB_clk),
  186. CLKDEV_CON_ID("pioC", &pioC_clk),
  187. CLKDEV_CON_ID("pioD", &pioD_clk),
  188. };
  189. static struct clk_lookup usart_clocks_lookups[] = {
  190. CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
  191. CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
  192. CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
  193. CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
  194. CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
  195. };
  196. /*
  197. * The four programmable clocks.
  198. * You must configure pin multiplexing to bring these signals out.
  199. */
  200. static struct clk pck0 = {
  201. .name = "pck0",
  202. .pmc_mask = AT91_PMC_PCK0,
  203. .type = CLK_TYPE_PROGRAMMABLE,
  204. .id = 0,
  205. };
  206. static struct clk pck1 = {
  207. .name = "pck1",
  208. .pmc_mask = AT91_PMC_PCK1,
  209. .type = CLK_TYPE_PROGRAMMABLE,
  210. .id = 1,
  211. };
  212. static struct clk pck2 = {
  213. .name = "pck2",
  214. .pmc_mask = AT91_PMC_PCK2,
  215. .type = CLK_TYPE_PROGRAMMABLE,
  216. .id = 2,
  217. };
  218. static struct clk pck3 = {
  219. .name = "pck3",
  220. .pmc_mask = AT91_PMC_PCK3,
  221. .type = CLK_TYPE_PROGRAMMABLE,
  222. .id = 3,
  223. };
  224. static void __init at91rm9200_register_clocks(void)
  225. {
  226. int i;
  227. for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
  228. clk_register(periph_clocks[i]);
  229. clkdev_add_table(periph_clocks_lookups,
  230. ARRAY_SIZE(periph_clocks_lookups));
  231. clkdev_add_table(usart_clocks_lookups,
  232. ARRAY_SIZE(usart_clocks_lookups));
  233. clk_register(&pck0);
  234. clk_register(&pck1);
  235. clk_register(&pck2);
  236. clk_register(&pck3);
  237. }
  238. static struct clk_lookup console_clock_lookup;
  239. void __init at91rm9200_set_console_clock(int id)
  240. {
  241. if (id >= ARRAY_SIZE(usart_clocks_lookups))
  242. return;
  243. console_clock_lookup.con_id = "usart";
  244. console_clock_lookup.clk = usart_clocks_lookups[id].clk;
  245. clkdev_add(&console_clock_lookup);
  246. }
  247. /* --------------------------------------------------------------------
  248. * GPIO
  249. * -------------------------------------------------------------------- */
  250. static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
  251. {
  252. .id = AT91RM9200_ID_PIOA,
  253. .regbase = AT91RM9200_BASE_PIOA,
  254. }, {
  255. .id = AT91RM9200_ID_PIOB,
  256. .regbase = AT91RM9200_BASE_PIOB,
  257. }, {
  258. .id = AT91RM9200_ID_PIOC,
  259. .regbase = AT91RM9200_BASE_PIOC,
  260. }, {
  261. .id = AT91RM9200_ID_PIOD,
  262. .regbase = AT91RM9200_BASE_PIOD,
  263. }
  264. };
  265. static void at91rm9200_idle(void)
  266. {
  267. /*
  268. * Disable the processor clock. The processor will be automatically
  269. * re-enabled by an interrupt or by a reset.
  270. */
  271. at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
  272. }
  273. static void at91rm9200_restart(char mode, const char *cmd)
  274. {
  275. /*
  276. * Perform a hardware reset with the use of the Watchdog timer.
  277. */
  278. at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
  279. at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
  280. }
  281. /* --------------------------------------------------------------------
  282. * AT91RM9200 processor initialization
  283. * -------------------------------------------------------------------- */
  284. static void __init at91rm9200_map_io(void)
  285. {
  286. /* Map peripherals */
  287. at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
  288. }
  289. static void __init at91rm9200_ioremap_registers(void)
  290. {
  291. at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
  292. at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
  293. }
  294. static void __init at91rm9200_initialize(void)
  295. {
  296. arm_pm_idle = at91rm9200_idle;
  297. arm_pm_restart = at91rm9200_restart;
  298. at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
  299. | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
  300. | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
  301. | (1 << AT91RM9200_ID_IRQ6);
  302. /* Initialize GPIO subsystem */
  303. at91_gpio_init(at91rm9200_gpio,
  304. cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
  305. }
  306. /* --------------------------------------------------------------------
  307. * Interrupt initialization
  308. * -------------------------------------------------------------------- */
  309. /*
  310. * The default interrupt priority levels (0 = lowest, 7 = highest).
  311. */
  312. static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
  313. 7, /* Advanced Interrupt Controller (FIQ) */
  314. 7, /* System Peripherals */
  315. 1, /* Parallel IO Controller A */
  316. 1, /* Parallel IO Controller B */
  317. 1, /* Parallel IO Controller C */
  318. 1, /* Parallel IO Controller D */
  319. 5, /* USART 0 */
  320. 5, /* USART 1 */
  321. 5, /* USART 2 */
  322. 5, /* USART 3 */
  323. 0, /* Multimedia Card Interface */
  324. 2, /* USB Device Port */
  325. 6, /* Two-Wire Interface */
  326. 5, /* Serial Peripheral Interface */
  327. 4, /* Serial Synchronous Controller 0 */
  328. 4, /* Serial Synchronous Controller 1 */
  329. 4, /* Serial Synchronous Controller 2 */
  330. 0, /* Timer Counter 0 */
  331. 0, /* Timer Counter 1 */
  332. 0, /* Timer Counter 2 */
  333. 0, /* Timer Counter 3 */
  334. 0, /* Timer Counter 4 */
  335. 0, /* Timer Counter 5 */
  336. 2, /* USB Host port */
  337. 3, /* Ethernet MAC */
  338. 0, /* Advanced Interrupt Controller (IRQ0) */
  339. 0, /* Advanced Interrupt Controller (IRQ1) */
  340. 0, /* Advanced Interrupt Controller (IRQ2) */
  341. 0, /* Advanced Interrupt Controller (IRQ3) */
  342. 0, /* Advanced Interrupt Controller (IRQ4) */
  343. 0, /* Advanced Interrupt Controller (IRQ5) */
  344. 0 /* Advanced Interrupt Controller (IRQ6) */
  345. };
  346. struct at91_init_soc __initdata at91rm9200_soc = {
  347. .map_io = at91rm9200_map_io,
  348. .default_irq_priority = at91rm9200_default_irq_priority,
  349. .ioremap_registers = at91rm9200_ioremap_registers,
  350. .register_clocks = at91rm9200_register_clocks,
  351. .init = at91rm9200_initialize,
  352. };