devices.c 8.2 KB

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  1. /*
  2. * Author: MontaVista Software, Inc.
  3. * <source@mvista.com>
  4. *
  5. * Based on the OMAP devices.c
  6. *
  7. * 2005 (c) MontaVista Software, Inc. This file is licensed under the
  8. * terms of the GNU General Public License version 2. This program is
  9. * licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. *
  12. * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  13. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License
  17. * as published by the Free Software Foundation; either version 2
  18. * of the License, or (at your option) any later version.
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  27. * MA 02110-1301, USA.
  28. */
  29. #include <linux/module.h>
  30. #include <linux/kernel.h>
  31. #include <linux/init.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/gpio.h>
  34. #include <mach/irqs.h>
  35. #include <mach/hardware.h>
  36. #include <mach/common.h>
  37. #include "devices.h"
  38. /*
  39. * Resource definition for the MXC IrDA
  40. */
  41. static struct resource mxc_irda_resources[] = {
  42. [0] = {
  43. .start = UART3_BASE_ADDR,
  44. .end = UART3_BASE_ADDR + SZ_4K - 1,
  45. .flags = IORESOURCE_MEM,
  46. },
  47. [1] = {
  48. .start = MXC_INT_UART3,
  49. .end = MXC_INT_UART3,
  50. .flags = IORESOURCE_IRQ,
  51. },
  52. };
  53. /* Platform Data for MXC IrDA */
  54. struct platform_device mxc_irda_device = {
  55. .name = "mxc_irda",
  56. .id = 0,
  57. .num_resources = ARRAY_SIZE(mxc_irda_resources),
  58. .resource = mxc_irda_resources,
  59. };
  60. /*
  61. * General Purpose Timer
  62. * - i.MX1: 2 timer (slighly different register handling)
  63. * - i.MX21: 3 timer
  64. * - i.MX27: 6 timer
  65. */
  66. /* We use gpt0 as system timer, so do not add a device for this one */
  67. static struct resource timer1_resources[] = {
  68. [0] = {
  69. .start = GPT2_BASE_ADDR,
  70. .end = GPT2_BASE_ADDR + 0x17,
  71. .flags = IORESOURCE_MEM
  72. },
  73. [1] = {
  74. .start = MXC_INT_GPT2,
  75. .end = MXC_INT_GPT2,
  76. .flags = IORESOURCE_IRQ,
  77. }
  78. };
  79. struct platform_device mxc_gpt1 = {
  80. .name = "imx_gpt",
  81. .id = 1,
  82. .num_resources = ARRAY_SIZE(timer1_resources),
  83. .resource = timer1_resources
  84. };
  85. static struct resource timer2_resources[] = {
  86. [0] = {
  87. .start = GPT3_BASE_ADDR,
  88. .end = GPT3_BASE_ADDR + 0x17,
  89. .flags = IORESOURCE_MEM
  90. },
  91. [1] = {
  92. .start = MXC_INT_GPT3,
  93. .end = MXC_INT_GPT3,
  94. .flags = IORESOURCE_IRQ,
  95. }
  96. };
  97. struct platform_device mxc_gpt2 = {
  98. .name = "imx_gpt",
  99. .id = 2,
  100. .num_resources = ARRAY_SIZE(timer2_resources),
  101. .resource = timer2_resources
  102. };
  103. #ifdef CONFIG_MACH_MX27
  104. static struct resource timer3_resources[] = {
  105. [0] = {
  106. .start = GPT4_BASE_ADDR,
  107. .end = GPT4_BASE_ADDR + 0x17,
  108. .flags = IORESOURCE_MEM
  109. },
  110. [1] = {
  111. .start = MXC_INT_GPT4,
  112. .end = MXC_INT_GPT4,
  113. .flags = IORESOURCE_IRQ,
  114. }
  115. };
  116. struct platform_device mxc_gpt3 = {
  117. .name = "imx_gpt",
  118. .id = 3,
  119. .num_resources = ARRAY_SIZE(timer3_resources),
  120. .resource = timer3_resources
  121. };
  122. static struct resource timer4_resources[] = {
  123. [0] = {
  124. .start = GPT5_BASE_ADDR,
  125. .end = GPT5_BASE_ADDR + 0x17,
  126. .flags = IORESOURCE_MEM
  127. },
  128. [1] = {
  129. .start = MXC_INT_GPT5,
  130. .end = MXC_INT_GPT5,
  131. .flags = IORESOURCE_IRQ,
  132. }
  133. };
  134. struct platform_device mxc_gpt4 = {
  135. .name = "imx_gpt",
  136. .id = 4,
  137. .num_resources = ARRAY_SIZE(timer4_resources),
  138. .resource = timer4_resources
  139. };
  140. static struct resource timer5_resources[] = {
  141. [0] = {
  142. .start = GPT6_BASE_ADDR,
  143. .end = GPT6_BASE_ADDR + 0x17,
  144. .flags = IORESOURCE_MEM
  145. },
  146. [1] = {
  147. .start = MXC_INT_GPT6,
  148. .end = MXC_INT_GPT6,
  149. .flags = IORESOURCE_IRQ,
  150. }
  151. };
  152. struct platform_device mxc_gpt5 = {
  153. .name = "imx_gpt",
  154. .id = 5,
  155. .num_resources = ARRAY_SIZE(timer5_resources),
  156. .resource = timer5_resources
  157. };
  158. #endif
  159. /*
  160. * Watchdog:
  161. * - i.MX1
  162. * - i.MX21
  163. * - i.MX27
  164. */
  165. static struct resource mxc_wdt_resources[] = {
  166. {
  167. .start = WDOG_BASE_ADDR,
  168. .end = WDOG_BASE_ADDR + 0x30,
  169. .flags = IORESOURCE_MEM,
  170. },
  171. };
  172. struct platform_device mxc_wdt = {
  173. .name = "mxc_wdt",
  174. .id = 0,
  175. .num_resources = ARRAY_SIZE(mxc_wdt_resources),
  176. .resource = mxc_wdt_resources,
  177. };
  178. static struct resource mxc_w1_master_resources[] = {
  179. {
  180. .start = OWIRE_BASE_ADDR,
  181. .end = OWIRE_BASE_ADDR + SZ_4K - 1,
  182. .flags = IORESOURCE_MEM,
  183. },
  184. };
  185. struct platform_device mxc_w1_master_device = {
  186. .name = "mxc_w1",
  187. .id = 0,
  188. .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
  189. .resource = mxc_w1_master_resources,
  190. };
  191. static struct resource mxc_nand_resources[] = {
  192. {
  193. .start = NFC_BASE_ADDR,
  194. .end = NFC_BASE_ADDR + 0xfff,
  195. .flags = IORESOURCE_MEM
  196. }, {
  197. .start = MXC_INT_NANDFC,
  198. .end = MXC_INT_NANDFC,
  199. .flags = IORESOURCE_IRQ
  200. },
  201. };
  202. struct platform_device mxc_nand_device = {
  203. .name = "mxc_nand",
  204. .id = 0,
  205. .num_resources = ARRAY_SIZE(mxc_nand_resources),
  206. .resource = mxc_nand_resources,
  207. };
  208. #ifdef CONFIG_FB_IMX
  209. /*
  210. * lcdc:
  211. * - i.MX1: the basic controller
  212. * - i.MX21: to be checked
  213. * - i.MX27: like i.MX1, with slightly variations
  214. */
  215. static struct resource mxc_fb[] = {
  216. {
  217. .start = LCDC_BASE_ADDR,
  218. .end = LCDC_BASE_ADDR + 0xFFF,
  219. .flags = IORESOURCE_MEM,
  220. },
  221. {
  222. .start = MXC_INT_LCDC,
  223. .end = MXC_INT_LCDC,
  224. .flags = IORESOURCE_IRQ,
  225. }
  226. };
  227. /* mxc lcd driver */
  228. struct platform_device mxc_fb_device = {
  229. .name = "imx-fb",
  230. .id = 0,
  231. .num_resources = ARRAY_SIZE(mxc_fb),
  232. .resource = mxc_fb,
  233. .dev = {
  234. .coherent_dma_mask = 0xFFFFFFFF,
  235. },
  236. };
  237. #endif
  238. #ifdef CONFIG_MACH_MX27
  239. static struct resource mxc_fec_resources[] = {
  240. {
  241. .start = FEC_BASE_ADDR,
  242. .end = FEC_BASE_ADDR + 0xfff,
  243. .flags = IORESOURCE_MEM
  244. }, {
  245. .start = MXC_INT_FEC,
  246. .end = MXC_INT_FEC,
  247. .flags = IORESOURCE_IRQ
  248. },
  249. };
  250. struct platform_device mxc_fec_device = {
  251. .name = "fec",
  252. .id = 0,
  253. .num_resources = ARRAY_SIZE(mxc_fec_resources),
  254. .resource = mxc_fec_resources,
  255. };
  256. #endif
  257. static struct resource mxc_i2c_1_resources[] = {
  258. [0] = {
  259. .start = I2C_BASE_ADDR,
  260. .end = I2C_BASE_ADDR + 0x0fff,
  261. .flags = IORESOURCE_MEM
  262. },
  263. [1] = {
  264. .start = MXC_INT_I2C,
  265. .end = MXC_INT_I2C,
  266. .flags = IORESOURCE_IRQ
  267. }
  268. };
  269. struct platform_device mxc_i2c_device0 = {
  270. .name = "imx-i2c",
  271. .id = 0,
  272. .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
  273. .resource = mxc_i2c_1_resources
  274. };
  275. #ifdef CONFIG_MACH_MX27
  276. static struct resource mxc_i2c_2_resources[] = {
  277. [0] = {
  278. .start = I2C2_BASE_ADDR,
  279. .end = I2C2_BASE_ADDR + 0x0fff,
  280. .flags = IORESOURCE_MEM
  281. },
  282. [1] = {
  283. .start = MXC_INT_I2C2,
  284. .end = MXC_INT_I2C2,
  285. .flags = IORESOURCE_IRQ
  286. }
  287. };
  288. struct platform_device mxc_i2c_device1 = {
  289. .name = "imx-i2c",
  290. .id = 1,
  291. .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
  292. .resource = mxc_i2c_2_resources
  293. };
  294. #endif
  295. static struct resource mxc_pwm_resources[] = {
  296. [0] = {
  297. .start = PWM_BASE_ADDR,
  298. .end = PWM_BASE_ADDR + 0x0fff,
  299. .flags = IORESOURCE_MEM
  300. },
  301. [1] = {
  302. .start = MXC_INT_PWM,
  303. .end = MXC_INT_PWM,
  304. .flags = IORESOURCE_IRQ,
  305. }
  306. };
  307. struct platform_device mxc_pwm_device = {
  308. .name = "mxc_pwm",
  309. .id = 0,
  310. .num_resources = ARRAY_SIZE(mxc_pwm_resources),
  311. .resource = mxc_pwm_resources
  312. };
  313. /* GPIO port description */
  314. static struct mxc_gpio_port imx_gpio_ports[] = {
  315. [0] = {
  316. .chip.label = "gpio-0",
  317. .irq = MXC_INT_GPIO,
  318. .base = IO_ADDRESS(GPIO_BASE_ADDR),
  319. .virtual_irq_start = MXC_GPIO_IRQ_START,
  320. },
  321. [1] = {
  322. .chip.label = "gpio-1",
  323. .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
  324. .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
  325. },
  326. [2] = {
  327. .chip.label = "gpio-2",
  328. .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
  329. .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
  330. },
  331. [3] = {
  332. .chip.label = "gpio-3",
  333. .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
  334. .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
  335. },
  336. [4] = {
  337. .chip.label = "gpio-4",
  338. .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
  339. .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
  340. },
  341. [5] = {
  342. .chip.label = "gpio-5",
  343. .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
  344. .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
  345. }
  346. };
  347. int __init mxc_register_gpios(void)
  348. {
  349. return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
  350. }