langwell_udc.c 80 KB

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  1. /*
  2. * Intel Langwell USB Device Controller driver
  3. * Copyright (C) 2008-2009, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. */
  19. /* #undef DEBUG */
  20. /* #undef VERBOSE */
  21. #if defined(CONFIG_USB_LANGWELL_OTG)
  22. #define OTG_TRANSCEIVER
  23. #endif
  24. #include <linux/module.h>
  25. #include <linux/pci.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/kernel.h>
  28. #include <linux/delay.h>
  29. #include <linux/ioport.h>
  30. #include <linux/sched.h>
  31. #include <linux/slab.h>
  32. #include <linux/smp_lock.h>
  33. #include <linux/errno.h>
  34. #include <linux/init.h>
  35. #include <linux/timer.h>
  36. #include <linux/list.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/moduleparam.h>
  39. #include <linux/device.h>
  40. #include <linux/usb/ch9.h>
  41. #include <linux/usb/gadget.h>
  42. #include <linux/usb/otg.h>
  43. #include <linux/pm.h>
  44. #include <linux/io.h>
  45. #include <linux/irq.h>
  46. #include <asm/system.h>
  47. #include <asm/unaligned.h>
  48. #include "langwell_udc.h"
  49. #define DRIVER_DESC "Intel Langwell USB Device Controller driver"
  50. #define DRIVER_VERSION "16 May 2009"
  51. static const char driver_name[] = "langwell_udc";
  52. static const char driver_desc[] = DRIVER_DESC;
  53. /* controller device global variable */
  54. static struct langwell_udc *the_controller;
  55. /* for endpoint 0 operations */
  56. static const struct usb_endpoint_descriptor
  57. langwell_ep0_desc = {
  58. .bLength = USB_DT_ENDPOINT_SIZE,
  59. .bDescriptorType = USB_DT_ENDPOINT,
  60. .bEndpointAddress = 0,
  61. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  62. .wMaxPacketSize = EP0_MAX_PKT_SIZE,
  63. };
  64. /*-------------------------------------------------------------------------*/
  65. /* debugging */
  66. #ifdef DEBUG
  67. #define DBG(dev, fmt, args...) \
  68. pr_debug("%s %s: " fmt , driver_name, \
  69. pci_name(dev->pdev), ## args)
  70. #else
  71. #define DBG(dev, fmt, args...) \
  72. do { } while (0)
  73. #endif /* DEBUG */
  74. #ifdef VERBOSE
  75. #define VDBG DBG
  76. #else
  77. #define VDBG(dev, fmt, args...) \
  78. do { } while (0)
  79. #endif /* VERBOSE */
  80. #define ERROR(dev, fmt, args...) \
  81. pr_err("%s %s: " fmt , driver_name, \
  82. pci_name(dev->pdev), ## args)
  83. #define WARNING(dev, fmt, args...) \
  84. pr_warning("%s %s: " fmt , driver_name, \
  85. pci_name(dev->pdev), ## args)
  86. #define INFO(dev, fmt, args...) \
  87. pr_info("%s %s: " fmt , driver_name, \
  88. pci_name(dev->pdev), ## args)
  89. #ifdef VERBOSE
  90. static inline void print_all_registers(struct langwell_udc *dev)
  91. {
  92. int i;
  93. /* Capability Registers */
  94. printk(KERN_DEBUG "Capability Registers (offset: "
  95. "0x%04x, length: 0x%08x)\n",
  96. CAP_REG_OFFSET,
  97. (u32)sizeof(struct langwell_cap_regs));
  98. printk(KERN_DEBUG "caplength=0x%02x\n",
  99. readb(&dev->cap_regs->caplength));
  100. printk(KERN_DEBUG "hciversion=0x%04x\n",
  101. readw(&dev->cap_regs->hciversion));
  102. printk(KERN_DEBUG "hcsparams=0x%08x\n",
  103. readl(&dev->cap_regs->hcsparams));
  104. printk(KERN_DEBUG "hccparams=0x%08x\n",
  105. readl(&dev->cap_regs->hccparams));
  106. printk(KERN_DEBUG "dciversion=0x%04x\n",
  107. readw(&dev->cap_regs->dciversion));
  108. printk(KERN_DEBUG "dccparams=0x%08x\n",
  109. readl(&dev->cap_regs->dccparams));
  110. /* Operational Registers */
  111. printk(KERN_DEBUG "Operational Registers (offset: "
  112. "0x%04x, length: 0x%08x)\n",
  113. OP_REG_OFFSET,
  114. (u32)sizeof(struct langwell_op_regs));
  115. printk(KERN_DEBUG "extsts=0x%08x\n",
  116. readl(&dev->op_regs->extsts));
  117. printk(KERN_DEBUG "extintr=0x%08x\n",
  118. readl(&dev->op_regs->extintr));
  119. printk(KERN_DEBUG "usbcmd=0x%08x\n",
  120. readl(&dev->op_regs->usbcmd));
  121. printk(KERN_DEBUG "usbsts=0x%08x\n",
  122. readl(&dev->op_regs->usbsts));
  123. printk(KERN_DEBUG "usbintr=0x%08x\n",
  124. readl(&dev->op_regs->usbintr));
  125. printk(KERN_DEBUG "frindex=0x%08x\n",
  126. readl(&dev->op_regs->frindex));
  127. printk(KERN_DEBUG "ctrldssegment=0x%08x\n",
  128. readl(&dev->op_regs->ctrldssegment));
  129. printk(KERN_DEBUG "deviceaddr=0x%08x\n",
  130. readl(&dev->op_regs->deviceaddr));
  131. printk(KERN_DEBUG "endpointlistaddr=0x%08x\n",
  132. readl(&dev->op_regs->endpointlistaddr));
  133. printk(KERN_DEBUG "ttctrl=0x%08x\n",
  134. readl(&dev->op_regs->ttctrl));
  135. printk(KERN_DEBUG "burstsize=0x%08x\n",
  136. readl(&dev->op_regs->burstsize));
  137. printk(KERN_DEBUG "txfilltuning=0x%08x\n",
  138. readl(&dev->op_regs->txfilltuning));
  139. printk(KERN_DEBUG "txttfilltuning=0x%08x\n",
  140. readl(&dev->op_regs->txttfilltuning));
  141. printk(KERN_DEBUG "ic_usb=0x%08x\n",
  142. readl(&dev->op_regs->ic_usb));
  143. printk(KERN_DEBUG "ulpi_viewport=0x%08x\n",
  144. readl(&dev->op_regs->ulpi_viewport));
  145. printk(KERN_DEBUG "configflag=0x%08x\n",
  146. readl(&dev->op_regs->configflag));
  147. printk(KERN_DEBUG "portsc1=0x%08x\n",
  148. readl(&dev->op_regs->portsc1));
  149. printk(KERN_DEBUG "devlc=0x%08x\n",
  150. readl(&dev->op_regs->devlc));
  151. printk(KERN_DEBUG "otgsc=0x%08x\n",
  152. readl(&dev->op_regs->otgsc));
  153. printk(KERN_DEBUG "usbmode=0x%08x\n",
  154. readl(&dev->op_regs->usbmode));
  155. printk(KERN_DEBUG "endptnak=0x%08x\n",
  156. readl(&dev->op_regs->endptnak));
  157. printk(KERN_DEBUG "endptnaken=0x%08x\n",
  158. readl(&dev->op_regs->endptnaken));
  159. printk(KERN_DEBUG "endptsetupstat=0x%08x\n",
  160. readl(&dev->op_regs->endptsetupstat));
  161. printk(KERN_DEBUG "endptprime=0x%08x\n",
  162. readl(&dev->op_regs->endptprime));
  163. printk(KERN_DEBUG "endptflush=0x%08x\n",
  164. readl(&dev->op_regs->endptflush));
  165. printk(KERN_DEBUG "endptstat=0x%08x\n",
  166. readl(&dev->op_regs->endptstat));
  167. printk(KERN_DEBUG "endptcomplete=0x%08x\n",
  168. readl(&dev->op_regs->endptcomplete));
  169. for (i = 0; i < dev->ep_max / 2; i++) {
  170. printk(KERN_DEBUG "endptctrl[%d]=0x%08x\n",
  171. i, readl(&dev->op_regs->endptctrl[i]));
  172. }
  173. }
  174. #endif /* VERBOSE */
  175. /*-------------------------------------------------------------------------*/
  176. #define DIR_STRING(bAddress) (((bAddress) & USB_DIR_IN) ? "in" : "out")
  177. #define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
  178. USB_DIR_IN) : ((ep)->desc->bEndpointAddress \
  179. & USB_DIR_IN) == USB_DIR_IN)
  180. #ifdef DEBUG
  181. static char *type_string(u8 bmAttributes)
  182. {
  183. switch ((bmAttributes) & USB_ENDPOINT_XFERTYPE_MASK) {
  184. case USB_ENDPOINT_XFER_BULK:
  185. return "bulk";
  186. case USB_ENDPOINT_XFER_ISOC:
  187. return "iso";
  188. case USB_ENDPOINT_XFER_INT:
  189. return "int";
  190. };
  191. return "control";
  192. }
  193. #endif
  194. /* configure endpoint control registers */
  195. static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
  196. unsigned char is_in, unsigned char ep_type)
  197. {
  198. struct langwell_udc *dev;
  199. u32 endptctrl;
  200. dev = ep->dev;
  201. VDBG(dev, "---> %s()\n", __func__);
  202. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  203. if (is_in) { /* TX */
  204. if (ep_num)
  205. endptctrl |= EPCTRL_TXR;
  206. endptctrl |= EPCTRL_TXE;
  207. endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
  208. } else { /* RX */
  209. if (ep_num)
  210. endptctrl |= EPCTRL_RXR;
  211. endptctrl |= EPCTRL_RXE;
  212. endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
  213. }
  214. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  215. VDBG(dev, "<--- %s()\n", __func__);
  216. }
  217. /* reset ep0 dQH and endptctrl */
  218. static void ep0_reset(struct langwell_udc *dev)
  219. {
  220. struct langwell_ep *ep;
  221. int i;
  222. VDBG(dev, "---> %s()\n", __func__);
  223. /* ep0 in and out */
  224. for (i = 0; i < 2; i++) {
  225. ep = &dev->ep[i];
  226. ep->dev = dev;
  227. /* ep0 dQH */
  228. ep->dqh = &dev->ep_dqh[i];
  229. /* configure ep0 endpoint capabilities in dQH */
  230. ep->dqh->dqh_ios = 1;
  231. ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
  232. /* FIXME: enable ep0-in HW zero length termination select */
  233. if (is_in(ep))
  234. ep->dqh->dqh_zlt = 0;
  235. ep->dqh->dqh_mult = 0;
  236. /* configure ep0 control registers */
  237. ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
  238. }
  239. VDBG(dev, "<--- %s()\n", __func__);
  240. return;
  241. }
  242. /*-------------------------------------------------------------------------*/
  243. /* endpoints operations */
  244. /* configure endpoint, making it usable */
  245. static int langwell_ep_enable(struct usb_ep *_ep,
  246. const struct usb_endpoint_descriptor *desc)
  247. {
  248. struct langwell_udc *dev;
  249. struct langwell_ep *ep;
  250. u16 max = 0;
  251. unsigned long flags;
  252. int retval = 0;
  253. unsigned char zlt, ios = 0, mult = 0;
  254. ep = container_of(_ep, struct langwell_ep, ep);
  255. dev = ep->dev;
  256. VDBG(dev, "---> %s()\n", __func__);
  257. if (!_ep || !desc || ep->desc
  258. || desc->bDescriptorType != USB_DT_ENDPOINT)
  259. return -EINVAL;
  260. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  261. return -ESHUTDOWN;
  262. max = le16_to_cpu(desc->wMaxPacketSize);
  263. /*
  264. * disable HW zero length termination select
  265. * driver handles zero length packet through req->req.zero
  266. */
  267. zlt = 1;
  268. /*
  269. * sanity check type, direction, address, and then
  270. * initialize the endpoint capabilities fields in dQH
  271. */
  272. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  273. case USB_ENDPOINT_XFER_CONTROL:
  274. ios = 1;
  275. break;
  276. case USB_ENDPOINT_XFER_BULK:
  277. if ((dev->gadget.speed == USB_SPEED_HIGH
  278. && max != 512)
  279. || (dev->gadget.speed == USB_SPEED_FULL
  280. && max > 64)) {
  281. goto done;
  282. }
  283. break;
  284. case USB_ENDPOINT_XFER_INT:
  285. if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
  286. goto done;
  287. switch (dev->gadget.speed) {
  288. case USB_SPEED_HIGH:
  289. if (max <= 1024)
  290. break;
  291. case USB_SPEED_FULL:
  292. if (max <= 64)
  293. break;
  294. default:
  295. if (max <= 8)
  296. break;
  297. goto done;
  298. }
  299. break;
  300. case USB_ENDPOINT_XFER_ISOC:
  301. if (strstr(ep->ep.name, "-bulk")
  302. || strstr(ep->ep.name, "-int"))
  303. goto done;
  304. switch (dev->gadget.speed) {
  305. case USB_SPEED_HIGH:
  306. if (max <= 1024)
  307. break;
  308. case USB_SPEED_FULL:
  309. if (max <= 1023)
  310. break;
  311. default:
  312. goto done;
  313. }
  314. /*
  315. * FIXME:
  316. * calculate transactions needed for high bandwidth iso
  317. */
  318. mult = (unsigned char)(1 + ((max >> 11) & 0x03));
  319. max = max & 0x8ff; /* bit 0~10 */
  320. /* 3 transactions at most */
  321. if (mult > 3)
  322. goto done;
  323. break;
  324. default:
  325. goto done;
  326. }
  327. spin_lock_irqsave(&dev->lock, flags);
  328. /* configure endpoint capabilities in dQH */
  329. ep->dqh->dqh_ios = ios;
  330. ep->dqh->dqh_mpl = cpu_to_le16(max);
  331. ep->dqh->dqh_zlt = zlt;
  332. ep->dqh->dqh_mult = mult;
  333. ep->ep.maxpacket = max;
  334. ep->desc = desc;
  335. ep->stopped = 0;
  336. ep->ep_num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  337. /* ep_type */
  338. ep->ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  339. /* configure endpoint control registers */
  340. ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
  341. DBG(dev, "enabled %s (ep%d%s-%s), max %04x\n",
  342. _ep->name,
  343. ep->ep_num,
  344. DIR_STRING(desc->bEndpointAddress),
  345. type_string(desc->bmAttributes),
  346. max);
  347. spin_unlock_irqrestore(&dev->lock, flags);
  348. done:
  349. VDBG(dev, "<--- %s()\n", __func__);
  350. return retval;
  351. }
  352. /*-------------------------------------------------------------------------*/
  353. /* retire a request */
  354. static void done(struct langwell_ep *ep, struct langwell_request *req,
  355. int status)
  356. {
  357. struct langwell_udc *dev = ep->dev;
  358. unsigned stopped = ep->stopped;
  359. struct langwell_dtd *curr_dtd, *next_dtd;
  360. int i;
  361. VDBG(dev, "---> %s()\n", __func__);
  362. /* remove the req from ep->queue */
  363. list_del_init(&req->queue);
  364. if (req->req.status == -EINPROGRESS)
  365. req->req.status = status;
  366. else
  367. status = req->req.status;
  368. /* free dTD for the request */
  369. next_dtd = req->head;
  370. for (i = 0; i < req->dtd_count; i++) {
  371. curr_dtd = next_dtd;
  372. if (i != req->dtd_count - 1)
  373. next_dtd = curr_dtd->next_dtd_virt;
  374. dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
  375. }
  376. if (req->mapped) {
  377. dma_unmap_single(&dev->pdev->dev, req->req.dma, req->req.length,
  378. is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  379. req->req.dma = DMA_ADDR_INVALID;
  380. req->mapped = 0;
  381. } else
  382. dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
  383. req->req.length,
  384. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  385. if (status != -ESHUTDOWN)
  386. DBG(dev, "complete %s, req %p, stat %d, len %u/%u\n",
  387. ep->ep.name, &req->req, status,
  388. req->req.actual, req->req.length);
  389. /* don't modify queue heads during completion callback */
  390. ep->stopped = 1;
  391. spin_unlock(&dev->lock);
  392. /* complete routine from gadget driver */
  393. if (req->req.complete)
  394. req->req.complete(&ep->ep, &req->req);
  395. spin_lock(&dev->lock);
  396. ep->stopped = stopped;
  397. VDBG(dev, "<--- %s()\n", __func__);
  398. }
  399. static void langwell_ep_fifo_flush(struct usb_ep *_ep);
  400. /* delete all endpoint requests, called with spinlock held */
  401. static void nuke(struct langwell_ep *ep, int status)
  402. {
  403. /* called with spinlock held */
  404. ep->stopped = 1;
  405. /* endpoint fifo flush */
  406. if (&ep->ep && ep->desc)
  407. langwell_ep_fifo_flush(&ep->ep);
  408. while (!list_empty(&ep->queue)) {
  409. struct langwell_request *req = NULL;
  410. req = list_entry(ep->queue.next, struct langwell_request,
  411. queue);
  412. done(ep, req, status);
  413. }
  414. }
  415. /*-------------------------------------------------------------------------*/
  416. /* endpoint is no longer usable */
  417. static int langwell_ep_disable(struct usb_ep *_ep)
  418. {
  419. struct langwell_ep *ep;
  420. unsigned long flags;
  421. struct langwell_udc *dev;
  422. int ep_num;
  423. u32 endptctrl;
  424. ep = container_of(_ep, struct langwell_ep, ep);
  425. dev = ep->dev;
  426. VDBG(dev, "---> %s()\n", __func__);
  427. if (!_ep || !ep->desc)
  428. return -EINVAL;
  429. spin_lock_irqsave(&dev->lock, flags);
  430. /* disable endpoint control register */
  431. ep_num = ep->ep_num;
  432. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  433. if (is_in(ep))
  434. endptctrl &= ~EPCTRL_TXE;
  435. else
  436. endptctrl &= ~EPCTRL_RXE;
  437. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  438. /* nuke all pending requests (does flush) */
  439. nuke(ep, -ESHUTDOWN);
  440. ep->desc = NULL;
  441. ep->stopped = 1;
  442. spin_unlock_irqrestore(&dev->lock, flags);
  443. DBG(dev, "disabled %s\n", _ep->name);
  444. VDBG(dev, "<--- %s()\n", __func__);
  445. return 0;
  446. }
  447. /* allocate a request object to use with this endpoint */
  448. static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
  449. gfp_t gfp_flags)
  450. {
  451. struct langwell_ep *ep;
  452. struct langwell_udc *dev;
  453. struct langwell_request *req = NULL;
  454. if (!_ep)
  455. return NULL;
  456. ep = container_of(_ep, struct langwell_ep, ep);
  457. dev = ep->dev;
  458. VDBG(dev, "---> %s()\n", __func__);
  459. req = kzalloc(sizeof(*req), gfp_flags);
  460. if (!req)
  461. return NULL;
  462. req->req.dma = DMA_ADDR_INVALID;
  463. INIT_LIST_HEAD(&req->queue);
  464. VDBG(dev, "alloc request for %s\n", _ep->name);
  465. VDBG(dev, "<--- %s()\n", __func__);
  466. return &req->req;
  467. }
  468. /* free a request object */
  469. static void langwell_free_request(struct usb_ep *_ep,
  470. struct usb_request *_req)
  471. {
  472. struct langwell_ep *ep;
  473. struct langwell_udc *dev;
  474. struct langwell_request *req = NULL;
  475. ep = container_of(_ep, struct langwell_ep, ep);
  476. dev = ep->dev;
  477. VDBG(dev, "---> %s()\n", __func__);
  478. if (!_ep || !_req)
  479. return;
  480. req = container_of(_req, struct langwell_request, req);
  481. WARN_ON(!list_empty(&req->queue));
  482. if (_req)
  483. kfree(req);
  484. VDBG(dev, "free request for %s\n", _ep->name);
  485. VDBG(dev, "<--- %s()\n", __func__);
  486. }
  487. /*-------------------------------------------------------------------------*/
  488. /* queue dTD and PRIME endpoint */
  489. static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
  490. {
  491. u32 bit_mask, usbcmd, endptstat, dtd_dma;
  492. u8 dtd_status;
  493. int i;
  494. struct langwell_dqh *dqh;
  495. struct langwell_udc *dev;
  496. dev = ep->dev;
  497. VDBG(dev, "---> %s()\n", __func__);
  498. i = ep->ep_num * 2 + is_in(ep);
  499. dqh = &dev->ep_dqh[i];
  500. if (ep->ep_num)
  501. VDBG(dev, "%s\n", ep->name);
  502. else
  503. /* ep0 */
  504. VDBG(dev, "%s-%s\n", ep->name, is_in(ep) ? "in" : "out");
  505. VDBG(dev, "ep_dqh[%d] addr: 0x%08x\n", i, (u32)&(dev->ep_dqh[i]));
  506. bit_mask = is_in(ep) ?
  507. (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
  508. VDBG(dev, "bit_mask = 0x%08x\n", bit_mask);
  509. /* check if the pipe is empty */
  510. if (!(list_empty(&ep->queue))) {
  511. /* add dTD to the end of linked list */
  512. struct langwell_request *lastreq;
  513. lastreq = list_entry(ep->queue.prev,
  514. struct langwell_request, queue);
  515. lastreq->tail->dtd_next =
  516. cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
  517. /* read prime bit, if 1 goto out */
  518. if (readl(&dev->op_regs->endptprime) & bit_mask)
  519. goto out;
  520. do {
  521. /* set ATDTW bit in USBCMD */
  522. usbcmd = readl(&dev->op_regs->usbcmd);
  523. writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
  524. /* read correct status bit */
  525. endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
  526. } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
  527. /* write ATDTW bit to 0 */
  528. usbcmd = readl(&dev->op_regs->usbcmd);
  529. writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
  530. if (endptstat)
  531. goto out;
  532. }
  533. /* write dQH next pointer and terminate bit to 0 */
  534. dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
  535. dqh->dtd_next = cpu_to_le32(dtd_dma);
  536. /* clear active and halt bit */
  537. dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
  538. dqh->dtd_status &= dtd_status;
  539. VDBG(dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
  540. /* write 1 to endptprime register to PRIME endpoint */
  541. bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
  542. VDBG(dev, "endprime bit_mask = 0x%08x\n", bit_mask);
  543. writel(bit_mask, &dev->op_regs->endptprime);
  544. out:
  545. VDBG(dev, "<--- %s()\n", __func__);
  546. return 0;
  547. }
  548. /* fill in the dTD structure to build a transfer descriptor */
  549. static struct langwell_dtd *build_dtd(struct langwell_request *req,
  550. unsigned *length, dma_addr_t *dma, int *is_last)
  551. {
  552. u32 buf_ptr;
  553. struct langwell_dtd *dtd;
  554. struct langwell_udc *dev;
  555. int i;
  556. dev = req->ep->dev;
  557. VDBG(dev, "---> %s()\n", __func__);
  558. /* the maximum transfer length, up to 16k bytes */
  559. *length = min(req->req.length - req->req.actual,
  560. (unsigned)DTD_MAX_TRANSFER_LENGTH);
  561. /* create dTD dma_pool resource */
  562. dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
  563. if (dtd == NULL)
  564. return dtd;
  565. dtd->dtd_dma = *dma;
  566. /* initialize buffer page pointers */
  567. buf_ptr = (u32)(req->req.dma + req->req.actual);
  568. for (i = 0; i < 5; i++)
  569. dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
  570. req->req.actual += *length;
  571. /* fill in total bytes with transfer size */
  572. dtd->dtd_total = cpu_to_le16(*length);
  573. VDBG(dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
  574. /* set is_last flag if req->req.zero is set or not */
  575. if (req->req.zero) {
  576. if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
  577. *is_last = 1;
  578. else
  579. *is_last = 0;
  580. } else if (req->req.length == req->req.actual) {
  581. *is_last = 1;
  582. } else
  583. *is_last = 0;
  584. if (*is_last == 0)
  585. VDBG(dev, "multi-dtd request!\n");
  586. /* set interrupt on complete bit for the last dTD */
  587. if (*is_last && !req->req.no_interrupt)
  588. dtd->dtd_ioc = 1;
  589. /* set multiplier override 0 for non-ISO and non-TX endpoint */
  590. dtd->dtd_multo = 0;
  591. /* set the active bit of status field to 1 */
  592. dtd->dtd_status = DTD_STS_ACTIVE;
  593. VDBG(dev, "dtd->dtd_status = 0x%02x\n", dtd->dtd_status);
  594. VDBG(dev, "length = %d, dma addr= 0x%08x\n", *length, (int)*dma);
  595. VDBG(dev, "<--- %s()\n", __func__);
  596. return dtd;
  597. }
  598. /* generate dTD linked list for a request */
  599. static int req_to_dtd(struct langwell_request *req)
  600. {
  601. unsigned count;
  602. int is_last, is_first = 1;
  603. struct langwell_dtd *dtd, *last_dtd = NULL;
  604. struct langwell_udc *dev;
  605. dma_addr_t dma;
  606. dev = req->ep->dev;
  607. VDBG(dev, "---> %s()\n", __func__);
  608. do {
  609. dtd = build_dtd(req, &count, &dma, &is_last);
  610. if (dtd == NULL)
  611. return -ENOMEM;
  612. if (is_first) {
  613. is_first = 0;
  614. req->head = dtd;
  615. } else {
  616. last_dtd->dtd_next = cpu_to_le32(dma);
  617. last_dtd->next_dtd_virt = dtd;
  618. }
  619. last_dtd = dtd;
  620. req->dtd_count++;
  621. } while (!is_last);
  622. /* set terminate bit to 1 for the last dTD */
  623. dtd->dtd_next = DTD_TERM;
  624. req->tail = dtd;
  625. VDBG(dev, "<--- %s()\n", __func__);
  626. return 0;
  627. }
  628. /*-------------------------------------------------------------------------*/
  629. /* queue (submits) an I/O requests to an endpoint */
  630. static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
  631. gfp_t gfp_flags)
  632. {
  633. struct langwell_request *req;
  634. struct langwell_ep *ep;
  635. struct langwell_udc *dev;
  636. unsigned long flags;
  637. int is_iso = 0, zlflag = 0;
  638. /* always require a cpu-view buffer */
  639. req = container_of(_req, struct langwell_request, req);
  640. ep = container_of(_ep, struct langwell_ep, ep);
  641. if (!_req || !_req->complete || !_req->buf
  642. || !list_empty(&req->queue)) {
  643. return -EINVAL;
  644. }
  645. if (unlikely(!_ep || !ep->desc))
  646. return -EINVAL;
  647. dev = ep->dev;
  648. req->ep = ep;
  649. VDBG(dev, "---> %s()\n", __func__);
  650. if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
  651. if (req->req.length > ep->ep.maxpacket)
  652. return -EMSGSIZE;
  653. is_iso = 1;
  654. }
  655. if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
  656. return -ESHUTDOWN;
  657. /* set up dma mapping in case the caller didn't */
  658. if (_req->dma == DMA_ADDR_INVALID) {
  659. /* WORKAROUND: WARN_ON(size == 0) */
  660. if (_req->length == 0) {
  661. VDBG(dev, "req->length: 0->1\n");
  662. zlflag = 1;
  663. _req->length++;
  664. }
  665. _req->dma = dma_map_single(&dev->pdev->dev,
  666. _req->buf, _req->length,
  667. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  668. if (zlflag && (_req->length == 1)) {
  669. VDBG(dev, "req->length: 1->0\n");
  670. zlflag = 0;
  671. _req->length = 0;
  672. }
  673. req->mapped = 1;
  674. VDBG(dev, "req->mapped = 1\n");
  675. } else {
  676. dma_sync_single_for_device(&dev->pdev->dev,
  677. _req->dma, _req->length,
  678. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  679. req->mapped = 0;
  680. VDBG(dev, "req->mapped = 0\n");
  681. }
  682. DBG(dev, "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
  683. _ep->name,
  684. _req, _req->length, _req->buf, _req->dma);
  685. _req->status = -EINPROGRESS;
  686. _req->actual = 0;
  687. req->dtd_count = 0;
  688. spin_lock_irqsave(&dev->lock, flags);
  689. /* build and put dTDs to endpoint queue */
  690. if (!req_to_dtd(req)) {
  691. queue_dtd(ep, req);
  692. } else {
  693. spin_unlock_irqrestore(&dev->lock, flags);
  694. return -ENOMEM;
  695. }
  696. /* update ep0 state */
  697. if (ep->ep_num == 0)
  698. dev->ep0_state = DATA_STATE_XMIT;
  699. if (likely(req != NULL)) {
  700. list_add_tail(&req->queue, &ep->queue);
  701. VDBG(dev, "list_add_tail() \n");
  702. }
  703. spin_unlock_irqrestore(&dev->lock, flags);
  704. VDBG(dev, "<--- %s()\n", __func__);
  705. return 0;
  706. }
  707. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  708. static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  709. {
  710. struct langwell_ep *ep;
  711. struct langwell_udc *dev;
  712. struct langwell_request *req;
  713. unsigned long flags;
  714. int stopped, ep_num, retval = 0;
  715. u32 endptctrl;
  716. ep = container_of(_ep, struct langwell_ep, ep);
  717. dev = ep->dev;
  718. VDBG(dev, "---> %s()\n", __func__);
  719. if (!_ep || !ep->desc || !_req)
  720. return -EINVAL;
  721. if (!dev->driver)
  722. return -ESHUTDOWN;
  723. spin_lock_irqsave(&dev->lock, flags);
  724. stopped = ep->stopped;
  725. /* quiesce dma while we patch the queue */
  726. ep->stopped = 1;
  727. ep_num = ep->ep_num;
  728. /* disable endpoint control register */
  729. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  730. if (is_in(ep))
  731. endptctrl &= ~EPCTRL_TXE;
  732. else
  733. endptctrl &= ~EPCTRL_RXE;
  734. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  735. /* make sure it's still queued on this endpoint */
  736. list_for_each_entry(req, &ep->queue, queue) {
  737. if (&req->req == _req)
  738. break;
  739. }
  740. if (&req->req != _req) {
  741. retval = -EINVAL;
  742. goto done;
  743. }
  744. /* queue head may be partially complete. */
  745. if (ep->queue.next == &req->queue) {
  746. DBG(dev, "unlink (%s) dma\n", _ep->name);
  747. _req->status = -ECONNRESET;
  748. langwell_ep_fifo_flush(&ep->ep);
  749. /* not the last request in endpoint queue */
  750. if (likely(ep->queue.next == &req->queue)) {
  751. struct langwell_dqh *dqh;
  752. struct langwell_request *next_req;
  753. dqh = ep->dqh;
  754. next_req = list_entry(req->queue.next,
  755. struct langwell_request, queue);
  756. /* point the dQH to the first dTD of next request */
  757. writel((u32) next_req->head, &dqh->dqh_current);
  758. }
  759. } else {
  760. struct langwell_request *prev_req;
  761. prev_req = list_entry(req->queue.prev,
  762. struct langwell_request, queue);
  763. writel(readl(&req->tail->dtd_next),
  764. &prev_req->tail->dtd_next);
  765. }
  766. done(ep, req, -ECONNRESET);
  767. done:
  768. /* enable endpoint again */
  769. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  770. if (is_in(ep))
  771. endptctrl |= EPCTRL_TXE;
  772. else
  773. endptctrl |= EPCTRL_RXE;
  774. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  775. ep->stopped = stopped;
  776. spin_unlock_irqrestore(&dev->lock, flags);
  777. VDBG(dev, "<--- %s()\n", __func__);
  778. return retval;
  779. }
  780. /*-------------------------------------------------------------------------*/
  781. /* endpoint set/clear halt */
  782. static void ep_set_halt(struct langwell_ep *ep, int value)
  783. {
  784. u32 endptctrl = 0;
  785. int ep_num;
  786. struct langwell_udc *dev = ep->dev;
  787. VDBG(dev, "---> %s()\n", __func__);
  788. ep_num = ep->ep_num;
  789. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  790. /* value: 1 - set halt, 0 - clear halt */
  791. if (value) {
  792. /* set the stall bit */
  793. if (is_in(ep))
  794. endptctrl |= EPCTRL_TXS;
  795. else
  796. endptctrl |= EPCTRL_RXS;
  797. } else {
  798. /* clear the stall bit and reset data toggle */
  799. if (is_in(ep)) {
  800. endptctrl &= ~EPCTRL_TXS;
  801. endptctrl |= EPCTRL_TXR;
  802. } else {
  803. endptctrl &= ~EPCTRL_RXS;
  804. endptctrl |= EPCTRL_RXR;
  805. }
  806. }
  807. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  808. VDBG(dev, "<--- %s()\n", __func__);
  809. }
  810. /* set the endpoint halt feature */
  811. static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
  812. {
  813. struct langwell_ep *ep;
  814. struct langwell_udc *dev;
  815. unsigned long flags;
  816. int retval = 0;
  817. ep = container_of(_ep, struct langwell_ep, ep);
  818. dev = ep->dev;
  819. VDBG(dev, "---> %s()\n", __func__);
  820. if (!_ep || !ep->desc)
  821. return -EINVAL;
  822. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  823. return -ESHUTDOWN;
  824. if (ep->desc && (ep->desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
  825. == USB_ENDPOINT_XFER_ISOC)
  826. return -EOPNOTSUPP;
  827. spin_lock_irqsave(&dev->lock, flags);
  828. /*
  829. * attempt to halt IN ep will fail if any transfer requests
  830. * are still queue
  831. */
  832. if (!list_empty(&ep->queue) && is_in(ep) && value) {
  833. /* IN endpoint FIFO holds bytes */
  834. DBG(dev, "%s FIFO holds bytes\n", _ep->name);
  835. retval = -EAGAIN;
  836. goto done;
  837. }
  838. /* endpoint set/clear halt */
  839. if (ep->ep_num) {
  840. ep_set_halt(ep, value);
  841. } else { /* endpoint 0 */
  842. dev->ep0_state = WAIT_FOR_SETUP;
  843. dev->ep0_dir = USB_DIR_OUT;
  844. }
  845. done:
  846. spin_unlock_irqrestore(&dev->lock, flags);
  847. DBG(dev, "%s %s halt\n", _ep->name, value ? "set" : "clear");
  848. VDBG(dev, "<--- %s()\n", __func__);
  849. return retval;
  850. }
  851. /* set the halt feature and ignores clear requests */
  852. static int langwell_ep_set_wedge(struct usb_ep *_ep)
  853. {
  854. struct langwell_ep *ep;
  855. struct langwell_udc *dev;
  856. ep = container_of(_ep, struct langwell_ep, ep);
  857. dev = ep->dev;
  858. VDBG(dev, "---> %s()\n", __func__);
  859. if (!_ep || !ep->desc)
  860. return -EINVAL;
  861. VDBG(dev, "<--- %s()\n", __func__);
  862. return usb_ep_set_halt(_ep);
  863. }
  864. /* flush contents of a fifo */
  865. static void langwell_ep_fifo_flush(struct usb_ep *_ep)
  866. {
  867. struct langwell_ep *ep;
  868. struct langwell_udc *dev;
  869. u32 flush_bit;
  870. unsigned long timeout;
  871. ep = container_of(_ep, struct langwell_ep, ep);
  872. dev = ep->dev;
  873. VDBG(dev, "---> %s()\n", __func__);
  874. if (!_ep || !ep->desc) {
  875. VDBG(dev, "ep or ep->desc is NULL\n");
  876. VDBG(dev, "<--- %s()\n", __func__);
  877. return;
  878. }
  879. VDBG(dev, "%s-%s fifo flush\n", _ep->name, is_in(ep) ? "in" : "out");
  880. /* flush endpoint buffer */
  881. if (ep->ep_num == 0)
  882. flush_bit = (1 << 16) | 1;
  883. else if (is_in(ep))
  884. flush_bit = 1 << (ep->ep_num + 16); /* TX */
  885. else
  886. flush_bit = 1 << ep->ep_num; /* RX */
  887. /* wait until flush complete */
  888. timeout = jiffies + FLUSH_TIMEOUT;
  889. do {
  890. writel(flush_bit, &dev->op_regs->endptflush);
  891. while (readl(&dev->op_regs->endptflush)) {
  892. if (time_after(jiffies, timeout)) {
  893. ERROR(dev, "ep flush timeout\n");
  894. goto done;
  895. }
  896. cpu_relax();
  897. }
  898. } while (readl(&dev->op_regs->endptstat) & flush_bit);
  899. done:
  900. VDBG(dev, "<--- %s()\n", __func__);
  901. }
  902. /* endpoints operations structure */
  903. static const struct usb_ep_ops langwell_ep_ops = {
  904. /* configure endpoint, making it usable */
  905. .enable = langwell_ep_enable,
  906. /* endpoint is no longer usable */
  907. .disable = langwell_ep_disable,
  908. /* allocate a request object to use with this endpoint */
  909. .alloc_request = langwell_alloc_request,
  910. /* free a request object */
  911. .free_request = langwell_free_request,
  912. /* queue (submits) an I/O requests to an endpoint */
  913. .queue = langwell_ep_queue,
  914. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  915. .dequeue = langwell_ep_dequeue,
  916. /* set the endpoint halt feature */
  917. .set_halt = langwell_ep_set_halt,
  918. /* set the halt feature and ignores clear requests */
  919. .set_wedge = langwell_ep_set_wedge,
  920. /* flush contents of a fifo */
  921. .fifo_flush = langwell_ep_fifo_flush,
  922. };
  923. /*-------------------------------------------------------------------------*/
  924. /* device controller usb_gadget_ops structure */
  925. /* returns the current frame number */
  926. static int langwell_get_frame(struct usb_gadget *_gadget)
  927. {
  928. struct langwell_udc *dev;
  929. u16 retval;
  930. if (!_gadget)
  931. return -ENODEV;
  932. dev = container_of(_gadget, struct langwell_udc, gadget);
  933. VDBG(dev, "---> %s()\n", __func__);
  934. retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
  935. VDBG(dev, "<--- %s()\n", __func__);
  936. return retval;
  937. }
  938. /* tries to wake up the host connected to this gadget */
  939. static int langwell_wakeup(struct usb_gadget *_gadget)
  940. {
  941. struct langwell_udc *dev;
  942. u32 portsc1, devlc;
  943. unsigned long flags;
  944. if (!_gadget)
  945. return 0;
  946. dev = container_of(_gadget, struct langwell_udc, gadget);
  947. VDBG(dev, "---> %s()\n", __func__);
  948. /* Remote Wakeup feature not enabled by host */
  949. if (!dev->remote_wakeup)
  950. return -ENOTSUPP;
  951. spin_lock_irqsave(&dev->lock, flags);
  952. portsc1 = readl(&dev->op_regs->portsc1);
  953. if (!(portsc1 & PORTS_SUSP)) {
  954. spin_unlock_irqrestore(&dev->lock, flags);
  955. return 0;
  956. }
  957. /* LPM L1 to L0, remote wakeup */
  958. if (dev->lpm && dev->lpm_state == LPM_L1) {
  959. portsc1 |= PORTS_SLP;
  960. writel(portsc1, &dev->op_regs->portsc1);
  961. }
  962. /* force port resume */
  963. if (dev->usb_state == USB_STATE_SUSPENDED) {
  964. portsc1 |= PORTS_FPR;
  965. writel(portsc1, &dev->op_regs->portsc1);
  966. }
  967. /* exit PHY low power suspend */
  968. devlc = readl(&dev->op_regs->devlc);
  969. VDBG(dev, "devlc = 0x%08x\n", devlc);
  970. devlc &= ~LPM_PHCD;
  971. writel(devlc, &dev->op_regs->devlc);
  972. spin_unlock_irqrestore(&dev->lock, flags);
  973. VDBG(dev, "<--- %s()\n", __func__);
  974. return 0;
  975. }
  976. /* notify controller that VBUS is powered or not */
  977. static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
  978. {
  979. struct langwell_udc *dev;
  980. unsigned long flags;
  981. u32 usbcmd;
  982. if (!_gadget)
  983. return -ENODEV;
  984. dev = container_of(_gadget, struct langwell_udc, gadget);
  985. VDBG(dev, "---> %s()\n", __func__);
  986. spin_lock_irqsave(&dev->lock, flags);
  987. VDBG(dev, "VBUS status: %s\n", is_active ? "on" : "off");
  988. dev->vbus_active = (is_active != 0);
  989. if (dev->driver && dev->softconnected && dev->vbus_active) {
  990. usbcmd = readl(&dev->op_regs->usbcmd);
  991. usbcmd |= CMD_RUNSTOP;
  992. writel(usbcmd, &dev->op_regs->usbcmd);
  993. } else {
  994. usbcmd = readl(&dev->op_regs->usbcmd);
  995. usbcmd &= ~CMD_RUNSTOP;
  996. writel(usbcmd, &dev->op_regs->usbcmd);
  997. }
  998. spin_unlock_irqrestore(&dev->lock, flags);
  999. VDBG(dev, "<--- %s()\n", __func__);
  1000. return 0;
  1001. }
  1002. /* constrain controller's VBUS power usage */
  1003. static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  1004. {
  1005. struct langwell_udc *dev;
  1006. if (!_gadget)
  1007. return -ENODEV;
  1008. dev = container_of(_gadget, struct langwell_udc, gadget);
  1009. VDBG(dev, "---> %s()\n", __func__);
  1010. if (dev->transceiver) {
  1011. VDBG(dev, "otg_set_power\n");
  1012. VDBG(dev, "<--- %s()\n", __func__);
  1013. return otg_set_power(dev->transceiver, mA);
  1014. }
  1015. VDBG(dev, "<--- %s()\n", __func__);
  1016. return -ENOTSUPP;
  1017. }
  1018. /* D+ pullup, software-controlled connect/disconnect to USB host */
  1019. static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
  1020. {
  1021. struct langwell_udc *dev;
  1022. u32 usbcmd;
  1023. unsigned long flags;
  1024. if (!_gadget)
  1025. return -ENODEV;
  1026. dev = container_of(_gadget, struct langwell_udc, gadget);
  1027. VDBG(dev, "---> %s()\n", __func__);
  1028. spin_lock_irqsave(&dev->lock, flags);
  1029. dev->softconnected = (is_on != 0);
  1030. if (dev->driver && dev->softconnected && dev->vbus_active) {
  1031. usbcmd = readl(&dev->op_regs->usbcmd);
  1032. usbcmd |= CMD_RUNSTOP;
  1033. writel(usbcmd, &dev->op_regs->usbcmd);
  1034. } else {
  1035. usbcmd = readl(&dev->op_regs->usbcmd);
  1036. usbcmd &= ~CMD_RUNSTOP;
  1037. writel(usbcmd, &dev->op_regs->usbcmd);
  1038. }
  1039. spin_unlock_irqrestore(&dev->lock, flags);
  1040. VDBG(dev, "<--- %s()\n", __func__);
  1041. return 0;
  1042. }
  1043. /* device controller usb_gadget_ops structure */
  1044. static const struct usb_gadget_ops langwell_ops = {
  1045. /* returns the current frame number */
  1046. .get_frame = langwell_get_frame,
  1047. /* tries to wake up the host connected to this gadget */
  1048. .wakeup = langwell_wakeup,
  1049. /* set the device selfpowered feature, always selfpowered */
  1050. /* .set_selfpowered = langwell_set_selfpowered, */
  1051. /* notify controller that VBUS is powered or not */
  1052. .vbus_session = langwell_vbus_session,
  1053. /* constrain controller's VBUS power usage */
  1054. .vbus_draw = langwell_vbus_draw,
  1055. /* D+ pullup, software-controlled connect/disconnect to USB host */
  1056. .pullup = langwell_pullup,
  1057. };
  1058. /*-------------------------------------------------------------------------*/
  1059. /* device controller operations */
  1060. /* reset device controller */
  1061. static int langwell_udc_reset(struct langwell_udc *dev)
  1062. {
  1063. u32 usbcmd, usbmode, devlc, endpointlistaddr;
  1064. unsigned long timeout;
  1065. if (!dev)
  1066. return -EINVAL;
  1067. DBG(dev, "---> %s()\n", __func__);
  1068. /* set controller to stop state */
  1069. usbcmd = readl(&dev->op_regs->usbcmd);
  1070. usbcmd &= ~CMD_RUNSTOP;
  1071. writel(usbcmd, &dev->op_regs->usbcmd);
  1072. /* reset device controller */
  1073. usbcmd = readl(&dev->op_regs->usbcmd);
  1074. usbcmd |= CMD_RST;
  1075. writel(usbcmd, &dev->op_regs->usbcmd);
  1076. /* wait for reset to complete */
  1077. timeout = jiffies + RESET_TIMEOUT;
  1078. while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
  1079. if (time_after(jiffies, timeout)) {
  1080. ERROR(dev, "device reset timeout\n");
  1081. return -ETIMEDOUT;
  1082. }
  1083. cpu_relax();
  1084. }
  1085. /* set controller to device mode */
  1086. usbmode = readl(&dev->op_regs->usbmode);
  1087. usbmode |= MODE_DEVICE;
  1088. /* turn setup lockout off, require setup tripwire in usbcmd */
  1089. usbmode |= MODE_SLOM;
  1090. writel(usbmode, &dev->op_regs->usbmode);
  1091. usbmode = readl(&dev->op_regs->usbmode);
  1092. VDBG(dev, "usbmode=0x%08x\n", usbmode);
  1093. /* Write-Clear setup status */
  1094. writel(0, &dev->op_regs->usbsts);
  1095. /* if support USB LPM, ACK all LPM token */
  1096. if (dev->lpm) {
  1097. devlc = readl(&dev->op_regs->devlc);
  1098. devlc &= ~LPM_STL; /* don't STALL LPM token */
  1099. devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
  1100. writel(devlc, &dev->op_regs->devlc);
  1101. }
  1102. /* fill endpointlistaddr register */
  1103. endpointlistaddr = dev->ep_dqh_dma;
  1104. endpointlistaddr &= ENDPOINTLISTADDR_MASK;
  1105. writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
  1106. VDBG(dev, "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
  1107. dev->ep_dqh, endpointlistaddr,
  1108. readl(&dev->op_regs->endpointlistaddr));
  1109. DBG(dev, "<--- %s()\n", __func__);
  1110. return 0;
  1111. }
  1112. /* reinitialize device controller endpoints */
  1113. static int eps_reinit(struct langwell_udc *dev)
  1114. {
  1115. struct langwell_ep *ep;
  1116. char name[14];
  1117. int i;
  1118. VDBG(dev, "---> %s()\n", __func__);
  1119. /* initialize ep0 */
  1120. ep = &dev->ep[0];
  1121. ep->dev = dev;
  1122. strncpy(ep->name, "ep0", sizeof(ep->name));
  1123. ep->ep.name = ep->name;
  1124. ep->ep.ops = &langwell_ep_ops;
  1125. ep->stopped = 0;
  1126. ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
  1127. ep->ep_num = 0;
  1128. ep->desc = &langwell_ep0_desc;
  1129. INIT_LIST_HEAD(&ep->queue);
  1130. ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
  1131. /* initialize other endpoints */
  1132. for (i = 2; i < dev->ep_max; i++) {
  1133. ep = &dev->ep[i];
  1134. if (i % 2)
  1135. snprintf(name, sizeof(name), "ep%din", i / 2);
  1136. else
  1137. snprintf(name, sizeof(name), "ep%dout", i / 2);
  1138. ep->dev = dev;
  1139. strncpy(ep->name, name, sizeof(ep->name));
  1140. ep->ep.name = ep->name;
  1141. ep->ep.ops = &langwell_ep_ops;
  1142. ep->stopped = 0;
  1143. ep->ep.maxpacket = (unsigned short) ~0;
  1144. ep->ep_num = i / 2;
  1145. INIT_LIST_HEAD(&ep->queue);
  1146. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1147. ep->dqh = &dev->ep_dqh[i];
  1148. }
  1149. VDBG(dev, "<--- %s()\n", __func__);
  1150. return 0;
  1151. }
  1152. /* enable interrupt and set controller to run state */
  1153. static void langwell_udc_start(struct langwell_udc *dev)
  1154. {
  1155. u32 usbintr, usbcmd;
  1156. DBG(dev, "---> %s()\n", __func__);
  1157. /* enable interrupts */
  1158. usbintr = INTR_ULPIE /* ULPI */
  1159. | INTR_SLE /* suspend */
  1160. /* | INTR_SRE SOF received */
  1161. | INTR_URE /* USB reset */
  1162. | INTR_AAE /* async advance */
  1163. | INTR_SEE /* system error */
  1164. | INTR_FRE /* frame list rollover */
  1165. | INTR_PCE /* port change detect */
  1166. | INTR_UEE /* USB error interrupt */
  1167. | INTR_UE; /* USB interrupt */
  1168. writel(usbintr, &dev->op_regs->usbintr);
  1169. /* clear stopped bit */
  1170. dev->stopped = 0;
  1171. /* set controller to run */
  1172. usbcmd = readl(&dev->op_regs->usbcmd);
  1173. usbcmd |= CMD_RUNSTOP;
  1174. writel(usbcmd, &dev->op_regs->usbcmd);
  1175. DBG(dev, "<--- %s()\n", __func__);
  1176. return;
  1177. }
  1178. /* disable interrupt and set controller to stop state */
  1179. static void langwell_udc_stop(struct langwell_udc *dev)
  1180. {
  1181. u32 usbcmd;
  1182. DBG(dev, "---> %s()\n", __func__);
  1183. /* disable all interrupts */
  1184. writel(0, &dev->op_regs->usbintr);
  1185. /* set stopped bit */
  1186. dev->stopped = 1;
  1187. /* set controller to stop state */
  1188. usbcmd = readl(&dev->op_regs->usbcmd);
  1189. usbcmd &= ~CMD_RUNSTOP;
  1190. writel(usbcmd, &dev->op_regs->usbcmd);
  1191. DBG(dev, "<--- %s()\n", __func__);
  1192. return;
  1193. }
  1194. /* stop all USB activities */
  1195. static void stop_activity(struct langwell_udc *dev,
  1196. struct usb_gadget_driver *driver)
  1197. {
  1198. struct langwell_ep *ep;
  1199. DBG(dev, "---> %s()\n", __func__);
  1200. nuke(&dev->ep[0], -ESHUTDOWN);
  1201. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1202. nuke(ep, -ESHUTDOWN);
  1203. }
  1204. /* report disconnect; the driver is already quiesced */
  1205. if (driver) {
  1206. spin_unlock(&dev->lock);
  1207. driver->disconnect(&dev->gadget);
  1208. spin_lock(&dev->lock);
  1209. }
  1210. DBG(dev, "<--- %s()\n", __func__);
  1211. }
  1212. /*-------------------------------------------------------------------------*/
  1213. /* device "function" sysfs attribute file */
  1214. static ssize_t show_function(struct device *_dev,
  1215. struct device_attribute *attr, char *buf)
  1216. {
  1217. struct langwell_udc *dev = the_controller;
  1218. if (!dev->driver || !dev->driver->function
  1219. || strlen(dev->driver->function) > PAGE_SIZE)
  1220. return 0;
  1221. return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
  1222. }
  1223. static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
  1224. /* device "langwell_udc" sysfs attribute file */
  1225. static ssize_t show_langwell_udc(struct device *_dev,
  1226. struct device_attribute *attr, char *buf)
  1227. {
  1228. struct langwell_udc *dev = the_controller;
  1229. struct langwell_request *req;
  1230. struct langwell_ep *ep = NULL;
  1231. char *next;
  1232. unsigned size;
  1233. unsigned t;
  1234. unsigned i;
  1235. unsigned long flags;
  1236. u32 tmp_reg;
  1237. next = buf;
  1238. size = PAGE_SIZE;
  1239. spin_lock_irqsave(&dev->lock, flags);
  1240. /* driver basic information */
  1241. t = scnprintf(next, size,
  1242. DRIVER_DESC "\n"
  1243. "%s version: %s\n"
  1244. "Gadget driver: %s\n\n",
  1245. driver_name, DRIVER_VERSION,
  1246. dev->driver ? dev->driver->driver.name : "(none)");
  1247. size -= t;
  1248. next += t;
  1249. /* device registers */
  1250. tmp_reg = readl(&dev->op_regs->usbcmd);
  1251. t = scnprintf(next, size,
  1252. "USBCMD reg:\n"
  1253. "SetupTW: %d\n"
  1254. "Run/Stop: %s\n\n",
  1255. (tmp_reg & CMD_SUTW) ? 1 : 0,
  1256. (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
  1257. size -= t;
  1258. next += t;
  1259. tmp_reg = readl(&dev->op_regs->usbsts);
  1260. t = scnprintf(next, size,
  1261. "USB Status Reg:\n"
  1262. "Device Suspend: %d\n"
  1263. "Reset Received: %d\n"
  1264. "System Error: %s\n"
  1265. "USB Error Interrupt: %s\n\n",
  1266. (tmp_reg & STS_SLI) ? 1 : 0,
  1267. (tmp_reg & STS_URI) ? 1 : 0,
  1268. (tmp_reg & STS_SEI) ? "Error" : "No error",
  1269. (tmp_reg & STS_UEI) ? "Error detected" : "No error");
  1270. size -= t;
  1271. next += t;
  1272. tmp_reg = readl(&dev->op_regs->usbintr);
  1273. t = scnprintf(next, size,
  1274. "USB Intrrupt Enable Reg:\n"
  1275. "Sleep Enable: %d\n"
  1276. "SOF Received Enable: %d\n"
  1277. "Reset Enable: %d\n"
  1278. "System Error Enable: %d\n"
  1279. "Port Change Dectected Enable: %d\n"
  1280. "USB Error Intr Enable: %d\n"
  1281. "USB Intr Enable: %d\n\n",
  1282. (tmp_reg & INTR_SLE) ? 1 : 0,
  1283. (tmp_reg & INTR_SRE) ? 1 : 0,
  1284. (tmp_reg & INTR_URE) ? 1 : 0,
  1285. (tmp_reg & INTR_SEE) ? 1 : 0,
  1286. (tmp_reg & INTR_PCE) ? 1 : 0,
  1287. (tmp_reg & INTR_UEE) ? 1 : 0,
  1288. (tmp_reg & INTR_UE) ? 1 : 0);
  1289. size -= t;
  1290. next += t;
  1291. tmp_reg = readl(&dev->op_regs->frindex);
  1292. t = scnprintf(next, size,
  1293. "USB Frame Index Reg:\n"
  1294. "Frame Number is 0x%08x\n\n",
  1295. (tmp_reg & FRINDEX_MASK));
  1296. size -= t;
  1297. next += t;
  1298. tmp_reg = readl(&dev->op_regs->deviceaddr);
  1299. t = scnprintf(next, size,
  1300. "USB Device Address Reg:\n"
  1301. "Device Addr is 0x%x\n\n",
  1302. USBADR(tmp_reg));
  1303. size -= t;
  1304. next += t;
  1305. tmp_reg = readl(&dev->op_regs->endpointlistaddr);
  1306. t = scnprintf(next, size,
  1307. "USB Endpoint List Address Reg:\n"
  1308. "Endpoint List Pointer is 0x%x\n\n",
  1309. EPBASE(tmp_reg));
  1310. size -= t;
  1311. next += t;
  1312. tmp_reg = readl(&dev->op_regs->portsc1);
  1313. t = scnprintf(next, size,
  1314. "USB Port Status & Control Reg:\n"
  1315. "Port Reset: %s\n"
  1316. "Port Suspend Mode: %s\n"
  1317. "Over-current Change: %s\n"
  1318. "Port Enable/Disable Change: %s\n"
  1319. "Port Enabled/Disabled: %s\n"
  1320. "Current Connect Status: %s\n\n",
  1321. (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
  1322. (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
  1323. (tmp_reg & PORTS_OCC) ? "Detected" : "No",
  1324. (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
  1325. (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
  1326. (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached");
  1327. size -= t;
  1328. next += t;
  1329. tmp_reg = readl(&dev->op_regs->devlc);
  1330. t = scnprintf(next, size,
  1331. "Device LPM Control Reg:\n"
  1332. "Parallel Transceiver : %d\n"
  1333. "Serial Transceiver : %d\n"
  1334. "Port Speed: %s\n"
  1335. "Port Force Full Speed Connenct: %s\n"
  1336. "PHY Low Power Suspend Clock Disable: %s\n"
  1337. "BmAttributes: %d\n\n",
  1338. LPM_PTS(tmp_reg),
  1339. (tmp_reg & LPM_STS) ? 1 : 0,
  1340. ({
  1341. char *s;
  1342. switch (LPM_PSPD(tmp_reg)) {
  1343. case LPM_SPEED_FULL:
  1344. s = "Full Speed"; break;
  1345. case LPM_SPEED_LOW:
  1346. s = "Low Speed"; break;
  1347. case LPM_SPEED_HIGH:
  1348. s = "High Speed"; break;
  1349. default:
  1350. s = "Unknown Speed"; break;
  1351. }
  1352. s;
  1353. }),
  1354. (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
  1355. (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
  1356. LPM_BA(tmp_reg));
  1357. size -= t;
  1358. next += t;
  1359. tmp_reg = readl(&dev->op_regs->usbmode);
  1360. t = scnprintf(next, size,
  1361. "USB Mode Reg:\n"
  1362. "Controller Mode is : %s\n\n", ({
  1363. char *s;
  1364. switch (MODE_CM(tmp_reg)) {
  1365. case MODE_IDLE:
  1366. s = "Idle"; break;
  1367. case MODE_DEVICE:
  1368. s = "Device Controller"; break;
  1369. case MODE_HOST:
  1370. s = "Host Controller"; break;
  1371. default:
  1372. s = "None"; break;
  1373. }
  1374. s;
  1375. }));
  1376. size -= t;
  1377. next += t;
  1378. tmp_reg = readl(&dev->op_regs->endptsetupstat);
  1379. t = scnprintf(next, size,
  1380. "Endpoint Setup Status Reg:\n"
  1381. "SETUP on ep 0x%04x\n\n",
  1382. tmp_reg & SETUPSTAT_MASK);
  1383. size -= t;
  1384. next += t;
  1385. for (i = 0; i < dev->ep_max / 2; i++) {
  1386. tmp_reg = readl(&dev->op_regs->endptctrl[i]);
  1387. t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
  1388. i, tmp_reg);
  1389. size -= t;
  1390. next += t;
  1391. }
  1392. tmp_reg = readl(&dev->op_regs->endptprime);
  1393. t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
  1394. size -= t;
  1395. next += t;
  1396. /* langwell_udc, langwell_ep, langwell_request structure information */
  1397. ep = &dev->ep[0];
  1398. t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
  1399. ep->ep.name, ep->ep.maxpacket, ep->ep_num);
  1400. size -= t;
  1401. next += t;
  1402. if (list_empty(&ep->queue)) {
  1403. t = scnprintf(next, size, "its req queue is empty\n\n");
  1404. size -= t;
  1405. next += t;
  1406. } else {
  1407. list_for_each_entry(req, &ep->queue, queue) {
  1408. t = scnprintf(next, size,
  1409. "req %p actual 0x%x length 0x%x buf %p\n",
  1410. &req->req, req->req.actual,
  1411. req->req.length, req->req.buf);
  1412. size -= t;
  1413. next += t;
  1414. }
  1415. }
  1416. /* other gadget->eplist ep */
  1417. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1418. if (ep->desc) {
  1419. t = scnprintf(next, size,
  1420. "\n%s MaxPacketSize: 0x%x, "
  1421. "ep_num: %d\n",
  1422. ep->ep.name, ep->ep.maxpacket,
  1423. ep->ep_num);
  1424. size -= t;
  1425. next += t;
  1426. if (list_empty(&ep->queue)) {
  1427. t = scnprintf(next, size,
  1428. "its req queue is empty\n\n");
  1429. size -= t;
  1430. next += t;
  1431. } else {
  1432. list_for_each_entry(req, &ep->queue, queue) {
  1433. t = scnprintf(next, size,
  1434. "req %p actual 0x%x length "
  1435. "0x%x buf %p\n",
  1436. &req->req, req->req.actual,
  1437. req->req.length, req->req.buf);
  1438. size -= t;
  1439. next += t;
  1440. }
  1441. }
  1442. }
  1443. }
  1444. spin_unlock_irqrestore(&dev->lock, flags);
  1445. return PAGE_SIZE - size;
  1446. }
  1447. static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
  1448. /*-------------------------------------------------------------------------*/
  1449. /*
  1450. * when a driver is successfully registered, it will receive
  1451. * control requests including set_configuration(), which enables
  1452. * non-control requests. then usb traffic follows until a
  1453. * disconnect is reported. then a host may connect again, or
  1454. * the driver might get unbound.
  1455. */
  1456. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1457. {
  1458. struct langwell_udc *dev = the_controller;
  1459. unsigned long flags;
  1460. int retval;
  1461. if (!dev)
  1462. return -ENODEV;
  1463. DBG(dev, "---> %s()\n", __func__);
  1464. if (dev->driver)
  1465. return -EBUSY;
  1466. spin_lock_irqsave(&dev->lock, flags);
  1467. /* hook up the driver ... */
  1468. driver->driver.bus = NULL;
  1469. dev->driver = driver;
  1470. dev->gadget.dev.driver = &driver->driver;
  1471. spin_unlock_irqrestore(&dev->lock, flags);
  1472. retval = driver->bind(&dev->gadget);
  1473. if (retval) {
  1474. DBG(dev, "bind to driver %s --> %d\n",
  1475. driver->driver.name, retval);
  1476. dev->driver = NULL;
  1477. dev->gadget.dev.driver = NULL;
  1478. return retval;
  1479. }
  1480. retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
  1481. if (retval)
  1482. goto err_unbind;
  1483. dev->usb_state = USB_STATE_ATTACHED;
  1484. dev->ep0_state = WAIT_FOR_SETUP;
  1485. dev->ep0_dir = USB_DIR_OUT;
  1486. /* enable interrupt and set controller to run state */
  1487. if (dev->got_irq)
  1488. langwell_udc_start(dev);
  1489. VDBG(dev, "After langwell_udc_start(), print all registers:\n");
  1490. #ifdef VERBOSE
  1491. print_all_registers(dev);
  1492. #endif
  1493. INFO(dev, "register driver: %s\n", driver->driver.name);
  1494. VDBG(dev, "<--- %s()\n", __func__);
  1495. return 0;
  1496. err_unbind:
  1497. driver->unbind(&dev->gadget);
  1498. dev->gadget.dev.driver = NULL;
  1499. dev->driver = NULL;
  1500. DBG(dev, "<--- %s()\n", __func__);
  1501. return retval;
  1502. }
  1503. EXPORT_SYMBOL(usb_gadget_register_driver);
  1504. /* unregister gadget driver */
  1505. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1506. {
  1507. struct langwell_udc *dev = the_controller;
  1508. unsigned long flags;
  1509. if (!dev)
  1510. return -ENODEV;
  1511. DBG(dev, "---> %s()\n", __func__);
  1512. if (unlikely(!driver || !driver->bind || !driver->unbind))
  1513. return -EINVAL;
  1514. /* unbind OTG transceiver */
  1515. if (dev->transceiver)
  1516. (void)otg_set_peripheral(dev->transceiver, 0);
  1517. /* disable interrupt and set controller to stop state */
  1518. langwell_udc_stop(dev);
  1519. dev->usb_state = USB_STATE_ATTACHED;
  1520. dev->ep0_state = WAIT_FOR_SETUP;
  1521. dev->ep0_dir = USB_DIR_OUT;
  1522. spin_lock_irqsave(&dev->lock, flags);
  1523. /* stop all usb activities */
  1524. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1525. stop_activity(dev, driver);
  1526. spin_unlock_irqrestore(&dev->lock, flags);
  1527. /* unbind gadget driver */
  1528. driver->unbind(&dev->gadget);
  1529. dev->gadget.dev.driver = NULL;
  1530. dev->driver = NULL;
  1531. device_remove_file(&dev->pdev->dev, &dev_attr_function);
  1532. INFO(dev, "unregistered driver '%s'\n", driver->driver.name);
  1533. DBG(dev, "<--- %s()\n", __func__);
  1534. return 0;
  1535. }
  1536. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1537. /*-------------------------------------------------------------------------*/
  1538. /*
  1539. * setup tripwire is used as a semaphore to ensure that the setup data
  1540. * payload is extracted from a dQH without being corrupted
  1541. */
  1542. static void setup_tripwire(struct langwell_udc *dev)
  1543. {
  1544. u32 usbcmd,
  1545. endptsetupstat;
  1546. unsigned long timeout;
  1547. struct langwell_dqh *dqh;
  1548. VDBG(dev, "---> %s()\n", __func__);
  1549. /* ep0 OUT dQH */
  1550. dqh = &dev->ep_dqh[EP_DIR_OUT];
  1551. /* Write-Clear endptsetupstat */
  1552. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  1553. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  1554. /* wait until endptsetupstat is cleared */
  1555. timeout = jiffies + SETUPSTAT_TIMEOUT;
  1556. while (readl(&dev->op_regs->endptsetupstat)) {
  1557. if (time_after(jiffies, timeout)) {
  1558. ERROR(dev, "setup_tripwire timeout\n");
  1559. break;
  1560. }
  1561. cpu_relax();
  1562. }
  1563. /* while a hazard exists when setup packet arrives */
  1564. do {
  1565. /* set setup tripwire bit */
  1566. usbcmd = readl(&dev->op_regs->usbcmd);
  1567. writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
  1568. /* copy the setup packet to local buffer */
  1569. memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
  1570. } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
  1571. /* Write-Clear setup tripwire bit */
  1572. usbcmd = readl(&dev->op_regs->usbcmd);
  1573. writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
  1574. VDBG(dev, "<--- %s()\n", __func__);
  1575. }
  1576. /* protocol ep0 stall, will automatically be cleared on new transaction */
  1577. static void ep0_stall(struct langwell_udc *dev)
  1578. {
  1579. u32 endptctrl;
  1580. VDBG(dev, "---> %s()\n", __func__);
  1581. /* set TX and RX to stall */
  1582. endptctrl = readl(&dev->op_regs->endptctrl[0]);
  1583. endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
  1584. writel(endptctrl, &dev->op_regs->endptctrl[0]);
  1585. /* update ep0 state */
  1586. dev->ep0_state = WAIT_FOR_SETUP;
  1587. dev->ep0_dir = USB_DIR_OUT;
  1588. VDBG(dev, "<--- %s()\n", __func__);
  1589. }
  1590. /* PRIME a status phase for ep0 */
  1591. static int prime_status_phase(struct langwell_udc *dev, int dir)
  1592. {
  1593. struct langwell_request *req;
  1594. struct langwell_ep *ep;
  1595. int status = 0;
  1596. VDBG(dev, "---> %s()\n", __func__);
  1597. if (dir == EP_DIR_IN)
  1598. dev->ep0_dir = USB_DIR_IN;
  1599. else
  1600. dev->ep0_dir = USB_DIR_OUT;
  1601. ep = &dev->ep[0];
  1602. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1603. req = dev->status_req;
  1604. req->ep = ep;
  1605. req->req.length = 0;
  1606. req->req.status = -EINPROGRESS;
  1607. req->req.actual = 0;
  1608. req->req.complete = NULL;
  1609. req->dtd_count = 0;
  1610. if (!req_to_dtd(req))
  1611. status = queue_dtd(ep, req);
  1612. else
  1613. return -ENOMEM;
  1614. if (status)
  1615. ERROR(dev, "can't queue ep0 status request\n");
  1616. list_add_tail(&req->queue, &ep->queue);
  1617. VDBG(dev, "<--- %s()\n", __func__);
  1618. return status;
  1619. }
  1620. /* SET_ADDRESS request routine */
  1621. static void set_address(struct langwell_udc *dev, u16 value,
  1622. u16 index, u16 length)
  1623. {
  1624. VDBG(dev, "---> %s()\n", __func__);
  1625. /* save the new address to device struct */
  1626. dev->dev_addr = (u8) value;
  1627. VDBG(dev, "dev->dev_addr = %d\n", dev->dev_addr);
  1628. /* update usb state */
  1629. dev->usb_state = USB_STATE_ADDRESS;
  1630. /* STATUS phase */
  1631. if (prime_status_phase(dev, EP_DIR_IN))
  1632. ep0_stall(dev);
  1633. VDBG(dev, "<--- %s()\n", __func__);
  1634. }
  1635. /* return endpoint by windex */
  1636. static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
  1637. u16 wIndex)
  1638. {
  1639. struct langwell_ep *ep;
  1640. VDBG(dev, "---> %s()\n", __func__);
  1641. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  1642. return &dev->ep[0];
  1643. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1644. u8 bEndpointAddress;
  1645. if (!ep->desc)
  1646. continue;
  1647. bEndpointAddress = ep->desc->bEndpointAddress;
  1648. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  1649. continue;
  1650. if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
  1651. == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
  1652. return ep;
  1653. }
  1654. VDBG(dev, "<--- %s()\n", __func__);
  1655. return NULL;
  1656. }
  1657. /* return whether endpoint is stalled, 0: not stalled; 1: stalled */
  1658. static int ep_is_stall(struct langwell_ep *ep)
  1659. {
  1660. struct langwell_udc *dev = ep->dev;
  1661. u32 endptctrl;
  1662. int retval;
  1663. VDBG(dev, "---> %s()\n", __func__);
  1664. endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
  1665. if (is_in(ep))
  1666. retval = endptctrl & EPCTRL_TXS ? 1 : 0;
  1667. else
  1668. retval = endptctrl & EPCTRL_RXS ? 1 : 0;
  1669. VDBG(dev, "<--- %s()\n", __func__);
  1670. return retval;
  1671. }
  1672. /* GET_STATUS request routine */
  1673. static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
  1674. u16 index, u16 length)
  1675. {
  1676. struct langwell_request *req;
  1677. struct langwell_ep *ep;
  1678. u16 status_data = 0; /* 16 bits cpu view status data */
  1679. int status = 0;
  1680. VDBG(dev, "---> %s()\n", __func__);
  1681. ep = &dev->ep[0];
  1682. if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1683. /* get device status */
  1684. status_data = 1 << USB_DEVICE_SELF_POWERED;
  1685. status_data |= dev->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  1686. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
  1687. /* get interface status */
  1688. status_data = 0;
  1689. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
  1690. /* get endpoint status */
  1691. struct langwell_ep *epn;
  1692. epn = get_ep_by_windex(dev, index);
  1693. /* stall if endpoint doesn't exist */
  1694. if (!epn)
  1695. goto stall;
  1696. status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
  1697. }
  1698. dev->ep0_dir = USB_DIR_IN;
  1699. /* borrow the per device status_req */
  1700. req = dev->status_req;
  1701. /* fill in the reqest structure */
  1702. *((u16 *) req->req.buf) = cpu_to_le16(status_data);
  1703. req->ep = ep;
  1704. req->req.length = 2;
  1705. req->req.status = -EINPROGRESS;
  1706. req->req.actual = 0;
  1707. req->req.complete = NULL;
  1708. req->dtd_count = 0;
  1709. /* prime the data phase */
  1710. if (!req_to_dtd(req))
  1711. status = queue_dtd(ep, req);
  1712. else /* no mem */
  1713. goto stall;
  1714. if (status) {
  1715. ERROR(dev, "response error on GET_STATUS request\n");
  1716. goto stall;
  1717. }
  1718. list_add_tail(&req->queue, &ep->queue);
  1719. dev->ep0_state = DATA_STATE_XMIT;
  1720. VDBG(dev, "<--- %s()\n", __func__);
  1721. return;
  1722. stall:
  1723. ep0_stall(dev);
  1724. VDBG(dev, "<--- %s()\n", __func__);
  1725. }
  1726. /* setup packet interrupt handler */
  1727. static void handle_setup_packet(struct langwell_udc *dev,
  1728. struct usb_ctrlrequest *setup)
  1729. {
  1730. u16 wValue = le16_to_cpu(setup->wValue);
  1731. u16 wIndex = le16_to_cpu(setup->wIndex);
  1732. u16 wLength = le16_to_cpu(setup->wLength);
  1733. VDBG(dev, "---> %s()\n", __func__);
  1734. /* ep0 fifo flush */
  1735. nuke(&dev->ep[0], -ESHUTDOWN);
  1736. DBG(dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
  1737. setup->bRequestType, setup->bRequest,
  1738. wValue, wIndex, wLength);
  1739. /* RNDIS gadget delegate */
  1740. if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
  1741. /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
  1742. goto delegate;
  1743. }
  1744. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1745. if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
  1746. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1747. goto delegate;
  1748. }
  1749. /* We process some stardard setup requests here */
  1750. switch (setup->bRequest) {
  1751. case USB_REQ_GET_STATUS:
  1752. DBG(dev, "SETUP: USB_REQ_GET_STATUS\n");
  1753. /* get status, DATA and STATUS phase */
  1754. if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
  1755. != (USB_DIR_IN | USB_TYPE_STANDARD))
  1756. break;
  1757. get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
  1758. goto end;
  1759. case USB_REQ_SET_ADDRESS:
  1760. DBG(dev, "SETUP: USB_REQ_SET_ADDRESS\n");
  1761. /* STATUS phase */
  1762. if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
  1763. | USB_RECIP_DEVICE))
  1764. break;
  1765. set_address(dev, wValue, wIndex, wLength);
  1766. goto end;
  1767. case USB_REQ_CLEAR_FEATURE:
  1768. case USB_REQ_SET_FEATURE:
  1769. /* STATUS phase */
  1770. {
  1771. int rc = -EOPNOTSUPP;
  1772. if (setup->bRequest == USB_REQ_SET_FEATURE)
  1773. DBG(dev, "SETUP: USB_REQ_SET_FEATURE\n");
  1774. else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
  1775. DBG(dev, "SETUP: USB_REQ_CLEAR_FEATURE\n");
  1776. if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
  1777. == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
  1778. struct langwell_ep *epn;
  1779. epn = get_ep_by_windex(dev, wIndex);
  1780. /* stall if endpoint doesn't exist */
  1781. if (!epn) {
  1782. ep0_stall(dev);
  1783. goto end;
  1784. }
  1785. if (wValue != 0 || wLength != 0
  1786. || epn->ep_num > dev->ep_max)
  1787. break;
  1788. spin_unlock(&dev->lock);
  1789. rc = langwell_ep_set_halt(&epn->ep,
  1790. (setup->bRequest == USB_REQ_SET_FEATURE)
  1791. ? 1 : 0);
  1792. spin_lock(&dev->lock);
  1793. } else if ((setup->bRequestType & (USB_RECIP_MASK
  1794. | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
  1795. | USB_TYPE_STANDARD)) {
  1796. if (!gadget_is_otg(&dev->gadget))
  1797. break;
  1798. else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) {
  1799. dev->gadget.b_hnp_enable = 1;
  1800. #ifdef OTG_TRANSCEIVER
  1801. if (!dev->lotg->otg.default_a)
  1802. dev->lotg->hsm.b_hnp_enable = 1;
  1803. #endif
  1804. } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
  1805. dev->gadget.a_hnp_support = 1;
  1806. else if (setup->bRequest ==
  1807. USB_DEVICE_A_ALT_HNP_SUPPORT)
  1808. dev->gadget.a_alt_hnp_support = 1;
  1809. else
  1810. break;
  1811. rc = 0;
  1812. } else
  1813. break;
  1814. if (rc == 0) {
  1815. if (prime_status_phase(dev, EP_DIR_IN))
  1816. ep0_stall(dev);
  1817. }
  1818. goto end;
  1819. }
  1820. case USB_REQ_GET_DESCRIPTOR:
  1821. DBG(dev, "SETUP: USB_REQ_GET_DESCRIPTOR\n");
  1822. goto delegate;
  1823. case USB_REQ_SET_DESCRIPTOR:
  1824. DBG(dev, "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
  1825. goto delegate;
  1826. case USB_REQ_GET_CONFIGURATION:
  1827. DBG(dev, "SETUP: USB_REQ_GET_CONFIGURATION\n");
  1828. goto delegate;
  1829. case USB_REQ_SET_CONFIGURATION:
  1830. DBG(dev, "SETUP: USB_REQ_SET_CONFIGURATION\n");
  1831. goto delegate;
  1832. case USB_REQ_GET_INTERFACE:
  1833. DBG(dev, "SETUP: USB_REQ_GET_INTERFACE\n");
  1834. goto delegate;
  1835. case USB_REQ_SET_INTERFACE:
  1836. DBG(dev, "SETUP: USB_REQ_SET_INTERFACE\n");
  1837. goto delegate;
  1838. case USB_REQ_SYNCH_FRAME:
  1839. DBG(dev, "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
  1840. goto delegate;
  1841. default:
  1842. /* delegate USB standard requests to the gadget driver */
  1843. goto delegate;
  1844. delegate:
  1845. /* USB requests handled by gadget */
  1846. if (wLength) {
  1847. /* DATA phase from gadget, STATUS phase from udc */
  1848. dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
  1849. ? USB_DIR_IN : USB_DIR_OUT;
  1850. VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n",
  1851. dev->ep0_dir, wLength);
  1852. spin_unlock(&dev->lock);
  1853. if (dev->driver->setup(&dev->gadget,
  1854. &dev->local_setup_buff) < 0)
  1855. ep0_stall(dev);
  1856. spin_lock(&dev->lock);
  1857. dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
  1858. ? DATA_STATE_XMIT : DATA_STATE_RECV;
  1859. } else {
  1860. /* no DATA phase, IN STATUS phase from gadget */
  1861. dev->ep0_dir = USB_DIR_IN;
  1862. VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n",
  1863. dev->ep0_dir, wLength);
  1864. spin_unlock(&dev->lock);
  1865. if (dev->driver->setup(&dev->gadget,
  1866. &dev->local_setup_buff) < 0)
  1867. ep0_stall(dev);
  1868. spin_lock(&dev->lock);
  1869. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1870. }
  1871. break;
  1872. }
  1873. end:
  1874. VDBG(dev, "<--- %s()\n", __func__);
  1875. return;
  1876. }
  1877. /* transfer completion, process endpoint request and free the completed dTDs
  1878. * for this request
  1879. */
  1880. static int process_ep_req(struct langwell_udc *dev, int index,
  1881. struct langwell_request *curr_req)
  1882. {
  1883. struct langwell_dtd *curr_dtd;
  1884. struct langwell_dqh *curr_dqh;
  1885. int td_complete, actual, remaining_length;
  1886. int i, dir;
  1887. u8 dtd_status = 0;
  1888. int retval = 0;
  1889. curr_dqh = &dev->ep_dqh[index];
  1890. dir = index % 2;
  1891. curr_dtd = curr_req->head;
  1892. td_complete = 0;
  1893. actual = curr_req->req.length;
  1894. VDBG(dev, "---> %s()\n", __func__);
  1895. for (i = 0; i < curr_req->dtd_count; i++) {
  1896. remaining_length = le16_to_cpu(curr_dtd->dtd_total);
  1897. actual -= remaining_length;
  1898. /* command execution states by dTD */
  1899. dtd_status = curr_dtd->dtd_status;
  1900. if (!dtd_status) {
  1901. /* transfers completed successfully */
  1902. if (!remaining_length) {
  1903. td_complete++;
  1904. VDBG(dev, "dTD transmitted successfully\n");
  1905. } else {
  1906. if (dir) {
  1907. VDBG(dev, "TX dTD remains data\n");
  1908. retval = -EPROTO;
  1909. break;
  1910. } else {
  1911. td_complete++;
  1912. break;
  1913. }
  1914. }
  1915. } else {
  1916. /* transfers completed with errors */
  1917. if (dtd_status & DTD_STS_ACTIVE) {
  1918. DBG(dev, "request not completed\n");
  1919. retval = 1;
  1920. return retval;
  1921. } else if (dtd_status & DTD_STS_HALTED) {
  1922. ERROR(dev, "dTD error %08x dQH[%d]\n",
  1923. dtd_status, index);
  1924. /* clear the errors and halt condition */
  1925. curr_dqh->dtd_status = 0;
  1926. retval = -EPIPE;
  1927. break;
  1928. } else if (dtd_status & DTD_STS_DBE) {
  1929. DBG(dev, "data buffer (overflow) error\n");
  1930. retval = -EPROTO;
  1931. break;
  1932. } else if (dtd_status & DTD_STS_TRE) {
  1933. DBG(dev, "transaction(ISO) error\n");
  1934. retval = -EILSEQ;
  1935. break;
  1936. } else
  1937. ERROR(dev, "unknown error (0x%x)!\n",
  1938. dtd_status);
  1939. }
  1940. if (i != curr_req->dtd_count - 1)
  1941. curr_dtd = (struct langwell_dtd *)
  1942. curr_dtd->next_dtd_virt;
  1943. }
  1944. if (retval)
  1945. return retval;
  1946. curr_req->req.actual = actual;
  1947. VDBG(dev, "<--- %s()\n", __func__);
  1948. return 0;
  1949. }
  1950. /* complete DATA or STATUS phase of ep0 prime status phase if needed */
  1951. static void ep0_req_complete(struct langwell_udc *dev,
  1952. struct langwell_ep *ep0, struct langwell_request *req)
  1953. {
  1954. u32 new_addr;
  1955. VDBG(dev, "---> %s()\n", __func__);
  1956. if (dev->usb_state == USB_STATE_ADDRESS) {
  1957. /* set the new address */
  1958. new_addr = (u32)dev->dev_addr;
  1959. writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
  1960. new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
  1961. VDBG(dev, "new_addr = %d\n", new_addr);
  1962. }
  1963. done(ep0, req, 0);
  1964. switch (dev->ep0_state) {
  1965. case DATA_STATE_XMIT:
  1966. /* receive status phase */
  1967. if (prime_status_phase(dev, EP_DIR_OUT))
  1968. ep0_stall(dev);
  1969. break;
  1970. case DATA_STATE_RECV:
  1971. /* send status phase */
  1972. if (prime_status_phase(dev, EP_DIR_IN))
  1973. ep0_stall(dev);
  1974. break;
  1975. case WAIT_FOR_OUT_STATUS:
  1976. dev->ep0_state = WAIT_FOR_SETUP;
  1977. break;
  1978. case WAIT_FOR_SETUP:
  1979. ERROR(dev, "unexpect ep0 packets\n");
  1980. break;
  1981. default:
  1982. ep0_stall(dev);
  1983. break;
  1984. }
  1985. VDBG(dev, "<--- %s()\n", __func__);
  1986. }
  1987. /* USB transfer completion interrupt */
  1988. static void handle_trans_complete(struct langwell_udc *dev)
  1989. {
  1990. u32 complete_bits;
  1991. int i, ep_num, dir, bit_mask, status;
  1992. struct langwell_ep *epn;
  1993. struct langwell_request *curr_req, *temp_req;
  1994. VDBG(dev, "---> %s()\n", __func__);
  1995. complete_bits = readl(&dev->op_regs->endptcomplete);
  1996. VDBG(dev, "endptcomplete register: 0x%08x\n", complete_bits);
  1997. /* Write-Clear the bits in endptcomplete register */
  1998. writel(complete_bits, &dev->op_regs->endptcomplete);
  1999. if (!complete_bits) {
  2000. DBG(dev, "complete_bits = 0\n");
  2001. goto done;
  2002. }
  2003. for (i = 0; i < dev->ep_max; i++) {
  2004. ep_num = i / 2;
  2005. dir = i % 2;
  2006. bit_mask = 1 << (ep_num + 16 * dir);
  2007. if (!(complete_bits & bit_mask))
  2008. continue;
  2009. /* ep0 */
  2010. if (i == 1)
  2011. epn = &dev->ep[0];
  2012. else
  2013. epn = &dev->ep[i];
  2014. if (epn->name == NULL) {
  2015. WARNING(dev, "invalid endpoint\n");
  2016. continue;
  2017. }
  2018. if (i < 2)
  2019. /* ep0 in and out */
  2020. DBG(dev, "%s-%s transfer completed\n",
  2021. epn->name,
  2022. is_in(epn) ? "in" : "out");
  2023. else
  2024. DBG(dev, "%s transfer completed\n", epn->name);
  2025. /* process the req queue until an uncomplete request */
  2026. list_for_each_entry_safe(curr_req, temp_req,
  2027. &epn->queue, queue) {
  2028. status = process_ep_req(dev, i, curr_req);
  2029. VDBG(dev, "%s req status: %d\n", epn->name, status);
  2030. if (status)
  2031. break;
  2032. /* write back status to req */
  2033. curr_req->req.status = status;
  2034. /* ep0 request completion */
  2035. if (ep_num == 0) {
  2036. ep0_req_complete(dev, epn, curr_req);
  2037. break;
  2038. } else {
  2039. done(epn, curr_req, status);
  2040. }
  2041. }
  2042. }
  2043. done:
  2044. VDBG(dev, "<--- %s()\n", __func__);
  2045. return;
  2046. }
  2047. /* port change detect interrupt handler */
  2048. static void handle_port_change(struct langwell_udc *dev)
  2049. {
  2050. u32 portsc1, devlc;
  2051. u32 speed;
  2052. VDBG(dev, "---> %s()\n", __func__);
  2053. if (dev->bus_reset)
  2054. dev->bus_reset = 0;
  2055. portsc1 = readl(&dev->op_regs->portsc1);
  2056. devlc = readl(&dev->op_regs->devlc);
  2057. VDBG(dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
  2058. portsc1, devlc);
  2059. /* bus reset is finished */
  2060. if (!(portsc1 & PORTS_PR)) {
  2061. /* get the speed */
  2062. speed = LPM_PSPD(devlc);
  2063. switch (speed) {
  2064. case LPM_SPEED_HIGH:
  2065. dev->gadget.speed = USB_SPEED_HIGH;
  2066. break;
  2067. case LPM_SPEED_FULL:
  2068. dev->gadget.speed = USB_SPEED_FULL;
  2069. break;
  2070. case LPM_SPEED_LOW:
  2071. dev->gadget.speed = USB_SPEED_LOW;
  2072. break;
  2073. default:
  2074. dev->gadget.speed = USB_SPEED_UNKNOWN;
  2075. break;
  2076. }
  2077. VDBG(dev, "speed = %d, dev->gadget.speed = %d\n",
  2078. speed, dev->gadget.speed);
  2079. }
  2080. /* LPM L0 to L1 */
  2081. if (dev->lpm && dev->lpm_state == LPM_L0)
  2082. if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
  2083. INFO(dev, "LPM L0 to L1\n");
  2084. dev->lpm_state = LPM_L1;
  2085. }
  2086. /* LPM L1 to L0, force resume or remote wakeup finished */
  2087. if (dev->lpm && dev->lpm_state == LPM_L1)
  2088. if (!(portsc1 & PORTS_SUSP)) {
  2089. if (portsc1 & PORTS_SLP)
  2090. INFO(dev, "LPM L1 to L0, force resume\n");
  2091. else
  2092. INFO(dev, "LPM L1 to L0, remote wakeup\n");
  2093. dev->lpm_state = LPM_L0;
  2094. }
  2095. /* update USB state */
  2096. if (!dev->resume_state)
  2097. dev->usb_state = USB_STATE_DEFAULT;
  2098. VDBG(dev, "<--- %s()\n", __func__);
  2099. }
  2100. /* USB reset interrupt handler */
  2101. static void handle_usb_reset(struct langwell_udc *dev)
  2102. {
  2103. u32 deviceaddr,
  2104. endptsetupstat,
  2105. endptcomplete;
  2106. unsigned long timeout;
  2107. VDBG(dev, "---> %s()\n", __func__);
  2108. /* Write-Clear the device address */
  2109. deviceaddr = readl(&dev->op_regs->deviceaddr);
  2110. writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
  2111. dev->dev_addr = 0;
  2112. /* clear usb state */
  2113. dev->resume_state = 0;
  2114. /* LPM L1 to L0, reset */
  2115. if (dev->lpm)
  2116. dev->lpm_state = LPM_L0;
  2117. dev->ep0_dir = USB_DIR_OUT;
  2118. dev->ep0_state = WAIT_FOR_SETUP;
  2119. dev->remote_wakeup = 0; /* default to 0 on reset */
  2120. dev->gadget.b_hnp_enable = 0;
  2121. dev->gadget.a_hnp_support = 0;
  2122. dev->gadget.a_alt_hnp_support = 0;
  2123. /* Write-Clear all the setup token semaphores */
  2124. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  2125. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  2126. /* Write-Clear all the endpoint complete status bits */
  2127. endptcomplete = readl(&dev->op_regs->endptcomplete);
  2128. writel(endptcomplete, &dev->op_regs->endptcomplete);
  2129. /* wait until all endptprime bits cleared */
  2130. timeout = jiffies + PRIME_TIMEOUT;
  2131. while (readl(&dev->op_regs->endptprime)) {
  2132. if (time_after(jiffies, timeout)) {
  2133. ERROR(dev, "USB reset timeout\n");
  2134. break;
  2135. }
  2136. cpu_relax();
  2137. }
  2138. /* write 1s to endptflush register to clear any primed buffers */
  2139. writel((u32) ~0, &dev->op_regs->endptflush);
  2140. if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
  2141. VDBG(dev, "USB bus reset\n");
  2142. /* bus is reseting */
  2143. dev->bus_reset = 1;
  2144. /* reset all the queues, stop all USB activities */
  2145. stop_activity(dev, dev->driver);
  2146. dev->usb_state = USB_STATE_DEFAULT;
  2147. } else {
  2148. VDBG(dev, "device controller reset\n");
  2149. /* controller reset */
  2150. langwell_udc_reset(dev);
  2151. /* reset all the queues, stop all USB activities */
  2152. stop_activity(dev, dev->driver);
  2153. /* reset ep0 dQH and endptctrl */
  2154. ep0_reset(dev);
  2155. /* enable interrupt and set controller to run state */
  2156. langwell_udc_start(dev);
  2157. dev->usb_state = USB_STATE_ATTACHED;
  2158. }
  2159. #ifdef OTG_TRANSCEIVER
  2160. /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */
  2161. if (!dev->lotg->otg.default_a)
  2162. dev->lotg->hsm.b_hnp_enable = 0;
  2163. #endif
  2164. VDBG(dev, "<--- %s()\n", __func__);
  2165. }
  2166. /* USB bus suspend/resume interrupt */
  2167. static void handle_bus_suspend(struct langwell_udc *dev)
  2168. {
  2169. u32 devlc;
  2170. DBG(dev, "---> %s()\n", __func__);
  2171. dev->resume_state = dev->usb_state;
  2172. dev->usb_state = USB_STATE_SUSPENDED;
  2173. #ifdef OTG_TRANSCEIVER
  2174. if (dev->lotg->otg.default_a) {
  2175. if (dev->lotg->hsm.b_bus_suspend_vld == 1) {
  2176. dev->lotg->hsm.b_bus_suspend = 1;
  2177. /* notify transceiver the state changes */
  2178. if (spin_trylock(&dev->lotg->wq_lock)) {
  2179. langwell_update_transceiver();
  2180. spin_unlock(&dev->lotg->wq_lock);
  2181. }
  2182. }
  2183. dev->lotg->hsm.b_bus_suspend_vld++;
  2184. } else {
  2185. if (!dev->lotg->hsm.a_bus_suspend) {
  2186. dev->lotg->hsm.a_bus_suspend = 1;
  2187. /* notify transceiver the state changes */
  2188. if (spin_trylock(&dev->lotg->wq_lock)) {
  2189. langwell_update_transceiver();
  2190. spin_unlock(&dev->lotg->wq_lock);
  2191. }
  2192. }
  2193. }
  2194. #endif
  2195. /* report suspend to the driver */
  2196. if (dev->driver) {
  2197. if (dev->driver->suspend) {
  2198. spin_unlock(&dev->lock);
  2199. dev->driver->suspend(&dev->gadget);
  2200. spin_lock(&dev->lock);
  2201. DBG(dev, "suspend %s\n", dev->driver->driver.name);
  2202. }
  2203. }
  2204. /* enter PHY low power suspend */
  2205. devlc = readl(&dev->op_regs->devlc);
  2206. VDBG(dev, "devlc = 0x%08x\n", devlc);
  2207. devlc |= LPM_PHCD;
  2208. writel(devlc, &dev->op_regs->devlc);
  2209. DBG(dev, "<--- %s()\n", __func__);
  2210. }
  2211. static void handle_bus_resume(struct langwell_udc *dev)
  2212. {
  2213. u32 devlc;
  2214. DBG(dev, "---> %s()\n", __func__);
  2215. dev->usb_state = dev->resume_state;
  2216. dev->resume_state = 0;
  2217. /* exit PHY low power suspend */
  2218. devlc = readl(&dev->op_regs->devlc);
  2219. VDBG(dev, "devlc = 0x%08x\n", devlc);
  2220. devlc &= ~LPM_PHCD;
  2221. writel(devlc, &dev->op_regs->devlc);
  2222. #ifdef OTG_TRANSCEIVER
  2223. if (dev->lotg->otg.default_a == 0)
  2224. dev->lotg->hsm.a_bus_suspend = 0;
  2225. #endif
  2226. /* report resume to the driver */
  2227. if (dev->driver) {
  2228. if (dev->driver->resume) {
  2229. spin_unlock(&dev->lock);
  2230. dev->driver->resume(&dev->gadget);
  2231. spin_lock(&dev->lock);
  2232. DBG(dev, "resume %s\n", dev->driver->driver.name);
  2233. }
  2234. }
  2235. DBG(dev, "<--- %s()\n", __func__);
  2236. }
  2237. /* USB device controller interrupt handler */
  2238. static irqreturn_t langwell_irq(int irq, void *_dev)
  2239. {
  2240. struct langwell_udc *dev = _dev;
  2241. u32 usbsts,
  2242. usbintr,
  2243. irq_sts,
  2244. portsc1;
  2245. VDBG(dev, "---> %s()\n", __func__);
  2246. if (dev->stopped) {
  2247. VDBG(dev, "handle IRQ_NONE\n");
  2248. VDBG(dev, "<--- %s()\n", __func__);
  2249. return IRQ_NONE;
  2250. }
  2251. spin_lock(&dev->lock);
  2252. /* USB status */
  2253. usbsts = readl(&dev->op_regs->usbsts);
  2254. /* USB interrupt enable */
  2255. usbintr = readl(&dev->op_regs->usbintr);
  2256. irq_sts = usbsts & usbintr;
  2257. VDBG(dev, "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
  2258. usbsts, usbintr, irq_sts);
  2259. if (!irq_sts) {
  2260. VDBG(dev, "handle IRQ_NONE\n");
  2261. VDBG(dev, "<--- %s()\n", __func__);
  2262. spin_unlock(&dev->lock);
  2263. return IRQ_NONE;
  2264. }
  2265. /* Write-Clear interrupt status bits */
  2266. writel(irq_sts, &dev->op_regs->usbsts);
  2267. /* resume from suspend */
  2268. portsc1 = readl(&dev->op_regs->portsc1);
  2269. if (dev->usb_state == USB_STATE_SUSPENDED)
  2270. if (!(portsc1 & PORTS_SUSP))
  2271. handle_bus_resume(dev);
  2272. /* USB interrupt */
  2273. if (irq_sts & STS_UI) {
  2274. VDBG(dev, "USB interrupt\n");
  2275. /* setup packet received from ep0 */
  2276. if (readl(&dev->op_regs->endptsetupstat)
  2277. & EP0SETUPSTAT_MASK) {
  2278. VDBG(dev, "USB SETUP packet received interrupt\n");
  2279. /* setup tripwire semaphone */
  2280. setup_tripwire(dev);
  2281. handle_setup_packet(dev, &dev->local_setup_buff);
  2282. }
  2283. /* USB transfer completion */
  2284. if (readl(&dev->op_regs->endptcomplete)) {
  2285. VDBG(dev, "USB transfer completion interrupt\n");
  2286. handle_trans_complete(dev);
  2287. }
  2288. }
  2289. /* SOF received interrupt (for ISO transfer) */
  2290. if (irq_sts & STS_SRI) {
  2291. /* FIXME */
  2292. /* VDBG(dev, "SOF received interrupt\n"); */
  2293. }
  2294. /* port change detect interrupt */
  2295. if (irq_sts & STS_PCI) {
  2296. VDBG(dev, "port change detect interrupt\n");
  2297. handle_port_change(dev);
  2298. }
  2299. /* suspend interrrupt */
  2300. if (irq_sts & STS_SLI) {
  2301. VDBG(dev, "suspend interrupt\n");
  2302. handle_bus_suspend(dev);
  2303. }
  2304. /* USB reset interrupt */
  2305. if (irq_sts & STS_URI) {
  2306. VDBG(dev, "USB reset interrupt\n");
  2307. handle_usb_reset(dev);
  2308. }
  2309. /* USB error or system error interrupt */
  2310. if (irq_sts & (STS_UEI | STS_SEI)) {
  2311. /* FIXME */
  2312. WARNING(dev, "error IRQ, irq_sts: %x\n", irq_sts);
  2313. }
  2314. spin_unlock(&dev->lock);
  2315. VDBG(dev, "<--- %s()\n", __func__);
  2316. return IRQ_HANDLED;
  2317. }
  2318. /*-------------------------------------------------------------------------*/
  2319. /* release device structure */
  2320. static void gadget_release(struct device *_dev)
  2321. {
  2322. struct langwell_udc *dev = the_controller;
  2323. DBG(dev, "---> %s()\n", __func__);
  2324. complete(dev->done);
  2325. DBG(dev, "<--- %s()\n", __func__);
  2326. kfree(dev);
  2327. }
  2328. /* tear down the binding between this driver and the pci device */
  2329. static void langwell_udc_remove(struct pci_dev *pdev)
  2330. {
  2331. struct langwell_udc *dev = the_controller;
  2332. DECLARE_COMPLETION(done);
  2333. BUG_ON(dev->driver);
  2334. DBG(dev, "---> %s()\n", __func__);
  2335. dev->done = &done;
  2336. /* free memory allocated in probe */
  2337. if (dev->dtd_pool)
  2338. dma_pool_destroy(dev->dtd_pool);
  2339. if (dev->status_req) {
  2340. kfree(dev->status_req->req.buf);
  2341. kfree(dev->status_req);
  2342. }
  2343. if (dev->ep_dqh)
  2344. dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
  2345. dev->ep_dqh, dev->ep_dqh_dma);
  2346. kfree(dev->ep);
  2347. /* diable IRQ handler */
  2348. if (dev->got_irq)
  2349. free_irq(pdev->irq, dev);
  2350. #ifndef OTG_TRANSCEIVER
  2351. if (dev->cap_regs)
  2352. iounmap(dev->cap_regs);
  2353. if (dev->region)
  2354. release_mem_region(pci_resource_start(pdev, 0),
  2355. pci_resource_len(pdev, 0));
  2356. if (dev->enabled)
  2357. pci_disable_device(pdev);
  2358. #else
  2359. if (dev->transceiver) {
  2360. otg_put_transceiver(dev->transceiver);
  2361. dev->transceiver = NULL;
  2362. dev->lotg = NULL;
  2363. }
  2364. #endif
  2365. dev->cap_regs = NULL;
  2366. INFO(dev, "unbind\n");
  2367. DBG(dev, "<--- %s()\n", __func__);
  2368. device_unregister(&dev->gadget.dev);
  2369. device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
  2370. #ifndef OTG_TRANSCEIVER
  2371. pci_set_drvdata(pdev, NULL);
  2372. #endif
  2373. /* free dev, wait for the release() finished */
  2374. wait_for_completion(&done);
  2375. the_controller = NULL;
  2376. }
  2377. /*
  2378. * wrap this driver around the specified device, but
  2379. * don't respond over USB until a gadget driver binds to us.
  2380. */
  2381. static int langwell_udc_probe(struct pci_dev *pdev,
  2382. const struct pci_device_id *id)
  2383. {
  2384. struct langwell_udc *dev;
  2385. #ifndef OTG_TRANSCEIVER
  2386. unsigned long resource, len;
  2387. #endif
  2388. void __iomem *base = NULL;
  2389. size_t size;
  2390. int retval;
  2391. if (the_controller) {
  2392. dev_warn(&pdev->dev, "ignoring\n");
  2393. return -EBUSY;
  2394. }
  2395. /* alloc, and start init */
  2396. dev = kzalloc(sizeof *dev, GFP_KERNEL);
  2397. if (dev == NULL) {
  2398. retval = -ENOMEM;
  2399. goto error;
  2400. }
  2401. /* initialize device spinlock */
  2402. spin_lock_init(&dev->lock);
  2403. dev->pdev = pdev;
  2404. DBG(dev, "---> %s()\n", __func__);
  2405. #ifdef OTG_TRANSCEIVER
  2406. /* PCI device is already enabled by otg_transceiver driver */
  2407. dev->enabled = 1;
  2408. /* mem region and register base */
  2409. dev->region = 1;
  2410. dev->transceiver = otg_get_transceiver();
  2411. dev->lotg = otg_to_langwell(dev->transceiver);
  2412. base = dev->lotg->regs;
  2413. #else
  2414. pci_set_drvdata(pdev, dev);
  2415. /* now all the pci goodies ... */
  2416. if (pci_enable_device(pdev) < 0) {
  2417. retval = -ENODEV;
  2418. goto error;
  2419. }
  2420. dev->enabled = 1;
  2421. /* control register: BAR 0 */
  2422. resource = pci_resource_start(pdev, 0);
  2423. len = pci_resource_len(pdev, 0);
  2424. if (!request_mem_region(resource, len, driver_name)) {
  2425. ERROR(dev, "controller already in use\n");
  2426. retval = -EBUSY;
  2427. goto error;
  2428. }
  2429. dev->region = 1;
  2430. base = ioremap_nocache(resource, len);
  2431. #endif
  2432. if (base == NULL) {
  2433. ERROR(dev, "can't map memory\n");
  2434. retval = -EFAULT;
  2435. goto error;
  2436. }
  2437. dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
  2438. VDBG(dev, "dev->cap_regs: %p\n", dev->cap_regs);
  2439. dev->op_regs = (struct langwell_op_regs __iomem *)
  2440. (base + OP_REG_OFFSET);
  2441. VDBG(dev, "dev->op_regs: %p\n", dev->op_regs);
  2442. /* irq setup after old hardware is cleaned up */
  2443. if (!pdev->irq) {
  2444. ERROR(dev, "No IRQ. Check PCI setup!\n");
  2445. retval = -ENODEV;
  2446. goto error;
  2447. }
  2448. #ifndef OTG_TRANSCEIVER
  2449. INFO(dev, "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
  2450. pdev->irq, resource, len, base);
  2451. /* enables bus-mastering for device dev */
  2452. pci_set_master(pdev);
  2453. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
  2454. driver_name, dev) != 0) {
  2455. ERROR(dev, "request interrupt %d failed\n", pdev->irq);
  2456. retval = -EBUSY;
  2457. goto error;
  2458. }
  2459. dev->got_irq = 1;
  2460. #endif
  2461. /* set stopped bit */
  2462. dev->stopped = 1;
  2463. /* capabilities and endpoint number */
  2464. dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
  2465. dev->dciversion = readw(&dev->cap_regs->dciversion);
  2466. dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
  2467. VDBG(dev, "dev->lpm: %d\n", dev->lpm);
  2468. VDBG(dev, "dev->dciversion: 0x%04x\n", dev->dciversion);
  2469. VDBG(dev, "dccparams: 0x%08x\n", readl(&dev->cap_regs->dccparams));
  2470. VDBG(dev, "dev->devcap: %d\n", dev->devcap);
  2471. if (!dev->devcap) {
  2472. ERROR(dev, "can't support device mode\n");
  2473. retval = -ENODEV;
  2474. goto error;
  2475. }
  2476. /* a pair of endpoints (out/in) for each address */
  2477. dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
  2478. VDBG(dev, "dev->ep_max: %d\n", dev->ep_max);
  2479. /* allocate endpoints memory */
  2480. dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
  2481. GFP_KERNEL);
  2482. if (!dev->ep) {
  2483. ERROR(dev, "allocate endpoints memory failed\n");
  2484. retval = -ENOMEM;
  2485. goto error;
  2486. }
  2487. /* allocate device dQH memory */
  2488. size = dev->ep_max * sizeof(struct langwell_dqh);
  2489. VDBG(dev, "orig size = %d\n", size);
  2490. if (size < DQH_ALIGNMENT)
  2491. size = DQH_ALIGNMENT;
  2492. else if ((size % DQH_ALIGNMENT) != 0) {
  2493. size += DQH_ALIGNMENT + 1;
  2494. size &= ~(DQH_ALIGNMENT - 1);
  2495. }
  2496. dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
  2497. &dev->ep_dqh_dma, GFP_KERNEL);
  2498. if (!dev->ep_dqh) {
  2499. ERROR(dev, "allocate dQH memory failed\n");
  2500. retval = -ENOMEM;
  2501. goto error;
  2502. }
  2503. dev->ep_dqh_size = size;
  2504. VDBG(dev, "ep_dqh_size = %d\n", dev->ep_dqh_size);
  2505. /* initialize ep0 status request structure */
  2506. dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
  2507. if (!dev->status_req) {
  2508. ERROR(dev, "allocate status_req memory failed\n");
  2509. retval = -ENOMEM;
  2510. goto error;
  2511. }
  2512. INIT_LIST_HEAD(&dev->status_req->queue);
  2513. /* allocate a small amount of memory to get valid address */
  2514. dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
  2515. dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
  2516. dev->resume_state = USB_STATE_NOTATTACHED;
  2517. dev->usb_state = USB_STATE_POWERED;
  2518. dev->ep0_dir = USB_DIR_OUT;
  2519. dev->remote_wakeup = 0; /* default to 0 on reset */
  2520. #ifndef OTG_TRANSCEIVER
  2521. /* reset device controller */
  2522. langwell_udc_reset(dev);
  2523. #endif
  2524. /* initialize gadget structure */
  2525. dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
  2526. dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
  2527. INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
  2528. dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
  2529. dev->gadget.is_dualspeed = 1; /* support dual speed */
  2530. #ifdef OTG_TRANSCEIVER
  2531. dev->gadget.is_otg = 1; /* support otg mode */
  2532. #endif
  2533. /* the "gadget" abstracts/virtualizes the controller */
  2534. dev_set_name(&dev->gadget.dev, "gadget");
  2535. dev->gadget.dev.parent = &pdev->dev;
  2536. dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
  2537. dev->gadget.dev.release = gadget_release;
  2538. dev->gadget.name = driver_name; /* gadget name */
  2539. /* controller endpoints reinit */
  2540. eps_reinit(dev);
  2541. #ifndef OTG_TRANSCEIVER
  2542. /* reset ep0 dQH and endptctrl */
  2543. ep0_reset(dev);
  2544. #endif
  2545. /* create dTD dma_pool resource */
  2546. dev->dtd_pool = dma_pool_create("langwell_dtd",
  2547. &dev->pdev->dev,
  2548. sizeof(struct langwell_dtd),
  2549. DTD_ALIGNMENT,
  2550. DMA_BOUNDARY);
  2551. if (!dev->dtd_pool) {
  2552. retval = -ENOMEM;
  2553. goto error;
  2554. }
  2555. /* done */
  2556. INFO(dev, "%s\n", driver_desc);
  2557. INFO(dev, "irq %d, pci mem %p\n", pdev->irq, base);
  2558. INFO(dev, "Driver version: " DRIVER_VERSION "\n");
  2559. INFO(dev, "Support (max) %d endpoints\n", dev->ep_max);
  2560. INFO(dev, "Device interface version: 0x%04x\n", dev->dciversion);
  2561. INFO(dev, "Controller mode: %s\n", dev->devcap ? "Device" : "Host");
  2562. INFO(dev, "Support USB LPM: %s\n", dev->lpm ? "Yes" : "No");
  2563. VDBG(dev, "After langwell_udc_probe(), print all registers:\n");
  2564. #ifdef VERBOSE
  2565. print_all_registers(dev);
  2566. #endif
  2567. the_controller = dev;
  2568. retval = device_register(&dev->gadget.dev);
  2569. if (retval)
  2570. goto error;
  2571. retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
  2572. if (retval)
  2573. goto error;
  2574. VDBG(dev, "<--- %s()\n", __func__);
  2575. return 0;
  2576. error:
  2577. if (dev) {
  2578. DBG(dev, "<--- %s()\n", __func__);
  2579. langwell_udc_remove(pdev);
  2580. }
  2581. return retval;
  2582. }
  2583. /* device controller suspend */
  2584. static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
  2585. {
  2586. struct langwell_udc *dev = the_controller;
  2587. u32 devlc;
  2588. DBG(dev, "---> %s()\n", __func__);
  2589. /* disable interrupt and set controller to stop state */
  2590. langwell_udc_stop(dev);
  2591. /* diable IRQ handler */
  2592. if (dev->got_irq)
  2593. free_irq(pdev->irq, dev);
  2594. dev->got_irq = 0;
  2595. /* save PCI state */
  2596. pci_save_state(pdev);
  2597. /* set device power state */
  2598. pci_set_power_state(pdev, PCI_D3hot);
  2599. /* enter PHY low power suspend */
  2600. devlc = readl(&dev->op_regs->devlc);
  2601. VDBG(dev, "devlc = 0x%08x\n", devlc);
  2602. devlc |= LPM_PHCD;
  2603. writel(devlc, &dev->op_regs->devlc);
  2604. DBG(dev, "<--- %s()\n", __func__);
  2605. return 0;
  2606. }
  2607. /* device controller resume */
  2608. static int langwell_udc_resume(struct pci_dev *pdev)
  2609. {
  2610. struct langwell_udc *dev = the_controller;
  2611. u32 devlc;
  2612. DBG(dev, "---> %s()\n", __func__);
  2613. /* exit PHY low power suspend */
  2614. devlc = readl(&dev->op_regs->devlc);
  2615. VDBG(dev, "devlc = 0x%08x\n", devlc);
  2616. devlc &= ~LPM_PHCD;
  2617. writel(devlc, &dev->op_regs->devlc);
  2618. /* set device D0 power state */
  2619. pci_set_power_state(pdev, PCI_D0);
  2620. /* restore PCI state */
  2621. pci_restore_state(pdev);
  2622. /* enable IRQ handler */
  2623. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED, driver_name, dev)
  2624. != 0) {
  2625. ERROR(dev, "request interrupt %d failed\n", pdev->irq);
  2626. return -1;
  2627. }
  2628. dev->got_irq = 1;
  2629. /* reset and start controller to run state */
  2630. if (dev->stopped) {
  2631. /* reset device controller */
  2632. langwell_udc_reset(dev);
  2633. /* reset ep0 dQH and endptctrl */
  2634. ep0_reset(dev);
  2635. /* start device if gadget is loaded */
  2636. if (dev->driver)
  2637. langwell_udc_start(dev);
  2638. }
  2639. /* reset USB status */
  2640. dev->usb_state = USB_STATE_ATTACHED;
  2641. dev->ep0_state = WAIT_FOR_SETUP;
  2642. dev->ep0_dir = USB_DIR_OUT;
  2643. DBG(dev, "<--- %s()\n", __func__);
  2644. return 0;
  2645. }
  2646. /* pci driver shutdown */
  2647. static void langwell_udc_shutdown(struct pci_dev *pdev)
  2648. {
  2649. struct langwell_udc *dev = the_controller;
  2650. u32 usbmode;
  2651. DBG(dev, "---> %s()\n", __func__);
  2652. /* reset controller mode to IDLE */
  2653. usbmode = readl(&dev->op_regs->usbmode);
  2654. DBG(dev, "usbmode = 0x%08x\n", usbmode);
  2655. usbmode &= (~3 | MODE_IDLE);
  2656. writel(usbmode, &dev->op_regs->usbmode);
  2657. DBG(dev, "<--- %s()\n", __func__);
  2658. }
  2659. /*-------------------------------------------------------------------------*/
  2660. static const struct pci_device_id pci_ids[] = { {
  2661. .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
  2662. .class_mask = ~0,
  2663. .vendor = 0x8086,
  2664. .device = 0x0811,
  2665. .subvendor = PCI_ANY_ID,
  2666. .subdevice = PCI_ANY_ID,
  2667. }, { /* end: all zeroes */ }
  2668. };
  2669. MODULE_DEVICE_TABLE(pci, pci_ids);
  2670. static struct pci_driver langwell_pci_driver = {
  2671. .name = (char *) driver_name,
  2672. .id_table = pci_ids,
  2673. .probe = langwell_udc_probe,
  2674. .remove = langwell_udc_remove,
  2675. /* device controller suspend/resume */
  2676. .suspend = langwell_udc_suspend,
  2677. .resume = langwell_udc_resume,
  2678. .shutdown = langwell_udc_shutdown,
  2679. };
  2680. MODULE_DESCRIPTION(DRIVER_DESC);
  2681. MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
  2682. MODULE_VERSION(DRIVER_VERSION);
  2683. MODULE_LICENSE("GPL");
  2684. static int __init init(void)
  2685. {
  2686. #ifdef OTG_TRANSCEIVER
  2687. return langwell_register_peripheral(&langwell_pci_driver);
  2688. #else
  2689. return pci_register_driver(&langwell_pci_driver);
  2690. #endif
  2691. }
  2692. module_init(init);
  2693. static void __exit cleanup(void)
  2694. {
  2695. #ifdef OTG_TRANSCEIVER
  2696. return langwell_unregister_peripheral(&langwell_pci_driver);
  2697. #else
  2698. pci_unregister_driver(&langwell_pci_driver);
  2699. #endif
  2700. }
  2701. module_exit(cleanup);