tx.c 31 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/tcp.h>
  12. #include <linux/ip.h>
  13. #include <linux/in.h>
  14. #include <linux/if_ether.h>
  15. #include <linux/highmem.h>
  16. #include "net_driver.h"
  17. #include "tx.h"
  18. #include "efx.h"
  19. #include "falcon.h"
  20. #include "workarounds.h"
  21. /*
  22. * TX descriptor ring full threshold
  23. *
  24. * The tx_queue descriptor ring fill-level must fall below this value
  25. * before we restart the netif queue
  26. */
  27. #define EFX_NETDEV_TX_THRESHOLD(_tx_queue) \
  28. (_tx_queue->efx->type->txd_ring_mask / 2u)
  29. /* We want to be able to nest calls to netif_stop_queue(), since each
  30. * channel can have an individual stop on the queue.
  31. */
  32. void efx_stop_queue(struct efx_nic *efx)
  33. {
  34. spin_lock_bh(&efx->netif_stop_lock);
  35. EFX_TRACE(efx, "stop TX queue\n");
  36. atomic_inc(&efx->netif_stop_count);
  37. netif_stop_queue(efx->net_dev);
  38. spin_unlock_bh(&efx->netif_stop_lock);
  39. }
  40. /* Wake netif's TX queue
  41. * We want to be able to nest calls to netif_stop_queue(), since each
  42. * channel can have an individual stop on the queue.
  43. */
  44. void efx_wake_queue(struct efx_nic *efx)
  45. {
  46. local_bh_disable();
  47. if (atomic_dec_and_lock(&efx->netif_stop_count,
  48. &efx->netif_stop_lock)) {
  49. EFX_TRACE(efx, "waking TX queue\n");
  50. netif_wake_queue(efx->net_dev);
  51. spin_unlock(&efx->netif_stop_lock);
  52. }
  53. local_bh_enable();
  54. }
  55. static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  56. struct efx_tx_buffer *buffer)
  57. {
  58. if (buffer->unmap_len) {
  59. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  60. dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len -
  61. buffer->unmap_len);
  62. if (buffer->unmap_single)
  63. pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len,
  64. PCI_DMA_TODEVICE);
  65. else
  66. pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len,
  67. PCI_DMA_TODEVICE);
  68. buffer->unmap_len = 0;
  69. buffer->unmap_single = false;
  70. }
  71. if (buffer->skb) {
  72. dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  73. buffer->skb = NULL;
  74. EFX_TRACE(tx_queue->efx, "TX queue %d transmission id %x "
  75. "complete\n", tx_queue->queue, read_ptr);
  76. }
  77. }
  78. /**
  79. * struct efx_tso_header - a DMA mapped buffer for packet headers
  80. * @next: Linked list of free ones.
  81. * The list is protected by the TX queue lock.
  82. * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
  83. * @dma_addr: The DMA address of the header below.
  84. *
  85. * This controls the memory used for a TSO header. Use TSOH_DATA()
  86. * to find the packet header data. Use TSOH_SIZE() to calculate the
  87. * total size required for a given packet header length. TSO headers
  88. * in the free list are exactly %TSOH_STD_SIZE bytes in size.
  89. */
  90. struct efx_tso_header {
  91. union {
  92. struct efx_tso_header *next;
  93. size_t unmap_len;
  94. };
  95. dma_addr_t dma_addr;
  96. };
  97. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  98. struct sk_buff *skb);
  99. static void efx_fini_tso(struct efx_tx_queue *tx_queue);
  100. static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
  101. struct efx_tso_header *tsoh);
  102. static void efx_tsoh_free(struct efx_tx_queue *tx_queue,
  103. struct efx_tx_buffer *buffer)
  104. {
  105. if (buffer->tsoh) {
  106. if (likely(!buffer->tsoh->unmap_len)) {
  107. buffer->tsoh->next = tx_queue->tso_headers_free;
  108. tx_queue->tso_headers_free = buffer->tsoh;
  109. } else {
  110. efx_tsoh_heap_free(tx_queue, buffer->tsoh);
  111. }
  112. buffer->tsoh = NULL;
  113. }
  114. }
  115. /*
  116. * Add a socket buffer to a TX queue
  117. *
  118. * This maps all fragments of a socket buffer for DMA and adds them to
  119. * the TX queue. The queue's insert pointer will be incremented by
  120. * the number of fragments in the socket buffer.
  121. *
  122. * If any DMA mapping fails, any mapped fragments will be unmapped,
  123. * the queue's insert pointer will be restored to its original value.
  124. *
  125. * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
  126. * You must hold netif_tx_lock() to call this function.
  127. */
  128. static int efx_enqueue_skb(struct efx_tx_queue *tx_queue,
  129. struct sk_buff *skb)
  130. {
  131. struct efx_nic *efx = tx_queue->efx;
  132. struct pci_dev *pci_dev = efx->pci_dev;
  133. struct efx_tx_buffer *buffer;
  134. skb_frag_t *fragment;
  135. struct page *page;
  136. int page_offset;
  137. unsigned int len, unmap_len = 0, fill_level, insert_ptr, misalign;
  138. dma_addr_t dma_addr, unmap_addr = 0;
  139. unsigned int dma_len;
  140. bool unmap_single;
  141. int q_space, i = 0;
  142. int rc = NETDEV_TX_OK;
  143. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  144. if (skb_shinfo((struct sk_buff *)skb)->gso_size)
  145. return efx_enqueue_skb_tso(tx_queue, skb);
  146. /* Get size of the initial fragment */
  147. len = skb_headlen(skb);
  148. /* Pad if necessary */
  149. if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
  150. EFX_BUG_ON_PARANOID(skb->data_len);
  151. len = 32 + 1;
  152. if (skb_pad(skb, len - skb->len))
  153. return NETDEV_TX_OK;
  154. }
  155. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  156. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  157. /* Map for DMA. Use pci_map_single rather than pci_map_page
  158. * since this is more efficient on machines with sparse
  159. * memory.
  160. */
  161. unmap_single = true;
  162. dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  163. /* Process all fragments */
  164. while (1) {
  165. if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr)))
  166. goto pci_err;
  167. /* Store fields for marking in the per-fragment final
  168. * descriptor */
  169. unmap_len = len;
  170. unmap_addr = dma_addr;
  171. /* Add to TX queue, splitting across DMA boundaries */
  172. do {
  173. if (unlikely(q_space-- <= 0)) {
  174. /* It might be that completions have
  175. * happened since the xmit path last
  176. * checked. Update the xmit path's
  177. * copy of read_count.
  178. */
  179. ++tx_queue->stopped;
  180. /* This memory barrier protects the
  181. * change of stopped from the access
  182. * of read_count. */
  183. smp_mb();
  184. tx_queue->old_read_count =
  185. *(volatile unsigned *)
  186. &tx_queue->read_count;
  187. fill_level = (tx_queue->insert_count
  188. - tx_queue->old_read_count);
  189. q_space = (efx->type->txd_ring_mask - 1 -
  190. fill_level);
  191. if (unlikely(q_space-- <= 0))
  192. goto stop;
  193. smp_mb();
  194. --tx_queue->stopped;
  195. }
  196. insert_ptr = (tx_queue->insert_count &
  197. efx->type->txd_ring_mask);
  198. buffer = &tx_queue->buffer[insert_ptr];
  199. efx_tsoh_free(tx_queue, buffer);
  200. EFX_BUG_ON_PARANOID(buffer->tsoh);
  201. EFX_BUG_ON_PARANOID(buffer->skb);
  202. EFX_BUG_ON_PARANOID(buffer->len);
  203. EFX_BUG_ON_PARANOID(!buffer->continuation);
  204. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  205. dma_len = (((~dma_addr) & efx->type->tx_dma_mask) + 1);
  206. if (likely(dma_len > len))
  207. dma_len = len;
  208. misalign = (unsigned)dma_addr & efx->type->bug5391_mask;
  209. if (misalign && dma_len + misalign > 512)
  210. dma_len = 512 - misalign;
  211. /* Fill out per descriptor fields */
  212. buffer->len = dma_len;
  213. buffer->dma_addr = dma_addr;
  214. len -= dma_len;
  215. dma_addr += dma_len;
  216. ++tx_queue->insert_count;
  217. } while (len);
  218. /* Transfer ownership of the unmapping to the final buffer */
  219. buffer->unmap_single = unmap_single;
  220. buffer->unmap_len = unmap_len;
  221. unmap_len = 0;
  222. /* Get address and size of next fragment */
  223. if (i >= skb_shinfo(skb)->nr_frags)
  224. break;
  225. fragment = &skb_shinfo(skb)->frags[i];
  226. len = fragment->size;
  227. page = fragment->page;
  228. page_offset = fragment->page_offset;
  229. i++;
  230. /* Map for DMA */
  231. unmap_single = false;
  232. dma_addr = pci_map_page(pci_dev, page, page_offset, len,
  233. PCI_DMA_TODEVICE);
  234. }
  235. /* Transfer ownership of the skb to the final buffer */
  236. buffer->skb = skb;
  237. buffer->continuation = false;
  238. /* Pass off to hardware */
  239. falcon_push_buffers(tx_queue);
  240. return NETDEV_TX_OK;
  241. pci_err:
  242. EFX_ERR_RL(efx, " TX queue %d could not map skb with %d bytes %d "
  243. "fragments for DMA\n", tx_queue->queue, skb->len,
  244. skb_shinfo(skb)->nr_frags + 1);
  245. /* Mark the packet as transmitted, and free the SKB ourselves */
  246. dev_kfree_skb_any((struct sk_buff *)skb);
  247. goto unwind;
  248. stop:
  249. rc = NETDEV_TX_BUSY;
  250. if (tx_queue->stopped == 1)
  251. efx_stop_queue(efx);
  252. unwind:
  253. /* Work backwards until we hit the original insert pointer value */
  254. while (tx_queue->insert_count != tx_queue->write_count) {
  255. --tx_queue->insert_count;
  256. insert_ptr = tx_queue->insert_count & efx->type->txd_ring_mask;
  257. buffer = &tx_queue->buffer[insert_ptr];
  258. efx_dequeue_buffer(tx_queue, buffer);
  259. buffer->len = 0;
  260. }
  261. /* Free the fragment we were mid-way through pushing */
  262. if (unmap_len) {
  263. if (unmap_single)
  264. pci_unmap_single(pci_dev, unmap_addr, unmap_len,
  265. PCI_DMA_TODEVICE);
  266. else
  267. pci_unmap_page(pci_dev, unmap_addr, unmap_len,
  268. PCI_DMA_TODEVICE);
  269. }
  270. return rc;
  271. }
  272. /* Remove packets from the TX queue
  273. *
  274. * This removes packets from the TX queue, up to and including the
  275. * specified index.
  276. */
  277. static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  278. unsigned int index)
  279. {
  280. struct efx_nic *efx = tx_queue->efx;
  281. unsigned int stop_index, read_ptr;
  282. unsigned int mask = tx_queue->efx->type->txd_ring_mask;
  283. stop_index = (index + 1) & mask;
  284. read_ptr = tx_queue->read_count & mask;
  285. while (read_ptr != stop_index) {
  286. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  287. if (unlikely(buffer->len == 0)) {
  288. EFX_ERR(tx_queue->efx, "TX queue %d spurious TX "
  289. "completion id %x\n", tx_queue->queue,
  290. read_ptr);
  291. efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  292. return;
  293. }
  294. efx_dequeue_buffer(tx_queue, buffer);
  295. buffer->continuation = true;
  296. buffer->len = 0;
  297. ++tx_queue->read_count;
  298. read_ptr = tx_queue->read_count & mask;
  299. }
  300. }
  301. /* Initiate a packet transmission on the specified TX queue.
  302. * Note that returning anything other than NETDEV_TX_OK will cause the
  303. * OS to free the skb.
  304. *
  305. * This function is split out from efx_hard_start_xmit to allow the
  306. * loopback test to direct packets via specific TX queues. It is
  307. * therefore a non-static inline, so as not to penalise performance
  308. * for non-loopback transmissions.
  309. *
  310. * Context: netif_tx_lock held
  311. */
  312. inline int efx_xmit(struct efx_nic *efx,
  313. struct efx_tx_queue *tx_queue, struct sk_buff *skb)
  314. {
  315. int rc;
  316. /* Map fragments for DMA and add to TX queue */
  317. rc = efx_enqueue_skb(tx_queue, skb);
  318. return rc;
  319. }
  320. /* Initiate a packet transmission. We use one channel per CPU
  321. * (sharing when we have more CPUs than channels). On Falcon, the TX
  322. * completion events will be directed back to the CPU that transmitted
  323. * the packet, which should be cache-efficient.
  324. *
  325. * Context: non-blocking.
  326. * Note that returning anything other than NETDEV_TX_OK will cause the
  327. * OS to free the skb.
  328. */
  329. int efx_hard_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
  330. {
  331. struct efx_nic *efx = netdev_priv(net_dev);
  332. struct efx_tx_queue *tx_queue;
  333. if (unlikely(efx->port_inhibited))
  334. return NETDEV_TX_BUSY;
  335. if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
  336. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_OFFLOAD_CSUM];
  337. else
  338. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_NO_CSUM];
  339. return efx_xmit(efx, tx_queue, skb);
  340. }
  341. void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  342. {
  343. unsigned fill_level;
  344. struct efx_nic *efx = tx_queue->efx;
  345. EFX_BUG_ON_PARANOID(index > efx->type->txd_ring_mask);
  346. efx_dequeue_buffers(tx_queue, index);
  347. /* See if we need to restart the netif queue. This barrier
  348. * separates the update of read_count from the test of
  349. * stopped. */
  350. smp_mb();
  351. if (unlikely(tx_queue->stopped) && likely(efx->port_enabled)) {
  352. fill_level = tx_queue->insert_count - tx_queue->read_count;
  353. if (fill_level < EFX_NETDEV_TX_THRESHOLD(tx_queue)) {
  354. EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
  355. /* Do this under netif_tx_lock(), to avoid racing
  356. * with efx_xmit(). */
  357. netif_tx_lock(efx->net_dev);
  358. if (tx_queue->stopped) {
  359. tx_queue->stopped = 0;
  360. efx_wake_queue(efx);
  361. }
  362. netif_tx_unlock(efx->net_dev);
  363. }
  364. }
  365. }
  366. int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
  367. {
  368. struct efx_nic *efx = tx_queue->efx;
  369. unsigned int txq_size;
  370. int i, rc;
  371. EFX_LOG(efx, "creating TX queue %d\n", tx_queue->queue);
  372. /* Allocate software ring */
  373. txq_size = (efx->type->txd_ring_mask + 1) * sizeof(*tx_queue->buffer);
  374. tx_queue->buffer = kzalloc(txq_size, GFP_KERNEL);
  375. if (!tx_queue->buffer)
  376. return -ENOMEM;
  377. for (i = 0; i <= efx->type->txd_ring_mask; ++i)
  378. tx_queue->buffer[i].continuation = true;
  379. /* Allocate hardware ring */
  380. rc = falcon_probe_tx(tx_queue);
  381. if (rc)
  382. goto fail;
  383. return 0;
  384. fail:
  385. kfree(tx_queue->buffer);
  386. tx_queue->buffer = NULL;
  387. return rc;
  388. }
  389. void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
  390. {
  391. EFX_LOG(tx_queue->efx, "initialising TX queue %d\n", tx_queue->queue);
  392. tx_queue->insert_count = 0;
  393. tx_queue->write_count = 0;
  394. tx_queue->read_count = 0;
  395. tx_queue->old_read_count = 0;
  396. BUG_ON(tx_queue->stopped);
  397. /* Set up TX descriptor ring */
  398. falcon_init_tx(tx_queue);
  399. }
  400. void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
  401. {
  402. struct efx_tx_buffer *buffer;
  403. if (!tx_queue->buffer)
  404. return;
  405. /* Free any buffers left in the ring */
  406. while (tx_queue->read_count != tx_queue->write_count) {
  407. buffer = &tx_queue->buffer[tx_queue->read_count &
  408. tx_queue->efx->type->txd_ring_mask];
  409. efx_dequeue_buffer(tx_queue, buffer);
  410. buffer->continuation = true;
  411. buffer->len = 0;
  412. ++tx_queue->read_count;
  413. }
  414. }
  415. void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
  416. {
  417. EFX_LOG(tx_queue->efx, "shutting down TX queue %d\n", tx_queue->queue);
  418. /* Flush TX queue, remove descriptor ring */
  419. falcon_fini_tx(tx_queue);
  420. efx_release_tx_buffers(tx_queue);
  421. /* Free up TSO header cache */
  422. efx_fini_tso(tx_queue);
  423. /* Release queue's stop on port, if any */
  424. if (tx_queue->stopped) {
  425. tx_queue->stopped = 0;
  426. efx_wake_queue(tx_queue->efx);
  427. }
  428. }
  429. void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
  430. {
  431. EFX_LOG(tx_queue->efx, "destroying TX queue %d\n", tx_queue->queue);
  432. falcon_remove_tx(tx_queue);
  433. kfree(tx_queue->buffer);
  434. tx_queue->buffer = NULL;
  435. }
  436. /* Efx TCP segmentation acceleration.
  437. *
  438. * Why? Because by doing it here in the driver we can go significantly
  439. * faster than the GSO.
  440. *
  441. * Requires TX checksum offload support.
  442. */
  443. /* Number of bytes inserted at the start of a TSO header buffer,
  444. * similar to NET_IP_ALIGN.
  445. */
  446. #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  447. #define TSOH_OFFSET 0
  448. #else
  449. #define TSOH_OFFSET NET_IP_ALIGN
  450. #endif
  451. #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
  452. /* Total size of struct efx_tso_header, buffer and padding */
  453. #define TSOH_SIZE(hdr_len) \
  454. (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
  455. /* Size of blocks on free list. Larger blocks must be allocated from
  456. * the heap.
  457. */
  458. #define TSOH_STD_SIZE 128
  459. #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
  460. #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
  461. #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
  462. #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
  463. /**
  464. * struct tso_state - TSO state for an SKB
  465. * @out_len: Remaining length in current segment
  466. * @seqnum: Current sequence number
  467. * @ipv4_id: Current IPv4 ID, host endian
  468. * @packet_space: Remaining space in current packet
  469. * @dma_addr: DMA address of current position
  470. * @in_len: Remaining length in current SKB fragment
  471. * @unmap_len: Length of SKB fragment
  472. * @unmap_addr: DMA address of SKB fragment
  473. * @unmap_single: DMA single vs page mapping flag
  474. * @header_len: Number of bytes of header
  475. * @full_packet_size: Number of bytes to put in each outgoing segment
  476. *
  477. * The state used during segmentation. It is put into this data structure
  478. * just to make it easy to pass into inline functions.
  479. */
  480. struct tso_state {
  481. /* Output position */
  482. unsigned out_len;
  483. unsigned seqnum;
  484. unsigned ipv4_id;
  485. unsigned packet_space;
  486. /* Input position */
  487. dma_addr_t dma_addr;
  488. unsigned in_len;
  489. unsigned unmap_len;
  490. dma_addr_t unmap_addr;
  491. bool unmap_single;
  492. unsigned header_len;
  493. int full_packet_size;
  494. };
  495. /*
  496. * Verify that our various assumptions about sk_buffs and the conditions
  497. * under which TSO will be attempted hold true.
  498. */
  499. static void efx_tso_check_safe(struct sk_buff *skb)
  500. {
  501. __be16 protocol = skb->protocol;
  502. EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
  503. protocol);
  504. if (protocol == htons(ETH_P_8021Q)) {
  505. /* Find the encapsulated protocol; reset network header
  506. * and transport header based on that. */
  507. struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
  508. protocol = veh->h_vlan_encapsulated_proto;
  509. skb_set_network_header(skb, sizeof(*veh));
  510. if (protocol == htons(ETH_P_IP))
  511. skb_set_transport_header(skb, sizeof(*veh) +
  512. 4 * ip_hdr(skb)->ihl);
  513. }
  514. EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IP));
  515. EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
  516. EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
  517. + (tcp_hdr(skb)->doff << 2u)) >
  518. skb_headlen(skb));
  519. }
  520. /*
  521. * Allocate a page worth of efx_tso_header structures, and string them
  522. * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
  523. */
  524. static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
  525. {
  526. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  527. struct efx_tso_header *tsoh;
  528. dma_addr_t dma_addr;
  529. u8 *base_kva, *kva;
  530. base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
  531. if (base_kva == NULL) {
  532. EFX_ERR(tx_queue->efx, "Unable to allocate page for TSO"
  533. " headers\n");
  534. return -ENOMEM;
  535. }
  536. /* pci_alloc_consistent() allocates pages. */
  537. EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
  538. for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
  539. tsoh = (struct efx_tso_header *)kva;
  540. tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
  541. tsoh->next = tx_queue->tso_headers_free;
  542. tx_queue->tso_headers_free = tsoh;
  543. }
  544. return 0;
  545. }
  546. /* Free up a TSO header, and all others in the same page. */
  547. static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
  548. struct efx_tso_header *tsoh,
  549. struct pci_dev *pci_dev)
  550. {
  551. struct efx_tso_header **p;
  552. unsigned long base_kva;
  553. dma_addr_t base_dma;
  554. base_kva = (unsigned long)tsoh & PAGE_MASK;
  555. base_dma = tsoh->dma_addr & PAGE_MASK;
  556. p = &tx_queue->tso_headers_free;
  557. while (*p != NULL) {
  558. if (((unsigned long)*p & PAGE_MASK) == base_kva)
  559. *p = (*p)->next;
  560. else
  561. p = &(*p)->next;
  562. }
  563. pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
  564. }
  565. static struct efx_tso_header *
  566. efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
  567. {
  568. struct efx_tso_header *tsoh;
  569. tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
  570. if (unlikely(!tsoh))
  571. return NULL;
  572. tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
  573. TSOH_BUFFER(tsoh), header_len,
  574. PCI_DMA_TODEVICE);
  575. if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev,
  576. tsoh->dma_addr))) {
  577. kfree(tsoh);
  578. return NULL;
  579. }
  580. tsoh->unmap_len = header_len;
  581. return tsoh;
  582. }
  583. static void
  584. efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
  585. {
  586. pci_unmap_single(tx_queue->efx->pci_dev,
  587. tsoh->dma_addr, tsoh->unmap_len,
  588. PCI_DMA_TODEVICE);
  589. kfree(tsoh);
  590. }
  591. /**
  592. * efx_tx_queue_insert - push descriptors onto the TX queue
  593. * @tx_queue: Efx TX queue
  594. * @dma_addr: DMA address of fragment
  595. * @len: Length of fragment
  596. * @final_buffer: The final buffer inserted into the queue
  597. *
  598. * Push descriptors onto the TX queue. Return 0 on success or 1 if
  599. * @tx_queue full.
  600. */
  601. static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
  602. dma_addr_t dma_addr, unsigned len,
  603. struct efx_tx_buffer **final_buffer)
  604. {
  605. struct efx_tx_buffer *buffer;
  606. struct efx_nic *efx = tx_queue->efx;
  607. unsigned dma_len, fill_level, insert_ptr, misalign;
  608. int q_space;
  609. EFX_BUG_ON_PARANOID(len <= 0);
  610. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  611. /* -1 as there is no way to represent all descriptors used */
  612. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  613. while (1) {
  614. if (unlikely(q_space-- <= 0)) {
  615. /* It might be that completions have happened
  616. * since the xmit path last checked. Update
  617. * the xmit path's copy of read_count.
  618. */
  619. ++tx_queue->stopped;
  620. /* This memory barrier protects the change of
  621. * stopped from the access of read_count. */
  622. smp_mb();
  623. tx_queue->old_read_count =
  624. *(volatile unsigned *)&tx_queue->read_count;
  625. fill_level = (tx_queue->insert_count
  626. - tx_queue->old_read_count);
  627. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  628. if (unlikely(q_space-- <= 0)) {
  629. *final_buffer = NULL;
  630. return 1;
  631. }
  632. smp_mb();
  633. --tx_queue->stopped;
  634. }
  635. insert_ptr = tx_queue->insert_count & efx->type->txd_ring_mask;
  636. buffer = &tx_queue->buffer[insert_ptr];
  637. ++tx_queue->insert_count;
  638. EFX_BUG_ON_PARANOID(tx_queue->insert_count -
  639. tx_queue->read_count >
  640. efx->type->txd_ring_mask);
  641. efx_tsoh_free(tx_queue, buffer);
  642. EFX_BUG_ON_PARANOID(buffer->len);
  643. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  644. EFX_BUG_ON_PARANOID(buffer->skb);
  645. EFX_BUG_ON_PARANOID(!buffer->continuation);
  646. EFX_BUG_ON_PARANOID(buffer->tsoh);
  647. buffer->dma_addr = dma_addr;
  648. /* Ensure we do not cross a boundary unsupported by H/W */
  649. dma_len = (~dma_addr & efx->type->tx_dma_mask) + 1;
  650. misalign = (unsigned)dma_addr & efx->type->bug5391_mask;
  651. if (misalign && dma_len + misalign > 512)
  652. dma_len = 512 - misalign;
  653. /* If there is enough space to send then do so */
  654. if (dma_len >= len)
  655. break;
  656. buffer->len = dma_len; /* Don't set the other members */
  657. dma_addr += dma_len;
  658. len -= dma_len;
  659. }
  660. EFX_BUG_ON_PARANOID(!len);
  661. buffer->len = len;
  662. *final_buffer = buffer;
  663. return 0;
  664. }
  665. /*
  666. * Put a TSO header into the TX queue.
  667. *
  668. * This is special-cased because we know that it is small enough to fit in
  669. * a single fragment, and we know it doesn't cross a page boundary. It
  670. * also allows us to not worry about end-of-packet etc.
  671. */
  672. static void efx_tso_put_header(struct efx_tx_queue *tx_queue,
  673. struct efx_tso_header *tsoh, unsigned len)
  674. {
  675. struct efx_tx_buffer *buffer;
  676. buffer = &tx_queue->buffer[tx_queue->insert_count &
  677. tx_queue->efx->type->txd_ring_mask];
  678. efx_tsoh_free(tx_queue, buffer);
  679. EFX_BUG_ON_PARANOID(buffer->len);
  680. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  681. EFX_BUG_ON_PARANOID(buffer->skb);
  682. EFX_BUG_ON_PARANOID(!buffer->continuation);
  683. EFX_BUG_ON_PARANOID(buffer->tsoh);
  684. buffer->len = len;
  685. buffer->dma_addr = tsoh->dma_addr;
  686. buffer->tsoh = tsoh;
  687. ++tx_queue->insert_count;
  688. }
  689. /* Remove descriptors put into a tx_queue. */
  690. static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
  691. {
  692. struct efx_tx_buffer *buffer;
  693. dma_addr_t unmap_addr;
  694. /* Work backwards until we hit the original insert pointer value */
  695. while (tx_queue->insert_count != tx_queue->write_count) {
  696. --tx_queue->insert_count;
  697. buffer = &tx_queue->buffer[tx_queue->insert_count &
  698. tx_queue->efx->type->txd_ring_mask];
  699. efx_tsoh_free(tx_queue, buffer);
  700. EFX_BUG_ON_PARANOID(buffer->skb);
  701. buffer->len = 0;
  702. buffer->continuation = true;
  703. if (buffer->unmap_len) {
  704. unmap_addr = (buffer->dma_addr + buffer->len -
  705. buffer->unmap_len);
  706. if (buffer->unmap_single)
  707. pci_unmap_single(tx_queue->efx->pci_dev,
  708. unmap_addr, buffer->unmap_len,
  709. PCI_DMA_TODEVICE);
  710. else
  711. pci_unmap_page(tx_queue->efx->pci_dev,
  712. unmap_addr, buffer->unmap_len,
  713. PCI_DMA_TODEVICE);
  714. buffer->unmap_len = 0;
  715. }
  716. }
  717. }
  718. /* Parse the SKB header and initialise state. */
  719. static void tso_start(struct tso_state *st, const struct sk_buff *skb)
  720. {
  721. /* All ethernet/IP/TCP headers combined size is TCP header size
  722. * plus offset of TCP header relative to start of packet.
  723. */
  724. st->header_len = ((tcp_hdr(skb)->doff << 2u)
  725. + PTR_DIFF(tcp_hdr(skb), skb->data));
  726. st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size;
  727. st->ipv4_id = ntohs(ip_hdr(skb)->id);
  728. st->seqnum = ntohl(tcp_hdr(skb)->seq);
  729. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
  730. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
  731. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
  732. st->packet_space = st->full_packet_size;
  733. st->out_len = skb->len - st->header_len;
  734. st->unmap_len = 0;
  735. st->unmap_single = false;
  736. }
  737. static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
  738. skb_frag_t *frag)
  739. {
  740. st->unmap_addr = pci_map_page(efx->pci_dev, frag->page,
  741. frag->page_offset, frag->size,
  742. PCI_DMA_TODEVICE);
  743. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  744. st->unmap_single = false;
  745. st->unmap_len = frag->size;
  746. st->in_len = frag->size;
  747. st->dma_addr = st->unmap_addr;
  748. return 0;
  749. }
  750. return -ENOMEM;
  751. }
  752. static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx,
  753. const struct sk_buff *skb)
  754. {
  755. int hl = st->header_len;
  756. int len = skb_headlen(skb) - hl;
  757. st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl,
  758. len, PCI_DMA_TODEVICE);
  759. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  760. st->unmap_single = true;
  761. st->unmap_len = len;
  762. st->in_len = len;
  763. st->dma_addr = st->unmap_addr;
  764. return 0;
  765. }
  766. return -ENOMEM;
  767. }
  768. /**
  769. * tso_fill_packet_with_fragment - form descriptors for the current fragment
  770. * @tx_queue: Efx TX queue
  771. * @skb: Socket buffer
  772. * @st: TSO state
  773. *
  774. * Form descriptors for the current fragment, until we reach the end
  775. * of fragment or end-of-packet. Return 0 on success, 1 if not enough
  776. * space in @tx_queue.
  777. */
  778. static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
  779. const struct sk_buff *skb,
  780. struct tso_state *st)
  781. {
  782. struct efx_tx_buffer *buffer;
  783. int n, end_of_packet, rc;
  784. if (st->in_len == 0)
  785. return 0;
  786. if (st->packet_space == 0)
  787. return 0;
  788. EFX_BUG_ON_PARANOID(st->in_len <= 0);
  789. EFX_BUG_ON_PARANOID(st->packet_space <= 0);
  790. n = min(st->in_len, st->packet_space);
  791. st->packet_space -= n;
  792. st->out_len -= n;
  793. st->in_len -= n;
  794. rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
  795. if (likely(rc == 0)) {
  796. if (st->out_len == 0)
  797. /* Transfer ownership of the skb */
  798. buffer->skb = skb;
  799. end_of_packet = st->out_len == 0 || st->packet_space == 0;
  800. buffer->continuation = !end_of_packet;
  801. if (st->in_len == 0) {
  802. /* Transfer ownership of the pci mapping */
  803. buffer->unmap_len = st->unmap_len;
  804. buffer->unmap_single = st->unmap_single;
  805. st->unmap_len = 0;
  806. }
  807. }
  808. st->dma_addr += n;
  809. return rc;
  810. }
  811. /**
  812. * tso_start_new_packet - generate a new header and prepare for the new packet
  813. * @tx_queue: Efx TX queue
  814. * @skb: Socket buffer
  815. * @st: TSO state
  816. *
  817. * Generate a new header and prepare for the new packet. Return 0 on
  818. * success, or -1 if failed to alloc header.
  819. */
  820. static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
  821. const struct sk_buff *skb,
  822. struct tso_state *st)
  823. {
  824. struct efx_tso_header *tsoh;
  825. struct iphdr *tsoh_iph;
  826. struct tcphdr *tsoh_th;
  827. unsigned ip_length;
  828. u8 *header;
  829. /* Allocate a DMA-mapped header buffer. */
  830. if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) {
  831. if (tx_queue->tso_headers_free == NULL) {
  832. if (efx_tsoh_block_alloc(tx_queue))
  833. return -1;
  834. }
  835. EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
  836. tsoh = tx_queue->tso_headers_free;
  837. tx_queue->tso_headers_free = tsoh->next;
  838. tsoh->unmap_len = 0;
  839. } else {
  840. tx_queue->tso_long_headers++;
  841. tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len);
  842. if (unlikely(!tsoh))
  843. return -1;
  844. }
  845. header = TSOH_BUFFER(tsoh);
  846. tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
  847. tsoh_iph = (struct iphdr *)(header + SKB_IPV4_OFF(skb));
  848. /* Copy and update the headers. */
  849. memcpy(header, skb->data, st->header_len);
  850. tsoh_th->seq = htonl(st->seqnum);
  851. st->seqnum += skb_shinfo(skb)->gso_size;
  852. if (st->out_len > skb_shinfo(skb)->gso_size) {
  853. /* This packet will not finish the TSO burst. */
  854. ip_length = st->full_packet_size - ETH_HDR_LEN(skb);
  855. tsoh_th->fin = 0;
  856. tsoh_th->psh = 0;
  857. } else {
  858. /* This packet will be the last in the TSO burst. */
  859. ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len;
  860. tsoh_th->fin = tcp_hdr(skb)->fin;
  861. tsoh_th->psh = tcp_hdr(skb)->psh;
  862. }
  863. tsoh_iph->tot_len = htons(ip_length);
  864. /* Linux leaves suitable gaps in the IP ID space for us to fill. */
  865. tsoh_iph->id = htons(st->ipv4_id);
  866. st->ipv4_id++;
  867. st->packet_space = skb_shinfo(skb)->gso_size;
  868. ++tx_queue->tso_packets;
  869. /* Form a descriptor for this header. */
  870. efx_tso_put_header(tx_queue, tsoh, st->header_len);
  871. return 0;
  872. }
  873. /**
  874. * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
  875. * @tx_queue: Efx TX queue
  876. * @skb: Socket buffer
  877. *
  878. * Context: You must hold netif_tx_lock() to call this function.
  879. *
  880. * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
  881. * @skb was not enqueued. In all cases @skb is consumed. Return
  882. * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
  883. */
  884. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  885. struct sk_buff *skb)
  886. {
  887. struct efx_nic *efx = tx_queue->efx;
  888. int frag_i, rc, rc2 = NETDEV_TX_OK;
  889. struct tso_state state;
  890. /* Verify TSO is safe - these checks should never fail. */
  891. efx_tso_check_safe(skb);
  892. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  893. tso_start(&state, skb);
  894. /* Assume that skb header area contains exactly the headers, and
  895. * all payload is in the frag list.
  896. */
  897. if (skb_headlen(skb) == state.header_len) {
  898. /* Grab the first payload fragment. */
  899. EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
  900. frag_i = 0;
  901. rc = tso_get_fragment(&state, efx,
  902. skb_shinfo(skb)->frags + frag_i);
  903. if (rc)
  904. goto mem_err;
  905. } else {
  906. rc = tso_get_head_fragment(&state, efx, skb);
  907. if (rc)
  908. goto mem_err;
  909. frag_i = -1;
  910. }
  911. if (tso_start_new_packet(tx_queue, skb, &state) < 0)
  912. goto mem_err;
  913. while (1) {
  914. rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
  915. if (unlikely(rc))
  916. goto stop;
  917. /* Move onto the next fragment? */
  918. if (state.in_len == 0) {
  919. if (++frag_i >= skb_shinfo(skb)->nr_frags)
  920. /* End of payload reached. */
  921. break;
  922. rc = tso_get_fragment(&state, efx,
  923. skb_shinfo(skb)->frags + frag_i);
  924. if (rc)
  925. goto mem_err;
  926. }
  927. /* Start at new packet? */
  928. if (state.packet_space == 0 &&
  929. tso_start_new_packet(tx_queue, skb, &state) < 0)
  930. goto mem_err;
  931. }
  932. /* Pass off to hardware */
  933. falcon_push_buffers(tx_queue);
  934. tx_queue->tso_bursts++;
  935. return NETDEV_TX_OK;
  936. mem_err:
  937. EFX_ERR(efx, "Out of memory for TSO headers, or PCI mapping error\n");
  938. dev_kfree_skb_any((struct sk_buff *)skb);
  939. goto unwind;
  940. stop:
  941. rc2 = NETDEV_TX_BUSY;
  942. /* Stop the queue if it wasn't stopped before. */
  943. if (tx_queue->stopped == 1)
  944. efx_stop_queue(efx);
  945. unwind:
  946. /* Free the DMA mapping we were in the process of writing out */
  947. if (state.unmap_len) {
  948. if (state.unmap_single)
  949. pci_unmap_single(efx->pci_dev, state.unmap_addr,
  950. state.unmap_len, PCI_DMA_TODEVICE);
  951. else
  952. pci_unmap_page(efx->pci_dev, state.unmap_addr,
  953. state.unmap_len, PCI_DMA_TODEVICE);
  954. }
  955. efx_enqueue_unwind(tx_queue);
  956. return rc2;
  957. }
  958. /*
  959. * Free up all TSO datastructures associated with tx_queue. This
  960. * routine should be called only once the tx_queue is both empty and
  961. * will no longer be used.
  962. */
  963. static void efx_fini_tso(struct efx_tx_queue *tx_queue)
  964. {
  965. unsigned i;
  966. if (tx_queue->buffer) {
  967. for (i = 0; i <= tx_queue->efx->type->txd_ring_mask; ++i)
  968. efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
  969. }
  970. while (tx_queue->tso_headers_free != NULL)
  971. efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
  972. tx_queue->efx->pci_dev);
  973. }