dl2k.c 48 KB

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  1. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  2. /*
  3. Copyright (c) 2001, 2002 by D-Link Corporation
  4. Written by Edward Peng.<edward_peng@dlink.com.tw>
  5. Created 03-May-2001, base on Linux' sundance.c.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. */
  11. #define DRV_NAME "DL2000/TC902x-based linux driver"
  12. #define DRV_VERSION "v1.19"
  13. #define DRV_RELDATE "2007/08/12"
  14. #include "dl2k.h"
  15. #include <linux/dma-mapping.h>
  16. static char version[] __devinitdata =
  17. KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
  18. #define MAX_UNITS 8
  19. static int mtu[MAX_UNITS];
  20. static int vlan[MAX_UNITS];
  21. static int jumbo[MAX_UNITS];
  22. static char *media[MAX_UNITS];
  23. static int tx_flow=-1;
  24. static int rx_flow=-1;
  25. static int copy_thresh;
  26. static int rx_coalesce=10; /* Rx frame count each interrupt */
  27. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  28. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  29. MODULE_AUTHOR ("Edward Peng");
  30. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  31. MODULE_LICENSE("GPL");
  32. module_param_array(mtu, int, NULL, 0);
  33. module_param_array(media, charp, NULL, 0);
  34. module_param_array(vlan, int, NULL, 0);
  35. module_param_array(jumbo, int, NULL, 0);
  36. module_param(tx_flow, int, 0);
  37. module_param(rx_flow, int, 0);
  38. module_param(copy_thresh, int, 0);
  39. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  40. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
  41. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  42. /* Enable the default interrupts */
  43. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  44. UpdateStats | LinkEvent)
  45. #define EnableInt() \
  46. writew(DEFAULT_INTR, ioaddr + IntEnable)
  47. static const int max_intrloop = 50;
  48. static const int multicast_filter_limit = 0x40;
  49. static int rio_open (struct net_device *dev);
  50. static void rio_timer (unsigned long data);
  51. static void rio_tx_timeout (struct net_device *dev);
  52. static void alloc_list (struct net_device *dev);
  53. static int start_xmit (struct sk_buff *skb, struct net_device *dev);
  54. static irqreturn_t rio_interrupt (int irq, void *dev_instance);
  55. static void rio_free_tx (struct net_device *dev, int irq);
  56. static void tx_error (struct net_device *dev, int tx_status);
  57. static int receive_packet (struct net_device *dev);
  58. static void rio_error (struct net_device *dev, int int_status);
  59. static int change_mtu (struct net_device *dev, int new_mtu);
  60. static void set_multicast (struct net_device *dev);
  61. static struct net_device_stats *get_stats (struct net_device *dev);
  62. static int clear_stats (struct net_device *dev);
  63. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  64. static int rio_close (struct net_device *dev);
  65. static int find_miiphy (struct net_device *dev);
  66. static int parse_eeprom (struct net_device *dev);
  67. static int read_eeprom (long ioaddr, int eep_addr);
  68. static int mii_wait_link (struct net_device *dev, int wait);
  69. static int mii_set_media (struct net_device *dev);
  70. static int mii_get_media (struct net_device *dev);
  71. static int mii_set_media_pcs (struct net_device *dev);
  72. static int mii_get_media_pcs (struct net_device *dev);
  73. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  74. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  75. u16 data);
  76. static const struct ethtool_ops ethtool_ops;
  77. static const struct net_device_ops netdev_ops = {
  78. .ndo_open = rio_open,
  79. .ndo_start_xmit = start_xmit,
  80. .ndo_stop = rio_close,
  81. .ndo_get_stats = get_stats,
  82. .ndo_validate_addr = eth_validate_addr,
  83. .ndo_set_mac_address = eth_mac_addr,
  84. .ndo_set_multicast_list = set_multicast,
  85. .ndo_do_ioctl = rio_ioctl,
  86. .ndo_tx_timeout = rio_tx_timeout,
  87. .ndo_change_mtu = change_mtu,
  88. };
  89. static int __devinit
  90. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  91. {
  92. struct net_device *dev;
  93. struct netdev_private *np;
  94. static int card_idx;
  95. int chip_idx = ent->driver_data;
  96. int err, irq;
  97. long ioaddr;
  98. static int version_printed;
  99. void *ring_space;
  100. dma_addr_t ring_dma;
  101. if (!version_printed++)
  102. printk ("%s", version);
  103. err = pci_enable_device (pdev);
  104. if (err)
  105. return err;
  106. irq = pdev->irq;
  107. err = pci_request_regions (pdev, "dl2k");
  108. if (err)
  109. goto err_out_disable;
  110. pci_set_master (pdev);
  111. dev = alloc_etherdev (sizeof (*np));
  112. if (!dev) {
  113. err = -ENOMEM;
  114. goto err_out_res;
  115. }
  116. SET_NETDEV_DEV(dev, &pdev->dev);
  117. #ifdef MEM_MAPPING
  118. ioaddr = pci_resource_start (pdev, 1);
  119. ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
  120. if (!ioaddr) {
  121. err = -ENOMEM;
  122. goto err_out_dev;
  123. }
  124. #else
  125. ioaddr = pci_resource_start (pdev, 0);
  126. #endif
  127. dev->base_addr = ioaddr;
  128. dev->irq = irq;
  129. np = netdev_priv(dev);
  130. np->chip_id = chip_idx;
  131. np->pdev = pdev;
  132. spin_lock_init (&np->tx_lock);
  133. spin_lock_init (&np->rx_lock);
  134. /* Parse manual configuration */
  135. np->an_enable = 1;
  136. np->tx_coalesce = 1;
  137. if (card_idx < MAX_UNITS) {
  138. if (media[card_idx] != NULL) {
  139. np->an_enable = 0;
  140. if (strcmp (media[card_idx], "auto") == 0 ||
  141. strcmp (media[card_idx], "autosense") == 0 ||
  142. strcmp (media[card_idx], "0") == 0 ) {
  143. np->an_enable = 2;
  144. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  145. strcmp (media[card_idx], "4") == 0) {
  146. np->speed = 100;
  147. np->full_duplex = 1;
  148. } else if (strcmp (media[card_idx], "100mbps_hd") == 0
  149. || strcmp (media[card_idx], "3") == 0) {
  150. np->speed = 100;
  151. np->full_duplex = 0;
  152. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  153. strcmp (media[card_idx], "2") == 0) {
  154. np->speed = 10;
  155. np->full_duplex = 1;
  156. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  157. strcmp (media[card_idx], "1") == 0) {
  158. np->speed = 10;
  159. np->full_duplex = 0;
  160. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  161. strcmp (media[card_idx], "6") == 0) {
  162. np->speed=1000;
  163. np->full_duplex=1;
  164. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  165. strcmp (media[card_idx], "5") == 0) {
  166. np->speed = 1000;
  167. np->full_duplex = 0;
  168. } else {
  169. np->an_enable = 1;
  170. }
  171. }
  172. if (jumbo[card_idx] != 0) {
  173. np->jumbo = 1;
  174. dev->mtu = MAX_JUMBO;
  175. } else {
  176. np->jumbo = 0;
  177. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  178. dev->mtu = mtu[card_idx];
  179. }
  180. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  181. vlan[card_idx] : 0;
  182. if (rx_coalesce > 0 && rx_timeout > 0) {
  183. np->rx_coalesce = rx_coalesce;
  184. np->rx_timeout = rx_timeout;
  185. np->coalesce = 1;
  186. }
  187. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  188. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  189. if (tx_coalesce < 1)
  190. tx_coalesce = 1;
  191. else if (tx_coalesce > TX_RING_SIZE-1)
  192. tx_coalesce = TX_RING_SIZE - 1;
  193. }
  194. dev->netdev_ops = &netdev_ops;
  195. dev->watchdog_timeo = TX_TIMEOUT;
  196. SET_ETHTOOL_OPS(dev, &ethtool_ops);
  197. #if 0
  198. dev->features = NETIF_F_IP_CSUM;
  199. #endif
  200. pci_set_drvdata (pdev, dev);
  201. ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
  202. if (!ring_space)
  203. goto err_out_iounmap;
  204. np->tx_ring = (struct netdev_desc *) ring_space;
  205. np->tx_ring_dma = ring_dma;
  206. ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
  207. if (!ring_space)
  208. goto err_out_unmap_tx;
  209. np->rx_ring = (struct netdev_desc *) ring_space;
  210. np->rx_ring_dma = ring_dma;
  211. /* Parse eeprom data */
  212. parse_eeprom (dev);
  213. /* Find PHY address */
  214. err = find_miiphy (dev);
  215. if (err)
  216. goto err_out_unmap_rx;
  217. /* Fiber device? */
  218. np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
  219. np->link_status = 0;
  220. /* Set media and reset PHY */
  221. if (np->phy_media) {
  222. /* default Auto-Negotiation for fiber deivices */
  223. if (np->an_enable == 2) {
  224. np->an_enable = 1;
  225. }
  226. mii_set_media_pcs (dev);
  227. } else {
  228. /* Auto-Negotiation is mandatory for 1000BASE-T,
  229. IEEE 802.3ab Annex 28D page 14 */
  230. if (np->speed == 1000)
  231. np->an_enable = 1;
  232. mii_set_media (dev);
  233. }
  234. err = register_netdev (dev);
  235. if (err)
  236. goto err_out_unmap_rx;
  237. card_idx++;
  238. printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
  239. dev->name, np->name, dev->dev_addr, irq);
  240. if (tx_coalesce > 1)
  241. printk(KERN_INFO "tx_coalesce:\t%d packets\n",
  242. tx_coalesce);
  243. if (np->coalesce)
  244. printk(KERN_INFO "rx_coalesce:\t%d packets\n"
  245. KERN_INFO "rx_timeout: \t%d ns\n",
  246. np->rx_coalesce, np->rx_timeout*640);
  247. if (np->vlan)
  248. printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
  249. return 0;
  250. err_out_unmap_rx:
  251. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
  252. err_out_unmap_tx:
  253. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
  254. err_out_iounmap:
  255. #ifdef MEM_MAPPING
  256. iounmap ((void *) ioaddr);
  257. err_out_dev:
  258. #endif
  259. free_netdev (dev);
  260. err_out_res:
  261. pci_release_regions (pdev);
  262. err_out_disable:
  263. pci_disable_device (pdev);
  264. return err;
  265. }
  266. static int
  267. find_miiphy (struct net_device *dev)
  268. {
  269. int i, phy_found = 0;
  270. struct netdev_private *np;
  271. long ioaddr;
  272. np = netdev_priv(dev);
  273. ioaddr = dev->base_addr;
  274. np->phy_addr = 1;
  275. for (i = 31; i >= 0; i--) {
  276. int mii_status = mii_read (dev, i, 1);
  277. if (mii_status != 0xffff && mii_status != 0x0000) {
  278. np->phy_addr = i;
  279. phy_found++;
  280. }
  281. }
  282. if (!phy_found) {
  283. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  284. return -ENODEV;
  285. }
  286. return 0;
  287. }
  288. static int
  289. parse_eeprom (struct net_device *dev)
  290. {
  291. int i, j;
  292. long ioaddr = dev->base_addr;
  293. u8 sromdata[256];
  294. u8 *psib;
  295. u32 crc;
  296. PSROM_t psrom = (PSROM_t) sromdata;
  297. struct netdev_private *np = netdev_priv(dev);
  298. int cid, next;
  299. #ifdef MEM_MAPPING
  300. ioaddr = pci_resource_start (np->pdev, 0);
  301. #endif
  302. /* Read eeprom */
  303. for (i = 0; i < 128; i++) {
  304. ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom (ioaddr, i));
  305. }
  306. #ifdef MEM_MAPPING
  307. ioaddr = dev->base_addr;
  308. #endif
  309. if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
  310. /* Check CRC */
  311. crc = ~ether_crc_le (256 - 4, sromdata);
  312. if (psrom->crc != crc) {
  313. printk (KERN_ERR "%s: EEPROM data CRC error.\n",
  314. dev->name);
  315. return -1;
  316. }
  317. }
  318. /* Set MAC address */
  319. for (i = 0; i < 6; i++)
  320. dev->dev_addr[i] = psrom->mac_addr[i];
  321. if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
  322. return 0;
  323. }
  324. /* Parse Software Information Block */
  325. i = 0x30;
  326. psib = (u8 *) sromdata;
  327. do {
  328. cid = psib[i++];
  329. next = psib[i++];
  330. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  331. printk (KERN_ERR "Cell data error\n");
  332. return -1;
  333. }
  334. switch (cid) {
  335. case 0: /* Format version */
  336. break;
  337. case 1: /* End of cell */
  338. return 0;
  339. case 2: /* Duplex Polarity */
  340. np->duplex_polarity = psib[i];
  341. writeb (readb (ioaddr + PhyCtrl) | psib[i],
  342. ioaddr + PhyCtrl);
  343. break;
  344. case 3: /* Wake Polarity */
  345. np->wake_polarity = psib[i];
  346. break;
  347. case 9: /* Adapter description */
  348. j = (next - i > 255) ? 255 : next - i;
  349. memcpy (np->name, &(psib[i]), j);
  350. break;
  351. case 4:
  352. case 5:
  353. case 6:
  354. case 7:
  355. case 8: /* Reversed */
  356. break;
  357. default: /* Unknown cell */
  358. return -1;
  359. }
  360. i = next;
  361. } while (1);
  362. return 0;
  363. }
  364. static int
  365. rio_open (struct net_device *dev)
  366. {
  367. struct netdev_private *np = netdev_priv(dev);
  368. long ioaddr = dev->base_addr;
  369. int i;
  370. u16 macctrl;
  371. i = request_irq (dev->irq, &rio_interrupt, IRQF_SHARED, dev->name, dev);
  372. if (i)
  373. return i;
  374. /* Reset all logic functions */
  375. writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
  376. ioaddr + ASICCtrl + 2);
  377. mdelay(10);
  378. /* DebugCtrl bit 4, 5, 9 must set */
  379. writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
  380. /* Jumbo frame */
  381. if (np->jumbo != 0)
  382. writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
  383. alloc_list (dev);
  384. /* Get station address */
  385. for (i = 0; i < 6; i++)
  386. writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
  387. set_multicast (dev);
  388. if (np->coalesce) {
  389. writel (np->rx_coalesce | np->rx_timeout << 16,
  390. ioaddr + RxDMAIntCtrl);
  391. }
  392. /* Set RIO to poll every N*320nsec. */
  393. writeb (0x20, ioaddr + RxDMAPollPeriod);
  394. writeb (0xff, ioaddr + TxDMAPollPeriod);
  395. writeb (0x30, ioaddr + RxDMABurstThresh);
  396. writeb (0x30, ioaddr + RxDMAUrgentThresh);
  397. writel (0x0007ffff, ioaddr + RmonStatMask);
  398. /* clear statistics */
  399. clear_stats (dev);
  400. /* VLAN supported */
  401. if (np->vlan) {
  402. /* priority field in RxDMAIntCtrl */
  403. writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
  404. ioaddr + RxDMAIntCtrl);
  405. /* VLANId */
  406. writew (np->vlan, ioaddr + VLANId);
  407. /* Length/Type should be 0x8100 */
  408. writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
  409. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  410. VLAN information tagged by TFC' VID, CFI fields. */
  411. writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
  412. ioaddr + MACCtrl);
  413. }
  414. init_timer (&np->timer);
  415. np->timer.expires = jiffies + 1*HZ;
  416. np->timer.data = (unsigned long) dev;
  417. np->timer.function = &rio_timer;
  418. add_timer (&np->timer);
  419. /* Start Tx/Rx */
  420. writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
  421. ioaddr + MACCtrl);
  422. macctrl = 0;
  423. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  424. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  425. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  426. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  427. writew(macctrl, ioaddr + MACCtrl);
  428. netif_start_queue (dev);
  429. /* Enable default interrupts */
  430. EnableInt ();
  431. return 0;
  432. }
  433. static void
  434. rio_timer (unsigned long data)
  435. {
  436. struct net_device *dev = (struct net_device *)data;
  437. struct netdev_private *np = netdev_priv(dev);
  438. unsigned int entry;
  439. int next_tick = 1*HZ;
  440. unsigned long flags;
  441. spin_lock_irqsave(&np->rx_lock, flags);
  442. /* Recover rx ring exhausted error */
  443. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  444. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  445. /* Re-allocate skbuffs to fill the descriptor ring */
  446. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  447. struct sk_buff *skb;
  448. entry = np->old_rx % RX_RING_SIZE;
  449. /* Dropped packets don't need to re-allocate */
  450. if (np->rx_skbuff[entry] == NULL) {
  451. skb = netdev_alloc_skb (dev, np->rx_buf_sz);
  452. if (skb == NULL) {
  453. np->rx_ring[entry].fraginfo = 0;
  454. printk (KERN_INFO
  455. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  456. dev->name, entry);
  457. break;
  458. }
  459. np->rx_skbuff[entry] = skb;
  460. /* 16 byte align the IP header */
  461. skb_reserve (skb, 2);
  462. np->rx_ring[entry].fraginfo =
  463. cpu_to_le64 (pci_map_single
  464. (np->pdev, skb->data, np->rx_buf_sz,
  465. PCI_DMA_FROMDEVICE));
  466. }
  467. np->rx_ring[entry].fraginfo |=
  468. cpu_to_le64((u64)np->rx_buf_sz << 48);
  469. np->rx_ring[entry].status = 0;
  470. } /* end for */
  471. } /* end if */
  472. spin_unlock_irqrestore (&np->rx_lock, flags);
  473. np->timer.expires = jiffies + next_tick;
  474. add_timer(&np->timer);
  475. }
  476. static void
  477. rio_tx_timeout (struct net_device *dev)
  478. {
  479. long ioaddr = dev->base_addr;
  480. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  481. dev->name, readl (ioaddr + TxStatus));
  482. rio_free_tx(dev, 0);
  483. dev->if_port = 0;
  484. dev->trans_start = jiffies; /* prevent tx timeout */
  485. }
  486. /* allocate and initialize Tx and Rx descriptors */
  487. static void
  488. alloc_list (struct net_device *dev)
  489. {
  490. struct netdev_private *np = netdev_priv(dev);
  491. int i;
  492. np->cur_rx = np->cur_tx = 0;
  493. np->old_rx = np->old_tx = 0;
  494. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  495. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  496. for (i = 0; i < TX_RING_SIZE; i++) {
  497. np->tx_skbuff[i] = NULL;
  498. np->tx_ring[i].status = cpu_to_le64 (TFDDone);
  499. np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
  500. ((i+1)%TX_RING_SIZE) *
  501. sizeof (struct netdev_desc));
  502. }
  503. /* Initialize Rx descriptors */
  504. for (i = 0; i < RX_RING_SIZE; i++) {
  505. np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
  506. ((i + 1) % RX_RING_SIZE) *
  507. sizeof (struct netdev_desc));
  508. np->rx_ring[i].status = 0;
  509. np->rx_ring[i].fraginfo = 0;
  510. np->rx_skbuff[i] = NULL;
  511. }
  512. /* Allocate the rx buffers */
  513. for (i = 0; i < RX_RING_SIZE; i++) {
  514. /* Allocated fixed size of skbuff */
  515. struct sk_buff *skb = netdev_alloc_skb (dev, np->rx_buf_sz);
  516. np->rx_skbuff[i] = skb;
  517. if (skb == NULL) {
  518. printk (KERN_ERR
  519. "%s: alloc_list: allocate Rx buffer error! ",
  520. dev->name);
  521. break;
  522. }
  523. skb_reserve (skb, 2); /* 16 byte align the IP header. */
  524. /* Rubicon now supports 40 bits of addressing space. */
  525. np->rx_ring[i].fraginfo =
  526. cpu_to_le64 ( pci_map_single (
  527. np->pdev, skb->data, np->rx_buf_sz,
  528. PCI_DMA_FROMDEVICE));
  529. np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
  530. }
  531. /* Set RFDListPtr */
  532. writel (np->rx_ring_dma, dev->base_addr + RFDListPtr0);
  533. writel (0, dev->base_addr + RFDListPtr1);
  534. return;
  535. }
  536. static int
  537. start_xmit (struct sk_buff *skb, struct net_device *dev)
  538. {
  539. struct netdev_private *np = netdev_priv(dev);
  540. struct netdev_desc *txdesc;
  541. unsigned entry;
  542. u32 ioaddr;
  543. u64 tfc_vlan_tag = 0;
  544. if (np->link_status == 0) { /* Link Down */
  545. dev_kfree_skb(skb);
  546. return NETDEV_TX_OK;
  547. }
  548. ioaddr = dev->base_addr;
  549. entry = np->cur_tx % TX_RING_SIZE;
  550. np->tx_skbuff[entry] = skb;
  551. txdesc = &np->tx_ring[entry];
  552. #if 0
  553. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  554. txdesc->status |=
  555. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  556. IPChecksumEnable);
  557. }
  558. #endif
  559. if (np->vlan) {
  560. tfc_vlan_tag = VLANTagInsert |
  561. ((u64)np->vlan << 32) |
  562. ((u64)skb->priority << 45);
  563. }
  564. txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
  565. skb->len,
  566. PCI_DMA_TODEVICE));
  567. txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
  568. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  569. * Work around: Always use 1 descriptor in 10Mbps mode */
  570. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  571. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  572. WordAlignDisable |
  573. TxDMAIndicate |
  574. (1 << FragCountShift));
  575. else
  576. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  577. WordAlignDisable |
  578. (1 << FragCountShift));
  579. /* TxDMAPollNow */
  580. writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
  581. /* Schedule ISR */
  582. writel(10000, ioaddr + CountDown);
  583. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  584. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  585. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  586. /* do nothing */
  587. } else if (!netif_queue_stopped(dev)) {
  588. netif_stop_queue (dev);
  589. }
  590. /* The first TFDListPtr */
  591. if (readl (dev->base_addr + TFDListPtr0) == 0) {
  592. writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
  593. dev->base_addr + TFDListPtr0);
  594. writel (0, dev->base_addr + TFDListPtr1);
  595. }
  596. return NETDEV_TX_OK;
  597. }
  598. static irqreturn_t
  599. rio_interrupt (int irq, void *dev_instance)
  600. {
  601. struct net_device *dev = dev_instance;
  602. struct netdev_private *np;
  603. unsigned int_status;
  604. long ioaddr;
  605. int cnt = max_intrloop;
  606. int handled = 0;
  607. ioaddr = dev->base_addr;
  608. np = netdev_priv(dev);
  609. while (1) {
  610. int_status = readw (ioaddr + IntStatus);
  611. writew (int_status, ioaddr + IntStatus);
  612. int_status &= DEFAULT_INTR;
  613. if (int_status == 0 || --cnt < 0)
  614. break;
  615. handled = 1;
  616. /* Processing received packets */
  617. if (int_status & RxDMAComplete)
  618. receive_packet (dev);
  619. /* TxDMAComplete interrupt */
  620. if ((int_status & (TxDMAComplete|IntRequested))) {
  621. int tx_status;
  622. tx_status = readl (ioaddr + TxStatus);
  623. if (tx_status & 0x01)
  624. tx_error (dev, tx_status);
  625. /* Free used tx skbuffs */
  626. rio_free_tx (dev, 1);
  627. }
  628. /* Handle uncommon events */
  629. if (int_status &
  630. (HostError | LinkEvent | UpdateStats))
  631. rio_error (dev, int_status);
  632. }
  633. if (np->cur_tx != np->old_tx)
  634. writel (100, ioaddr + CountDown);
  635. return IRQ_RETVAL(handled);
  636. }
  637. static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
  638. {
  639. return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
  640. }
  641. static void
  642. rio_free_tx (struct net_device *dev, int irq)
  643. {
  644. struct netdev_private *np = netdev_priv(dev);
  645. int entry = np->old_tx % TX_RING_SIZE;
  646. int tx_use = 0;
  647. unsigned long flag = 0;
  648. if (irq)
  649. spin_lock(&np->tx_lock);
  650. else
  651. spin_lock_irqsave(&np->tx_lock, flag);
  652. /* Free used tx skbuffs */
  653. while (entry != np->cur_tx) {
  654. struct sk_buff *skb;
  655. if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
  656. break;
  657. skb = np->tx_skbuff[entry];
  658. pci_unmap_single (np->pdev,
  659. desc_to_dma(&np->tx_ring[entry]),
  660. skb->len, PCI_DMA_TODEVICE);
  661. if (irq)
  662. dev_kfree_skb_irq (skb);
  663. else
  664. dev_kfree_skb (skb);
  665. np->tx_skbuff[entry] = NULL;
  666. entry = (entry + 1) % TX_RING_SIZE;
  667. tx_use++;
  668. }
  669. if (irq)
  670. spin_unlock(&np->tx_lock);
  671. else
  672. spin_unlock_irqrestore(&np->tx_lock, flag);
  673. np->old_tx = entry;
  674. /* If the ring is no longer full, clear tx_full and
  675. call netif_wake_queue() */
  676. if (netif_queue_stopped(dev) &&
  677. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  678. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  679. netif_wake_queue (dev);
  680. }
  681. }
  682. static void
  683. tx_error (struct net_device *dev, int tx_status)
  684. {
  685. struct netdev_private *np;
  686. long ioaddr = dev->base_addr;
  687. int frame_id;
  688. int i;
  689. np = netdev_priv(dev);
  690. frame_id = (tx_status & 0xffff0000);
  691. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  692. dev->name, tx_status, frame_id);
  693. np->stats.tx_errors++;
  694. /* Ttransmit Underrun */
  695. if (tx_status & 0x10) {
  696. np->stats.tx_fifo_errors++;
  697. writew (readw (ioaddr + TxStartThresh) + 0x10,
  698. ioaddr + TxStartThresh);
  699. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  700. writew (TxReset | DMAReset | FIFOReset | NetworkReset,
  701. ioaddr + ASICCtrl + 2);
  702. /* Wait for ResetBusy bit clear */
  703. for (i = 50; i > 0; i--) {
  704. if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
  705. break;
  706. mdelay (1);
  707. }
  708. rio_free_tx (dev, 1);
  709. /* Reset TFDListPtr */
  710. writel (np->tx_ring_dma +
  711. np->old_tx * sizeof (struct netdev_desc),
  712. dev->base_addr + TFDListPtr0);
  713. writel (0, dev->base_addr + TFDListPtr1);
  714. /* Let TxStartThresh stay default value */
  715. }
  716. /* Late Collision */
  717. if (tx_status & 0x04) {
  718. np->stats.tx_fifo_errors++;
  719. /* TxReset and clear FIFO */
  720. writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
  721. /* Wait reset done */
  722. for (i = 50; i > 0; i--) {
  723. if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
  724. break;
  725. mdelay (1);
  726. }
  727. /* Let TxStartThresh stay default value */
  728. }
  729. /* Maximum Collisions */
  730. #ifdef ETHER_STATS
  731. if (tx_status & 0x08)
  732. np->stats.collisions16++;
  733. #else
  734. if (tx_status & 0x08)
  735. np->stats.collisions++;
  736. #endif
  737. /* Restart the Tx */
  738. writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
  739. }
  740. static int
  741. receive_packet (struct net_device *dev)
  742. {
  743. struct netdev_private *np = netdev_priv(dev);
  744. int entry = np->cur_rx % RX_RING_SIZE;
  745. int cnt = 30;
  746. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  747. while (1) {
  748. struct netdev_desc *desc = &np->rx_ring[entry];
  749. int pkt_len;
  750. u64 frame_status;
  751. if (!(desc->status & cpu_to_le64(RFDDone)) ||
  752. !(desc->status & cpu_to_le64(FrameStart)) ||
  753. !(desc->status & cpu_to_le64(FrameEnd)))
  754. break;
  755. /* Chip omits the CRC. */
  756. frame_status = le64_to_cpu(desc->status);
  757. pkt_len = frame_status & 0xffff;
  758. if (--cnt < 0)
  759. break;
  760. /* Update rx error statistics, drop packet. */
  761. if (frame_status & RFS_Errors) {
  762. np->stats.rx_errors++;
  763. if (frame_status & (RxRuntFrame | RxLengthError))
  764. np->stats.rx_length_errors++;
  765. if (frame_status & RxFCSError)
  766. np->stats.rx_crc_errors++;
  767. if (frame_status & RxAlignmentError && np->speed != 1000)
  768. np->stats.rx_frame_errors++;
  769. if (frame_status & RxFIFOOverrun)
  770. np->stats.rx_fifo_errors++;
  771. } else {
  772. struct sk_buff *skb;
  773. /* Small skbuffs for short packets */
  774. if (pkt_len > copy_thresh) {
  775. pci_unmap_single (np->pdev,
  776. desc_to_dma(desc),
  777. np->rx_buf_sz,
  778. PCI_DMA_FROMDEVICE);
  779. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  780. np->rx_skbuff[entry] = NULL;
  781. } else if ((skb = netdev_alloc_skb(dev, pkt_len + 2))) {
  782. pci_dma_sync_single_for_cpu(np->pdev,
  783. desc_to_dma(desc),
  784. np->rx_buf_sz,
  785. PCI_DMA_FROMDEVICE);
  786. /* 16 byte align the IP header */
  787. skb_reserve (skb, 2);
  788. skb_copy_to_linear_data (skb,
  789. np->rx_skbuff[entry]->data,
  790. pkt_len);
  791. skb_put (skb, pkt_len);
  792. pci_dma_sync_single_for_device(np->pdev,
  793. desc_to_dma(desc),
  794. np->rx_buf_sz,
  795. PCI_DMA_FROMDEVICE);
  796. }
  797. skb->protocol = eth_type_trans (skb, dev);
  798. #if 0
  799. /* Checksum done by hw, but csum value unavailable. */
  800. if (np->pdev->pci_rev_id >= 0x0c &&
  801. !(frame_status & (TCPError | UDPError | IPError))) {
  802. skb->ip_summed = CHECKSUM_UNNECESSARY;
  803. }
  804. #endif
  805. netif_rx (skb);
  806. }
  807. entry = (entry + 1) % RX_RING_SIZE;
  808. }
  809. spin_lock(&np->rx_lock);
  810. np->cur_rx = entry;
  811. /* Re-allocate skbuffs to fill the descriptor ring */
  812. entry = np->old_rx;
  813. while (entry != np->cur_rx) {
  814. struct sk_buff *skb;
  815. /* Dropped packets don't need to re-allocate */
  816. if (np->rx_skbuff[entry] == NULL) {
  817. skb = netdev_alloc_skb(dev, np->rx_buf_sz);
  818. if (skb == NULL) {
  819. np->rx_ring[entry].fraginfo = 0;
  820. printk (KERN_INFO
  821. "%s: receive_packet: "
  822. "Unable to re-allocate Rx skbuff.#%d\n",
  823. dev->name, entry);
  824. break;
  825. }
  826. np->rx_skbuff[entry] = skb;
  827. /* 16 byte align the IP header */
  828. skb_reserve (skb, 2);
  829. np->rx_ring[entry].fraginfo =
  830. cpu_to_le64 (pci_map_single
  831. (np->pdev, skb->data, np->rx_buf_sz,
  832. PCI_DMA_FROMDEVICE));
  833. }
  834. np->rx_ring[entry].fraginfo |=
  835. cpu_to_le64((u64)np->rx_buf_sz << 48);
  836. np->rx_ring[entry].status = 0;
  837. entry = (entry + 1) % RX_RING_SIZE;
  838. }
  839. np->old_rx = entry;
  840. spin_unlock(&np->rx_lock);
  841. return 0;
  842. }
  843. static void
  844. rio_error (struct net_device *dev, int int_status)
  845. {
  846. long ioaddr = dev->base_addr;
  847. struct netdev_private *np = netdev_priv(dev);
  848. u16 macctrl;
  849. /* Link change event */
  850. if (int_status & LinkEvent) {
  851. if (mii_wait_link (dev, 10) == 0) {
  852. printk (KERN_INFO "%s: Link up\n", dev->name);
  853. if (np->phy_media)
  854. mii_get_media_pcs (dev);
  855. else
  856. mii_get_media (dev);
  857. if (np->speed == 1000)
  858. np->tx_coalesce = tx_coalesce;
  859. else
  860. np->tx_coalesce = 1;
  861. macctrl = 0;
  862. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  863. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  864. macctrl |= (np->tx_flow) ?
  865. TxFlowControlEnable : 0;
  866. macctrl |= (np->rx_flow) ?
  867. RxFlowControlEnable : 0;
  868. writew(macctrl, ioaddr + MACCtrl);
  869. np->link_status = 1;
  870. netif_carrier_on(dev);
  871. } else {
  872. printk (KERN_INFO "%s: Link off\n", dev->name);
  873. np->link_status = 0;
  874. netif_carrier_off(dev);
  875. }
  876. }
  877. /* UpdateStats statistics registers */
  878. if (int_status & UpdateStats) {
  879. get_stats (dev);
  880. }
  881. /* PCI Error, a catastronphic error related to the bus interface
  882. occurs, set GlobalReset and HostReset to reset. */
  883. if (int_status & HostError) {
  884. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  885. dev->name, int_status);
  886. writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
  887. mdelay (500);
  888. }
  889. }
  890. static struct net_device_stats *
  891. get_stats (struct net_device *dev)
  892. {
  893. long ioaddr = dev->base_addr;
  894. struct netdev_private *np = netdev_priv(dev);
  895. #ifdef MEM_MAPPING
  896. int i;
  897. #endif
  898. unsigned int stat_reg;
  899. /* All statistics registers need to be acknowledged,
  900. else statistic overflow could cause problems */
  901. np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
  902. np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
  903. np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
  904. np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
  905. np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
  906. np->stats.collisions += readl (ioaddr + SingleColFrames)
  907. + readl (ioaddr + MultiColFrames);
  908. /* detailed tx errors */
  909. stat_reg = readw (ioaddr + FramesAbortXSColls);
  910. np->stats.tx_aborted_errors += stat_reg;
  911. np->stats.tx_errors += stat_reg;
  912. stat_reg = readw (ioaddr + CarrierSenseErrors);
  913. np->stats.tx_carrier_errors += stat_reg;
  914. np->stats.tx_errors += stat_reg;
  915. /* Clear all other statistic register. */
  916. readl (ioaddr + McstOctetXmtOk);
  917. readw (ioaddr + BcstFramesXmtdOk);
  918. readl (ioaddr + McstFramesXmtdOk);
  919. readw (ioaddr + BcstFramesRcvdOk);
  920. readw (ioaddr + MacControlFramesRcvd);
  921. readw (ioaddr + FrameTooLongErrors);
  922. readw (ioaddr + InRangeLengthErrors);
  923. readw (ioaddr + FramesCheckSeqErrors);
  924. readw (ioaddr + FramesLostRxErrors);
  925. readl (ioaddr + McstOctetXmtOk);
  926. readl (ioaddr + BcstOctetXmtOk);
  927. readl (ioaddr + McstFramesXmtdOk);
  928. readl (ioaddr + FramesWDeferredXmt);
  929. readl (ioaddr + LateCollisions);
  930. readw (ioaddr + BcstFramesXmtdOk);
  931. readw (ioaddr + MacControlFramesXmtd);
  932. readw (ioaddr + FramesWEXDeferal);
  933. #ifdef MEM_MAPPING
  934. for (i = 0x100; i <= 0x150; i += 4)
  935. readl (ioaddr + i);
  936. #endif
  937. readw (ioaddr + TxJumboFrames);
  938. readw (ioaddr + RxJumboFrames);
  939. readw (ioaddr + TCPCheckSumErrors);
  940. readw (ioaddr + UDPCheckSumErrors);
  941. readw (ioaddr + IPCheckSumErrors);
  942. return &np->stats;
  943. }
  944. static int
  945. clear_stats (struct net_device *dev)
  946. {
  947. long ioaddr = dev->base_addr;
  948. #ifdef MEM_MAPPING
  949. int i;
  950. #endif
  951. /* All statistics registers need to be acknowledged,
  952. else statistic overflow could cause problems */
  953. readl (ioaddr + FramesRcvOk);
  954. readl (ioaddr + FramesXmtOk);
  955. readl (ioaddr + OctetRcvOk);
  956. readl (ioaddr + OctetXmtOk);
  957. readl (ioaddr + McstFramesRcvdOk);
  958. readl (ioaddr + SingleColFrames);
  959. readl (ioaddr + MultiColFrames);
  960. readl (ioaddr + LateCollisions);
  961. /* detailed rx errors */
  962. readw (ioaddr + FrameTooLongErrors);
  963. readw (ioaddr + InRangeLengthErrors);
  964. readw (ioaddr + FramesCheckSeqErrors);
  965. readw (ioaddr + FramesLostRxErrors);
  966. /* detailed tx errors */
  967. readw (ioaddr + FramesAbortXSColls);
  968. readw (ioaddr + CarrierSenseErrors);
  969. /* Clear all other statistic register. */
  970. readl (ioaddr + McstOctetXmtOk);
  971. readw (ioaddr + BcstFramesXmtdOk);
  972. readl (ioaddr + McstFramesXmtdOk);
  973. readw (ioaddr + BcstFramesRcvdOk);
  974. readw (ioaddr + MacControlFramesRcvd);
  975. readl (ioaddr + McstOctetXmtOk);
  976. readl (ioaddr + BcstOctetXmtOk);
  977. readl (ioaddr + McstFramesXmtdOk);
  978. readl (ioaddr + FramesWDeferredXmt);
  979. readw (ioaddr + BcstFramesXmtdOk);
  980. readw (ioaddr + MacControlFramesXmtd);
  981. readw (ioaddr + FramesWEXDeferal);
  982. #ifdef MEM_MAPPING
  983. for (i = 0x100; i <= 0x150; i += 4)
  984. readl (ioaddr + i);
  985. #endif
  986. readw (ioaddr + TxJumboFrames);
  987. readw (ioaddr + RxJumboFrames);
  988. readw (ioaddr + TCPCheckSumErrors);
  989. readw (ioaddr + UDPCheckSumErrors);
  990. readw (ioaddr + IPCheckSumErrors);
  991. return 0;
  992. }
  993. static int
  994. change_mtu (struct net_device *dev, int new_mtu)
  995. {
  996. struct netdev_private *np = netdev_priv(dev);
  997. int max = (np->jumbo) ? MAX_JUMBO : 1536;
  998. if ((new_mtu < 68) || (new_mtu > max)) {
  999. return -EINVAL;
  1000. }
  1001. dev->mtu = new_mtu;
  1002. return 0;
  1003. }
  1004. static void
  1005. set_multicast (struct net_device *dev)
  1006. {
  1007. long ioaddr = dev->base_addr;
  1008. u32 hash_table[2];
  1009. u16 rx_mode = 0;
  1010. struct netdev_private *np = netdev_priv(dev);
  1011. hash_table[0] = hash_table[1] = 0;
  1012. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  1013. hash_table[1] |= 0x02000000;
  1014. if (dev->flags & IFF_PROMISC) {
  1015. /* Receive all frames promiscuously. */
  1016. rx_mode = ReceiveAllFrames;
  1017. } else if ((dev->flags & IFF_ALLMULTI) ||
  1018. (dev->mc_count > multicast_filter_limit)) {
  1019. /* Receive broadcast and multicast frames */
  1020. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1021. } else if (dev->mc_count > 0) {
  1022. int i;
  1023. struct dev_mc_list *mclist;
  1024. /* Receive broadcast frames and multicast frames filtering
  1025. by Hashtable */
  1026. rx_mode =
  1027. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1028. for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  1029. i++, mclist=mclist->next)
  1030. {
  1031. int bit, index = 0;
  1032. int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
  1033. /* The inverted high significant 6 bits of CRC are
  1034. used as an index to hashtable */
  1035. for (bit = 0; bit < 6; bit++)
  1036. if (crc & (1 << (31 - bit)))
  1037. index |= (1 << bit);
  1038. hash_table[index / 32] |= (1 << (index % 32));
  1039. }
  1040. } else {
  1041. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1042. }
  1043. if (np->vlan) {
  1044. /* ReceiveVLANMatch field in ReceiveMode */
  1045. rx_mode |= ReceiveVLANMatch;
  1046. }
  1047. writel (hash_table[0], ioaddr + HashTable0);
  1048. writel (hash_table[1], ioaddr + HashTable1);
  1049. writew (rx_mode, ioaddr + ReceiveMode);
  1050. }
  1051. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1052. {
  1053. struct netdev_private *np = netdev_priv(dev);
  1054. strcpy(info->driver, "dl2k");
  1055. strcpy(info->version, DRV_VERSION);
  1056. strcpy(info->bus_info, pci_name(np->pdev));
  1057. }
  1058. static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1059. {
  1060. struct netdev_private *np = netdev_priv(dev);
  1061. if (np->phy_media) {
  1062. /* fiber device */
  1063. cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1064. cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1065. cmd->port = PORT_FIBRE;
  1066. cmd->transceiver = XCVR_INTERNAL;
  1067. } else {
  1068. /* copper device */
  1069. cmd->supported = SUPPORTED_10baseT_Half |
  1070. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1071. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1072. SUPPORTED_Autoneg | SUPPORTED_MII;
  1073. cmd->advertising = ADVERTISED_10baseT_Half |
  1074. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1075. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
  1076. ADVERTISED_Autoneg | ADVERTISED_MII;
  1077. cmd->port = PORT_MII;
  1078. cmd->transceiver = XCVR_INTERNAL;
  1079. }
  1080. if ( np->link_status ) {
  1081. cmd->speed = np->speed;
  1082. cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1083. } else {
  1084. cmd->speed = -1;
  1085. cmd->duplex = -1;
  1086. }
  1087. if ( np->an_enable)
  1088. cmd->autoneg = AUTONEG_ENABLE;
  1089. else
  1090. cmd->autoneg = AUTONEG_DISABLE;
  1091. cmd->phy_address = np->phy_addr;
  1092. return 0;
  1093. }
  1094. static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1095. {
  1096. struct netdev_private *np = netdev_priv(dev);
  1097. netif_carrier_off(dev);
  1098. if (cmd->autoneg == AUTONEG_ENABLE) {
  1099. if (np->an_enable)
  1100. return 0;
  1101. else {
  1102. np->an_enable = 1;
  1103. mii_set_media(dev);
  1104. return 0;
  1105. }
  1106. } else {
  1107. np->an_enable = 0;
  1108. if (np->speed == 1000) {
  1109. cmd->speed = SPEED_100;
  1110. cmd->duplex = DUPLEX_FULL;
  1111. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1112. }
  1113. switch(cmd->speed + cmd->duplex) {
  1114. case SPEED_10 + DUPLEX_HALF:
  1115. np->speed = 10;
  1116. np->full_duplex = 0;
  1117. break;
  1118. case SPEED_10 + DUPLEX_FULL:
  1119. np->speed = 10;
  1120. np->full_duplex = 1;
  1121. break;
  1122. case SPEED_100 + DUPLEX_HALF:
  1123. np->speed = 100;
  1124. np->full_duplex = 0;
  1125. break;
  1126. case SPEED_100 + DUPLEX_FULL:
  1127. np->speed = 100;
  1128. np->full_duplex = 1;
  1129. break;
  1130. case SPEED_1000 + DUPLEX_HALF:/* not supported */
  1131. case SPEED_1000 + DUPLEX_FULL:/* not supported */
  1132. default:
  1133. return -EINVAL;
  1134. }
  1135. mii_set_media(dev);
  1136. }
  1137. return 0;
  1138. }
  1139. static u32 rio_get_link(struct net_device *dev)
  1140. {
  1141. struct netdev_private *np = netdev_priv(dev);
  1142. return np->link_status;
  1143. }
  1144. static const struct ethtool_ops ethtool_ops = {
  1145. .get_drvinfo = rio_get_drvinfo,
  1146. .get_settings = rio_get_settings,
  1147. .set_settings = rio_set_settings,
  1148. .get_link = rio_get_link,
  1149. };
  1150. static int
  1151. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1152. {
  1153. int phy_addr;
  1154. struct netdev_private *np = netdev_priv(dev);
  1155. struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
  1156. struct netdev_desc *desc;
  1157. int i;
  1158. phy_addr = np->phy_addr;
  1159. switch (cmd) {
  1160. case SIOCDEVPRIVATE:
  1161. break;
  1162. case SIOCDEVPRIVATE + 1:
  1163. miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
  1164. break;
  1165. case SIOCDEVPRIVATE + 2:
  1166. mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
  1167. break;
  1168. case SIOCDEVPRIVATE + 3:
  1169. break;
  1170. case SIOCDEVPRIVATE + 4:
  1171. break;
  1172. case SIOCDEVPRIVATE + 5:
  1173. netif_stop_queue (dev);
  1174. break;
  1175. case SIOCDEVPRIVATE + 6:
  1176. netif_wake_queue (dev);
  1177. break;
  1178. case SIOCDEVPRIVATE + 7:
  1179. printk
  1180. ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
  1181. netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
  1182. np->old_rx);
  1183. break;
  1184. case SIOCDEVPRIVATE + 8:
  1185. printk("TX ring:\n");
  1186. for (i = 0; i < TX_RING_SIZE; i++) {
  1187. desc = &np->tx_ring[i];
  1188. printk
  1189. ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
  1190. i,
  1191. (u32) (np->tx_ring_dma + i * sizeof (*desc)),
  1192. (u32)le64_to_cpu(desc->next_desc),
  1193. (u32)le64_to_cpu(desc->status),
  1194. (u32)(le64_to_cpu(desc->fraginfo) >> 32),
  1195. (u32)le64_to_cpu(desc->fraginfo));
  1196. printk ("\n");
  1197. }
  1198. printk ("\n");
  1199. break;
  1200. default:
  1201. return -EOPNOTSUPP;
  1202. }
  1203. return 0;
  1204. }
  1205. #define EEP_READ 0x0200
  1206. #define EEP_BUSY 0x8000
  1207. /* Read the EEPROM word */
  1208. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1209. static int
  1210. read_eeprom (long ioaddr, int eep_addr)
  1211. {
  1212. int i = 1000;
  1213. outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
  1214. while (i-- > 0) {
  1215. if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
  1216. return inw (ioaddr + EepromData);
  1217. }
  1218. }
  1219. return 0;
  1220. }
  1221. enum phy_ctrl_bits {
  1222. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1223. MII_DUPLEX = 0x08,
  1224. };
  1225. #define mii_delay() readb(ioaddr)
  1226. static void
  1227. mii_sendbit (struct net_device *dev, u32 data)
  1228. {
  1229. long ioaddr = dev->base_addr + PhyCtrl;
  1230. data = (data) ? MII_DATA1 : 0;
  1231. data |= MII_WRITE;
  1232. data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
  1233. writeb (data, ioaddr);
  1234. mii_delay ();
  1235. writeb (data | MII_CLK, ioaddr);
  1236. mii_delay ();
  1237. }
  1238. static int
  1239. mii_getbit (struct net_device *dev)
  1240. {
  1241. long ioaddr = dev->base_addr + PhyCtrl;
  1242. u8 data;
  1243. data = (readb (ioaddr) & 0xf8) | MII_READ;
  1244. writeb (data, ioaddr);
  1245. mii_delay ();
  1246. writeb (data | MII_CLK, ioaddr);
  1247. mii_delay ();
  1248. return ((readb (ioaddr) >> 1) & 1);
  1249. }
  1250. static void
  1251. mii_send_bits (struct net_device *dev, u32 data, int len)
  1252. {
  1253. int i;
  1254. for (i = len - 1; i >= 0; i--) {
  1255. mii_sendbit (dev, data & (1 << i));
  1256. }
  1257. }
  1258. static int
  1259. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1260. {
  1261. u32 cmd;
  1262. int i;
  1263. u32 retval = 0;
  1264. /* Preamble */
  1265. mii_send_bits (dev, 0xffffffff, 32);
  1266. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1267. /* ST,OP = 0110'b for read operation */
  1268. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1269. mii_send_bits (dev, cmd, 14);
  1270. /* Turnaround */
  1271. if (mii_getbit (dev))
  1272. goto err_out;
  1273. /* Read data */
  1274. for (i = 0; i < 16; i++) {
  1275. retval |= mii_getbit (dev);
  1276. retval <<= 1;
  1277. }
  1278. /* End cycle */
  1279. mii_getbit (dev);
  1280. return (retval >> 1) & 0xffff;
  1281. err_out:
  1282. return 0;
  1283. }
  1284. static int
  1285. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1286. {
  1287. u32 cmd;
  1288. /* Preamble */
  1289. mii_send_bits (dev, 0xffffffff, 32);
  1290. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1291. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1292. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1293. mii_send_bits (dev, cmd, 32);
  1294. /* End cycle */
  1295. mii_getbit (dev);
  1296. return 0;
  1297. }
  1298. static int
  1299. mii_wait_link (struct net_device *dev, int wait)
  1300. {
  1301. __u16 bmsr;
  1302. int phy_addr;
  1303. struct netdev_private *np;
  1304. np = netdev_priv(dev);
  1305. phy_addr = np->phy_addr;
  1306. do {
  1307. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1308. if (bmsr & MII_BMSR_LINK_STATUS)
  1309. return 0;
  1310. mdelay (1);
  1311. } while (--wait > 0);
  1312. return -1;
  1313. }
  1314. static int
  1315. mii_get_media (struct net_device *dev)
  1316. {
  1317. __u16 negotiate;
  1318. __u16 bmsr;
  1319. __u16 mscr;
  1320. __u16 mssr;
  1321. int phy_addr;
  1322. struct netdev_private *np;
  1323. np = netdev_priv(dev);
  1324. phy_addr = np->phy_addr;
  1325. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1326. if (np->an_enable) {
  1327. if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
  1328. /* Auto-Negotiation not completed */
  1329. return -1;
  1330. }
  1331. negotiate = mii_read (dev, phy_addr, MII_ANAR) &
  1332. mii_read (dev, phy_addr, MII_ANLPAR);
  1333. mscr = mii_read (dev, phy_addr, MII_MSCR);
  1334. mssr = mii_read (dev, phy_addr, MII_MSSR);
  1335. if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) {
  1336. np->speed = 1000;
  1337. np->full_duplex = 1;
  1338. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1339. } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) {
  1340. np->speed = 1000;
  1341. np->full_duplex = 0;
  1342. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1343. } else if (negotiate & MII_ANAR_100BX_FD) {
  1344. np->speed = 100;
  1345. np->full_duplex = 1;
  1346. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1347. } else if (negotiate & MII_ANAR_100BX_HD) {
  1348. np->speed = 100;
  1349. np->full_duplex = 0;
  1350. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1351. } else if (negotiate & MII_ANAR_10BT_FD) {
  1352. np->speed = 10;
  1353. np->full_duplex = 1;
  1354. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1355. } else if (negotiate & MII_ANAR_10BT_HD) {
  1356. np->speed = 10;
  1357. np->full_duplex = 0;
  1358. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1359. }
  1360. if (negotiate & MII_ANAR_PAUSE) {
  1361. np->tx_flow &= 1;
  1362. np->rx_flow &= 1;
  1363. } else if (negotiate & MII_ANAR_ASYMMETRIC) {
  1364. np->tx_flow = 0;
  1365. np->rx_flow &= 1;
  1366. }
  1367. /* else tx_flow, rx_flow = user select */
  1368. } else {
  1369. __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1370. switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) {
  1371. case MII_BMCR_SPEED_1000:
  1372. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1373. break;
  1374. case MII_BMCR_SPEED_100:
  1375. printk (KERN_INFO "Operating at 100 Mbps, ");
  1376. break;
  1377. case 0:
  1378. printk (KERN_INFO "Operating at 10 Mbps, ");
  1379. }
  1380. if (bmcr & MII_BMCR_DUPLEX_MODE) {
  1381. printk ("Full duplex\n");
  1382. } else {
  1383. printk ("Half duplex\n");
  1384. }
  1385. }
  1386. if (np->tx_flow)
  1387. printk(KERN_INFO "Enable Tx Flow Control\n");
  1388. else
  1389. printk(KERN_INFO "Disable Tx Flow Control\n");
  1390. if (np->rx_flow)
  1391. printk(KERN_INFO "Enable Rx Flow Control\n");
  1392. else
  1393. printk(KERN_INFO "Disable Rx Flow Control\n");
  1394. return 0;
  1395. }
  1396. static int
  1397. mii_set_media (struct net_device *dev)
  1398. {
  1399. __u16 pscr;
  1400. __u16 bmcr;
  1401. __u16 bmsr;
  1402. __u16 anar;
  1403. int phy_addr;
  1404. struct netdev_private *np;
  1405. np = netdev_priv(dev);
  1406. phy_addr = np->phy_addr;
  1407. /* Does user set speed? */
  1408. if (np->an_enable) {
  1409. /* Advertise capabilities */
  1410. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1411. anar = mii_read (dev, phy_addr, MII_ANAR) &
  1412. ~MII_ANAR_100BX_FD &
  1413. ~MII_ANAR_100BX_HD &
  1414. ~MII_ANAR_100BT4 &
  1415. ~MII_ANAR_10BT_FD &
  1416. ~MII_ANAR_10BT_HD;
  1417. if (bmsr & MII_BMSR_100BX_FD)
  1418. anar |= MII_ANAR_100BX_FD;
  1419. if (bmsr & MII_BMSR_100BX_HD)
  1420. anar |= MII_ANAR_100BX_HD;
  1421. if (bmsr & MII_BMSR_100BT4)
  1422. anar |= MII_ANAR_100BT4;
  1423. if (bmsr & MII_BMSR_10BT_FD)
  1424. anar |= MII_ANAR_10BT_FD;
  1425. if (bmsr & MII_BMSR_10BT_HD)
  1426. anar |= MII_ANAR_10BT_HD;
  1427. anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC;
  1428. mii_write (dev, phy_addr, MII_ANAR, anar);
  1429. /* Enable Auto crossover */
  1430. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1431. pscr |= 3 << 5; /* 11'b */
  1432. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1433. /* Soft reset PHY */
  1434. mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
  1435. bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET;
  1436. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1437. mdelay(1);
  1438. } else {
  1439. /* Force speed setting */
  1440. /* 1) Disable Auto crossover */
  1441. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1442. pscr &= ~(3 << 5);
  1443. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1444. /* 2) PHY Reset */
  1445. bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1446. bmcr |= MII_BMCR_RESET;
  1447. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1448. /* 3) Power Down */
  1449. bmcr = 0x1940; /* must be 0x1940 */
  1450. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1451. mdelay (100); /* wait a certain time */
  1452. /* 4) Advertise nothing */
  1453. mii_write (dev, phy_addr, MII_ANAR, 0);
  1454. /* 5) Set media and Power Up */
  1455. bmcr = MII_BMCR_POWER_DOWN;
  1456. if (np->speed == 100) {
  1457. bmcr |= MII_BMCR_SPEED_100;
  1458. printk (KERN_INFO "Manual 100 Mbps, ");
  1459. } else if (np->speed == 10) {
  1460. printk (KERN_INFO "Manual 10 Mbps, ");
  1461. }
  1462. if (np->full_duplex) {
  1463. bmcr |= MII_BMCR_DUPLEX_MODE;
  1464. printk ("Full duplex\n");
  1465. } else {
  1466. printk ("Half duplex\n");
  1467. }
  1468. #if 0
  1469. /* Set 1000BaseT Master/Slave setting */
  1470. mscr = mii_read (dev, phy_addr, MII_MSCR);
  1471. mscr |= MII_MSCR_CFG_ENABLE;
  1472. mscr &= ~MII_MSCR_CFG_VALUE = 0;
  1473. #endif
  1474. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1475. mdelay(10);
  1476. }
  1477. return 0;
  1478. }
  1479. static int
  1480. mii_get_media_pcs (struct net_device *dev)
  1481. {
  1482. __u16 negotiate;
  1483. __u16 bmsr;
  1484. int phy_addr;
  1485. struct netdev_private *np;
  1486. np = netdev_priv(dev);
  1487. phy_addr = np->phy_addr;
  1488. bmsr = mii_read (dev, phy_addr, PCS_BMSR);
  1489. if (np->an_enable) {
  1490. if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
  1491. /* Auto-Negotiation not completed */
  1492. return -1;
  1493. }
  1494. negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
  1495. mii_read (dev, phy_addr, PCS_ANLPAR);
  1496. np->speed = 1000;
  1497. if (negotiate & PCS_ANAR_FULL_DUPLEX) {
  1498. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1499. np->full_duplex = 1;
  1500. } else {
  1501. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1502. np->full_duplex = 0;
  1503. }
  1504. if (negotiate & PCS_ANAR_PAUSE) {
  1505. np->tx_flow &= 1;
  1506. np->rx_flow &= 1;
  1507. } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
  1508. np->tx_flow = 0;
  1509. np->rx_flow &= 1;
  1510. }
  1511. /* else tx_flow, rx_flow = user select */
  1512. } else {
  1513. __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
  1514. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1515. if (bmcr & MII_BMCR_DUPLEX_MODE) {
  1516. printk ("Full duplex\n");
  1517. } else {
  1518. printk ("Half duplex\n");
  1519. }
  1520. }
  1521. if (np->tx_flow)
  1522. printk(KERN_INFO "Enable Tx Flow Control\n");
  1523. else
  1524. printk(KERN_INFO "Disable Tx Flow Control\n");
  1525. if (np->rx_flow)
  1526. printk(KERN_INFO "Enable Rx Flow Control\n");
  1527. else
  1528. printk(KERN_INFO "Disable Rx Flow Control\n");
  1529. return 0;
  1530. }
  1531. static int
  1532. mii_set_media_pcs (struct net_device *dev)
  1533. {
  1534. __u16 bmcr;
  1535. __u16 esr;
  1536. __u16 anar;
  1537. int phy_addr;
  1538. struct netdev_private *np;
  1539. np = netdev_priv(dev);
  1540. phy_addr = np->phy_addr;
  1541. /* Auto-Negotiation? */
  1542. if (np->an_enable) {
  1543. /* Advertise capabilities */
  1544. esr = mii_read (dev, phy_addr, PCS_ESR);
  1545. anar = mii_read (dev, phy_addr, MII_ANAR) &
  1546. ~PCS_ANAR_HALF_DUPLEX &
  1547. ~PCS_ANAR_FULL_DUPLEX;
  1548. if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
  1549. anar |= PCS_ANAR_HALF_DUPLEX;
  1550. if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
  1551. anar |= PCS_ANAR_FULL_DUPLEX;
  1552. anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
  1553. mii_write (dev, phy_addr, MII_ANAR, anar);
  1554. /* Soft reset PHY */
  1555. mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
  1556. bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN |
  1557. MII_BMCR_RESET;
  1558. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1559. mdelay(1);
  1560. } else {
  1561. /* Force speed setting */
  1562. /* PHY Reset */
  1563. bmcr = MII_BMCR_RESET;
  1564. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1565. mdelay(10);
  1566. if (np->full_duplex) {
  1567. bmcr = MII_BMCR_DUPLEX_MODE;
  1568. printk (KERN_INFO "Manual full duplex\n");
  1569. } else {
  1570. bmcr = 0;
  1571. printk (KERN_INFO "Manual half duplex\n");
  1572. }
  1573. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1574. mdelay(10);
  1575. /* Advertise nothing */
  1576. mii_write (dev, phy_addr, MII_ANAR, 0);
  1577. }
  1578. return 0;
  1579. }
  1580. static int
  1581. rio_close (struct net_device *dev)
  1582. {
  1583. long ioaddr = dev->base_addr;
  1584. struct netdev_private *np = netdev_priv(dev);
  1585. struct sk_buff *skb;
  1586. int i;
  1587. netif_stop_queue (dev);
  1588. /* Disable interrupts */
  1589. writew (0, ioaddr + IntEnable);
  1590. /* Stop Tx and Rx logics */
  1591. writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
  1592. free_irq (dev->irq, dev);
  1593. del_timer_sync (&np->timer);
  1594. /* Free all the skbuffs in the queue. */
  1595. for (i = 0; i < RX_RING_SIZE; i++) {
  1596. np->rx_ring[i].status = 0;
  1597. np->rx_ring[i].fraginfo = 0;
  1598. skb = np->rx_skbuff[i];
  1599. if (skb) {
  1600. pci_unmap_single(np->pdev,
  1601. desc_to_dma(&np->rx_ring[i]),
  1602. skb->len, PCI_DMA_FROMDEVICE);
  1603. dev_kfree_skb (skb);
  1604. np->rx_skbuff[i] = NULL;
  1605. }
  1606. }
  1607. for (i = 0; i < TX_RING_SIZE; i++) {
  1608. skb = np->tx_skbuff[i];
  1609. if (skb) {
  1610. pci_unmap_single(np->pdev,
  1611. desc_to_dma(&np->tx_ring[i]),
  1612. skb->len, PCI_DMA_TODEVICE);
  1613. dev_kfree_skb (skb);
  1614. np->tx_skbuff[i] = NULL;
  1615. }
  1616. }
  1617. return 0;
  1618. }
  1619. static void __devexit
  1620. rio_remove1 (struct pci_dev *pdev)
  1621. {
  1622. struct net_device *dev = pci_get_drvdata (pdev);
  1623. if (dev) {
  1624. struct netdev_private *np = netdev_priv(dev);
  1625. unregister_netdev (dev);
  1626. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
  1627. np->rx_ring_dma);
  1628. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
  1629. np->tx_ring_dma);
  1630. #ifdef MEM_MAPPING
  1631. iounmap ((char *) (dev->base_addr));
  1632. #endif
  1633. free_netdev (dev);
  1634. pci_release_regions (pdev);
  1635. pci_disable_device (pdev);
  1636. }
  1637. pci_set_drvdata (pdev, NULL);
  1638. }
  1639. static struct pci_driver rio_driver = {
  1640. .name = "dl2k",
  1641. .id_table = rio_pci_tbl,
  1642. .probe = rio_probe1,
  1643. .remove = __devexit_p(rio_remove1),
  1644. };
  1645. static int __init
  1646. rio_init (void)
  1647. {
  1648. return pci_register_driver(&rio_driver);
  1649. }
  1650. static void __exit
  1651. rio_exit (void)
  1652. {
  1653. pci_unregister_driver (&rio_driver);
  1654. }
  1655. module_init (rio_init);
  1656. module_exit (rio_exit);
  1657. /*
  1658. Compile command:
  1659. gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
  1660. Read Documentation/networking/dl2k.txt for details.
  1661. */