io.h 8.0 KB

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  1. /*
  2. * arch/arm/plat-omap/include/mach/io.h
  3. *
  4. * IO definitions for TI OMAP processors and boards
  5. *
  6. * Copied from arch/arm/mach-sa1100/include/mach/io.h
  7. * Copyright (C) 1997-1999 Russell King
  8. *
  9. * Copyright (C) 2009 Texas Instruments
  10. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. *
  17. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  18. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  19. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  20. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  23. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27. *
  28. * You should have received a copy of the GNU General Public License along
  29. * with this program; if not, write to the Free Software Foundation, Inc.,
  30. * 675 Mass Ave, Cambridge, MA 02139, USA.
  31. *
  32. * Modifications:
  33. * 06-12-1997 RMK Created.
  34. * 07-04-1999 RMK Major cleanup
  35. */
  36. #ifndef __ASM_ARM_ARCH_IO_H
  37. #define __ASM_ARM_ARCH_IO_H
  38. #include <mach/hardware.h>
  39. #define IO_SPACE_LIMIT 0xffffffff
  40. /*
  41. * We don't actually have real ISA nor PCI buses, but there is so many
  42. * drivers out there that might just work if we fake them...
  43. */
  44. #define __io(a) __typesafe_io(a)
  45. #define __mem_pci(a) (a)
  46. /*
  47. * ----------------------------------------------------------------------------
  48. * I/O mapping
  49. * ----------------------------------------------------------------------------
  50. */
  51. #if defined(CONFIG_ARCH_OMAP1)
  52. #define IO_PHYS 0xFFFB0000
  53. #define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
  54. #define IO_SIZE 0x40000
  55. #define IO_VIRT (IO_PHYS - IO_OFFSET)
  56. #define __IO_ADDRESS(pa) ((pa) - IO_OFFSET)
  57. #define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
  58. #define io_v2p(va) ((va) + IO_OFFSET)
  59. #elif defined(CONFIG_ARCH_OMAP2)
  60. /* We map both L3 and L4 on OMAP2 */
  61. #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */
  62. #define L3_24XX_VIRT 0xf8000000
  63. #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
  64. #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */
  65. #define L4_24XX_VIRT 0xd8000000
  66. #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
  67. #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
  68. #define L4_WK_243X_VIRT 0xd9000000
  69. #define L4_WK_243X_SIZE SZ_1M
  70. #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
  71. #define OMAP243X_GPMC_VIRT 0xFE000000
  72. #define OMAP243X_GPMC_SIZE SZ_1M
  73. #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
  74. #define OMAP243X_SDRC_VIRT 0xFD000000
  75. #define OMAP243X_SDRC_SIZE SZ_1M
  76. #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
  77. #define OMAP243X_SMS_VIRT 0xFC000000
  78. #define OMAP243X_SMS_SIZE SZ_1M
  79. #define IO_OFFSET 0x90000000
  80. #define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
  81. #define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
  82. #define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
  83. /* DSP */
  84. #define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
  85. #define DSP_MEM_24XX_VIRT 0xe0000000
  86. #define DSP_MEM_24XX_SIZE 0x28000
  87. #define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
  88. #define DSP_IPI_24XX_VIRT 0xe1000000
  89. #define DSP_IPI_24XX_SIZE SZ_4K
  90. #define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
  91. #define DSP_MMU_24XX_VIRT 0xe2000000
  92. #define DSP_MMU_24XX_SIZE SZ_4K
  93. #elif defined(CONFIG_ARCH_OMAP3)
  94. /* We map both L3 and L4 on OMAP3 */
  95. #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */
  96. #define L3_34XX_VIRT 0xf8000000
  97. #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
  98. #define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */
  99. #define L4_34XX_VIRT 0xd8000000
  100. #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
  101. /*
  102. * Need to look at the Size 4M for L4.
  103. * VPOM3430 was not working for Int controller
  104. */
  105. #define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */
  106. #define L4_WK_34XX_VIRT 0xd8300000
  107. #define L4_WK_34XX_SIZE SZ_1M
  108. #define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */
  109. #define L4_PER_34XX_VIRT 0xd9000000
  110. #define L4_PER_34XX_SIZE SZ_1M
  111. #define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */
  112. #define L4_EMU_34XX_VIRT 0xe4000000
  113. #define L4_EMU_34XX_SIZE SZ_64M
  114. #define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */
  115. #define OMAP34XX_GPMC_VIRT 0xFE000000
  116. #define OMAP34XX_GPMC_SIZE SZ_1M
  117. #define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */
  118. #define OMAP343X_SMS_VIRT 0xFC000000
  119. #define OMAP343X_SMS_SIZE SZ_1M
  120. #define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */
  121. #define OMAP343X_SDRC_VIRT 0xFD000000
  122. #define OMAP343X_SDRC_SIZE SZ_1M
  123. #define IO_OFFSET 0x90000000
  124. #define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
  125. #define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
  126. #define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
  127. /* DSP */
  128. #define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
  129. #define DSP_MEM_34XX_VIRT 0xe0000000
  130. #define DSP_MEM_34XX_SIZE 0x28000
  131. #define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
  132. #define DSP_IPI_34XX_VIRT 0xe1000000
  133. #define DSP_IPI_34XX_SIZE SZ_4K
  134. #define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
  135. #define DSP_MMU_34XX_VIRT 0xe2000000
  136. #define DSP_MMU_34XX_SIZE SZ_4K
  137. #elif defined(CONFIG_ARCH_OMAP4)
  138. /* We map both L3 and L4 on OMAP4 */
  139. #define L3_44XX_PHYS L3_44XX_BASE
  140. #define L3_44XX_VIRT 0xd4000000
  141. #define L3_44XX_SIZE SZ_1M
  142. #define L4_44XX_PHYS L4_44XX_BASE
  143. #define L4_44XX_VIRT 0xda000000
  144. #define L4_44XX_SIZE SZ_4M
  145. #define L4_WK_44XX_PHYS L4_WK_44XX_BASE
  146. #define L4_WK_44XX_VIRT 0xda300000
  147. #define L4_WK_44XX_SIZE SZ_1M
  148. #define L4_PER_44XX_PHYS L4_PER_44XX_BASE
  149. #define L4_PER_44XX_VIRT 0xd8000000
  150. #define L4_PER_44XX_SIZE SZ_4M
  151. #define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
  152. #define L4_EMU_44XX_VIRT 0xe4000000
  153. #define L4_EMU_44XX_SIZE SZ_64M
  154. #define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
  155. #define OMAP44XX_GPMC_VIRT 0xe0000000
  156. #define OMAP44XX_GPMC_SIZE SZ_1M
  157. #define IO_OFFSET 0x90000000
  158. #define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
  159. #define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
  160. #define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
  161. #endif
  162. #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
  163. #define OMAP1_IO_ADDRESS(pa) IOMEM(__OMAP1_IO_ADDRESS(pa))
  164. #define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
  165. #ifdef __ASSEMBLER__
  166. #define IOMEM(x) (x)
  167. #else
  168. #define IOMEM(x) ((void __force __iomem *)(x))
  169. /*
  170. * Functions to access the OMAP IO region
  171. *
  172. * NOTE: - Use omap_read/write[bwl] for physical register addresses
  173. * - Use __raw_read/write[bwl]() for virtual register addresses
  174. * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
  175. * - DO NOT use hardcoded virtual addresses to allow changing the
  176. * IO address space again if needed
  177. */
  178. #define omap_readb(a) __raw_readb(IO_ADDRESS(a))
  179. #define omap_readw(a) __raw_readw(IO_ADDRESS(a))
  180. #define omap_readl(a) __raw_readl(IO_ADDRESS(a))
  181. #define omap_writeb(v,a) __raw_writeb(v, IO_ADDRESS(a))
  182. #define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a))
  183. #define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a))
  184. struct omap_sdrc_params;
  185. extern void omap1_map_common_io(void);
  186. extern void omap1_init_common_hw(void);
  187. extern void omap2_map_common_io(void);
  188. extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
  189. #define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
  190. #define __arch_iounmap(v) omap_iounmap(v)
  191. void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
  192. void omap_iounmap(volatile void __iomem *addr);
  193. #endif
  194. #endif