tifm_ms.c 17 KB

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  1. /*
  2. * TI FlashMedia driver
  3. *
  4. * Copyright (C) 2007 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Special thanks to Carlos Corbacho for providing various MemoryStick cards
  11. * that made this driver possible.
  12. *
  13. */
  14. #include <linux/tifm.h>
  15. #include <linux/memstick.h>
  16. #include <linux/highmem.h>
  17. #include <linux/scatterlist.h>
  18. #include <linux/log2.h>
  19. #include <asm/io.h>
  20. #define DRIVER_NAME "tifm_ms"
  21. #define DRIVER_VERSION "0.1"
  22. static int no_dma;
  23. module_param(no_dma, bool, 0644);
  24. #define TIFM_MS_TIMEOUT 0x00100
  25. #define TIFM_MS_BADCRC 0x00200
  26. #define TIFM_MS_EOTPC 0x01000
  27. #define TIFM_MS_INT 0x02000
  28. /* The meaning of the bit majority in this constant is unknown. */
  29. #define TIFM_MS_SERIAL 0x04010
  30. #define TIFM_MS_SYS_LATCH 0x00100
  31. #define TIFM_MS_SYS_NOT_RDY 0x00800
  32. #define TIFM_MS_SYS_DATA 0x10000
  33. /* Hardware flags */
  34. enum {
  35. CMD_READY = 0x0001,
  36. FIFO_READY = 0x0002,
  37. CARD_READY = 0x0004,
  38. DATA_CARRY = 0x0008
  39. };
  40. struct tifm_ms {
  41. struct tifm_dev *dev;
  42. unsigned short eject:1,
  43. no_dma:1;
  44. unsigned short cmd_flags;
  45. unsigned int mode_mask;
  46. unsigned int block_pos;
  47. unsigned long timeout_jiffies;
  48. struct timer_list timer;
  49. struct memstick_request *req;
  50. unsigned int io_word;
  51. };
  52. static void tifm_ms_read_fifo(struct tifm_ms *host, unsigned int fifo_offset,
  53. struct page *pg, unsigned int page_off,
  54. unsigned int length)
  55. {
  56. struct tifm_dev *sock = host->dev;
  57. unsigned int cnt = 0, off = 0;
  58. unsigned char *buf = kmap_atomic(pg, KM_BIO_DST_IRQ) + page_off;
  59. if (host->cmd_flags & DATA_CARRY) {
  60. while ((fifo_offset & 3) && length) {
  61. buf[off++] = host->io_word & 0xff;
  62. host->io_word >>= 8;
  63. length--;
  64. fifo_offset++;
  65. }
  66. if (!(fifo_offset & 3))
  67. host->cmd_flags &= ~DATA_CARRY;
  68. if (!length)
  69. return;
  70. }
  71. do {
  72. host->io_word = readl(sock->addr + SOCK_FIFO_ACCESS
  73. + fifo_offset);
  74. cnt = 4;
  75. while (length && cnt) {
  76. buf[off++] = (host->io_word >> 8) & 0xff;
  77. cnt--;
  78. length--;
  79. }
  80. fifo_offset += 4 - cnt;
  81. } while (length);
  82. if (cnt)
  83. host->cmd_flags |= DATA_CARRY;
  84. kunmap_atomic(buf - page_off, KM_BIO_DST_IRQ);
  85. }
  86. static void tifm_ms_write_fifo(struct tifm_ms *host, unsigned int fifo_offset,
  87. struct page *pg, unsigned int page_off,
  88. unsigned int length)
  89. {
  90. struct tifm_dev *sock = host->dev;
  91. unsigned int cnt = 0, off = 0;
  92. unsigned char *buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + page_off;
  93. if (host->cmd_flags & DATA_CARRY) {
  94. while (fifo_offset & 3) {
  95. host->io_word |= buf[off++] << (8 * (fifo_offset & 3));
  96. length--;
  97. fifo_offset++;
  98. }
  99. if (!(fifo_offset & 3)) {
  100. writel(host->io_word, sock->addr + SOCK_FIFO_ACCESS
  101. + fifo_offset - 4);
  102. host->cmd_flags &= ~DATA_CARRY;
  103. }
  104. if (!length)
  105. return;
  106. }
  107. do {
  108. cnt = 4;
  109. host->io_word = 0;
  110. while (length && cnt) {
  111. host->io_word |= buf[off++] << (4 - cnt);
  112. cnt--;
  113. length--;
  114. }
  115. fifo_offset += 4 - cnt;
  116. if (!cnt)
  117. writel(host->io_word, sock->addr + SOCK_FIFO_ACCESS
  118. + fifo_offset - 4);
  119. } while (length);
  120. if (cnt)
  121. host->cmd_flags |= DATA_CARRY;
  122. kunmap_atomic(buf - page_off, KM_BIO_SRC_IRQ);
  123. }
  124. static void tifm_ms_move_block(struct tifm_ms *host, unsigned int length)
  125. {
  126. unsigned int t_size;
  127. unsigned int off = host->req->sg.offset + host->block_pos;
  128. unsigned int p_off, p_cnt;
  129. struct page *pg;
  130. unsigned long flags;
  131. dev_dbg(&host->dev->dev, "moving block\n");
  132. local_irq_save(flags);
  133. t_size = length;
  134. while (t_size) {
  135. pg = nth_page(sg_page(&host->req->sg), off >> PAGE_SHIFT);
  136. p_off = offset_in_page(off);
  137. p_cnt = PAGE_SIZE - p_off;
  138. p_cnt = min(p_cnt, t_size);
  139. if (host->req->data_dir == WRITE)
  140. tifm_ms_write_fifo(host, length - t_size,
  141. pg, p_off, p_cnt);
  142. else
  143. tifm_ms_read_fifo(host, length - t_size,
  144. pg, p_off, p_cnt);
  145. t_size -= p_cnt;
  146. }
  147. local_irq_restore(flags);
  148. }
  149. static int tifm_ms_transfer_data(struct tifm_ms *host, int skip)
  150. {
  151. struct tifm_dev *sock = host->dev;
  152. unsigned int length = host->req->sg.length - host->block_pos;
  153. if (!length)
  154. return 1;
  155. if (length > TIFM_FIFO_SIZE)
  156. length = TIFM_FIFO_SIZE;
  157. if (!skip) {
  158. tifm_ms_move_block(host, length);
  159. host->block_pos += length;
  160. }
  161. if ((host->req->data_dir == READ)
  162. && (host->block_pos == host->req->sg.length))
  163. return 1;
  164. writel(ilog2(length) - 2, sock->addr + SOCK_FIFO_PAGE_SIZE);
  165. if (host->req->data_dir == WRITE)
  166. writel((1 << 8) | TIFM_DMA_TX, sock->addr + SOCK_DMA_CONTROL);
  167. else
  168. writel((1 << 8), sock->addr + SOCK_DMA_CONTROL);
  169. return 0;
  170. }
  171. static int tifm_ms_issue_cmd(struct tifm_ms *host)
  172. {
  173. struct tifm_dev *sock = host->dev;
  174. unsigned char *data;
  175. unsigned int data_len = 0, cmd = 0, cmd_mask = 0, cnt, tval = 0;
  176. host->cmd_flags = 0;
  177. if (host->req->io_type == MEMSTICK_IO_SG) {
  178. if (!host->no_dma) {
  179. if (1 != tifm_map_sg(sock, &host->req->sg, 1,
  180. host->req->data_dir == READ
  181. ? PCI_DMA_FROMDEVICE
  182. : PCI_DMA_TODEVICE)) {
  183. host->req->error = -ENOMEM;
  184. return host->req->error;
  185. }
  186. data_len = sg_dma_len(&host->req->sg);
  187. } else
  188. data_len = host->req->sg.length;
  189. writel(TIFM_FIFO_INT_SETALL,
  190. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  191. writel(TIFM_FIFO_ENABLE,
  192. sock->addr + SOCK_FIFO_CONTROL);
  193. writel(TIFM_FIFO_INTMASK,
  194. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  195. if (!host->no_dma) {
  196. writel(ilog2(data_len) - 2,
  197. sock->addr + SOCK_FIFO_PAGE_SIZE);
  198. writel(sg_dma_address(&host->req->sg),
  199. sock->addr + SOCK_DMA_ADDRESS);
  200. if (host->req->data_dir == WRITE)
  201. writel((1 << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
  202. sock->addr + SOCK_DMA_CONTROL);
  203. else
  204. writel((1 << 8) | TIFM_DMA_EN,
  205. sock->addr + SOCK_DMA_CONTROL);
  206. } else {
  207. tifm_ms_transfer_data(host,
  208. host->req->data_dir == READ);
  209. }
  210. cmd_mask = readl(sock->addr + SOCK_MS_SYSTEM);
  211. cmd_mask |= TIFM_MS_SYS_DATA | TIFM_MS_SYS_NOT_RDY;
  212. writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM);
  213. } else if (host->req->io_type == MEMSTICK_IO_VAL) {
  214. data = host->req->data;
  215. data_len = host->req->data_len;
  216. cmd_mask = host->mode_mask | 0x2607; /* unknown constant */
  217. if (host->req->data_dir == WRITE) {
  218. cmd_mask |= TIFM_MS_SYS_LATCH;
  219. writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM);
  220. for (cnt = 0; (data_len - cnt) >= 4; cnt += 4) {
  221. writel(TIFM_MS_SYS_LATCH
  222. | readl(sock->addr + SOCK_MS_SYSTEM),
  223. sock->addr + SOCK_MS_SYSTEM);
  224. __raw_writel(*(unsigned int *)(data + cnt),
  225. sock->addr + SOCK_MS_DATA);
  226. dev_dbg(&sock->dev, "writing %x\n",
  227. *(int *)(data + cnt));
  228. }
  229. switch (data_len - cnt) {
  230. case 3:
  231. tval |= data[cnt + 2] << 16;
  232. case 2:
  233. tval |= data[cnt + 1] << 8;
  234. case 1:
  235. tval |= data[cnt];
  236. writel(TIFM_MS_SYS_LATCH
  237. | readl(sock->addr + SOCK_MS_SYSTEM),
  238. sock->addr + SOCK_MS_SYSTEM);
  239. writel(tval, sock->addr + SOCK_MS_DATA);
  240. dev_dbg(&sock->dev, "writing %x\n", tval);
  241. }
  242. writel(TIFM_MS_SYS_LATCH
  243. | readl(sock->addr + SOCK_MS_SYSTEM),
  244. sock->addr + SOCK_MS_SYSTEM);
  245. writel(0, sock->addr + SOCK_MS_DATA);
  246. dev_dbg(&sock->dev, "writing %x\n", 0);
  247. } else
  248. writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM);
  249. cmd_mask = readl(sock->addr + SOCK_MS_SYSTEM);
  250. cmd_mask &= ~TIFM_MS_SYS_DATA;
  251. cmd_mask |= TIFM_MS_SYS_NOT_RDY;
  252. dev_dbg(&sock->dev, "mask %x\n", cmd_mask);
  253. writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM);
  254. } else
  255. BUG();
  256. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  257. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  258. sock->addr + SOCK_CONTROL);
  259. host->req->error = 0;
  260. cmd = (host->req->tpc & 0xf) << 12;
  261. cmd |= data_len;
  262. writel(cmd, sock->addr + SOCK_MS_COMMAND);
  263. dev_dbg(&sock->dev, "executing TPC %x, %x\n", cmd, cmd_mask);
  264. return 0;
  265. }
  266. static void tifm_ms_complete_cmd(struct tifm_ms *host)
  267. {
  268. struct tifm_dev *sock = host->dev;
  269. struct memstick_host *msh = tifm_get_drvdata(sock);
  270. unsigned int tval = 0, data_len;
  271. unsigned char *data;
  272. int rc;
  273. del_timer(&host->timer);
  274. if (host->req->io_type == MEMSTICK_IO_SG) {
  275. if (!host->no_dma)
  276. tifm_unmap_sg(sock, &host->req->sg, 1,
  277. host->req->data_dir == READ
  278. ? PCI_DMA_FROMDEVICE
  279. : PCI_DMA_TODEVICE);
  280. } else if (host->req->io_type == MEMSTICK_IO_VAL) {
  281. writel(~TIFM_MS_SYS_DATA & readl(sock->addr + SOCK_MS_SYSTEM),
  282. sock->addr + SOCK_MS_SYSTEM);
  283. data = host->req->data;
  284. data_len = host->req->data_len;
  285. if (host->req->data_dir == READ) {
  286. for (rc = 0; (data_len - rc) >= 4; rc += 4)
  287. *(int *)(data + rc)
  288. = __raw_readl(sock->addr
  289. + SOCK_MS_DATA);
  290. if (data_len - rc)
  291. tval = readl(sock->addr + SOCK_MS_DATA);
  292. switch (data_len - rc) {
  293. case 3:
  294. data[rc + 2] = (tval >> 16) & 0xff;
  295. case 2:
  296. data[rc + 1] = (tval >> 8) & 0xff;
  297. case 1:
  298. data[rc] = tval & 0xff;
  299. }
  300. readl(sock->addr + SOCK_MS_DATA);
  301. }
  302. }
  303. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  304. sock->addr + SOCK_CONTROL);
  305. do {
  306. rc = memstick_next_req(msh, &host->req);
  307. } while (!rc && tifm_ms_issue_cmd(host));
  308. }
  309. static int tifm_ms_check_status(struct tifm_ms *host)
  310. {
  311. if (!host->req->error) {
  312. if (!(host->cmd_flags & CMD_READY))
  313. return 1;
  314. if ((host->req->io_type == MEMSTICK_IO_SG)
  315. && !(host->cmd_flags & FIFO_READY))
  316. return 1;
  317. if (host->req->need_card_int
  318. && !(host->cmd_flags & CARD_READY))
  319. return 1;
  320. }
  321. return 0;
  322. }
  323. /* Called from interrupt handler */
  324. static void tifm_ms_data_event(struct tifm_dev *sock)
  325. {
  326. struct tifm_ms *host;
  327. unsigned int fifo_status = 0;
  328. int rc = 1;
  329. spin_lock(&sock->lock);
  330. host = memstick_priv((struct memstick_host *)tifm_get_drvdata(sock));
  331. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  332. dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
  333. fifo_status, host->cmd_flags);
  334. if (host->req) {
  335. if (fifo_status & TIFM_FIFO_READY) {
  336. if (!host->no_dma || tifm_ms_transfer_data(host, 0)) {
  337. host->cmd_flags |= FIFO_READY;
  338. rc = tifm_ms_check_status(host);
  339. }
  340. }
  341. }
  342. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  343. if (!rc)
  344. tifm_ms_complete_cmd(host);
  345. spin_unlock(&sock->lock);
  346. }
  347. /* Called from interrupt handler */
  348. static void tifm_ms_card_event(struct tifm_dev *sock)
  349. {
  350. struct tifm_ms *host;
  351. unsigned int host_status = 0;
  352. int rc = 1;
  353. spin_lock(&sock->lock);
  354. host = memstick_priv((struct memstick_host *)tifm_get_drvdata(sock));
  355. host_status = readl(sock->addr + SOCK_MS_STATUS);
  356. dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
  357. host_status, host->cmd_flags);
  358. if (host->req) {
  359. if (host_status & TIFM_MS_TIMEOUT)
  360. host->req->error = -ETIME;
  361. else if (host_status & TIFM_MS_BADCRC)
  362. host->req->error = -EILSEQ;
  363. if (host->req->error) {
  364. writel(TIFM_FIFO_INT_SETALL,
  365. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  366. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  367. }
  368. if (host_status & TIFM_MS_EOTPC)
  369. host->cmd_flags |= CMD_READY;
  370. if (host_status & TIFM_MS_INT)
  371. host->cmd_flags |= CARD_READY;
  372. rc = tifm_ms_check_status(host);
  373. }
  374. writel(TIFM_MS_SYS_NOT_RDY | readl(sock->addr + SOCK_MS_SYSTEM),
  375. sock->addr + SOCK_MS_SYSTEM);
  376. writel((~TIFM_MS_SYS_DATA) & readl(sock->addr + SOCK_MS_SYSTEM),
  377. sock->addr + SOCK_MS_SYSTEM);
  378. if (!rc)
  379. tifm_ms_complete_cmd(host);
  380. spin_unlock(&sock->lock);
  381. return;
  382. }
  383. static void tifm_ms_request(struct memstick_host *msh)
  384. {
  385. struct tifm_ms *host = memstick_priv(msh);
  386. struct tifm_dev *sock = host->dev;
  387. unsigned long flags;
  388. int rc;
  389. spin_lock_irqsave(&sock->lock, flags);
  390. if (host->req) {
  391. printk(KERN_ERR "%s : unfinished request detected\n",
  392. sock->dev.bus_id);
  393. spin_unlock_irqrestore(&sock->lock, flags);
  394. tifm_eject(host->dev);
  395. return;
  396. }
  397. if (host->eject) {
  398. do {
  399. rc = memstick_next_req(msh, &host->req);
  400. if (!rc)
  401. host->req->error = -ETIME;
  402. } while (!rc);
  403. spin_unlock_irqrestore(&sock->lock, flags);
  404. return;
  405. }
  406. do {
  407. rc = memstick_next_req(msh, &host->req);
  408. } while (!rc && tifm_ms_issue_cmd(host));
  409. spin_unlock_irqrestore(&sock->lock, flags);
  410. return;
  411. }
  412. static void tifm_ms_set_param(struct memstick_host *msh,
  413. enum memstick_param param,
  414. int value)
  415. {
  416. struct tifm_ms *host = memstick_priv(msh);
  417. struct tifm_dev *sock = host->dev;
  418. unsigned long flags;
  419. spin_lock_irqsave(&sock->lock, flags);
  420. switch (param) {
  421. case MEMSTICK_POWER:
  422. /* this is set by card detection mechanism */
  423. break;
  424. case MEMSTICK_INTERFACE:
  425. if (value == MEMSTICK_SERIAL) {
  426. host->mode_mask = TIFM_MS_SERIAL;
  427. writel((~TIFM_CTRL_FAST_CLK)
  428. & readl(sock->addr + SOCK_CONTROL),
  429. sock->addr + SOCK_CONTROL);
  430. } else if (value == MEMSTICK_PARALLEL) {
  431. host->mode_mask = 0;
  432. writel(TIFM_CTRL_FAST_CLK
  433. | readl(sock->addr + SOCK_CONTROL),
  434. sock->addr + SOCK_CONTROL);
  435. }
  436. break;
  437. };
  438. spin_unlock_irqrestore(&sock->lock, flags);
  439. }
  440. static void tifm_ms_abort(unsigned long data)
  441. {
  442. struct tifm_ms *host = (struct tifm_ms *)data;
  443. dev_dbg(&host->dev->dev, "status %x\n",
  444. readl(host->dev->addr + SOCK_MS_STATUS));
  445. printk(KERN_ERR
  446. "%s : card failed to respond for a long period of time "
  447. "(%x, %x)\n",
  448. host->dev->dev.bus_id, host->req ? host->req->tpc : 0,
  449. host->cmd_flags);
  450. tifm_eject(host->dev);
  451. }
  452. static int tifm_ms_initialize_host(struct tifm_ms *host)
  453. {
  454. struct tifm_dev *sock = host->dev;
  455. struct memstick_host *msh = tifm_get_drvdata(sock);
  456. host->mode_mask = TIFM_MS_SERIAL;
  457. writel(0x8000, sock->addr + SOCK_MS_SYSTEM);
  458. writel(0x0200 | TIFM_MS_SYS_NOT_RDY, sock->addr + SOCK_MS_SYSTEM);
  459. writel(0xffffffff, sock->addr + SOCK_MS_STATUS);
  460. if (tifm_has_ms_pif(sock))
  461. msh->caps |= MEMSTICK_CAP_PARALLEL;
  462. return 0;
  463. }
  464. static int tifm_ms_probe(struct tifm_dev *sock)
  465. {
  466. struct memstick_host *msh;
  467. struct tifm_ms *host;
  468. int rc = -EIO;
  469. if (!(TIFM_SOCK_STATE_OCCUPIED
  470. & readl(sock->addr + SOCK_PRESENT_STATE))) {
  471. printk(KERN_WARNING "%s : card gone, unexpectedly\n",
  472. sock->dev.bus_id);
  473. return rc;
  474. }
  475. msh = memstick_alloc_host(sizeof(struct tifm_ms), &sock->dev);
  476. if (!msh)
  477. return -ENOMEM;
  478. host = memstick_priv(msh);
  479. tifm_set_drvdata(sock, msh);
  480. host->dev = sock;
  481. host->timeout_jiffies = msecs_to_jiffies(1000);
  482. host->no_dma = no_dma;
  483. setup_timer(&host->timer, tifm_ms_abort, (unsigned long)host);
  484. msh->request = tifm_ms_request;
  485. msh->set_param = tifm_ms_set_param;
  486. sock->card_event = tifm_ms_card_event;
  487. sock->data_event = tifm_ms_data_event;
  488. rc = tifm_ms_initialize_host(host);
  489. if (!rc)
  490. rc = memstick_add_host(msh);
  491. if (!rc)
  492. return 0;
  493. memstick_free_host(msh);
  494. return rc;
  495. }
  496. static void tifm_ms_remove(struct tifm_dev *sock)
  497. {
  498. struct memstick_host *msh = tifm_get_drvdata(sock);
  499. struct tifm_ms *host = memstick_priv(msh);
  500. int rc = 0;
  501. unsigned long flags;
  502. spin_lock_irqsave(&sock->lock, flags);
  503. host->eject = 1;
  504. if (host->req) {
  505. del_timer(&host->timer);
  506. writel(TIFM_FIFO_INT_SETALL,
  507. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  508. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  509. if ((host->req->io_type == MEMSTICK_IO_SG) && !host->no_dma)
  510. tifm_unmap_sg(sock, &host->req->sg, 1,
  511. host->req->data_dir == READ
  512. ? PCI_DMA_TODEVICE
  513. : PCI_DMA_FROMDEVICE);
  514. host->req->error = -ETIME;
  515. do {
  516. rc = memstick_next_req(msh, &host->req);
  517. if (!rc)
  518. host->req->error = -ETIME;
  519. } while (!rc);
  520. }
  521. spin_unlock_irqrestore(&sock->lock, flags);
  522. memstick_remove_host(msh);
  523. writel(0x0200 | TIFM_MS_SYS_NOT_RDY, sock->addr + SOCK_MS_SYSTEM);
  524. writel(0xffffffff, sock->addr + SOCK_MS_STATUS);
  525. memstick_free_host(msh);
  526. }
  527. #ifdef CONFIG_PM
  528. static int tifm_ms_suspend(struct tifm_dev *sock, pm_message_t state)
  529. {
  530. return 0;
  531. }
  532. static int tifm_ms_resume(struct tifm_dev *sock)
  533. {
  534. struct memstick_host *msh = tifm_get_drvdata(sock);
  535. struct tifm_ms *host = memstick_priv(msh);
  536. tifm_ms_initialize_host(host);
  537. memstick_detect_change(msh);
  538. return 0;
  539. }
  540. #else
  541. #define tifm_ms_suspend NULL
  542. #define tifm_ms_resume NULL
  543. #endif /* CONFIG_PM */
  544. static struct tifm_device_id tifm_ms_id_tbl[] = {
  545. { TIFM_TYPE_MS }, { 0 }
  546. };
  547. static struct tifm_driver tifm_ms_driver = {
  548. .driver = {
  549. .name = DRIVER_NAME,
  550. .owner = THIS_MODULE
  551. },
  552. .id_table = tifm_ms_id_tbl,
  553. .probe = tifm_ms_probe,
  554. .remove = tifm_ms_remove,
  555. .suspend = tifm_ms_suspend,
  556. .resume = tifm_ms_resume
  557. };
  558. static int __init tifm_ms_init(void)
  559. {
  560. return tifm_register_driver(&tifm_ms_driver);
  561. }
  562. static void __exit tifm_ms_exit(void)
  563. {
  564. tifm_unregister_driver(&tifm_ms_driver);
  565. }
  566. MODULE_AUTHOR("Alex Dubov");
  567. MODULE_DESCRIPTION("TI FlashMedia MemoryStick driver");
  568. MODULE_LICENSE("GPL");
  569. MODULE_DEVICE_TABLE(tifm, tifm_ms_id_tbl);
  570. MODULE_VERSION(DRIVER_VERSION);
  571. module_init(tifm_ms_init);
  572. module_exit(tifm_ms_exit);