at91sam9n12.dtsi 8.0 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. model = "Atmel AT91SAM9N12 SoC";
  12. compatible = "atmel,at91sam9n12";
  13. interrupt-parent = <&aic>;
  14. aliases {
  15. serial0 = &dbgu;
  16. serial1 = &usart0;
  17. serial2 = &usart1;
  18. serial3 = &usart2;
  19. serial4 = &usart3;
  20. gpio0 = &pioA;
  21. gpio1 = &pioB;
  22. gpio2 = &pioC;
  23. gpio3 = &pioD;
  24. tcb0 = &tcb0;
  25. tcb1 = &tcb1;
  26. i2c0 = &i2c0;
  27. i2c1 = &i2c1;
  28. };
  29. cpus {
  30. cpu@0 {
  31. compatible = "arm,arm926ejs";
  32. };
  33. };
  34. memory {
  35. reg = <0x20000000 0x10000000>;
  36. };
  37. ahb {
  38. compatible = "simple-bus";
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. ranges;
  42. apb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. aic: interrupt-controller@fffff000 {
  48. #interrupt-cells = <3>;
  49. compatible = "atmel,at91rm9200-aic";
  50. interrupt-controller;
  51. reg = <0xfffff000 0x200>;
  52. };
  53. ramc0: ramc@ffffe800 {
  54. compatible = "atmel,at91sam9g45-ddramc";
  55. reg = <0xffffe800 0x200>;
  56. };
  57. pmc: pmc@fffffc00 {
  58. compatible = "atmel,at91rm9200-pmc";
  59. reg = <0xfffffc00 0x100>;
  60. };
  61. rstc@fffffe00 {
  62. compatible = "atmel,at91sam9g45-rstc";
  63. reg = <0xfffffe00 0x10>;
  64. };
  65. pit: timer@fffffe30 {
  66. compatible = "atmel,at91sam9260-pit";
  67. reg = <0xfffffe30 0xf>;
  68. interrupts = <1 4 7>;
  69. };
  70. shdwc@fffffe10 {
  71. compatible = "atmel,at91sam9x5-shdwc";
  72. reg = <0xfffffe10 0x10>;
  73. };
  74. tcb0: timer@f8008000 {
  75. compatible = "atmel,at91sam9x5-tcb";
  76. reg = <0xf8008000 0x100>;
  77. interrupts = <17 4 0>;
  78. };
  79. tcb1: timer@f800c000 {
  80. compatible = "atmel,at91sam9x5-tcb";
  81. reg = <0xf800c000 0x100>;
  82. interrupts = <17 4 0>;
  83. };
  84. dma: dma-controller@ffffec00 {
  85. compatible = "atmel,at91sam9g45-dma";
  86. reg = <0xffffec00 0x200>;
  87. interrupts = <20 4 0>;
  88. };
  89. pinctrl@fffff400 {
  90. #address-cells = <1>;
  91. #size-cells = <1>;
  92. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  93. ranges = <0xfffff400 0xfffff400 0x800>;
  94. atmel,mux-mask = <
  95. /* A B C */
  96. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  97. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  98. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  99. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  100. >;
  101. /* shared pinctrl settings */
  102. dbgu {
  103. pinctrl_dbgu: dbgu-0 {
  104. atmel,pins =
  105. <0 9 0x1 0x0 /* PA9 periph A */
  106. 0 10 0x1 0x1>; /* PA10 periph with pullup */
  107. };
  108. };
  109. usart0 {
  110. pinctrl_usart0: usart0-0 {
  111. atmel,pins =
  112. <0 1 0x1 0x1 /* PA1 periph A with pullup */
  113. 0 0 0x1 0x0>; /* PA0 periph A */
  114. };
  115. pinctrl_usart0_rts: usart0_rts-0 {
  116. atmel,pins =
  117. <0 2 0x1 0x0>; /* PA2 periph A */
  118. };
  119. pinctrl_usart0_cts: usart0_cts-0 {
  120. atmel,pins =
  121. <0 3 0x1 0x0>; /* PA3 periph A */
  122. };
  123. };
  124. usart1 {
  125. pinctrl_usart1: usart1-0 {
  126. atmel,pins =
  127. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  128. 0 5 0x1 0x0>; /* PA5 periph A */
  129. };
  130. };
  131. usart2 {
  132. pinctrl_usart2: usart2-0 {
  133. atmel,pins =
  134. <0 8 0x1 0x1 /* PA8 periph A with pullup */
  135. 0 7 0x1 0x0>; /* PA7 periph A */
  136. };
  137. pinctrl_usart2_rts: usart2_rts-0 {
  138. atmel,pins =
  139. <1 0 0x2 0x0>; /* PB0 periph B */
  140. };
  141. pinctrl_usart2_cts: usart2_cts-0 {
  142. atmel,pins =
  143. <1 1 0x2 0x0>; /* PB1 periph B */
  144. };
  145. };
  146. usart3 {
  147. pinctrl_usart3: usart3-0 {
  148. atmel,pins =
  149. <2 23 0x2 0x1 /* PC23 periph B with pullup */
  150. 2 22 0x2 0x0>; /* PC22 periph B */
  151. };
  152. pinctrl_usart3_rts: usart3_rts-0 {
  153. atmel,pins =
  154. <2 24 0x2 0x0>; /* PC24 periph B */
  155. };
  156. pinctrl_usart3_cts: usart3_cts-0 {
  157. atmel,pins =
  158. <2 25 0x2 0x0>; /* PC25 periph B */
  159. };
  160. };
  161. uart0 {
  162. pinctrl_uart0: uart0-0 {
  163. atmel,pins =
  164. <2 9 0x3 0x1 /* PC9 periph C with pullup */
  165. 2 8 0x3 0x0>; /* PC8 periph C */
  166. };
  167. };
  168. uart1 {
  169. pinctrl_uart1: uart1-0 {
  170. atmel,pins =
  171. <2 16 0x3 0x1 /* PC17 periph C with pullup */
  172. 2 17 0x3 0x0>; /* PC16 periph C */
  173. };
  174. };
  175. nand {
  176. pinctrl_nand: nand-0 {
  177. atmel,pins =
  178. <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
  179. 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  180. };
  181. };
  182. pioA: gpio@fffff400 {
  183. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  184. reg = <0xfffff400 0x200>;
  185. interrupts = <2 4 1>;
  186. #gpio-cells = <2>;
  187. gpio-controller;
  188. interrupt-controller;
  189. #interrupt-cells = <2>;
  190. };
  191. pioB: gpio@fffff600 {
  192. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  193. reg = <0xfffff600 0x200>;
  194. interrupts = <2 4 1>;
  195. #gpio-cells = <2>;
  196. gpio-controller;
  197. interrupt-controller;
  198. #interrupt-cells = <2>;
  199. };
  200. pioC: gpio@fffff800 {
  201. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  202. reg = <0xfffff800 0x200>;
  203. interrupts = <3 4 1>;
  204. #gpio-cells = <2>;
  205. gpio-controller;
  206. interrupt-controller;
  207. #interrupt-cells = <2>;
  208. };
  209. pioD: gpio@fffffa00 {
  210. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  211. reg = <0xfffffa00 0x200>;
  212. interrupts = <3 4 1>;
  213. #gpio-cells = <2>;
  214. gpio-controller;
  215. interrupt-controller;
  216. #interrupt-cells = <2>;
  217. };
  218. };
  219. dbgu: serial@fffff200 {
  220. compatible = "atmel,at91sam9260-usart";
  221. reg = <0xfffff200 0x200>;
  222. interrupts = <1 4 7>;
  223. pinctrl-names = "default";
  224. pinctrl-0 = <&pinctrl_dbgu>;
  225. status = "disabled";
  226. };
  227. usart0: serial@f801c000 {
  228. compatible = "atmel,at91sam9260-usart";
  229. reg = <0xf801c000 0x4000>;
  230. interrupts = <5 4 5>;
  231. atmel,use-dma-rx;
  232. atmel,use-dma-tx;
  233. pinctrl-names = "default";
  234. pinctrl-0 = <&pinctrl_usart0>;
  235. status = "disabled";
  236. };
  237. usart1: serial@f8020000 {
  238. compatible = "atmel,at91sam9260-usart";
  239. reg = <0xf8020000 0x4000>;
  240. interrupts = <6 4 5>;
  241. atmel,use-dma-rx;
  242. atmel,use-dma-tx;
  243. pinctrl-names = "default";
  244. pinctrl-0 = <&pinctrl_usart1>;
  245. status = "disabled";
  246. };
  247. usart2: serial@f8024000 {
  248. compatible = "atmel,at91sam9260-usart";
  249. reg = <0xf8024000 0x4000>;
  250. interrupts = <7 4 5>;
  251. atmel,use-dma-rx;
  252. atmel,use-dma-tx;
  253. pinctrl-names = "default";
  254. pinctrl-0 = <&pinctrl_usart2>;
  255. status = "disabled";
  256. };
  257. usart3: serial@f8028000 {
  258. compatible = "atmel,at91sam9260-usart";
  259. reg = <0xf8028000 0x4000>;
  260. interrupts = <8 4 5>;
  261. atmel,use-dma-rx;
  262. atmel,use-dma-tx;
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&pinctrl_usart3>;
  265. status = "disabled";
  266. };
  267. i2c0: i2c@f8010000 {
  268. compatible = "atmel,at91sam9x5-i2c";
  269. reg = <0xf8010000 0x100>;
  270. interrupts = <9 4 6>;
  271. #address-cells = <1>;
  272. #size-cells = <0>;
  273. status = "disabled";
  274. };
  275. i2c1: i2c@f8014000 {
  276. compatible = "atmel,at91sam9x5-i2c";
  277. reg = <0xf8014000 0x100>;
  278. interrupts = <10 4 6>;
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. status = "disabled";
  282. };
  283. };
  284. nand0: nand@40000000 {
  285. compatible = "atmel,at91rm9200-nand";
  286. #address-cells = <1>;
  287. #size-cells = <1>;
  288. reg = < 0x40000000 0x10000000
  289. 0xffffe000 0x00000600
  290. 0xffffe600 0x00000200
  291. 0x00100000 0x00100000
  292. >;
  293. atmel,nand-addr-offset = <21>;
  294. atmel,nand-cmd-offset = <22>;
  295. pinctrl-names = "default";
  296. pinctrl-0 = <&pinctrl_nand>;
  297. gpios = <&pioD 5 0
  298. &pioD 4 0
  299. 0
  300. >;
  301. status = "disabled";
  302. };
  303. usb0: ohci@00500000 {
  304. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  305. reg = <0x00500000 0x00100000>;
  306. interrupts = <22 4 2>;
  307. status = "disabled";
  308. };
  309. };
  310. i2c@0 {
  311. compatible = "i2c-gpio";
  312. gpios = <&pioA 30 0 /* sda */
  313. &pioA 31 0 /* scl */
  314. >;
  315. i2c-gpio,sda-open-drain;
  316. i2c-gpio,scl-open-drain;
  317. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  318. #address-cells = <1>;
  319. #size-cells = <0>;
  320. status = "disabled";
  321. };
  322. };