oxygen_pcm.c 20 KB

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  1. /*
  2. * C-Media CMI8788 driver - PCM code
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/pci.h>
  20. #include <sound/control.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include "oxygen.h"
  25. static const struct snd_pcm_hardware oxygen_stereo_hardware = {
  26. .info = SNDRV_PCM_INFO_MMAP |
  27. SNDRV_PCM_INFO_MMAP_VALID |
  28. SNDRV_PCM_INFO_INTERLEAVED |
  29. SNDRV_PCM_INFO_PAUSE |
  30. SNDRV_PCM_INFO_SYNC_START,
  31. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  32. SNDRV_PCM_FMTBIT_S32_LE,
  33. .rates = SNDRV_PCM_RATE_32000 |
  34. SNDRV_PCM_RATE_44100 |
  35. SNDRV_PCM_RATE_48000 |
  36. SNDRV_PCM_RATE_64000 |
  37. SNDRV_PCM_RATE_88200 |
  38. SNDRV_PCM_RATE_96000 |
  39. SNDRV_PCM_RATE_176400 |
  40. SNDRV_PCM_RATE_192000,
  41. .rate_min = 32000,
  42. .rate_max = 192000,
  43. .channels_min = 2,
  44. .channels_max = 2,
  45. .buffer_bytes_max = 256 * 1024,
  46. .period_bytes_min = 128,
  47. .period_bytes_max = 128 * 1024,
  48. .periods_min = 2,
  49. .periods_max = 2048,
  50. };
  51. static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
  52. .info = SNDRV_PCM_INFO_MMAP |
  53. SNDRV_PCM_INFO_MMAP_VALID |
  54. SNDRV_PCM_INFO_INTERLEAVED |
  55. SNDRV_PCM_INFO_PAUSE |
  56. SNDRV_PCM_INFO_SYNC_START,
  57. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  58. SNDRV_PCM_FMTBIT_S32_LE,
  59. .rates = SNDRV_PCM_RATE_32000 |
  60. SNDRV_PCM_RATE_44100 |
  61. SNDRV_PCM_RATE_48000 |
  62. SNDRV_PCM_RATE_64000 |
  63. SNDRV_PCM_RATE_88200 |
  64. SNDRV_PCM_RATE_96000 |
  65. SNDRV_PCM_RATE_176400 |
  66. SNDRV_PCM_RATE_192000,
  67. .rate_min = 32000,
  68. .rate_max = 192000,
  69. .channels_min = 2,
  70. .channels_max = 8,
  71. .buffer_bytes_max = 2048 * 1024,
  72. .period_bytes_min = 128,
  73. .period_bytes_max = 256 * 1024,
  74. .periods_min = 2,
  75. .periods_max = 16384,
  76. };
  77. static const struct snd_pcm_hardware oxygen_ac97_hardware = {
  78. .info = SNDRV_PCM_INFO_MMAP |
  79. SNDRV_PCM_INFO_MMAP_VALID |
  80. SNDRV_PCM_INFO_INTERLEAVED |
  81. SNDRV_PCM_INFO_PAUSE |
  82. SNDRV_PCM_INFO_SYNC_START,
  83. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  84. .rates = SNDRV_PCM_RATE_48000,
  85. .rate_min = 48000,
  86. .rate_max = 48000,
  87. .channels_min = 2,
  88. .channels_max = 2,
  89. .buffer_bytes_max = 256 * 1024,
  90. .period_bytes_min = 128,
  91. .period_bytes_max = 128 * 1024,
  92. .periods_min = 2,
  93. .periods_max = 2048,
  94. };
  95. static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
  96. [PCM_A] = &oxygen_stereo_hardware,
  97. [PCM_B] = &oxygen_stereo_hardware,
  98. [PCM_C] = &oxygen_stereo_hardware,
  99. [PCM_SPDIF] = &oxygen_stereo_hardware,
  100. [PCM_MULTICH] = &oxygen_multichannel_hardware,
  101. [PCM_AC97] = &oxygen_ac97_hardware,
  102. };
  103. static inline unsigned int
  104. oxygen_substream_channel(struct snd_pcm_substream *substream)
  105. {
  106. return (unsigned int)(uintptr_t)substream->runtime->private_data;
  107. }
  108. static int oxygen_open(struct snd_pcm_substream *substream,
  109. unsigned int channel)
  110. {
  111. struct oxygen *chip = snd_pcm_substream_chip(substream);
  112. struct snd_pcm_runtime *runtime = substream->runtime;
  113. int err;
  114. runtime->private_data = (void *)(uintptr_t)channel;
  115. runtime->hw = *oxygen_hardware[channel];
  116. if (chip->model->pcm_hardware_filter)
  117. chip->model->pcm_hardware_filter(channel, &runtime->hw);
  118. err = snd_pcm_hw_constraint_step(runtime, 0,
  119. SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
  120. if (err < 0)
  121. return err;
  122. err = snd_pcm_hw_constraint_step(runtime, 0,
  123. SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
  124. if (err < 0)
  125. return err;
  126. if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
  127. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  128. if (err < 0)
  129. return err;
  130. }
  131. if (runtime->hw.channels_max > 2) {
  132. err = snd_pcm_hw_constraint_step(runtime, 0,
  133. SNDRV_PCM_HW_PARAM_CHANNELS,
  134. 2);
  135. if (err < 0)
  136. return err;
  137. }
  138. snd_pcm_set_sync(substream);
  139. chip->streams[channel] = substream;
  140. mutex_lock(&chip->mutex);
  141. chip->pcm_active |= 1 << channel;
  142. if (channel == PCM_SPDIF) {
  143. chip->spdif_pcm_bits = chip->spdif_bits;
  144. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
  145. ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  146. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  147. SNDRV_CTL_EVENT_MASK_INFO,
  148. &chip->controls[CONTROL_SPDIF_PCM]->id);
  149. }
  150. mutex_unlock(&chip->mutex);
  151. return 0;
  152. }
  153. static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
  154. {
  155. return oxygen_open(substream, PCM_A);
  156. }
  157. static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
  158. {
  159. return oxygen_open(substream, PCM_B);
  160. }
  161. static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
  162. {
  163. return oxygen_open(substream, PCM_C);
  164. }
  165. static int oxygen_spdif_open(struct snd_pcm_substream *substream)
  166. {
  167. return oxygen_open(substream, PCM_SPDIF);
  168. }
  169. static int oxygen_multich_open(struct snd_pcm_substream *substream)
  170. {
  171. return oxygen_open(substream, PCM_MULTICH);
  172. }
  173. static int oxygen_ac97_open(struct snd_pcm_substream *substream)
  174. {
  175. return oxygen_open(substream, PCM_AC97);
  176. }
  177. static int oxygen_close(struct snd_pcm_substream *substream)
  178. {
  179. struct oxygen *chip = snd_pcm_substream_chip(substream);
  180. unsigned int channel = oxygen_substream_channel(substream);
  181. mutex_lock(&chip->mutex);
  182. chip->pcm_active &= ~(1 << channel);
  183. if (channel == PCM_SPDIF) {
  184. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
  185. SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  186. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  187. SNDRV_CTL_EVENT_MASK_INFO,
  188. &chip->controls[CONTROL_SPDIF_PCM]->id);
  189. }
  190. if (channel == PCM_SPDIF || channel == PCM_MULTICH)
  191. oxygen_update_spdif_source(chip);
  192. mutex_unlock(&chip->mutex);
  193. chip->streams[channel] = NULL;
  194. return 0;
  195. }
  196. static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
  197. {
  198. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  199. return OXYGEN_FORMAT_24;
  200. else
  201. return OXYGEN_FORMAT_16;
  202. }
  203. static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
  204. {
  205. switch (params_rate(hw_params)) {
  206. case 32000:
  207. return OXYGEN_RATE_32000;
  208. case 44100:
  209. return OXYGEN_RATE_44100;
  210. default: /* 48000 */
  211. return OXYGEN_RATE_48000;
  212. case 64000:
  213. return OXYGEN_RATE_64000;
  214. case 88200:
  215. return OXYGEN_RATE_88200;
  216. case 96000:
  217. return OXYGEN_RATE_96000;
  218. case 176400:
  219. return OXYGEN_RATE_176400;
  220. case 192000:
  221. return OXYGEN_RATE_192000;
  222. }
  223. }
  224. static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
  225. {
  226. return params_rate(hw_params) <= 96000
  227. ? OXYGEN_I2S_MCLK_256 : OXYGEN_I2S_MCLK_128;
  228. }
  229. static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
  230. {
  231. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  232. return OXYGEN_I2S_BITS_24;
  233. else
  234. return OXYGEN_I2S_BITS_16;
  235. }
  236. static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
  237. {
  238. switch (params_channels(hw_params)) {
  239. default: /* 2 */
  240. return OXYGEN_PLAY_CHANNELS_2;
  241. case 4:
  242. return OXYGEN_PLAY_CHANNELS_4;
  243. case 6:
  244. return OXYGEN_PLAY_CHANNELS_6;
  245. case 8:
  246. return OXYGEN_PLAY_CHANNELS_8;
  247. }
  248. }
  249. static const unsigned int channel_base_registers[PCM_COUNT] = {
  250. [PCM_A] = OXYGEN_DMA_A_ADDRESS,
  251. [PCM_B] = OXYGEN_DMA_B_ADDRESS,
  252. [PCM_C] = OXYGEN_DMA_C_ADDRESS,
  253. [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
  254. [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
  255. [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
  256. };
  257. static int oxygen_hw_params(struct snd_pcm_substream *substream,
  258. struct snd_pcm_hw_params *hw_params)
  259. {
  260. struct oxygen *chip = snd_pcm_substream_chip(substream);
  261. unsigned int channel = oxygen_substream_channel(substream);
  262. int err;
  263. err = snd_pcm_lib_malloc_pages(substream,
  264. params_buffer_bytes(hw_params));
  265. if (err < 0)
  266. return err;
  267. oxygen_write32(chip, channel_base_registers[channel],
  268. (u32)substream->runtime->dma_addr);
  269. if (channel == PCM_MULTICH) {
  270. oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
  271. params_buffer_bytes(hw_params) / 4 - 1);
  272. oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
  273. params_period_bytes(hw_params) / 4 - 1);
  274. } else {
  275. oxygen_write16(chip, channel_base_registers[channel] + 4,
  276. params_buffer_bytes(hw_params) / 4 - 1);
  277. oxygen_write16(chip, channel_base_registers[channel] + 6,
  278. params_period_bytes(hw_params) / 4 - 1);
  279. }
  280. return 0;
  281. }
  282. static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
  283. struct snd_pcm_hw_params *hw_params)
  284. {
  285. struct oxygen *chip = snd_pcm_substream_chip(substream);
  286. int err;
  287. err = oxygen_hw_params(substream, hw_params);
  288. if (err < 0)
  289. return err;
  290. spin_lock_irq(&chip->reg_lock);
  291. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  292. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
  293. OXYGEN_REC_FORMAT_A_MASK);
  294. oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
  295. oxygen_rate(hw_params) |
  296. oxygen_i2s_mclk(hw_params) |
  297. chip->model->adc_i2s_format |
  298. oxygen_i2s_bits(hw_params),
  299. OXYGEN_I2S_RATE_MASK |
  300. OXYGEN_I2S_FORMAT_MASK |
  301. OXYGEN_I2S_MCLK_MASK |
  302. OXYGEN_I2S_BITS_MASK);
  303. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  304. OXYGEN_REC_A_ROUTE_I2S_ADC_1,
  305. OXYGEN_REC_A_ROUTE_MASK);
  306. spin_unlock_irq(&chip->reg_lock);
  307. mutex_lock(&chip->mutex);
  308. chip->model->set_adc_params(chip, hw_params);
  309. mutex_unlock(&chip->mutex);
  310. return 0;
  311. }
  312. static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
  313. struct snd_pcm_hw_params *hw_params)
  314. {
  315. struct oxygen *chip = snd_pcm_substream_chip(substream);
  316. int err;
  317. err = oxygen_hw_params(substream, hw_params);
  318. if (err < 0)
  319. return err;
  320. spin_lock_irq(&chip->reg_lock);
  321. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  322. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
  323. OXYGEN_REC_FORMAT_B_MASK);
  324. oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
  325. oxygen_rate(hw_params) |
  326. oxygen_i2s_mclk(hw_params) |
  327. chip->model->adc_i2s_format |
  328. oxygen_i2s_bits(hw_params),
  329. OXYGEN_I2S_RATE_MASK |
  330. OXYGEN_I2S_FORMAT_MASK |
  331. OXYGEN_I2S_MCLK_MASK |
  332. OXYGEN_I2S_BITS_MASK);
  333. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  334. OXYGEN_REC_B_ROUTE_I2S_ADC_2,
  335. OXYGEN_REC_B_ROUTE_MASK);
  336. spin_unlock_irq(&chip->reg_lock);
  337. mutex_lock(&chip->mutex);
  338. chip->model->set_adc_params(chip, hw_params);
  339. mutex_unlock(&chip->mutex);
  340. return 0;
  341. }
  342. static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
  343. struct snd_pcm_hw_params *hw_params)
  344. {
  345. struct oxygen *chip = snd_pcm_substream_chip(substream);
  346. int err;
  347. err = oxygen_hw_params(substream, hw_params);
  348. if (err < 0)
  349. return err;
  350. spin_lock_irq(&chip->reg_lock);
  351. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  352. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
  353. OXYGEN_REC_FORMAT_C_MASK);
  354. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  355. OXYGEN_REC_C_ROUTE_SPDIF,
  356. OXYGEN_REC_C_ROUTE_MASK);
  357. spin_unlock_irq(&chip->reg_lock);
  358. return 0;
  359. }
  360. static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
  361. struct snd_pcm_hw_params *hw_params)
  362. {
  363. struct oxygen *chip = snd_pcm_substream_chip(substream);
  364. int err;
  365. err = oxygen_hw_params(substream, hw_params);
  366. if (err < 0)
  367. return err;
  368. spin_lock_irq(&chip->reg_lock);
  369. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  370. OXYGEN_SPDIF_OUT_ENABLE);
  371. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  372. oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
  373. OXYGEN_SPDIF_FORMAT_MASK);
  374. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  375. oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
  376. OXYGEN_SPDIF_OUT_RATE_MASK);
  377. oxygen_update_spdif_source(chip);
  378. spin_unlock_irq(&chip->reg_lock);
  379. return 0;
  380. }
  381. static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
  382. struct snd_pcm_hw_params *hw_params)
  383. {
  384. struct oxygen *chip = snd_pcm_substream_chip(substream);
  385. int err;
  386. err = oxygen_hw_params(substream, hw_params);
  387. if (err < 0)
  388. return err;
  389. spin_lock_irq(&chip->reg_lock);
  390. oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
  391. oxygen_play_channels(hw_params),
  392. OXYGEN_PLAY_CHANNELS_MASK);
  393. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  394. oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
  395. OXYGEN_MULTICH_FORMAT_MASK);
  396. oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
  397. oxygen_rate(hw_params) |
  398. chip->model->dac_i2s_format |
  399. oxygen_i2s_bits(hw_params),
  400. OXYGEN_I2S_RATE_MASK |
  401. OXYGEN_I2S_FORMAT_MASK |
  402. OXYGEN_I2S_BITS_MASK);
  403. oxygen_write16_masked(chip, OXYGEN_PLAY_ROUTING,
  404. OXYGEN_PLAY_MULTICH_I2S_DAC,
  405. OXYGEN_PLAY_MUTE01 | OXYGEN_PLAY_MUTE23 |
  406. OXYGEN_PLAY_MUTE45 | OXYGEN_PLAY_MUTE67 |
  407. OXYGEN_PLAY_MULTICH_MASK);
  408. oxygen_update_dac_routing(chip);
  409. oxygen_update_spdif_source(chip);
  410. spin_unlock_irq(&chip->reg_lock);
  411. mutex_lock(&chip->mutex);
  412. chip->model->set_dac_params(chip, hw_params);
  413. mutex_unlock(&chip->mutex);
  414. return 0;
  415. }
  416. static int oxygen_hw_free(struct snd_pcm_substream *substream)
  417. {
  418. struct oxygen *chip = snd_pcm_substream_chip(substream);
  419. unsigned int channel = oxygen_substream_channel(substream);
  420. spin_lock_irq(&chip->reg_lock);
  421. chip->interrupt_mask &= ~(1 << channel);
  422. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  423. spin_unlock_irq(&chip->reg_lock);
  424. return snd_pcm_lib_free_pages(substream);
  425. }
  426. static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
  427. {
  428. struct oxygen *chip = snd_pcm_substream_chip(substream);
  429. spin_lock_irq(&chip->reg_lock);
  430. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  431. OXYGEN_SPDIF_OUT_ENABLE);
  432. spin_unlock_irq(&chip->reg_lock);
  433. return oxygen_hw_free(substream);
  434. }
  435. static int oxygen_prepare(struct snd_pcm_substream *substream)
  436. {
  437. struct oxygen *chip = snd_pcm_substream_chip(substream);
  438. unsigned int channel = oxygen_substream_channel(substream);
  439. unsigned int channel_mask = 1 << channel;
  440. spin_lock_irq(&chip->reg_lock);
  441. oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  442. oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  443. chip->interrupt_mask |= channel_mask;
  444. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  445. spin_unlock_irq(&chip->reg_lock);
  446. return 0;
  447. }
  448. static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
  449. {
  450. struct oxygen *chip = snd_pcm_substream_chip(substream);
  451. struct snd_pcm_substream *s;
  452. unsigned int mask = 0;
  453. int pausing;
  454. switch (cmd) {
  455. case SNDRV_PCM_TRIGGER_STOP:
  456. case SNDRV_PCM_TRIGGER_START:
  457. pausing = 0;
  458. break;
  459. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  460. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  461. pausing = 1;
  462. break;
  463. default:
  464. return -EINVAL;
  465. }
  466. snd_pcm_group_for_each_entry(s, substream) {
  467. if (snd_pcm_substream_chip(s) == chip) {
  468. mask |= 1 << oxygen_substream_channel(s);
  469. snd_pcm_trigger_done(s, substream);
  470. }
  471. }
  472. spin_lock(&chip->reg_lock);
  473. if (!pausing) {
  474. if (cmd == SNDRV_PCM_TRIGGER_START)
  475. chip->pcm_running |= mask;
  476. else
  477. chip->pcm_running &= ~mask;
  478. oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
  479. } else {
  480. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  481. oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  482. else
  483. oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  484. }
  485. spin_unlock(&chip->reg_lock);
  486. return 0;
  487. }
  488. static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
  489. {
  490. struct oxygen *chip = snd_pcm_substream_chip(substream);
  491. struct snd_pcm_runtime *runtime = substream->runtime;
  492. unsigned int channel = oxygen_substream_channel(substream);
  493. u32 curr_addr;
  494. /* no spinlock, this read should be atomic */
  495. curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
  496. return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
  497. }
  498. static struct snd_pcm_ops oxygen_rec_a_ops = {
  499. .open = oxygen_rec_a_open,
  500. .close = oxygen_close,
  501. .ioctl = snd_pcm_lib_ioctl,
  502. .hw_params = oxygen_rec_a_hw_params,
  503. .hw_free = oxygen_hw_free,
  504. .prepare = oxygen_prepare,
  505. .trigger = oxygen_trigger,
  506. .pointer = oxygen_pointer,
  507. };
  508. static struct snd_pcm_ops oxygen_rec_b_ops = {
  509. .open = oxygen_rec_b_open,
  510. .close = oxygen_close,
  511. .ioctl = snd_pcm_lib_ioctl,
  512. .hw_params = oxygen_rec_b_hw_params,
  513. .hw_free = oxygen_hw_free,
  514. .prepare = oxygen_prepare,
  515. .trigger = oxygen_trigger,
  516. .pointer = oxygen_pointer,
  517. };
  518. static struct snd_pcm_ops oxygen_rec_c_ops = {
  519. .open = oxygen_rec_c_open,
  520. .close = oxygen_close,
  521. .ioctl = snd_pcm_lib_ioctl,
  522. .hw_params = oxygen_rec_c_hw_params,
  523. .hw_free = oxygen_hw_free,
  524. .prepare = oxygen_prepare,
  525. .trigger = oxygen_trigger,
  526. .pointer = oxygen_pointer,
  527. };
  528. static struct snd_pcm_ops oxygen_spdif_ops = {
  529. .open = oxygen_spdif_open,
  530. .close = oxygen_close,
  531. .ioctl = snd_pcm_lib_ioctl,
  532. .hw_params = oxygen_spdif_hw_params,
  533. .hw_free = oxygen_spdif_hw_free,
  534. .prepare = oxygen_prepare,
  535. .trigger = oxygen_trigger,
  536. .pointer = oxygen_pointer,
  537. };
  538. static struct snd_pcm_ops oxygen_multich_ops = {
  539. .open = oxygen_multich_open,
  540. .close = oxygen_close,
  541. .ioctl = snd_pcm_lib_ioctl,
  542. .hw_params = oxygen_multich_hw_params,
  543. .hw_free = oxygen_hw_free,
  544. .prepare = oxygen_prepare,
  545. .trigger = oxygen_trigger,
  546. .pointer = oxygen_pointer,
  547. };
  548. static struct snd_pcm_ops oxygen_ac97_ops = {
  549. .open = oxygen_ac97_open,
  550. .close = oxygen_close,
  551. .ioctl = snd_pcm_lib_ioctl,
  552. .hw_params = oxygen_hw_params,
  553. .hw_free = oxygen_hw_free,
  554. .prepare = oxygen_prepare,
  555. .trigger = oxygen_trigger,
  556. .pointer = oxygen_pointer,
  557. };
  558. static void oxygen_pcm_free(struct snd_pcm *pcm)
  559. {
  560. snd_pcm_lib_preallocate_free_for_all(pcm);
  561. }
  562. int __devinit oxygen_pcm_init(struct oxygen *chip)
  563. {
  564. struct snd_pcm *pcm;
  565. int outs, ins;
  566. int err;
  567. outs = 1; /* OXYGEN_CHANNEL_MULTICH is always used */
  568. ins = !!(chip->model->used_channels & (OXYGEN_CHANNEL_A |
  569. OXYGEN_CHANNEL_B));
  570. err = snd_pcm_new(chip->card, "Analog", 0, outs, ins, &pcm);
  571. if (err < 0)
  572. return err;
  573. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_multich_ops);
  574. if (chip->model->used_channels & OXYGEN_CHANNEL_A)
  575. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  576. &oxygen_rec_a_ops);
  577. else if (chip->model->used_channels & OXYGEN_CHANNEL_B)
  578. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  579. &oxygen_rec_b_ops);
  580. pcm->private_data = chip;
  581. pcm->private_free = oxygen_pcm_free;
  582. strcpy(pcm->name, "Analog");
  583. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
  584. SNDRV_DMA_TYPE_DEV,
  585. snd_dma_pci_data(chip->pci),
  586. 512 * 1024, 2048 * 1024);
  587. if (ins)
  588. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
  589. SNDRV_DMA_TYPE_DEV,
  590. snd_dma_pci_data(chip->pci),
  591. 128 * 1024, 256 * 1024);
  592. outs = !!(chip->model->used_channels & OXYGEN_CHANNEL_SPDIF);
  593. ins = !!(chip->model->used_channels & OXYGEN_CHANNEL_C);
  594. if (outs | ins) {
  595. err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
  596. if (err < 0)
  597. return err;
  598. if (outs)
  599. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  600. &oxygen_spdif_ops);
  601. if (ins)
  602. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  603. &oxygen_rec_c_ops);
  604. pcm->private_data = chip;
  605. pcm->private_free = oxygen_pcm_free;
  606. strcpy(pcm->name, "Digital");
  607. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  608. snd_dma_pci_data(chip->pci),
  609. 128 * 1024, 256 * 1024);
  610. }
  611. outs = chip->has_ac97_1 &&
  612. (chip->model->used_channels & OXYGEN_CHANNEL_AC97);
  613. ins = (chip->model->used_channels & (OXYGEN_CHANNEL_A |
  614. OXYGEN_CHANNEL_B))
  615. == (OXYGEN_CHANNEL_A | OXYGEN_CHANNEL_B);
  616. if (outs | ins) {
  617. err = snd_pcm_new(chip->card, ins ? "Analog2" : "AC97",
  618. 2, outs, ins, &pcm);
  619. if (err < 0)
  620. return err;
  621. if (outs)
  622. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  623. &oxygen_ac97_ops);
  624. if (ins)
  625. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  626. &oxygen_rec_b_ops);
  627. pcm->private_data = chip;
  628. pcm->private_free = oxygen_pcm_free;
  629. strcpy(pcm->name, ins ? "Analog 2" : "Front Panel");
  630. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  631. snd_dma_pci_data(chip->pci),
  632. 128 * 1024, 256 * 1024);
  633. }
  634. return 0;
  635. }