irq_maskreg.c 2.7 KB

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  1. /*
  2. * linux/arch/sh/kernel/irq_maskreg.c
  3. *
  4. * Copyright (C) 2001 A&D Co., Ltd. <http://www.aandd.co.jp>
  5. *
  6. * This file may be copied or modified under the terms of the GNU
  7. * General Public License. See linux/COPYING for more information.
  8. *
  9. * Interrupt handling for Simple external interrupt mask register
  10. *
  11. * This is for the machine which have single 16 bit register
  12. * for masking external IRQ individually.
  13. * Each bit of the register is for masking each interrupt.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/irq.h>
  18. #include <asm/system.h>
  19. #include <asm/io.h>
  20. #include <asm/machvec.h>
  21. /* address of external interrupt mask register
  22. * address must be set prior to use these (maybe in init_XXX_irq())
  23. * XXX : is it better to use .config than specifying it in code? */
  24. unsigned short *irq_mask_register = 0;
  25. /* forward declaration */
  26. static unsigned int startup_maskreg_irq(unsigned int irq);
  27. static void shutdown_maskreg_irq(unsigned int irq);
  28. static void enable_maskreg_irq(unsigned int irq);
  29. static void disable_maskreg_irq(unsigned int irq);
  30. static void mask_and_ack_maskreg(unsigned int);
  31. static void end_maskreg_irq(unsigned int irq);
  32. /* hw_interrupt_type */
  33. static struct hw_interrupt_type maskreg_irq_type = {
  34. .typename = " Mask Register",
  35. .startup = startup_maskreg_irq,
  36. .shutdown = shutdown_maskreg_irq,
  37. .enable = enable_maskreg_irq,
  38. .disable = disable_maskreg_irq,
  39. .ack = mask_and_ack_maskreg,
  40. .end = end_maskreg_irq
  41. };
  42. /* actual implementatin */
  43. static unsigned int startup_maskreg_irq(unsigned int irq)
  44. {
  45. enable_maskreg_irq(irq);
  46. return 0; /* never anything pending */
  47. }
  48. static void shutdown_maskreg_irq(unsigned int irq)
  49. {
  50. disable_maskreg_irq(irq);
  51. }
  52. static void disable_maskreg_irq(unsigned int irq)
  53. {
  54. if (irq_mask_register) {
  55. unsigned long flags;
  56. unsigned short val, mask = 0x01 << irq;
  57. /* Set "irq"th bit */
  58. local_irq_save(flags);
  59. val = ctrl_inw((unsigned long)irq_mask_register);
  60. val |= mask;
  61. ctrl_outw(val, (unsigned long)irq_mask_register);
  62. local_irq_restore(flags);
  63. }
  64. }
  65. static void enable_maskreg_irq(unsigned int irq)
  66. {
  67. if (irq_mask_register) {
  68. unsigned long flags;
  69. unsigned short val, mask = ~(0x01 << irq);
  70. /* Clear "irq"th bit */
  71. local_irq_save(flags);
  72. val = ctrl_inw((unsigned long)irq_mask_register);
  73. val &= mask;
  74. ctrl_outw(val, (unsigned long)irq_mask_register);
  75. local_irq_restore(flags);
  76. }
  77. }
  78. static void mask_and_ack_maskreg(unsigned int irq)
  79. {
  80. disable_maskreg_irq(irq);
  81. }
  82. static void end_maskreg_irq(unsigned int irq)
  83. {
  84. if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  85. enable_maskreg_irq(irq);
  86. }
  87. void make_maskreg_irq(unsigned int irq)
  88. {
  89. disable_irq_nosync(irq);
  90. irq_desc[irq].chip = &maskreg_irq_type;
  91. disable_maskreg_irq(irq);
  92. }