s3c2440-irq.c 3.1 KB

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  1. /* linux/arch/arm/mach-s3c2410/s3c2440-irq.c
  2. *
  3. * Copyright (c) 2003,2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. * Changelog:
  21. * 25-Jul-2005 BJD Split from irq.c
  22. *
  23. */
  24. #include <linux/init.h>
  25. #include <linux/module.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/ioport.h>
  28. #include <linux/ptrace.h>
  29. #include <linux/sysdev.h>
  30. #include <asm/hardware.h>
  31. #include <asm/irq.h>
  32. #include <asm/io.h>
  33. #include <asm/mach/irq.h>
  34. #include <asm/arch/regs-irq.h>
  35. #include <asm/arch/regs-gpio.h>
  36. #include "cpu.h"
  37. #include "pm.h"
  38. #include "irq.h"
  39. /* WDT/AC97 */
  40. static void s3c_irq_demux_wdtac97(unsigned int irq,
  41. struct irqdesc *desc,
  42. struct pt_regs *regs)
  43. {
  44. unsigned int subsrc, submsk;
  45. struct irqdesc *mydesc;
  46. /* read the current pending interrupts, and the mask
  47. * for what it is available */
  48. subsrc = __raw_readl(S3C2410_SUBSRCPND);
  49. submsk = __raw_readl(S3C2410_INTSUBMSK);
  50. subsrc &= ~submsk;
  51. subsrc >>= 13;
  52. subsrc &= 3;
  53. if (subsrc != 0) {
  54. if (subsrc & 1) {
  55. mydesc = irq_desc + IRQ_S3C2440_WDT;
  56. desc_handle_irq(IRQ_S3C2440_WDT, mydesc, regs);
  57. }
  58. if (subsrc & 2) {
  59. mydesc = irq_desc + IRQ_S3C2440_AC97;
  60. desc_handle_irq(IRQ_S3C2440_AC97, mydesc, regs);
  61. }
  62. }
  63. }
  64. #define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
  65. static void
  66. s3c_irq_wdtac97_mask(unsigned int irqno)
  67. {
  68. s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13);
  69. }
  70. static void
  71. s3c_irq_wdtac97_unmask(unsigned int irqno)
  72. {
  73. s3c_irqsub_unmask(irqno, INTMSK_WDT);
  74. }
  75. static void
  76. s3c_irq_wdtac97_ack(unsigned int irqno)
  77. {
  78. s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
  79. }
  80. static struct irqchip s3c_irq_wdtac97 = {
  81. .mask = s3c_irq_wdtac97_mask,
  82. .unmask = s3c_irq_wdtac97_unmask,
  83. .ack = s3c_irq_wdtac97_ack,
  84. };
  85. static int s3c2440_irq_add(struct sys_device *sysdev)
  86. {
  87. unsigned int irqno;
  88. printk("S3C2440: IRQ Support\n");
  89. /* add new chained handler for wdt, ac7 */
  90. set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
  91. set_irq_handler(IRQ_WDT, do_level_IRQ);
  92. set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
  93. for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
  94. set_irq_chip(irqno, &s3c_irq_wdtac97);
  95. set_irq_handler(irqno, do_level_IRQ);
  96. set_irq_flags(irqno, IRQF_VALID);
  97. }
  98. return 0;
  99. }
  100. static struct sysdev_driver s3c2440_irq_driver = {
  101. .add = s3c2440_irq_add,
  102. };
  103. static int s3c2440_irq_init(void)
  104. {
  105. return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
  106. }
  107. arch_initcall(s3c2440_irq_init);