amd64_edac_inj.c 6.2 KB

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  1. #include "amd64_edac.h"
  2. static ssize_t amd64_inject_section_show(struct device *dev,
  3. struct device_attribute *mattr,
  4. char *buf)
  5. {
  6. struct mem_ctl_info *mci = to_mci(dev);
  7. struct amd64_pvt *pvt = mci->pvt_info;
  8. return sprintf(buf, "0x%x\n", pvt->injection.section);
  9. }
  10. /*
  11. * store error injection section value which refers to one of 4 16-byte sections
  12. * within a 64-byte cacheline
  13. *
  14. * range: 0..3
  15. */
  16. static ssize_t amd64_inject_section_store(struct device *dev,
  17. struct device_attribute *mattr,
  18. const char *data, size_t count)
  19. {
  20. struct mem_ctl_info *mci = to_mci(dev);
  21. struct amd64_pvt *pvt = mci->pvt_info;
  22. unsigned long value;
  23. int ret = 0;
  24. ret = strict_strtoul(data, 10, &value);
  25. if (ret != -EINVAL) {
  26. if (value > 3) {
  27. amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
  28. return -EINVAL;
  29. }
  30. pvt->injection.section = (u32) value;
  31. return count;
  32. }
  33. return ret;
  34. }
  35. static ssize_t amd64_inject_word_show(struct device *dev,
  36. struct device_attribute *mattr,
  37. char *buf)
  38. {
  39. struct mem_ctl_info *mci = to_mci(dev);
  40. struct amd64_pvt *pvt = mci->pvt_info;
  41. return sprintf(buf, "0x%x\n", pvt->injection.word);
  42. }
  43. /*
  44. * store error injection word value which refers to one of 9 16-bit word of the
  45. * 16-byte (128-bit + ECC bits) section
  46. *
  47. * range: 0..8
  48. */
  49. static ssize_t amd64_inject_word_store(struct device *dev,
  50. struct device_attribute *mattr,
  51. const char *data, size_t count)
  52. {
  53. struct mem_ctl_info *mci = to_mci(dev);
  54. struct amd64_pvt *pvt = mci->pvt_info;
  55. unsigned long value;
  56. int ret = 0;
  57. ret = strict_strtoul(data, 10, &value);
  58. if (ret != -EINVAL) {
  59. if (value > 8) {
  60. amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
  61. return -EINVAL;
  62. }
  63. pvt->injection.word = (u32) value;
  64. return count;
  65. }
  66. return ret;
  67. }
  68. static ssize_t amd64_inject_ecc_vector_show(struct device *dev,
  69. struct device_attribute *mattr,
  70. char *buf)
  71. {
  72. struct mem_ctl_info *mci = to_mci(dev);
  73. struct amd64_pvt *pvt = mci->pvt_info;
  74. return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
  75. }
  76. /*
  77. * store 16 bit error injection vector which enables injecting errors to the
  78. * corresponding bit within the error injection word above. When used during a
  79. * DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
  80. */
  81. static ssize_t amd64_inject_ecc_vector_store(struct device *dev,
  82. struct device_attribute *mattr,
  83. const char *data, size_t count)
  84. {
  85. struct mem_ctl_info *mci = to_mci(dev);
  86. struct amd64_pvt *pvt = mci->pvt_info;
  87. unsigned long value;
  88. int ret = 0;
  89. ret = strict_strtoul(data, 16, &value);
  90. if (ret != -EINVAL) {
  91. if (value & 0xFFFF0000) {
  92. amd64_warn("%s: invalid EccVector: 0x%lx\n",
  93. __func__, value);
  94. return -EINVAL;
  95. }
  96. pvt->injection.bit_map = (u32) value;
  97. return count;
  98. }
  99. return ret;
  100. }
  101. /*
  102. * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
  103. * fields needed by the injection registers and read the NB Array Data Port.
  104. */
  105. static ssize_t amd64_inject_read_store(struct device *dev,
  106. struct device_attribute *mattr,
  107. const char *data, size_t count)
  108. {
  109. struct mem_ctl_info *mci = to_mci(dev);
  110. struct amd64_pvt *pvt = mci->pvt_info;
  111. unsigned long value;
  112. u32 section, word_bits;
  113. int ret = 0;
  114. ret = strict_strtoul(data, 10, &value);
  115. if (ret != -EINVAL) {
  116. /* Form value to choose 16-byte section of cacheline */
  117. section = F10_NB_ARRAY_DRAM_ECC |
  118. SET_NB_ARRAY_ADDRESS(pvt->injection.section);
  119. amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
  120. word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
  121. pvt->injection.bit_map);
  122. /* Issue 'word' and 'bit' along with the READ request */
  123. amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
  124. debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
  125. return count;
  126. }
  127. return ret;
  128. }
  129. /*
  130. * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
  131. * fields needed by the injection registers.
  132. */
  133. static ssize_t amd64_inject_write_store(struct device *dev,
  134. struct device_attribute *mattr,
  135. const char *data, size_t count)
  136. {
  137. struct mem_ctl_info *mci = to_mci(dev);
  138. struct amd64_pvt *pvt = mci->pvt_info;
  139. unsigned long value;
  140. u32 section, word_bits;
  141. int ret = 0;
  142. ret = strict_strtoul(data, 10, &value);
  143. if (ret != -EINVAL) {
  144. /* Form value to choose 16-byte section of cacheline */
  145. section = F10_NB_ARRAY_DRAM_ECC |
  146. SET_NB_ARRAY_ADDRESS(pvt->injection.section);
  147. amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
  148. word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
  149. pvt->injection.bit_map);
  150. /* Issue 'word' and 'bit' along with the READ request */
  151. amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
  152. debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
  153. return count;
  154. }
  155. return ret;
  156. }
  157. /*
  158. * update NUM_INJ_ATTRS in case you add new members
  159. */
  160. static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR,
  161. amd64_inject_section_show, amd64_inject_section_store);
  162. static DEVICE_ATTR(inject_word, S_IRUGO | S_IWUSR,
  163. amd64_inject_word_show, amd64_inject_word_store);
  164. static DEVICE_ATTR(inject_ecc_vector, S_IRUGO | S_IWUSR,
  165. amd64_inject_ecc_vector_show, amd64_inject_ecc_vector_store);
  166. static DEVICE_ATTR(inject_write, S_IRUGO | S_IWUSR,
  167. NULL, amd64_inject_write_store);
  168. static DEVICE_ATTR(inject_read, S_IRUGO | S_IWUSR,
  169. NULL, amd64_inject_read_store);
  170. int amd64_create_sysfs_inject_files(struct mem_ctl_info *mci)
  171. {
  172. int rc;
  173. rc = device_create_file(&mci->dev, &dev_attr_inject_section);
  174. if (rc < 0)
  175. return rc;
  176. rc = device_create_file(&mci->dev, &dev_attr_inject_word);
  177. if (rc < 0)
  178. return rc;
  179. rc = device_create_file(&mci->dev, &dev_attr_inject_ecc_vector);
  180. if (rc < 0)
  181. return rc;
  182. rc = device_create_file(&mci->dev, &dev_attr_inject_write);
  183. if (rc < 0)
  184. return rc;
  185. rc = device_create_file(&mci->dev, &dev_attr_inject_read);
  186. if (rc < 0)
  187. return rc;
  188. return 0;
  189. }
  190. void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci)
  191. {
  192. device_remove_file(&mci->dev, &dev_attr_inject_section);
  193. device_remove_file(&mci->dev, &dev_attr_inject_word);
  194. device_remove_file(&mci->dev, &dev_attr_inject_ecc_vector);
  195. device_remove_file(&mci->dev, &dev_attr_inject_write);
  196. device_remove_file(&mci->dev, &dev_attr_inject_read);
  197. }